AU2000276258A1 - Method and apparatus for performing computations using residue arithmetic - Google Patents

Method and apparatus for performing computations using residue arithmetic

Info

Publication number
AU2000276258A1
AU2000276258A1 AU2000276258A AU7625800A AU2000276258A1 AU 2000276258 A1 AU2000276258 A1 AU 2000276258A1 AU 2000276258 A AU2000276258 A AU 2000276258A AU 7625800 A AU7625800 A AU 7625800A AU 2000276258 A1 AU2000276258 A1 AU 2000276258A1
Authority
AU
Australia
Prior art keywords
residue
performing computations
computing
logic gates
residue arithmetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2000276258A
Inventor
Jonathon D. Mellott
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Athena Group Inc
Original Assignee
Athena Group Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Athena Group Inc filed Critical Athena Group Inc
Publication of AU2000276258A1 publication Critical patent/AU2000276258A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/14—Conversion to or from non-weighted codes
    • H03M7/18—Conversion to or from residue codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/729—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic using representation by a residue number system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Apparatus For Radiation Diagnosis (AREA)
  • Error Detection And Correction (AREA)

Abstract

The subject invention pertains to a method and apparatus for performing computations using residue arithmetic. The subject method and apparatus can utilize logic gates for performing calculations such as multiplication by a constant, computing a number theoretic logarithm of a residue for a given base αi and modulus pi, and computing the product of two residues, modulo pi. The use of logic gates can offer advantages when compared with the use of ROMs for table look-up functions in integrated RNS digital signal processor implementations.
AU2000276258A 2000-05-12 2000-10-03 Method and apparatus for performing computations using residue arithmetic Abandoned AU2000276258A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/569,944 US7523151B1 (en) 2000-05-12 2000-05-12 Method and apparatus for performing computations using residue arithmetic
US09569944 2000-05-12
PCT/US2000/027221 WO2001088694A1 (en) 2000-05-12 2000-10-03 Method and apparatus for performing computations using residue arithmetic

Publications (1)

Publication Number Publication Date
AU2000276258A1 true AU2000276258A1 (en) 2001-11-26

Family

ID=24277555

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2000276258A Abandoned AU2000276258A1 (en) 2000-05-12 2000-10-03 Method and apparatus for performing computations using residue arithmetic

Country Status (7)

Country Link
US (3) US7523151B1 (en)
EP (1) EP1281118B1 (en)
JP (1) JP2004514960A (en)
AT (1) ATE347133T1 (en)
AU (1) AU2000276258A1 (en)
DE (1) DE60032181T2 (en)
WO (1) WO2001088694A1 (en)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006195563A (en) * 2005-01-11 2006-07-27 Renesas Technology Corp Arithmetic processing unit
FR2895605A1 (en) * 2005-12-22 2007-06-29 Thomson Licensing Sas METHOD FOR RECEIVING MULTIPLE CARRIER SIGNAL, TRANSMITTING METHOD, RECEIVER AND TRANSMITTER THEREFOR
US8312551B2 (en) 2007-02-15 2012-11-13 Harris Corporation Low level sequence as an anti-tamper Mechanism
US8611530B2 (en) 2007-05-22 2013-12-17 Harris Corporation Encryption via induced unweighted errors
US20090104357A1 (en) * 2007-10-17 2009-04-23 Dattilo Vincent P Mutli-layer composite coloring coating process
US8363830B2 (en) 2008-02-07 2013-01-29 Harris Corporation Cryptographic system configured to perform a mixed radix conversion with a priori defined statistical artifacts
US8320557B2 (en) 2008-05-08 2012-11-27 Harris Corporation Cryptographic system including a mixed radix number generator with chosen statistical artifacts
US8325702B2 (en) 2008-08-29 2012-12-04 Harris Corporation Multi-tier ad-hoc network in which at least two types of non-interfering waveforms are communicated during a timeslot
US8351484B2 (en) 2008-12-29 2013-01-08 Harris Corporation Communications system employing chaotic spreading codes with static offsets
US8406276B2 (en) 2008-12-29 2013-03-26 Harris Corporation Communications system employing orthogonal chaotic spreading codes
US8457077B2 (en) 2009-03-03 2013-06-04 Harris Corporation Communications system employing orthogonal chaotic spreading codes
US8428102B2 (en) * 2009-06-08 2013-04-23 Harris Corporation Continuous time chaos dithering
US8509284B2 (en) * 2009-06-08 2013-08-13 Harris Corporation Symbol duration dithering for secured chaotic communications
US8428103B2 (en) 2009-06-10 2013-04-23 Harris Corporation Discrete time chaos dithering
US8406352B2 (en) 2009-07-01 2013-03-26 Harris Corporation Symbol estimation for chaotic spread spectrum signal
US8385385B2 (en) 2009-07-01 2013-02-26 Harris Corporation Permission-based secure multiple access communication systems
US8369376B2 (en) 2009-07-01 2013-02-05 Harris Corporation Bit error rate reduction in chaotic communications
US8379689B2 (en) * 2009-07-01 2013-02-19 Harris Corporation Anti-jam communications having selectively variable peak-to-average power ratio including a chaotic constant amplitude zero autocorrelation waveform
US8363700B2 (en) * 2009-07-01 2013-01-29 Harris Corporation Rake receiver for spread spectrum chaotic communications systems
US8340295B2 (en) * 2009-07-01 2012-12-25 Harris Corporation High-speed cryptographic system using chaotic sequences
US8428104B2 (en) 2009-07-01 2013-04-23 Harris Corporation Permission-based multiple access communications systems
US8369377B2 (en) 2009-07-22 2013-02-05 Harris Corporation Adaptive link communications using adaptive chaotic spread waveform
US8848909B2 (en) 2009-07-22 2014-09-30 Harris Corporation Permission-based TDMA chaotic communication systems
US20110137969A1 (en) * 2009-12-09 2011-06-09 Mangesh Sadafale Apparatus and circuits for shared flow graph based discrete cosine transform
US8345725B2 (en) * 2010-03-11 2013-01-01 Harris Corporation Hidden Markov Model detection for spread spectrum waveforms
KR101171199B1 (en) 2011-03-29 2012-08-06 경남대학교 산학협력단 A method and fast multiplier using crt
RU2503992C2 (en) * 2011-09-27 2014-01-10 Федеральное государственное автономное образовательное учреждение высшего профессионального образования "Северо-Кавказский федеральный университет" Device for comparing numbers presented in residue number system
US9712185B2 (en) * 2012-05-19 2017-07-18 Olsen Ip Reserve, Llc System and method for improved fractional binary to fractional residue converter and multipler
US9179406B2 (en) * 2012-10-17 2015-11-03 Qualcomm Incorporated Method and apparatus for enhanced sleep mode tiering to optimize standby time and test yield
RU2557444C1 (en) * 2014-07-16 2015-07-20 Федеральное государственное бюджетное образовательное учреждение высшего образования "Вятский государственный университет" Device for comparing numbers in system of residual classes based on interval-positional characteristics
WO2016021472A1 (en) * 2014-08-05 2016-02-11 シャープ株式会社 Method for producing imaging panel, imaging panel, and x-ray imaging device
EP3513293A4 (en) * 2016-09-16 2020-05-20 University Of Southern California Systems and methods for mitigating faults in combinatory logic
US10387122B1 (en) 2018-05-04 2019-08-20 Olsen Ip Reserve, Llc Residue number matrix multiplier
US10992314B2 (en) * 2019-01-21 2021-04-27 Olsen Ip Reserve, Llc Residue number systems and methods for arithmetic error detection and correction
US11029920B1 (en) 2020-10-21 2021-06-08 Chariot Technologies Lab, Inc. Execution of a conditional statement by an arithmetic and/or bitwise unit
RU2747371C1 (en) * 2020-10-22 2021-05-04 федеральное государственное автономное образовательное учреждение высшего образования "Северо-Кавказский федеральный университет" Device for determining the sign of number represented in residue number system
US11669665B1 (en) * 2020-11-16 2023-06-06 Synopsys, Inc. Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimization
RU2767450C1 (en) * 2021-04-01 2022-03-17 федеральное государственное автономное образовательное учреждение высшего образования "Северо-Кавказский федеральный университет" Method of determining sign of number in system of residual classes

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3609328A (en) * 1968-12-19 1971-09-28 Bell Telephone Labor Inc Multiaperture ferrite residue arithmetic unit
US4107783A (en) * 1977-02-02 1978-08-15 The Board Of Trustees Of The Leland Stanford Junior University System for processing arithmetic information using residue arithmetic
US4281391A (en) 1979-01-15 1981-07-28 Leland Stanford Junior University Number theoretic processor
US4363106A (en) 1980-08-13 1982-12-07 Environmental Research Institute Of Michigan Computation module for addition and multiplication in residue arithmetic
US4506340A (en) 1983-04-04 1985-03-19 Honeywell Information Systems Inc. Method and apparatus for producing the residue of the product of two residues
US4709345A (en) 1985-04-04 1987-11-24 Harris Corporation Apparatus for executing Chinese remainder theorem for residue decoding through quotient-remainder conversion
JPS61271536A (en) * 1985-05-27 1986-12-01 Matsushita Electric Ind Co Ltd Logical arithmetic unit
GB8703136D0 (en) 1987-02-11 1987-03-18 Univ Cardiff Filtering electrical signals
AU2366588A (en) 1987-10-12 1989-04-13 Sony Corporation Method and apparatus for encoding and decoding data in residue number system
FR2622713A1 (en) 1987-10-30 1989-05-05 Thomson Csf CALCULATION CIRCUIT USING RESIDUAL ARITHMETICS
US4948959A (en) * 1988-07-15 1990-08-14 The Boeing Company Optical computer including pipelined conversion of numbers to residue representation
JP2930325B2 (en) 1989-07-29 1999-08-03 ソニー株式会社 Digital signal processing circuit
US5077793A (en) * 1989-09-29 1991-12-31 The Boeing Company Residue number encryption and decryption system
US5107451A (en) 1990-01-30 1992-04-21 The Boeing Company Method and apparatus for pipelined detection of overflow in residue arithmetic multiplication
JPH05252045A (en) 1992-03-04 1993-09-28 Sony Corp Residue arithmetic processing circuit
US5424971A (en) 1992-11-12 1995-06-13 Vlsi Technology, Inc. Unsigned constant multiplier compiler
US5619535A (en) * 1994-07-27 1997-04-08 Alvarez, Jr.; Cesar E. Digital frequency synthesizer
US6195386B1 (en) * 1994-09-26 2001-02-27 Texas Instruments Incorporated Parallel decision feedback equalizer
US5987487A (en) * 1996-03-11 1999-11-16 Cirrus Logic, Inc. Methods and apparatus for the processing of digital signals
JP3615622B2 (en) * 1996-06-28 2005-02-02 株式会社ルネサステクノロジ Microcomputer

Also Published As

Publication number Publication date
DE60032181D1 (en) 2007-01-11
US20100030832A1 (en) 2010-02-04
US8180821B2 (en) 2012-05-15
US20120284319A1 (en) 2012-11-08
EP1281118B1 (en) 2006-11-29
US8965943B2 (en) 2015-02-24
EP1281118A1 (en) 2003-02-05
DE60032181T2 (en) 2007-03-29
JP2004514960A (en) 2004-05-20
US7523151B1 (en) 2009-04-21
WO2001088694A1 (en) 2001-11-22
ATE347133T1 (en) 2006-12-15

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