JP2004503087A - Method of forming a patterned insulating layer on a metal layer - Google Patents

Abstract

The present invention relates to a method for forming a patterned insulating layer (14) on a metal layer (12). According to the method, the insulating layer (14) is applied to the metal layer (12), the covering material (16) is applied to the insulating layer (14), and the insulating material (14) and the covering material (16) are applied. Is etched by a plasma etching process. Patterning the covering material (16) following deposition on the insulating layer (14), and performing a plasma etching process subsequent to patterning the covering material (16) to form a patterned and planarized insulating layer (14). To form

Description

[0001]
The present invention provides a method for depositing an insulating material on a metal layer, depositing a covering material on the insulating layer, and etching the insulating material and the covering material by a plasma etching process. To a method of forming
[0002]
In the manufacture of prior art integrated circuits, it is often necessary to apply an insulating layer on a metal layer. This insulating layer serves to insulate the lower metal layer from another upper metal layer which is subsequently applied to the insulating layer. For the purposeful contact of the metal layers separated by the insulating layer, contact holes (vias) are formed in the insulating layer before depositing the upper metal layer. As an insulating layer, an oxide layer (TEOS) is often used, which is planarized before depositing the upper metal layer. A common method for forming contact holes in a planarized intermediate layer is an etching method.
[0003]
FIG. 3 illustrates a process step of a standard method of the prior art in a sectional view.
[0004]
FIG. 3a shows a substrate 110 on the left, on which two patterned metal tracks 112 are arranged. After patterning of this first metal layer 112, an oxide layer (TEOS) 114 is deposited, as shown on the right side of FIG. 3a.
[0005]
FIG. 3b shows the first resist application of the device for the purpose of planarization. The left side of FIG. 3b is equal to the right side of FIG. 3a. On the right side of FIG. 3 b, there is a well-planarizing resist 116 on the oxide layer 114 for better smoothing the steps in the oxide layer 114.
[0006]
FIG. 3c shows the first plasma etching process. The left side of FIG. 3c is equal to the right side of FIG. 3b. In a plasma etching process, the resist 116 and the oxide layer 114 are etched to a defined minimum thickness at approximately the same etch rate. Thereby, the planarized oxide layer 114 shown on the right side of FIG. 3C is obtained. The plasma etching process is set so that the etching rates are as close as possible for the resist layer 116 and the oxide layer 114, for example by a suitable choice of oxygen concentration. Thus, in the ideal case, the surface of the resist layer 116 is shown on the surface of the oxide layer 114.
[0007]
FIG. 3d shows a second oxide deposition. The left side of FIG. 3d is equal to the right side of FIG. 3c. After the second oxide deposition, all oxide layers 114, 118 having at least an almost flat surface are obtained.
[0008]
FIG. 3e shows another step for applying the resist layer 120. The left side of FIG. 3e is equal to the right side of FIG. 3d. After the second resist coating performed here, a resist layer 120 on all the oxide layers 114 and 118 is obtained.
[0009]
FIG. 3f shows a method of patterning the resist layer 120 by photolithography. An opening 122 is formed in the resist layer 120 by the photolithography process. The left side of FIG. 3f is equal to the right side of FIG. 3e. On the right side of FIG. 3f, the final state of the photolithographic process is shown, in which the resist layer 120 now has an opening 122, so that the oxide layers 114, 118 are partially exposed.
[0010]
FIG. 3g shows the first step of the plasma etching process for forming contact holes in the oxide layers 114, 118. The left side of FIG. 3g is equal to the right side of FIG. 3f. The first isotropic plasma etching step forms a recess 124 in the surface of the oxide 114, 118 in the region of the hole 122 in the resist layer 120 by etching.
[0011]
FIG. 3h illustrates a further plasma etching step. On the left side of FIG. 3h, the same state as shown on the right side of FIG. 3h is shown. The anisotropic etching process complete etches the contact holes in the oxide layers 114, 118, and these contact holes now comprise an isotropic portion 124 and an anisotropic portion 126.
[0012]
FIG. 3i shows that the remaining resist layer 120 is removed by a plasma etching process. The left side of FIG. 3i is equal to the right side of FIG. 3h. The plasma etching process removes resist 120, resulting in oxide layers 114, 118 having contact holes 124 disposed over metal layer 112 and partially planarized. The flattening of the upper hole edges in the region 124 of the contact holes 124, 126 ensures good edge covering of the upper metal layer which is subsequently deposited in the respective holes 124, 126.
[0013]
The method illustrated in FIG. 3 provides a well planarized insulating layer. However, it is significantly more expensive due to the majority of the process steps. The upper hole edge of the contact hole is only partially flattened. In principle, the probability of defects may increase based on the majority of the process steps.
[0014]
Advantages of the Invention The present invention provides for patterning the covering material following deposition on the insulating layer and performing a plasma etching process subsequent to patterning the covering material, thereby forming a patterned and planarized insulating layer. Based on a method according to claim 1. Thus, according to the present invention, after applying the covering material to the insulating layer, a first plasma etching process is first performed, followed by re-forming the oxide layer by another oxide deposition, applying a resist layer again, and It is not necessary to pattern this for the first time to form the desired pattern in the oxide layer. Rather, it is possible to pattern the covering material subsequent to its application to the insulating layer and to form the desired pattern of the insulating layer in a subsequent plasma etching process. In this case, it should be noted that the thickness of the oxide layer is large enough before the application of the covering layer, for example this thickness is the sum of the separately deposited oxide layers in the prior art. May be approximately equal to
[0015]
Advantageously, the covering material is a resist. Resists can be easily applied to the oxide layer, and they are particularly suitable for forming masks.
[0016]
In this connection, it is particularly effective to pattern the covering material by photolithography.
[0017]
This forms a very precise pattern, which then manifests itself positively in the precision of tightly packed integrated circuits.
[0018]
The insulating layer is preferably an oxide layer (TEOS). Oxide layers have proven to be advantageous as insulating layers in tightly packed integrated circuits.
[0019]
The plasma etching process is carried out in one step, wherein the ratio of the covering material etching rate to the insulating material etching rate is advantageously 1 ± 0.4. At such an etch rate ratio, with the appropriate thickness of the deposited layer, it is possible to achieve the desired result in the same manner, ie with only one manufacturing step.
[0020]
On the other hand, the plasma etching process comprises a plurality of steps, wherein at least one isotropic recess is formed in the insulating layer by etching in a first step, and at least one anisotropic recess is formed by etching in a second step. It is also advantageous to form a through hole in the insulating layer, to planarize in the third step and to finish etch the anisotropic recess in the fourth step to form a through hole. In this way, the contact hole can be formed with a particularly controlled structure. A suitable choice of the layer thickness and the etching parameters results in a contact hole whose surface is advantageously chamfered.
[0021]
Furthermore, the plasma etching process comprises a plurality of steps, wherein in a first step the ratio of the covering material etching rate to the insulating material etching rate is greater than one, wherein the primary covering material is etched and at least one A step is formed in the insulating layer, and in a second step the ratio of the etching rate of the covering material to the etching rate of the insulating layer is 1 ± 0.4, wherein at least one recess is formed in the insulating layer by etching. Advantageously, the planarization is carried out, the recess is further etched for a fixed time in a third step and the recess is finished etched in a fourth step to form a through-hole. Thereby, in a first step, the removal of the covering material can firstly be taken into account, while in a second step the etching of the recesses in the insulating layer by a suitable choice of the ratio of the covering material etching rate to the insulating material etching rate. Start and perform planarization. Then, in the third step, the ratio of the etch rates is not important; rather, the recess is further etched over a fixed period of time. In the fourth step, where the covering material may have already been completely removed, the etching rate is not a problem, only the final etching to form the contact holes.
[0022]
Similarly, the plasma etching process has a plurality of steps, wherein in a first step the ratio of the covering material etching rate to the insulating material etching rate is greater than 1 while insulating at least one step for a fixed time. Formed in the layer, wherein in a second step the ratio of the covering material etching rate to the insulating material etching rate is greater than 1, wherein the primary covering material is etched, and in the third step the covering material etching rate to the insulating material etching rate. The ratio is 1 ± 0.4, in which case at least one recess is formed in the insulating layer by etching and planarization is performed, and in a fourth step the recess is further etched for a fixed time to form a through hole. It is advantageous to form and finish etch the recess in a fifth step. Thus, in this embodiment, the step is first formed in the insulating layer for a fixed time, with only a small amount of the covering material being removed by the plasma etching process. Thereby, firstly well-defined initial conditions for the further etching step are created, which leads to particularly accurate results with respect to the surface pattern of the insulating layer.
[0023]
In a particularly preferred embodiment of the method according to the invention, the insulating layer is applied by a single deposition. Even if the deposition of the insulating material can be performed in multiple steps and the insulating layer is based on the quality and thickness required in each case and is effective, the number of process steps is sometimes reduced with respect to the economics of the method For this purpose, it is advantageous to apply the insulating material in a single step.
[0024]
In some cases, it is advantageous to remove the remaining covering material following the plasma etching process by plasma stripping. Thereby, the original plasma etching process can be configured such that the covering material remains on the insulating layer even at the end of the plasma etching process, with respect to the layer thickness to be deposited and the etching rate ratio. Thereafter, it is removed by plasma stripping.
[0025]
Then, according to a further embodiment of the method according to the invention, another upper metal layer is deposited on the completed device comprising a metal layer and an insulating layer. Contact holes with chamfered surfaces are suitable for ensuring good edge covering, in particular for depositing another metal layer. Thus, the method can ultimately be used for the production of often needed multilayer metallization with an insulating layer in an intermediate position.
[0026]
The invention is based on the surprising result that the simplification of the manufacturing method can be achieved by combining the planarization and the etching of the contact holes. Nevertheless, satisfactory results are obtained, especially with regard to the form of the contact holes. By reducing the number of process steps in the manufacture of integrated circuits, the number of defects is reduced, which leads to higher yields. The shape of the contact holes is influenced by changing the process parameters according to the invention, for example by changing the parameters of the plasma etching process with respect to the type of resist, the type of photolithography and the thickness of the layers, and in particular the ratio of the etching rates. Can be exerted. The desired chamfering of the contact holes results in its enlargement. This enlargement can be compensated for by dimensional adaptation in the exposure mask used in lithography and used in patterning the resist mask.
[0027]
BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be described, by way of example, with reference to the accompanying drawings, in which: FIG.
[0028]
FIG. 1 shows the process steps of a first embodiment of the method according to the invention in different schematic layer structures.
[0029]
FIG. 1a shows a cross-section of a substrate 10 and a patterned metal track 12 disposed thereon. The device shown on the left-hand side of this FIG. 1a is shifted by oxide deposition to a device shown on the right-hand side and additionally arranged above the substrate 10 and the patterned metal tracks 12. 3a, it is clear that the oxide layer 14 of FIG. 1a has a greater thickness than the prior art oxide layer 114 of FIG. 3a. For example, the thickness of the oxide layer 14 can correspond to the sum of the thicknesses of two deposits of the prior art oxide layer according to FIG.
[0030]
FIG. 1 b shows the application of the resist layer 16. The left part of FIG. 1b is equal to the right part of FIG. 1a. In the right part of FIG. 1b, a resist layer 16 is shown in addition to the substrate 10, the metal tracks 12 and the oxide layer 14.
[0031]
This drawing is shown again on the left side of FIG. 1c. According to the method of the present invention, a lithography process is performed subsequent to the application of the resist layer 16. This is shown in FIG. 1c. On the right side of FIG. 1 c, holes 22 in the resist layer are recognized, which expose some areas of the surface of the oxide layer 14.
[0032]
FIG. 1d shows the first step of the plasma etching process. The left side of FIG. 1d is equal to the right side of FIG. 1c. First, an isotropic etching process is performed, which is selected to be shorter than the prior art isotropic etching described in connection with FIG. 3g. The isotropic etching process forms a depression 24 in the surface of the oxide layer 14 in the region of the through hole 22 in the resist layer 16.
[0033]
FIG. 1e shows anisotropic etching as a further step in the plasma etching process. The left side of FIG. 1e is equal to the right side of FIG. 1d. On the right-hand side of FIG. 1 e, an anisotropic recess 26 is additionally shown as a continuation of the recess 24.
[0034]
FIG. 1f shows a further step of the plasma etching process for planarization and further formation of recesses 24, 26 in oxide layer 14. The left side of FIG. 1f is equal to the right side of FIG. 1e. On the right side of FIG. 1f, a flattened layer sequence consisting of the substrate 10, the metal path 12, and the oxide layer 14 having the recesses 24, 26 is shown. It has already been recognized that the recesses 24, 26 have a chamfered surface.
[0035]
FIG. 1g shows how the device is finish etched. The left side of FIG. 1g is equal to the right side of FIG. 1f. The recesses 24, 26 are further processed by plasma etching so as to produce through holes 28, which preferably penetrate the oxide layer 14 with chamfered edges.
[0036]
The rate of removal of each layer or the ratio of the removal rates is highly dependent on the parameters of the plasma etching process. By proper selection and variation of this parameter, layers can be selectively and intentionally removed in various process steps, which in turn improves the accuracy in the manufacturing process.
[0037]
An example of a multi-stage plasma etching process as part of a method according to the invention for changing the parameters of the etching process during the manufacturing process is shown in FIG. The left side of FIG. 2a is equal to the right side of FIG. 1d. The planarization step shown in FIG. 2a is performed by plasma etching. In this case, the etching parameters are advantageously set such that the resist layer 16 is etched. In the oxide layer 14, the steps 30 are exclusively etched. On the right-hand side of FIG. 2a, it is recognized that the resist layer 16 has already been significantly removed, while only a small step 30 is present in the oxide layer.
[0038]
FIG. 2b now shows how to further process with different etching parameters. In this case, the diagram on the left in FIG. 2b is equivalent to the diagram on the right in FIG. 2a. Here, the etching parameters are selected such that the resist etch rate is approximately equal to the oxide layer etch rate. Thus, a subsequent formation of the recess 30 in the oxide layer 14 is achieved simultaneously with a high degree of planarization etching.
[0039]
FIG. 2c shows another step of the plasma etching process. The left side of FIG. 2c is equal to the right side of FIG. 2b. The recess 30 is subsequently formed by further etching. The result is shown on the right in FIG. 2c. Now the etch rate is no longer important. A fixed time for the process steps corresponding to FIG. 2c can be set.
[0040]
In FIG. 2D, the recess 30 is further processed to the through hole 28. In this case, the left side of FIG. 2d is equal to the right side of FIG. 2c. The completed through hole 28 is shown on the right side of FIG. 2d. In this process step, the ratio of resist to oxide etch rates is not critical.
[0041]
The layer sequence shown on the right in FIGS. 1g and 2d forms a starting point for depositing further metallization layers. Contact holes with chamfered surfaces are particularly suitable for depositing another metal layer. Since they guarantee good edge covering. Thereby, the method can ultimately be used to produce frequently needed multilayer metallization with an intermediate insulating layer.
[0042]
The above description of the embodiments according to the present invention is only for explanation of the present invention and does not limit the present invention. Various changes and modifications may be made within the scope of the present invention without departing from the scope of the present invention and equivalents thereof.
[Brief description of the drawings]
FIG.
FIG. 2 is a sectional view of a layer sequence occurring in a first embodiment of the method according to the invention.
FIG. 2
FIG. 4 is a sectional view of a layer sequence occurring in a second embodiment of the method according to the invention.
FIG. 3
1 is a cross-sectional view of a layer sequence produced by a method according to the prior art.
[Explanation of symbols]
Reference Signs List 10 substrate, 12 metal layer (metal path), 14 insulating material (insulating layer, oxide layer), 16 covering material (resist layer), 22 holes, 24 isotropic recess (dent), 26 anisotropic recess, 28 through hole , 30 steps (recess)

Claims (11)

Depositing an insulating material (14) on the metal layer (12);
Applying a covering material (16) to the insulating layer (14) and etching the insulating material (14) and the covering material (16) in a plasma etching process to form a patterned insulation on the metal layer (12). In the method for forming the layer (14),
The covering material (16) is patterned following deposition on the insulating layer (14), and a plasma etching process is performed subsequent to patterning the covering material (16), wherein the patterned and planarized insulating layer ( 14) A method for forming a patterned insulating layer on a metal layer, the method comprising: The method according to claim 1, wherein the covering material (16) is a resist. 3. The method according to claim 1, wherein the covering material is patterned by photolithography. 4. The method according to claim 1, wherein the insulating layer is an oxide layer (TEOS). 5. The method as claimed in claim 1, wherein the plasma etching process is carried out in one step, wherein the ratio of the covering material etching rate to the insulating material etching rate is 1 ± 0.4. The plasma etching process comprises a plurality of steps, wherein at least one isotropic recess (24) is formed in the insulating layer (14) by etching in a first step;
Forming at least one anisotropic recess (26) in the insulating layer (14) by etching in a second step;
A method according to any one of the preceding claims, wherein planarization is performed in a third step and finish etching of the anisotropic recess (26) is performed in a fourth step to form through holes (28). The plasma etching process has a plurality of steps, wherein in a first step the ratio of the covering material etching rate to the insulating material etching rate is greater than 1, wherein the primary covering material (16) is etched and the at least one step is performed. Forming a portion (30) in the insulating layer (14);
In a second step, the ratio of the covering material etching rate to the insulating material etching rate is 1 ± 0.4, wherein at least one recess (30) is formed in the insulating layer (14) by etching and planarization is performed. Do
7. The method according to claim 1, wherein the recess is further etched for a fixed time in a third step and the recess is final etched in a fourth step to form a through-hole. The method of claim 1. The plasma etching process comprises a plurality of steps, wherein in a first step the ratio of the covering material etching rate to the insulating material etching rate is greater than 1 with at least one step in the insulating layer for a fixed time. Forming
In a second step, the ratio of the covering material etch rate to the insulating material etch rate is greater than one, wherein the primary covering material is etched;
In a third step, the ratio of the covering material etching rate to the insulating material etching rate is 1 ± 0.4, wherein at least one recess is formed in the insulating layer by etching and planarized;
The method according to any of the preceding claims, wherein the recess is further etched for a fixed time in a fourth step and the recess is finish etched in a fifth step to form a through hole. 9. The method according to claim 1, wherein the insulating material is applied in a single deposition. 10. The method according to claim 1, wherein the covering material remaining after the plasma etching process is removed by plasma stripping. 11. The method according to claim 1, wherein another metal layer is applied to the completed device comprising the metal layer (12) and the insulating layer (14).

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