JP2004363628A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To inhibit parasitic capacity between a gate electrode and source/drain region in the manufacturing method of an MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor) having a embedded gate electrode. <P>SOLUTION: The manufacturing method comprises the steps of depositing an amorphous cerium dioxide film (CeO<SB>2</SB>) 112 by, for example, CVD (Chemical Vapor Deposition), as shown in Fig. (f); forming a single-crystal CeO<SB>2</SB>film 111 only at the bottom face of a trench 121, in such a manner that the single-crystal CeO<SB>2</SB>film is formed in epitaxial growth from the amorphous CeO<SB>2</SB>film 112 on a silicon substrate 11 by for example heat treatment of 450°C, as shown in Fig. (g); depositing, for example, tungsten film as shown in Fig. (h); and forming a gate electrode 15 in padding inside the trench 121, in such a manner that the tungsten film and a low dielectric copnstant insulating film are planarized, until the front surface of a TEOS (tetraethylorthosilicate)-based silicon oxide film 19 is exposed by, for example, CMP (Chemical Mechanical Polishing). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device including a MISFET formed by embedding a gate electrode in a trench, and a method of manufacturing the same.

  In recent years, demands for higher integration and higher speed of semiconductor devices have been increasing. In order to fulfill these demands, reductions and miniaturizations between elements and element dimensions have been promoted, while lowering the internal wiring material and reducing parasitic capacitance have been studied.

Particularly, in the gate electrode where the RC delay appears remarkably, reduction of the resistance is a major issue. Therefore, recently, in order to reduce the resistance of the gate electrode, a polycide gate having a two-layer structure of a polysilicon film and a metal silicide film has been widely adopted. The refractory metal silicide film is promising as a low-resistance wiring material because its resistance is about one digit lower than that of a polysilicon film. As the silicide, tungsten silicide (WSi _x) has been most widely used heretofore.

  However, in order to cope with fine wiring of 0.15 μm or less, it is required to further reduce the resistance of the wiring and to shorten the delay time. In order to realize a gate electrode having a low sheet resistance of 1 Ω / □ or less using tungsten silicide, the thickness of the silicide layer must be increased. Therefore, it is required to achieve a low sheet resistance without increasing the aspect ratio of the electrode.

  Under such circumstances, a structure in which a metal film is directly stacked on a gate insulating film without a polysilicon film interposed therebetween, that is, a so-called metal gate electrode structure is expected to be promising. However, unlike the conventional gate electrode, there are problems such as difficulty in processing the gate electrode and poor heat resistance.

  In order to avoid the above-mentioned problem, a method of forming a trench-embedded gate electrode has been proposed. Specifically, after forming a dummy gate electrode pattern, a diffusion layer is formed over the dummy gate. Thereafter, a gate sidewall insulating film and an interlayer insulating film are formed around the dummy gate. Then, a groove is formed by peeling off the dummy gate, and a metal material constituting a gate electrode is buried in the groove. By using this method, it is possible to lower the temperature of the heating step after the formation of the metal gate electrode.

  However, when the gate insulating film is formed by deposition, the insulating film is deposited not only on the bottom surface of the trench but also on the side surface. In particular, when a high-dielectric film is used as a gate insulating film, a structure in which a high-dielectric film material is formed on the gate side wall is obtained.

  The insulating film on the side wall of the gate electrode is reflected not only in the capacitance between wirings between adjacent gate electrodes / wirings, but also between the gate electrode and the contact connecting the source / drain region and the upper wiring, and between the source / drain and the wiring. It also affects the capacitance between the gate electrodes. That is, when an insulating film having a high dielectric constant is used for the side wall of the gate electrode, there is a problem that the parasitic capacitance of the wiring is increased and the operation speed of the circuit is reduced.

  A method of manufacturing a MISFET in which a gate electrode is buried in a trench has been proposed. However, if this manufacturing method is used, a gate insulating film will be formed also on a side wall of the gate electrode. The gate insulating film formed on the side wall of the gate electrode is not only reflected on the capacitance between wirings between adjacent gate electrodes / wirings, but also between the gate electrode and the contact connecting the source / drain region and the upper wiring. It also affects the parasitic capacitance between the source / drain and the gate electrode. That is, if an insulating film having a high dielectric constant is formed on the side wall of the gate electrode, there is a problem that the parasitic capacitance of the wiring increases.

  An object of the present invention is to form an insulating film having a lower dielectric constant than a gate electrode in a self-aligned manner on a side wall of the gate electrode for a MISFET having a buried type gate electrode to reduce parasitic capacitance and to operate the circuit. An object of the present invention is to provide a semiconductor device capable of suppressing a reduction in speed and a method for manufacturing the same.

  The present invention is configured as described below to achieve the above object.

  A semiconductor device according to an example of the present invention includes a source and a drain formed on a semiconductor substrate, a crystallized gate insulating film formed on the semiconductor substrate in a region between the source and the drain, and the gate insulating film. It is characterized by comprising a gate electrode formed thereon and an insulating film having an amorphous structure formed on the side surface of the gate electrode and having the same material as that of the gate insulating film.

  A method of manufacturing a semiconductor device according to an example of the present invention includes a step of forming a dummy gate in a region where a gate electrode is formed on a semiconductor substrate; a step of forming a sidewall spacer on a sidewall of the dummy gate; Forming a source / drain using the gate and the sidewall spacer as a mask, forming an interlayer insulating film on the semiconductor substrate so as to cover the dummy gate, and planarizing an upper surface of the interlayer insulating film; Exposing the upper surface of the dummy gate and the side wall spacer; removing the dummy gate to form a groove having a side wall formed of the side wall spacer and a bottom surface formed of the semiconductor substrate; Depositing an insulating film having an amorphous structure so as to cover the semiconductor substrate on the bottom surface of the groove; A step of epitaxially growing an insulating film having a single crystal structure from the insulating film to form a gate insulating film on the bottom surface of the groove, and a step of depositing a gate electrode material on the semiconductor substrate so as to fill the groove. Removing the gate electrode material and the amorphous structure insulating film on the interlayer insulating film, and burying the gate electrode in the trench.

  Preferred embodiments of the present invention are described below.

  Before depositing the gate electrode material, the amorphous structure insulating film on the side surface of the groove is removed by etching.

  Before depositing the gate electrode material, the amorphous structure insulating film on the side surface of the groove is modified into a conductor.

[Action]
The present invention has the following operations and effects by the above configuration.

  Since a gate insulating film having a high dielectric constant is not formed on the side wall of the gate electrode, the parasitic capacitance between the gate electrode and the source / drain is reduced, and the operation speed of the circuit can be improved.

  Further, when the insulating film having the amorphous structure is removed, the parasitic capacitance between the gate electrode and the source / drain can be further reduced, and the operation speed of the circuit can be improved.

  Before the deposition of the gate electrode material, a step of modifying the amorphous structure of the insulating film to make it a conductor is performed, thereby further reducing the parasitic capacitance between the gate electrode and the source / drain. The operation speed of the circuit can be improved.

  According to the present invention, since the gate insulating film having a high dielectric constant is not formed on the side wall of the gate electrode, the parasitic capacitance between the gate electrode and the source / drain is reduced, and the operation speed of the circuit is improved. be able to.

  Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a sectional view showing a configuration of a MISFET according to the first embodiment of the present invention.

  As shown in FIG. 1, a groove surrounding the element region of a p-type Si substrate 11 is formed, and an element isolation insulating film 13 is buried in the groove via a buffer oxide film 12.

A metal gate electrode 15 is formed in a device region on the Si substrate 11 with a Ta ₂ O ₅ gate insulating film 14 interposed therebetween. Metal gate electrode 15, the Al electrode 15 ₂ is composed from the Al electrode side wall and the bottom is a barrier layer formed of TiN (barrier metal) 15 ₁ Tokyo.

An n ^- source / drain 16 is formed on Si substrate 11 so as to sandwich metal gate electrode 15. Then, n ⁺ source / drain 17 is formed so as to sandwich metal gate electrode 15 and n ⁻ source / drain 16.

A TEOS-based silicon oxide film 19 is formed on the element isolation insulating film 13 and the n ⁺ source / drain 17 via a buffer oxide film 18. Low dielectric constant insulation, which has a lower dielectric constant than the silicon thermal oxide film, via the TEOS-based silicon oxide film 19 and the buffer oxide film 18 on the gate electrode 15 and on the Si substrate 11 where the TEOS-based silicon oxide film 19 is not formed. A film 20 is formed. A contact hole connected to the n ⁺ source / drain 17 is formed in the TEOS-based silicon oxide film 19 and the low dielectric constant insulating film 20, and an Al wiring 21 is formed in the contact hole.

The feature of this device is that the Ta ₂ O ₅ gate insulating film 14 exists only in a region directly below the metal gate electrode 15. Furthermore, the feature is that the side walls and the upper surface of the metal gate electrode 15 are covered with a low dielectric constant insulating film (Low-k film) 20.

  Next, a manufacturing process of this MOSFET will be described with reference to FIGS. 2 to 8 are process cross-sectional views illustrating a process of manufacturing the MISFET according to the first embodiment of the present invention.

  First, as shown in FIG. 2A, for example, a groove having a depth of about 200 nm is formed on the surface of an element isolation region of a silicon substrate 11 having a plane orientation (100), and its inner wall is thinly oxidized to form a buffer oxide film 12. Form. For example, after depositing a TEOS silicon oxide film system over the entire surface, by performing CMP or the like, an insulating film is buried in the trench, and an element isolation insulating film 13 having a trench isolation (STI: Shallow Trench Isolation) structure is formed. . If necessary, ion implantation for forming wells and channels is performed, and a buffer oxide film 18 having a thickness of about 6 nm is formed on the surface of the substrate.

  Next, as shown in FIG. 2B, a polysilicon film 31 and a silicon nitride film 32 are both deposited to a thickness of about 150 nm by LPCVD as a dummy gate material.

  Next, as shown in FIG. 2C, a resist pattern (not shown) is formed in the gate formation planned region by photolithography or EB drawing, and the silicon nitride film 32 other than the gate formation planned region is formed by RIE. After the polysilicon film 31 is removed by etching to form the dummy gate 33, the resist pattern is removed.

Next, as shown in FIG. 3D, an oxide film 34 of about 6 nm is formed on the side surface of the polysilicon film 31 by thermal oxidation. Next, as shown in FIG. 3E, ion implantation is performed using the dummy gate 33 as a mask to form the n ⁻ source / drain 16. For example, As ions are implanted at an acceleration voltage of 15 keV and a dose of 3 × 10 ¹⁴ cm ⁻² , for example. When a CMOS is formed, an n ⁺ diffusion layer and a p ⁺ diffusion layer are formed separately using a mask formed by a lithography technique.

  Next, as shown in FIG. 4F, a silicon nitride film is deposited to a thickness of about 70 nm, and the entire surface is subjected to RIE, so that the silicon nitride film is left only on the side surfaces of the dummy gates 33 to form sidewall spacers 35.

Next, as shown in FIG. 4G, an n ⁺ source / drain 17 having a higher concentration than the n ⁻ source / drain 16 is formed by ion implantation. For example, As ions are implanted at an acceleration voltage of 45 keV and a dose of 3 × 10 ¹⁵ cm ⁻² . When a CMOS is formed, an n ⁺ diffusion layer and a p ⁺ diffusion layer are formed separately using a mask formed by a lithography technique. Activation annealing (for example, RTA at 1000 ° C. for 10 seconds) of the source / drain diffusion layers may be performed every time immediately after ion implantation, or may be performed at once after all ion implantations are completed. Then, a TEOS-based silicon oxide film 19 is deposited on the entire surface to a thickness of about 350 nm by LPCVD.

  Next, as shown in FIG. 5H, the TEOS-based silicon oxide film 19 is etched back and planarized by CMP (Chemical Mechanical Polishing). In this CMP process, the silicon nitride films 32 and 35 serve as a stopper for CMP.

  Next, as shown in FIG. 5I, the silicon nitride film 32 of the dummy gate 33 is removed by wet etching using hot phosphoric acid. In this etching step, the upper portion of the sidewall spacer 35 made of the silicon nitride film is also etched, so that the height of the sidewall spacer 35 is slightly reduced.

  Next, as shown in FIG. 6 (j), the polysilicon film 31 of the dummy gate 33 is removed by CDE, and the buffer oxide film 18 is removed by wet etching with HF. A groove 26 is formed. Here, channel ions can be separately implanted into each of the NMOS and PMOS channel regions using lithography technology.

Next, as shown in FIG. 6K, a Ta ₂ O ₅ gate insulating film 14 is formed on the entire surface. A method for forming the Ta ₂ O ₅ gate insulating film 14 will be described below. The surface of the Si substrate 11 is irradiated with oxygen radicals to form a SiO ₂ layer having a thickness of about 0.2 to 0.3 nm, and subsequently, a Si ₃ N ₄ layer is formed using ammonia, silane or the like to have a thickness of about 0.6 nm in terms of an oxide film. (The actual film thickness is about 1.2 nm). A Ta ₂ O ₅ film is formed thereon by a CVD method in a thickness of about 1 nm in oxide film equivalent (about 5 nm in actual film thickness). In this case, the gate insulating film thickness becomes 2 nm or less in oxide film equivalent film thickness.

As another method of forming the Ta ₂ O ₅ gate insulating film 14, first, a SiO ₂ layer of about 1 nm is formed by thermal oxidation, and the surface is nitrided (N or less) at a low temperature (600 ° C. or lower) using nitrogen radicals. ² plasma nitriding). When the Si ₃ N ₄ layer is formed to have a thickness equivalent to an oxide film of about 0.6 nm (actual thickness is about 1.2 nm), the SiO ₂ layer has a thickness of about 0.4 nm. If a Ta ₂ O ₅ film is formed thereon with a thickness of about 1 nm in oxide film equivalent (about 5 nm in actual film thickness) by CVD, the thickness of the Ta ₂ O ₅ gate insulating film 14 is 2 nm in equivalent oxide film thickness. It is as follows.

Then, TiN15 ₁ and Al electrodes 15 _{and second} electrodes respectively as gate electrodes 10 nm, is deposited to a thickness of about 250 nm.

Next, as shown in FIG. 7L, the etch back is planarized by CMP using the side wall spacer 25 as a stopper, and the Ta ₂ O ₅ gate insulating film 14 and the gate electrode 15 are buried and formed in the groove 26.

Since the source / drain 16 and 17 (including activation) have already been formed and there is basically no high-temperature step of 450 ° C. or more thereafter, a metal material (Al, W, TiN, Ru, etc.) is used as the gate electrode. ) it is possible to use, also high dielectric film as a gate insulating film (high-k film: Ta ₂ O _5, etc. TiO _2, Si ₃ N ₄₎ or a ferroelectric film ((Ba, Sr) TiO ₃ etc.) can be used.

Next, as shown in FIG. 7 (m), the Ta ₂ O ₅ gate insulating film 14 on the TEOS-based silicon oxide film 19 which is difficult to be removed by CMP and is likely to remain is removed by CDE using CF ₄ and O ₂ gas. At the same time, the Ta ₂ O ₅ insulating film 14 and the side wall spacer 25 on the side surface of the metal gate electrode 15 are removed. The Ta ₂ O ₅ gate insulating film 14 remains only under the metal gate electrode 15 and does not exist on the side surface of the metal gate electrode 15 or on the TEOS-based silicon oxide film 19.

Generally, a buffer layer such as a thermal oxide film or a nitrided oxide film exists below the high dielectric film or the ferroelectric film in order to improve interface characteristics. Therefore, when the Ta ₂ O ₅ insulating film 14 and the side wall spacer 25 are removed, the buffer layer plays a role of an etching stopper, thereby preventing the Si substrate 11 from being scraped.

In the case of forming a Ta ₂ O ₅ film using Ta (OC ₂ H ₅ ) ₅ as a source gas, if the film forming process conditions are optimized, the film is grown in an island shape on the TEOS or the silicon nitride film to be sparse. When the film quality is realized and the film is formed on a silicon substrate or a thin thermal oxide film (in this embodiment, a portion such as a portion under a metal gate) can have a dense and uniform film quality. Therefore, only the Ta ₂ O ₅ insulating film 14 on the TEOS-based silicon oxide film 19 and the side wall of the metal gate electrode 15 is selectively removed, and the Ta ₂ O ₅ insulating film 14 under the metal gate electrode 15 remains. It is easy.

Next, as shown in FIG. 8N, a low dielectric constant insulating film (for example, having a dielectric constant of about 2.5) 20 is deposited so as to cover the side surface and the upper surface of the metal gate electrode 15. Then, after forming a contact hole connected to the n ⁺ source / drain 17 in the low dielectric constant insulating film 20 and the TEOS-based silicon oxide film 19, an Al wiring 21 as an upper wiring connected to the n ⁺ source / drain 17 is formed. I do.

As described above, in the MISFET formed according to the present invention, the high dielectric constant Ta ₂ O ₅ gate insulating film is not formed on the side wall of the metal gate electrode 15 and the dielectric constant is low on the side wall of the metal gate electrode. Since the film is formed, the wiring capacitance between the gate electrode 15 and the source / drain 16 and 17 is reduced, and the operation speed of the device is improved. Further, since the Ta ₂ O ₅ gate insulating film 14 exists only in the region below the gate electrode 15, the Ta ₂ O ₅ does not stop the contact RIE. That is, it is easy to open contact holes in the source / drain regions. Furthermore, since the high dielectric film on the side wall of the gate electrode 15 is removed, a transistor composition suitable for miniaturization and high integration of elements can be realized.

Note that, as the low dielectric constant insulating film, materials as shown in Table 1 can be used.

In Table 1, k indicates a dielectric constant, and T _g indicates a growth temperature.

[Second embodiment]
FIG. 9 shows a sectional view of the basic structure of the second embodiment. FIG. 9 is a sectional view illustrating a configuration of a semiconductor device according to the second embodiment of the present invention. In FIG. 9, the same portions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This device differs from the device shown in the first embodiment in that an epitaxial Si layer 91 is formed on the n ⁺ source / drain 17 and has an elevated source / drain structure. In addition, CoSi _{2 (} not shown) is formed on the epitaxial Si layer 91.

  In general, in an elevated source / drain structure, the gate-source / drain capacitance tends to be large, which tends to adversely affect the element operation speed. This is especially true if there is a high dielectric gate insulating film on the side surface of the metal gate. However, in the present embodiment, the high dielectric gate insulating film between the gate and the elevated source / drain is removed, and a low dielectric constant film (for example, a film having a dielectric constant of about 2.5) is inserted instead. Therefore, the gate-source / drain capacitance is greatly reduced.

  Therefore, the present invention is more effective when an elevated source / drain structure is employed.

[Third embodiment]
FIG. 10 shows a sectional view of the basic structure of the third embodiment. FIG. 10 is a cross-sectional view illustrating a configuration of a semiconductor device according to the third embodiment of the present invention. In FIG. 10, the same portions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This device differs from the device shown in the first embodiment in that the side wall spacer 35 is not removed. Since the Ta ₂ O ₅ gate insulating film 14 on the side surface of the metal gate electrode 15 has been removed, and the low dielectric constant insulating film 20 having a dielectric constant of, for example, about 2.5 is inserted therein, the element operation speed is improved. Further, in the present embodiment, since the side wall spacer 35 is left, even if the formation position of the contact hole connected to the n ⁺ source / drain 17 is slightly misaligned, the spacer remains without disappearing by the contact RIE. There is an advantage that a short circuit between the gate electrode and the contact hardly occurs.

  As shown in FIG. 10, even when the contact hole is formed by being raised above the side wall spacer 35, the insulation between the gate electrode 15 and the Al wiring 21 is maintained because the side wall spacer 35 remains.

[Fourth embodiment]
FIG. 11 shows a sectional view of the basic structure of the fourth embodiment. FIG. 11 is a sectional view illustrating a configuration of a semiconductor device according to a fourth embodiment of the present invention. In FIG. 11, the same portions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The feature of this device is that the gate insulating film at the bottom of the metal gate electrode 15 is a single-crystal CeO ₂ film 111 grown epitaxially, and the gate insulating film on the side surface of the metal gate electrode 15 is an amorphous CeO ₂ film 112.

The dielectric constant of the CeO ₂ film greatly depends on the film quality, and is about 70 to 80 for a single crystal itself, but about 4 for an amorphous structure, which is about the same as 3.6 for a silicon oxide film.

  Therefore, since a film having a low dielectric constant is formed on the side wall of the metal gate electrode 15, the capacitance between wirings between adjacent gate electrodes / wirings, the contact connecting the source / drain region and the upper wiring, and the gate electrode are formed. Can be suppressed from increasing in parasitic capacitance.

In FIG. 11, the side portions of the gate electrode 15 sidewall spacers 113 made of a silicon oxide film 113 ₁ and the silicon nitride film 113 ₂ which is formed. On the TEOS-based silicon oxide film 19, an interlayer insulating film 114 is formed. A contact electrode 115 composed of a titanium nitride film (barrier metal) 115 ₁ and a tungsten film 115 ₂ is formed so as to be connected to the n ⁺ source / drain 17.

  Next, a manufacturing process of the present apparatus will be described with reference to FIGS. 12 and 13 are process cross-sectional views showing a process for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

  First, as shown in FIG. 12A, similarly to the previous embodiment, after forming an element isolation insulating film 13 and a buffer oxide film 18 on a Si substrate 11, a polysilicon film 31 and a silicon nitride film 32 are sequentially formed. accumulate.

Next, as shown in FIG. 12B, the silicon nitride film 32 and the polysilicon film 31 are anisotropically etched into a desired pattern to form a dummy gate 33. Further, for example, As ions are implanted, and a heat treatment is performed at 950 ° C. for 30 seconds to form the n ⁻ source / drain 16.

Then, as shown in FIG. 12 (c), after depositing a silicon oxide film 113 ₁ and the silicon nitride film 113 _2, etching of the silicon nitride film 113 _2, and the silicon oxide film 113 _1, the side walls of the dummy gate 33 forming a sidewall spacer 113 surrounding a silicon nitride film 113 _2. Further, for example, n ⁺ source / drain 17 is formed by implanting P ⁺ ions and performing a heat treatment at 850 ° C. for 30 seconds.

  Next, as shown in FIG. 12D, a TEOS-based silicon oxide film 19 is deposited on the entire surface, and the TEOS-based silicon oxide film 19 is formed on the surface of the dummy gate 33 by, for example, a chemical mechanical polishing (CMP) method. Flatten until exposed.

Next, as shown in FIG. 12E, the dummy gate 33 is removed by peeling off the silicon nitride film 32 and the polysilicon film 31. However, the silicon nitride film 113 _{and second} side walls of the dummy gate 33, the silicon oxide film 113 ₁ is not removed for intervening. Then, the buffer oxide film 18, also a silicon oxide film 113 ₁ is peeled, the side wall is made of a silicon nitride film 113 _2, the bottom surface to form a groove portion 121 formed of Si substrate 11.

Further, as shown in FIG. 12F, an amorphous cerium dioxide film (CeO ₂ ) 112 is deposited by, for example, a CVD method.

Thereafter, as shown in FIG. 12G, a single crystal CeO ₂ film is epitaxially grown on the silicon substrate 11 from the amorphous CeO ₂ film 112 by, for example, heat treatment at 450 ° C., and the single crystal CeO ₂ is formed only on the bottom surface of the groove 121. _Two films 111 are formed.

Since the lattice constants of silicon and CeO ₂ are very close to 5.46 ° and 5.41 °, respectively, and so-called lattice mismatch is small, the single crystal CeO ₂ film 111 can be epitaxially grown on a silicon substrate. However, since the surface of the amorphous CeO ₂ film 112 directly in contact with the silicon substrate 11 is only the bottom surface of the groove 121, the single crystal CeO ₂ film 111 grows epitaxially only on the bottom surface of the groove 121 in a self-aligned manner.

  Thereafter, as shown in FIG. 12H, for example, a tungsten film is formed, and the tungsten film and the low dielectric constant insulating film are flattened by, eg, CMP until the surface of the TEOS-based silicon oxide film 19 is exposed. And the gate electrode 15 is buried in the groove 121.

Through the above steps, a transistor in which the side wall of the gate electrode 15 is covered with the amorphous CeO ₂ film 112 having a low dielectric constant and the single crystal CeO ₂ film 111 having a high dielectric constant is formed at the bottom of the gate electrode 15 is formed. be able to.

Further, as shown in FIG. 13I, after depositing an interlayer insulating film 114, a contact hole 131 is formed in the interlayer insulating film 114 on the n ⁺ source / drain 17 and the TEOS-based silicon oxide film 19. Thereafter, as shown in FIG. 13J, for example, after a titanium nitride film 115 ₁ and a tungsten film 115 ₂ are buried, the surface of the interlayer insulating film 114 is formed by a CMP method using the titanium nitride film 115 ₁ and the tungsten film 115 _2. The contact electrode 115 is formed by flattening until it is exposed.

At this time, since the insulating film between the contact electrode 115 and the gate electrode 15 is the CeO ₂ film 112 having a low dielectric constant, the parasitic capacitance between the contact and the electrode can be suppressed low, and the processing speed of the transistor can be reduced. It can be improved.

In this embodiment, a CeO ₂ film is used as an insulating film epitaxially grown on a silicon substrate. However, a zirconium oxide film (ZrO ₂ ), a hafnium oxide film (HfO ₂ ), a thorium oxide (ThO ₂ ), and an yttrium oxide film ( Y ₂ O ₃ ), a calcium fluoride film (CaF ₂ ), a tin-calcium fluoride film (CaSnF ₂ ), and a titanium barium oxide film (BaTiO ₃ ) can be used.

Note that epitaxial growth does not always occur when the lattice constant is close. For example, the relationship between the lattice constant A and the substrate and the lattice constant B of the deposited film, n _a A ≒ n _b B if (n _a, n _b is an integer), resulting epitaxial growth. In addition, if the lattice constants of the volume film and the substrate have a fixed relationship, epitaxial growth occurs.

Further, in this embodiment, the CeO ₂ film is epitaxially grown immediately after the film formation, but may be performed after the metal film is formed on the CeO ₂ film or after the CeO ₂ film and the metal film are flattened. Further, in this embodiment, the high dielectric constant insulating film is formed by the CVD method, but may be formed by a sputtering method or a vacuum evaporation method.

[Fifth Embodiment]
FIG. 14 shows a sectional view of the basic structure of the fifth embodiment. FIG. 14 is a sectional view illustrating a configuration of a semiconductor device according to a fourth embodiment of the present invention. In FIG. 14, the same portions as those in FIGS. 1 and 11 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The feature of this device is that the single crystal ZrO ₂ gate insulating film 141 is formed only on the bottom of the gate electrode 15, and the single crystal ZrO ₂ film is not formed on the side surface of the gate electrode 15.

In this device, since a single crystal ZrO ₂ film having a high dielectric constant is not formed between the contact electrode 115 and the gate electrode 15, the parasitic capacitance between the contact electrode 115 and the gate electrode 15 can be suppressed low. In addition, the processing speed of the transistor can be improved.

  Next, a manufacturing process of the present apparatus will be described. FIG. 15 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment of the present invention.

First, the same processes as those of the fourth embodiment described with reference to FIGS. 12A to 12E are performed. Next, as shown in FIG. 15A, an amorphous zirconium dioxide film (ZrO ₂ ) 151 is deposited by, for example, an anisotropic sputtering method.

Next, as shown in FIG. 15B, a single crystal ZrO ₂ film 151 is epitaxially grown on the Si substrate 11 from the amorphous ZrO ₂ 151 by, for example, heat treatment at 450 ° C. Since the lattice constants of silicon and ZrO ₂ are very close to 5.46 ° and 5.07 °, respectively, so-called lattice mismatch is small, the single crystal ZrO ₂ film 141 grows epitaxially on the Si substrate 11. However, since the surface of the amorphous ZrO ₂ film 151 directly in contact with the Si substrate 11 is only the bottom surface of the groove 121, the single crystal ZrO ₂ film 141 is epitaxially grown only on the bottom surface of the groove 121 in a self-aligned manner.

The dielectric constant of the ZrO ₂ film largely depends on the film quality, and is about 70 to 80 in the case of a single crystal structure, but is as low as about 4 in the case of an amorphous structure. Therefore, according to the present invention, it is possible to form a structure in which the single crystal ZrO ₂ film 141 having a high dielectric constant is arranged only at the bottom of the groove.

Thereafter, as shown in FIG. 15C, for example, a tungsten film is formed inside the trench 121, and further, the tungsten film and the amorphous ZrO ₂ film 151 are exposed to the surface of the TEOS-based silicon oxide film 19 by, eg, CMP. Then, the gate electrode 15 is buried in the trench 121.

By the steps described above, the sidewalls of the gate electrode 15 is covered with the silicon nitride film 113 _2, and a single crystal ZrO ₂ gate insulating film 141 of a high dielectric constant on the bottom of the gate electrode 15 to form a transistor formed .

Further, as shown in FIGS. 15D to 15E, a contact electrode 115 connected to the n ⁺ source / drain 17 is buried in the contact hole 131 in the same manner as in the previous embodiment. .

[Sixth embodiment]
FIG. 16 shows a sectional view of the basic structure of the sixth embodiment. FIG. 16 is a cross-sectional view illustrating a configuration of a semiconductor device according to a sixth embodiment of the present invention. In FIG. 16, the same parts as those in FIGS. 1 and 11 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The feature of this device is that the single-crystal CeO ₂ gate insulating film 111 is formed only on the bottom of the gate electrode 15, and the single-crystal CeO ₂ film is not formed on the side surface of the gate electrode 15.

In this device, since a single-crystal CeO ₂ film having a high dielectric constant is not formed between the contact electrode 115 and the gate electrode 15, the parasitic capacitance between the contact electrode 115 and the gate electrode 15 can be suppressed low. In addition, the processing speed of the transistor can be improved.

  Next, a manufacturing process of the present apparatus will be described. FIG. 17 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the sixth embodiment of the present invention.

First, the same processes as those of the fourth embodiment described with reference to FIGS. 12A to 12E are performed. Next, as shown in FIG. 17A, an amorphous cerium dioxide film (CeO ₂ ) 112 is deposited by, for example, a vacuum evaporation method.

Next, as shown in FIG. 17B, a single crystal CeO ₂ film 111 is epitaxially grown on the Si substrate 11 from the amorphous CeO ₂ film 112 by, for example, heat treatment at 450 ° C. Since the lattice constants of silicon and CeO ₂ are very close to 5.46 ° and 5.41 °, respectively, and so-called lattice mismatch is small, a single-crystal CeO ₂ film grows epitaxially on a silicon substrate. However, since the surface of the amorphous CeO ₂ film 112 directly in contact with the Si substrate 11 is only the bottom surface of the groove 121, the single-crystal CeO ₂ film 111 grows epitaxially only on the bottom surface of the groove 121 in a self-aligned manner.

The dielectric constant of the CeO ₂ film greatly depends on the film quality, and is about 70 to 80 in the case of a single crystal structure, but is as low as about 4 in the case of an amorphous structure. Therefore, according to the present invention, it is possible to form a structure in which the bottom surface of the groove 121 is the single-crystal CeO ₂ film 111 having a high dielectric constant and the side surface of the groove 121 is formed of the amorphous CeO ₂ film 112 having a low dielectric constant. .

Further, as shown in FIG. 17C, the amorphous CeO ₂ film 112 on the side surface of the groove 121 is peeled off using, for example, 10% diluted sulfuric acid. Since the etching selectivity between the single crystal CeO ₂ film 111 and the amorphous CeO ₂ film 112 is about 5 to 10, the amorphous CeO ₂ film 112 on the side surface of the groove 121 is left while the single crystal CeO ₂ film 111 on the bottom of the groove 121 is left. Can be peeled off.

  Next, as shown in FIG. 17D, for example, a tungsten film is formed on the entire surface, and the tungsten film is flattened by, eg, CMP until the surface of the TEOS-based silicon oxide film 19 is exposed. The gate electrode 15 is buried.

Through the above steps, a transistor using a single-crystal CeO ₂ gate insulating film 111 having a high dielectric constant without forming an insulating film with a high dielectric constant on the side wall of the gate electrode 15 can be formed.

Further, as shown in FIGS. 17E to 17F, a contact electrode 115 connected to the n ⁺ source / drain 17 is buried in the contact hole 131 in the same manner as in the previous embodiment. .

  In the present embodiment, selective etching is performed using sulfuric acid, but hydrofluoric acid, hydrochloric acid, or nitric acid may be used.

[Seventh embodiment]
FIG. 18 shows a sectional view of the basic structure of the seventh embodiment. FIG. 18 is a cross-sectional view illustrating a configuration of a semiconductor device according to a sixth embodiment of the present invention. In FIG. 18, the same parts as those in FIGS. 1 and 11 are denoted by the same reference numerals, and detailed description thereof will be omitted.

Features of the apparatus, only the bottom of the gate electrode 15 is formed is a single crystal HfO ₂ gate insulating film 181, the side surface portion of the gate electrode 15 without monocrystalline HfO ₂ film is formed, the HfN layer 182 It is formed.

In this device, since a single crystal HfO ₂ film having a high dielectric constant is not formed between the contact electrode 115 and the gate electrode 15, the parasitic capacitance between the contact electrode 115 and the gate electrode 15 can be suppressed low. In addition, the processing speed of the transistor can be improved.

  Next, a manufacturing process of the present apparatus will be described. FIG. 19 is a process sectional view illustrating the manufacturing process of the semiconductor device according to the seventh embodiment of the present invention.

First, the same processes as those of the fourth embodiment described with reference to FIGS. 12A to 12E are performed. Next, as shown in FIG. 19A, an amorphous hafnium dioxide film (HfO ₂ ) 191 is deposited by, for example, a CVD method.

Next, as shown in FIG. 19B, a single crystal HfO ₂ film 181 is epitaxially grown on the Si substrate 11 from the amorphous HfO ₂ film 191 by, for example, heat treatment at 450 ° C. However, since the surface of the amorphous HfO ₂ film 191 directly in contact with the Si substrate 11 is only the bottom surface of the groove 121, the single crystal HfO ₂ film 181 is epitaxially grown only on the bottom surface of the groove 121 in a self-aligned manner.

The dielectric constant of the HfO ₂ film largely depends on the quality of the film, and is about 70 to 80 for a single crystal structure, but as low as about 4 for an amorphous structure. Therefore, according to the present invention, it is possible to form a structure in which the bottom surface of the groove 121 is a single crystal HfO ₂ film 181 having a high dielectric constant, and the side surface of the groove 121 is an amorphous HfO ₂ film 191 having a low dielectric constant. It becomes.

Next, as shown in FIG. 19C, the surface of the amorphous HfO ₂ film 191 is nitrided by heating in, for example, an NH ₃ atmosphere, and an HfN film 182 is selectively formed. Amorphous HfO ₂ film 191, because nitriding speed is about 5 times faster than single crystal HfO ₂ film 181, a single crystal HfO ₂ film 181 of the bottom surface of the groove 121 is not less nitride, amorphous non-bottom surface of the groove 121 HfO _{The second} film 191 can be modified into an HfN film 182. Note that since the HfN film 182 is made of metal, the problem of the dielectric constant does not occur.

  Thereafter, as shown in FIG. 19D, for example, a tungsten film is formed inside the trench 121, and the tungsten film and the HfN film 182 are further flattened by, eg, CMP until the surface of the TEOS-based silicon oxide film 19 is exposed. And the gate electrode 15 is buried in the groove 121.

Through the above steps, a transistor in which an insulating film having a high dielectric constant is not formed on the side wall of the gate electrode and a single crystal HfO ₂ film having a high dielectric constant is formed can be formed.

Further, as shown in FIGS. 19E to 19F, a contact electrode 115 connected to the n ⁺ source / drain 17 is buried in the contact hole 131 in the same manner as in the previous embodiment. .

In this embodiment, the HfO ₂ film is formed into a chamber by thermal nitridation using NH ₃ , but may be formed by plasma nitridation. As a gas used for nitriding, in addition to NH ₃ , N ₂ , NH ₄ , NO, NO ₂ , N ₂ O or a combination gas of those gases may be a mixed gas with a gas containing no nitrogen.

  Note that the present invention is not limited to the above embodiment. For example, in the manufacturing method shown in the first to third embodiments, instead of removing the gate insulating film on the side wall of the gate electrode after forming the gate electrode, as shown in the fourth to seventh embodiments, An epitaxially grown gate insulating film may be formed on the bottom, and an amorphous insulating film may be formed on the side wall.

  In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

FIG. 2 is a cross-sectional view illustrating a configuration of the semiconductor device according to the first embodiment. FIG. 2 is a process cross-sectional view illustrating a manufacturing process of the semiconductor device in FIG. 1. FIG. 2 is a process cross-sectional view illustrating a manufacturing process of the semiconductor device in FIG. 1. FIG. 2 is a process cross-sectional view illustrating a manufacturing process of the semiconductor device in FIG. 1. FIG. 2 is a process cross-sectional view illustrating a manufacturing process of the semiconductor device in FIG. 1. FIG. 2 is a process cross-sectional view illustrating a manufacturing process of the semiconductor device in FIG. 1. FIG. 2 is a process cross-sectional view illustrating a manufacturing process of the semiconductor device in FIG. 1. FIG. 2 is a process cross-sectional view illustrating a manufacturing process of the semiconductor device in FIG. 1. FIG. 6 is a cross-sectional view illustrating a configuration of a semiconductor device according to a second embodiment. FIG. 13 is a cross-sectional view illustrating a configuration of a semiconductor device according to a third embodiment. FIG. 14 is a sectional view showing the configuration of a semiconductor device according to a fourth embodiment. FIG. 12 is a process cross-sectional view illustrating a manufacturing process of the semiconductor device in FIG. 11. FIG. 12 is a process cross-sectional view illustrating a manufacturing process of the semiconductor device in FIG. 11. FIG. 14 is a sectional view showing the configuration of a semiconductor device according to a fifth embodiment. FIG. 15 is a process cross-sectional view illustrating the manufacturing process of the semiconductor device in FIG. 14. FIG. 14 is a sectional view showing the configuration of a semiconductor device according to a sixth embodiment. FIG. 17 is a process cross-sectional view illustrating the manufacturing process of the semiconductor device in FIG. 16. FIG. 13 is a sectional view showing a configuration of a semiconductor device according to a seventh embodiment. FIG. 19 is a process sectional view illustrating the manufacturing process of the semiconductor device in FIG. 18;

Explanation of reference numerals

11 ... Si substrate, 12 ... buffer oxide film, 13 ... the element isolation insulating film, 14 ... gate insulating film, 15 ... metal gate electrode, 15 ₁ ... TiN, 15 ₂ ... Al electrode, 16 ... n ^- source / drain 17 ... n ⁺ source / drain, 18 ... buffer oxide film, 19 ... TEOS-based silicon oxide film, 20 ... low dielectric constant insulating film, 21 ... contact electrode, 25 ... side wall spacer, 26 ... groove, 31 ... polysilicon film, 32 ... silicon nitride film, 33 ... dummy gate, 34 ... oxide film, 35 ... sidewall spacer 111 ... monocrystalline CeO ₂ gate insulating film, 112 ... amorphous CeO ₂ film, 113 ... sidewall spacer 113 ₁ ... silicon oxide film, 113 ₂ ... silicon nitride film, 114 ... interlayer insulating film, 115 ... Al contact electrodes, 121 ... groove portion, 131 ... contact hole, 141 ... monocrystalline Z O ₂ gate insulating film, 115 ₁ ... titanium nitride film, 115 ₂ ... tungsten film, 151 ... amorphous ZrO ₂ film, 181 ... monocrystalline HfO ₂ gate insulating film, 182 ... HfN film, 191 ... amorphous HfO ₂ film

Claims (5)

A source and a drain formed on the semiconductor substrate;
A crystallized gate insulating film formed on the semiconductor substrate in a region between the source and the drain,
A gate electrode formed on the gate insulating film;
A semiconductor device comprising: an insulating film formed on a side surface of the gate electrode and having the same amorphous structure as a constituent material of the gate insulating film.   The gate insulating film and the insulating film are made of any one of cerium oxide, zirconium oxide, hafnium oxide, thorium oxide, yttrium oxide, calcium fluoride, tin / calcium fluoride film, and titanium barium oxide. 2. The semiconductor device according to claim 1, wherein: Forming a dummy gate in a region where a gate electrode is formed on a semiconductor substrate;
Forming a sidewall spacer on the sidewall of the dummy gate;
Forming a source / drain using the dummy gate and the sidewall spacer as a mask;
Forming an interlayer insulating film on the semiconductor substrate so as to cover the dummy gate;
Flattening the upper surface of the interlayer insulating film to expose the upper surfaces of the dummy gate and the sidewall spacer;
Removing the dummy gate and forming a groove having a side surface formed of the side wall spacer and a bottom surface formed of the semiconductor substrate;
Depositing an insulating film having an amorphous structure on the semiconductor substrate so as to cover the semiconductor substrate on the bottom of the trench;
A step of epitaxially growing an insulating film of a single crystal structure from the insulating film of the amorphous structure on the bottom surface of the groove, and forming a gate insulating film on the bottom surface of the groove;
Depositing a gate electrode material on the semiconductor substrate so as to bury the trench;
Removing the gate electrode material and the amorphous structure insulating film on the interlayer insulating film, and burying the gate electrode in the trench.   4. The method according to claim 3, wherein the insulating film having an amorphous structure on a side surface of the groove is removed by etching before depositing the gate electrode material.   5. The method according to claim 4, wherein before depositing the gate electrode material, the amorphous structure insulating film on the side surface of the groove is modified into a conductor.

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