JP2004362035A - Data input/output unit and data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To save processing executed by a control part during communication when a data input/output unit as a general purpose interface performs serial communication. <P>SOLUTION: The GPIO 1 comprises a shift clock generation circuit 11 for generating shift clocks for serial communication, and can output them via a corresponding terminal t. As output data, a plurality of bits related to serial communication can be written into a serial output data register 6 in advance of communication and can be sequentially output at the timing of the shift clocks. About input data, a serial input data register 8 capable of holding a plurality of bits related to serial communication can be provided to sequentially capture them at the timing of the shift clocks. The control part can thus perform serial communication without writing/continuously writing values into registers during communication as in a conventional scheme. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data input / output device configured as a general-purpose input / output interface, and a data processing device including such a data input / output device and communicating with an external device.
[0002]
[Prior art]
For example, a data processing device such as a DSP (Digital Signal Processor) that performs digital signal processing and a CPU (Central Processing Unit) provided in various information processing devices include a general-purpose device for performing data communication with an external device. In some cases, a general purpose input / output (GPIO) is provided in some cases.
The GPIO is configured so that each terminal can be used in a programmable manner in accordance with a communication mode (for example, the number of communication data, serial / parallel communication, or the like) with an external device. In other words, a general-purpose interface is realized by, for example, arbitrarily changing the assignment of the terminal to be used or switching the input / output of each terminal.
[0003]
FIG. 4 is a block diagram showing an example of such a GPIO configuration.
First, in the GPIO 100 shown in this figure, terminals t1, t2, and t3 are terminals for performing various data communications between a data processing device provided with the GPIO 100 and an external device. Here, a case is described in which only three terminals t1 to t3 are provided as terminals for performing communication with an external device. However, the number of these terminals depends on whether communication with the external device is possible. What is necessary is just to set arbitrarily according to the assumed number of data and the like.
[0004]
Each terminal t is provided with one input buffer 108 and one output buffer 109 as shown. An enable / disable signal from the input / output control register 104 is supplied to each of the output buffers 109-1 to 109-3 provided for each terminal t via the input / output control bus 107.
In this case, the output buffers 109-1 to 109-3 are turned on in response to, for example, the enable signal output from the input / output control register 104. Further, it is turned off in response to the disable signal.
That is, in this case, depending on the enable signal output from the input / output control register 104, the output buffer 109 is enabled, and the corresponding terminal t can be set to output. Also, depending on the disable signal, the input buffer 108 is enabled, and the corresponding terminal t can be set for input.
In this manner, in the GPIO 100, the input setting / output setting of each terminal t is switched depending on whether the enable signal or the disable signal is supplied to the output buffer 109 corresponding to each terminal t. It has been.
[0005]
The value of the enable / disable signal for setting the input / output for each terminal t as described above is stored in the input / output control register 104 by the core which performs the central control of, for example, a DSP or CPU provided with the GPIO 100. The data is input from an input / output control unit 101 shown in FIG.
In this case, a plurality of registers corresponding to the number of terminals t (the number of output buffers 109) are configured in the input / output control register 104. In addition, each of these registers is connected to a corresponding one of the output buffers 109-1 to 109-3 via the input / output control bus 107.
The core unit supplies the value as the enable / disable signal to the input / output control unit 101 and specifies the address of the input / output control register 104 to the input / output control register 104 having such a configuration. Can be written to the corresponding register in the. Then, the value held in the register is supplied to the corresponding output buffer 109 connected via the input / output control bus 107.
That is, the core unit specifies the data and the address to the input / output control unit 101 and writes the values corresponding to the respective registers in the input / output control register 104 in this manner, so that the input / output of the terminals t1 to t3 is performed. Settings can be made.
[0006]
The output data register 103 also includes a plurality of registers corresponding to each output buffer 109 in this case. Each of these registers is connected to a corresponding output buffer 109 via an output data bus 106. Then, also in this case, the core unit writes the values corresponding to these registers via the input / output control unit 101, thereby transmitting the value as the transmission data to the external device to the corresponding output buffer 109. Can be supplied.
Thus, the core unit can output a value as transmission data from a predetermined terminal t set in advance.
[0007]
Also, as the input data register 102, a number of registers corresponding to the input buffers 108-1 to 108-3 are provided. Each of the input data registers 102 is also connected to the corresponding input buffer 108 via the input data bus 105.
In this input data register 102, a value supplied from an external device to a required terminal t and obtained in a corresponding input buffer 108 is input to the corresponding register via an input data bus 105 shown.
The above-described core unit fetches input data from an external device by designating an address to the input / output control unit 101 and reading out the value held in the register in the input data register 102. Can be.
[0008]
Here, it is assumed that serial data communication is performed with, for example, an external device using the GPIO 100 having the above configuration. At this time, it is assumed that, for example, a shift clock necessary for such serial communication is transmitted at a terminal t1, output data is transmitted at a terminal t2, and input data is transmitted at a terminal t3, as shown in FIG.
In order to respond to such a condition, first, a core unit such as a DSP or a CPU including the GPIO 100 sets each terminal t using the input / output control register 104. That is, as described above, the input setting / output setting of each terminal t is determined by inputting a value to the input / output control register 104.
[0009]
After performing the input setting / output setting corresponding to each terminal t in this manner, the core unit outputs the corresponding values for the output data and the shift clock to be transmitted to the external device, respectively. 103 is output by writing. That is, in this case, the value of the output data is sequentially written bit by bit into the register corresponding to the terminal t2 in the output data register 103. As for the shift clock, a 1-bit value indicating H / L is sequentially written into the register corresponding to the terminal t1.
The values sequentially written to the output data register 103 are supplied to the corresponding output buffer 109 via the output data bus 106 as described above. Thus, in this case, the value constituting the output data is sequentially output from the terminal t2, and the value as the shift clock is sequentially output from the terminal t1. In other words, this allows the shift clock to be output from the terminal t1 and the output data to be output from the terminal t2 in accordance with the above-described conditions.
[0010]
At this time, the value of the input data input from the external device via the terminal t3 is sequentially supplied to the corresponding register in the input data register 102 via the input buffer 108-3. Then, the core unit sequentially reads out the 1-bit values sequentially held in the register corresponding to the terminal t3 by instructing the input / output control unit 101 to address.
Thus, the core unit can take in the input data supplied to the terminal t3.
[0011]
In the following patent document, a plurality of bits of data to be written by the core side at the time of communication are stored in a mask register in advance before starting communication, thereby reducing the processing load on the core unit at the time of communication. What is reduced is listed.
[Patent Document]
JP 2001-195384A
[0012]
[Problems to be solved by the invention]
As described above, when performing serial communication using the GPIO 100 according to the conventional configuration, the core unit always writes a value to the corresponding register in the output data register 103 in order to output a shift clock. I had to continue. Also, in order to output the output data continuously, it is necessary to sequentially write the value into the corresponding register one bit at a time.
In other words, the core unit in this case has to constantly write the values to the output data register 103 during communication when transmitting the shift clock and the output data to the external device.
Similarly, when reading data input from an external device, the data must always be read in order to continuously read values held in the registers in the input data register 102 without interruption. .
[0013]
For this reason, when serial communication is performed using the conventional GPIO 100 shown in FIG. 4, the core part of the data processing device is occupied by processing for performing such serial communication during communication. There has been a problem that other processing cannot be performed.
At this time, in order to realize the communication operation using the GPIO 100 as described above, a series of processing operations for causing the program of the core unit to perform the sequential reading and writing as described above must be described. As a result, there is a problem that the program code size increases.
[0014]
In addition, as described above, in the above-mentioned patent document, a plurality of bits of data to be written by the core side at the time of communication are held in a mask register in advance before the start of communication. Although the processing load on the core unit is reduced, according to this configuration, when performing serial communication, the core unit still needs to keep accessing the mask register in the shift clock cycle, and the core unit during serial communication No free time is obtained in the processing of.
[0015]
[Means for Solving the Problems]
In view of the above problems, the present invention is configured as follows as a data input / output device for performing data communication with an external device.
That is, first, there are provided first data holding means for holding output data, and second data holding means for holding serial data output by serial communication.
Then, the first data for selectively outputting the output data held in the first data holding means or the serial data held in the second data holding means in response to the supplied mode switching signal. Clock generating means for generating a communication clock for serial communication, and second selecting means for selectively outputting the supplied general-purpose clock or the communication clock in accordance with the mode switching signal. And was prepared.
[0016]
Further, in the present invention, a data processing device for performing data communication with an external device is configured as follows.
That is, first, a processor that executes predetermined data processing and controls the data communication is provided.
A first data holding unit that holds output data generated by the data processing; and a second holding unit that holds serial data output by serial communication among data generated by the data processing. And selectively outputting the output data held in the first data holding means or the serial data held in the second holding means in response to a mode switching signal supplied from the processor. The first selection means for outputting the first selection means is provided.
In addition, clock generation means for generating a communication clock for serial communication, and second selection means for selectively outputting the general-purpose clock or the communication clock supplied from the processor in response to the mode switching signal. Was provided.
[0017]
As described above, in the present invention, a communication clock (shift clock) required for serial communication is generated on the data input / output device side and output therefrom. Therefore, in this case, the processor (core unit) in the data processing device is used. In the case of (1), it is not necessary to continuously write the value to the register, for example, in order to sequentially output the value of the shift clock as in the related art.
Further, regarding the serial data output by serial communication, if the second data holding means can hold, for example, a plurality of bits of data, the processor can write the plurality of bits of data at one time. That is, in this case, the processor does not need to continuously write a value as serial data during serial communication.
As a result, as for the processor, the processing load for performing communication is reduced, and an idle time is obtained for processing during communication.
At this time, the general-purpose output data can be held in the first holding means. At this time, the first selection means is provided, so that the serial data and the general-purpose output data can be selectively stored. Can be output. Further, the provision of the second selecting means enables a communication clock for serial communication and a general-purpose clock to be selectively output.
That is, according to the present invention, a function as a general-purpose interface similar to the related art can be realized.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
FIG. 1 is a block diagram showing an example of the internal configuration of a data processing device according to an embodiment provided with an input / output device according to an embodiment of the present invention.
In FIG. 1, the data processing device of the embodiment is provided in a recording / reproducing device for various media such as a CD (Compact Disc) and a DVD (Digital Versatile Disc), and executes various audio signal processing. It has a configuration as a DSP (Digital Signal Processor).
First, in the DSP 50 as such an embodiment, the illustrated DPS core 51 performs digital audio signal processing on an input audio signal, and controls each unit via the illustrated first bus 55 and second bus 54. Performs overall control.
As shown, a program memory 52 and a data memory 53 are connected to the DSP core 51. The program memory 52 stores a program for realizing the above-described overall control. The data memory 53 is used as a work area of the DSP core 51.
[0019]
A timer 57, an ICU 58, a GPIO (General Purpose Input / output: general-purpose terminal) 1, and an audio interface 59 are connected to the DSP core 51 via a first bus 55.
The timer 57 is used for various measurements of the DSP core 51 and processing timing control.
Further, the ICU 58 controls an interrupt to the DSP core 51.
The GPIO 1 is an input / output device as an embodiment, and is a general-purpose external input / output interface configured to be able to programmably change the use of each terminal. The internal configuration of the GPIO 1 according to the embodiment will be described later with reference to FIG.
The audio interface 59 exchanges audio signals with an external device.
[0020]
The above-mentioned program memory 52 and data memory 53 are connected to a second bus 54, respectively, and a bus controller 56, an external memory interface 60, and a host interface 61 are connected to the second bus 54.
The bus controller 56 is also connected to the first bus 55, and controls communication via the first bus 55 and the second bus 54 based on the control of the DSP core 51.
The external memory interface 60 exchanges data with the external memory of the DSP 50.
The host interface 61 performs data transfer with a microcomputer provided with the DSP 50, for example, which controls the entire recording / reproducing apparatus.
[0021]
Here, in the DSP 50 configured as described above, each of the timer 57, the ICU 58, the GPIO 1, the audio interface 59, and the bus controller 56 connected to the DSP core 51 via the first bus 55 is internally provided with the DSP core. Registers that can be read from and written to 51 are provided, and these registers are memory-mapped. The DSP core 51 can control the operations of the above-described timer 57, ICU 58, GPIO1, audio interface 59, and bus controller 56 by writing values to these registers.
[0022]
Subsequently, an internal configuration of the GPIO 1 as an embodiment will be described with reference to FIG.
First, in this figure, in the GPIO 1 of the present embodiment, the illustrated input / output control unit 2, GPIO input / output data register 3, GPIO output data register 4, GPIO input / output control register 5, input data bus 14, output data bus 15 , The input / output control bus 16, the input buffers 20-1 to 20-n, and the output buffers 21-1 to 21-n, form a GPIO function unit. The GPIO function unit realizes a GPIO function similar to the conventional GPIO function.
[0023]
In the GPIO function unit, a set of an input buffer 20-1, an output buffer 21-1, an input buffer 20-2, an output buffer 21-2,... Are connected to the corresponding terminal t among the n terminals t1 to tn.
As shown, each of the input buffers 20-1 to 20-n is connected to the input data bus 14. Each of the output buffers 21-1 to 21-n is connected to the output data bus 15.
In the GPIO 1 of the present embodiment, the selector 18 and the selector 19 are disposed between the output buffer 21-1 and the output data bus 15 and between the output buffer 21-2 and the output data bus 15 as illustrated. Are respectively inserted. However, in the description of the GPIO function unit, for the sake of convenience, the description will be continued on the assumption that these selectors are not provided.
[0024]
Further, each of the output buffers 21-1 to 21-n is connected to the GPIO input / output control register 5 via an input / output control bus 16 shown in FIG. A supply path of an enable / disable signal from the GPIO input / output control register 5 to -n is formed.
Here, the output buffers 21-1 to 21-n are turned on in response to, for example, an enable signal output from the GPIO input / output control register 5. Further, it is turned off in response to the disable signal.
That is, in this case, depending on the enable signal output from the GPIO input / output control register 5, the output buffer 21 is enabled, and the corresponding terminal t is set to output. In addition, depending on the disable signal, the input buffer 20 becomes more effective, and the corresponding terminal t is set as an input.
In this way, in the GPIO function unit, the input setting / output setting of each terminal t is switched depending on whether the enable signal or the disable signal is supplied to the output buffer 21 corresponding to each terminal t. Can be
[0025]
The GPIO input / output control register 5 stores the value as the enable / disable signal for setting the input / output for each terminal t as described above from the DSP core 51 (control unit) shown in FIG. , Through the input / output control unit 2 shown in FIG.
The GPIO input / output control register 5 includes a plurality of registers corresponding to the number of terminals t (the number of output buffers 21). That is, a plurality of registers associated with each terminal t are configured. In addition, each of these registers is connected to a corresponding one of the output buffers 21-1 to 21-n via the input / output control bus 16.
The DPS core 51 supplies a value as an enable / disable signal to the input / output control unit 2 to the GPIO input / output control register 5 having such a configuration, and specifies the address of the enable / disable signal. A value can be written to a corresponding register in the register 5. Then, the value held in the register is supplied to the corresponding output buffer 21 connected via the input / output control bus 16 as described above.
In other words, the DSP core 51 as the control unit specifies the data and the address to the input / output control unit 2 in this manner, and writes the value corresponding to the required register in the input / output control register 5 to the terminal. The input / output setting of t1 to tn can be performed.
[0026]
The GPIO output data register 4 is also provided with a plurality of registers corresponding to each output buffer 21. Also in this case, each of these registers is connected to the corresponding output buffer 21 via the output data bus 15.
Then, also in this case, the DSP core 51 specifies a data and an address to the input / output control unit 2 and writes a value corresponding to a required register, thereby transmitting a value as transmission data to an external device. It can be supplied to the corresponding output buffer 21.
Thus, the DSP core 51 can output a value as transmission data from a predetermined terminal t set in advance.
[0027]
Also, as the GPIO input data register 3, a number of registers corresponding to the input buffers 20-1 to 20-n are provided. Each of the GPIO input data registers 3 is also connected to the corresponding input buffer 20 via the input data bus 14.
In the GPIO input data register 3, a value supplied from an external device to a required terminal t and obtained in a corresponding input buffer 20 is input to the corresponding register via the input data bus 14.
Then, the DSP core 51 designates an address to the input / output control unit 2 and reads out the value held in the register in the GPIO input data register 3, thereby taking in the input data from the external device. Can be.
[0028]
The input / output control unit 2 controls each of the registers shown in FIG. 1 (GPIO input data register 3, GPIO output data register 4, GPIO input / output control register 5, and serial output It reads / writes data from / to the data register 6, serial input data register 7, serial communication mode register 10, serial communication status register 12, and serial communication switching register 13).
For example, when data and address information are supplied as a write command from the DSP core 51, control is performed so that the data is written to a corresponding register indicated by the address information. Further, for example, when address information is supplied as a read command, a value held in a register indicated by the address information is read and transferred to the DSP core 51.
[0029]
In the GPIO function unit having the above configuration, as described above, the DSP core 51 as the control unit writes the value corresponding to the register in the GPIO input / output control register 5 to set the input / output of each terminal t. Is switched. Further, the terminal t to which output data is output is changed depending on which register in the GPIO output data register 4 is to be written.
Further, for input data from an external device, the value is held in the register corresponding to the terminal t to which the data is supplied, which is configured in the GPIO input data register 3 as described above. As a result, the DSP core 51 can capture this.
That is, depending on the configuration of such a GPIO function unit, it is possible to perform any communication using the terminals t1 to tn depending on the communication control operation of the DSP core 5, thereby realizing a general-purpose interface. It is.
[0030]
Here, in the GPIO 1 of the present embodiment, a serial communication unit 1a is provided as shown in the figure for the GPIO function unit having the above configuration.
The serial communication section 1a is provided for performing an operation specialized for serial communication with an external device. In this case, for example, as shown, the terminal t1 is configured to correspond to a form in which a shift clock is transmitted, the terminal t2 communicates output data, and the terminal t3 communicates input data.
[0031]
In the serial communication unit 1a, first, the input sides of the serial output data register 6, the serial communication mode register 10, the serial communication status register 12, and the serial communication switching register 13 are connected to the input / output control unit 2 described above. It is connected. Thus, the serial output data register 6, serial communication mode register 10, serial communication status register 12, and serial communication switching register 13 receive data supplied from the DSP core 51 via the input / output control unit 2. Input is enabled.
The output side of the serial input data register 8 is connected to the input / output control unit 2, so that the DSP core 51 outputs the value held in the serial input data register 8 via the input / output control unit 2. Can be taken in.
[0032]
The serial output data register 6 is configured to be able to simultaneously hold a plurality of bits of output data relating to serial communication, which is input from the DSP core 51 via the input / output control unit 2.
The output side of the serial output data register 6 is connected to the input side of the shift register 7. The output side of the shift register 7 is connected to one input terminal of the selector 19 described above.
The other input terminal of the selector 19 is connected to the output data bus 15 as shown in the figure. In this case, the selector 19 is connected to a register corresponding to the terminal t2 in the GPIO output data register 4 via the output data bus 15. I have.
The output side of the selector 19 is connected to the output buffer 21-2 (terminal t2) in this case.
[0033]
The input side of the serial input data register 8 is connected to the output side of the shift register 9.
The serial input data register 8 is configured to be able to simultaneously hold a plurality of bits of input data relating to serial communication input from the shift register 9.
In this case, the input side of the shift register 9 is connected to the input buffer 20-3 (terminal t3).
[0034]
The output of the serial communication mode register 10 is input to the shift clock generation circuit 11. The output of the serial communication status register 12 is also input to the shift clock generation circuit 11.
[0035]
The master clock used in the DSP 50 shown in FIG. 1 is input to the shift clock generation circuit 11. Then, based on the master clock input in this way and the output value from the serial communication mode register 10, a shift clock used for serial communication is generated.
The shift clock generated by the shift clock generation circuit 11 is supplied as a clock input to the shift register 7 and the shift register 9 described above.
Further, this shift clock is supplied to one input terminal of the selector 18 in this case, as shown in the figure.
[0036]
The other input terminal of the selector 18 is connected to the output data bus 15, and is connected to the register corresponding to the terminal t 1 in the GPIO output data register 4 via the output data bus 15.
The output side of the selector 18 is connected to the output buffer 21-1.
[0037]
The output of the serial communication switching register 13 is supplied to the selectors 18 and 19 via a communication switching bus 17 shown in the figure. In this case, one register is configured in the serial communication switching register 13. The value held in this register is supplied to the selectors 18 and 19 via the serial communication switching bus 17.
[0038]
FIG. 3 shows the contents of the functions of each register in the serial communication unit 1a having the above configuration.
First, the serial output data register 6 is a register for writing output data to be supplied to an external device during serial communication. As described above, the serial output data register 6 is configured to be able to simultaneously hold a plurality of bits of data relating to serial communication supplied from the DSP core 51 via the input / output control unit 2. In other words, in this case, a plurality of bits of output data to be output via the terminal t2 during serial communication can be simultaneously held. For example, in this case, it is assumed that 32-bit data can be simultaneously held as shown in the figure.
[0039]
The serial input data register 8 is a register for writing input data supplied from an external device during serial communication. The serial input data register 8 is also configured to be able to simultaneously hold a plurality of bits of data related to serial communication. That is, a plurality of bits of input data obtained at the terminal t3 during serial communication and input via the shift register 9 can be simultaneously held.
For example, it is assumed that the serial input data register 8 is configured to be capable of simultaneously holding 32 bits of data.
[0040]
The serial communication mode register 10 is a register for setting a format of serial communication performed with an external device.
The serial communication mode register 10 is used to set a bit length, an initial value (a value in a stopped state), an MSB / LSBfirst, and a frequency of a shift clock generated by the shift clock generating circuit 11 shown in FIG. Values are supplied from the DSP core 51 and are retained.
By supplying these values to the shift clock generation circuit 11, the items of the bit length of the shift clock, the initial value (the value in the stop state), the MSB / LSBfirst, and the frequency are set. It becomes.
[0041]
In this case, as shown in the figure, the bit length can be set to 1 to 32 bits. For this purpose, the serial communication mode register 10 in this case is supplied with data of a 5-bit configuration for setting such 1 to 32 bits from the DSP core 51 side.
H / L can be set as the shift clock stop state value (initial value), and 1-bit data for setting such H / L is supplied from the DSP core 51 side. For the MSB / LSBfirst, 1-bit data for setting the MSB / LSBfirst is supplied from the DSP core 51 side.
In this case, the frequency of the shift clock is set to the frequency division ratio of the master clock. For example, in this case, 1/64 to 1/8192 can be set as shown in the figure, and the DSP core 51 supplies 3-bit data for setting this.
[0042]
The serial communication status register 12 is a register for instructing the start of serial communication and monitoring the communication state.
In this case, the DSP core 51 can start serial communication by writing “1” into the serial communication status register 12, for example. Then, for example, “0” is written in response to the end of the operation for one transfer at the time of such communication.
From this, as for the value of the serial communication status register 12, "1" indicates that the data is being transferred and "0" indicates that the transfer is completed. Thus, by checking the value held in the serial communication status register 12, the communication state can be monitored.
[0043]
The serial communication switching register 13 is a register for switching between serial communication by the serial communication unit 1a and communication by the conventional GPIO function unit, and 1-bit data for performing such switching is stored in the DSP core 51 side. Supplied from
In this case, the DSP core 51 writes, for example, “0” in response to normal communication using the GPIO function unit. When serial communication is performed by the serial communication unit 1a, "1" is written.
[0044]
Here, an operation when serial communication is performed using the serial communication unit 1a having such a configuration will be described.
In this case, as described above, it is assumed that communication of the shift clock is performed at the terminal t1, output data is communicated at the terminal t2, and input data is communicated at the terminal t3.
First, in order to cope with such a condition, the DSP core 51 writes a value in a corresponding register in the GPIO input / output control register 5 by designating data and an address to the input / output control unit 2 and outputs the value to the output buffer An enable / disable signal corresponding to 21-1, 21-2, 21-3 is supplied.
That is, in this case, the enable signal is supplied to the output buffers 21-1 and 21-2, and the terminals t1 and t2 are set to output. Also, a disable signal is supplied to the output buffer 21-3, and the terminal t3 is set for input.
[0045]
In addition, the DSP core 51 writes “1” in the serial communication switching register 13 in order to switch to communication by the serial communication unit 1a.
By writing “1” to the serial communication switching register 13 in this manner, this value is input to the control terminals of the selectors 18 and 19 via the communication switching bus 17. In response to this, the selector 18 performs switching so as to input data from the shift clock generation circuit 11. In the selector 19, switching is performed so as to input data from the shift register 7 (that is, the serial output data register 6).
In other words, a state in which a shift clock can be output from the terminal t1 and output data can be output from the terminal t2 is thereby obtained.
[0046]
Further, the DSP core 51 writes values corresponding to the respective items described in FIG. 3 into the serial communication mode register 10 in order to set the format of the serial communication.
Thus, a state in which the shift clock generation circuit 11 generates the corresponding shift clock is obtained.
[0047]
Then, in the case of the present embodiment, the DSP core 51 writes a plurality of bits of output data into the serial output data register 6.
That is, in this case, as described above, the serial output data register 6 is configured to be able to hold a plurality of bits of data as output data. It is possible to write a plurality of bits of output data at a time.
The data held in the serial output data register 6 is loaded into the shift register 7 at an appropriate timing.
[0048]
Note that the order of input / output setting of each terminal t, switching of normal / serial communication, setting of shift clock, and writing of output data to the register described above may be arbitrary.
[0049]
After setting the input / output of each terminal t, switching the communication between normal / serial, setting the shift clock, and writing the output data to the register, the DSP core 51 starts the serial communication when the communication is started. The value “1” is written to the communication status register 12.
In response to this, the output of the shift clock from the shift clock generation circuit 11 is started, whereby the shift clock is output from the terminal t1 via the selector 18 and the output buffer 18.
That is, by providing the shift clock generating circuit 11, the shift clock to be supplied to the external device is automatically output via the terminal t1.
[0050]
The shift clock output from the shift clock generation circuit 11 is also supplied to clock inputs of the shift register 7 and the shift register 9.
Thus, the output data loaded is sequentially output from the shift register 7 at the timing of the shift clock. The output data sequentially output from the shift register 7 is output from the terminal t2 via the selector 19 and the output buffer 19 in this case.
That is, from this, the output data is automatically output to the external device based on the timing of the shift clock output from the shift clock generation circuit 11.
[0051]
In this case, the input data is supplied to the input data bus 14 via the terminal t3 and the input buffer 20-3. When the input data is supplied to the input data bus 14 in this manner, the input data is supplied to the shift register 9.
As described above, the shift clock from the shift clock generation circuit 11 is input to the shift register 9 at this time, so the input / output data supplied to the shift register 9 in this manner is the shift clock of this shift clock. The data is sequentially stored in the shift register 9 at the timing.
[0052]
The input data held in the shift register 9 is supplied to the serial input data register 8 at the timing when the serial communication ends.
Here, as described above, the serial input data register 8 in this case is configured to be able to hold a plurality of bits of the input data related to such serial communication. That is, the DSP core 51 in this case can take in the input data at a time after the serial input data register 8 holds the input data of a plurality of bits.
[0053]
According to the configuration of FIG. 2, the input data supplied to the input data bus 14 as described above is also input to the GPIO input data register 3. Therefore, at this time, the DSP core 51 can read from either the serial input data register 8 or the GPIO input data register 3. However, when reading from the GPIO input data register 3, the value held here is used. Must be read sequentially as in the past.
Therefore, when serial communication is performed by the serial communication unit 1a, the DSP core 51 must be programmed to read input data from the serial input data register 8.
[0054]
If it is determined that the serial communication has been completed, “0” is written to the serial communication status register 13. The writing of the value “0” is performed by the serial communication unit 1a in response to the detection that the communication has been completed. For example, the writing of such a value “0” may be performed by the shift clock generation circuit 11 according to the clock end timing.
By writing “0” to the serial communication status register 13 in this manner, for example, it indicates that one data transfer operation has been completed.
By supplying the transfer end notification to the ICU 58 at the timing when the value of the serial communication status register 13 becomes “0”, an interrupt to the DSP core 51 can be generated.
[0055]
As described above, in the GPIO 1 of the present embodiment, the shift clock generation circuit 11 is provided to generate the shift clock used for the serial communication. This eliminates the need to keep writing the value to the register in order to output the shift clock.
Further, since the serial output data register 8 holds a plurality of bits of output data and sequentially outputs the bits based on the shift clock generated by the shift clock generation circuit 11, the DSP core 51 performs serial communication. There is no need to continue writing output data to the register during the operation.
Further, in the present embodiment, since a plurality of bits of the input data obtained from the external device can be held at the same time, it is not necessary to continuously read the value from the register holding the input data.
[0056]
That is, according to the present embodiment, the DSP core 51 does not need to keep accessing the GPOI1 to perform communication of the shift clock, the output data, and the input data during the serial communication. , DSP core 51 can perform other processing even during communication.
[0057]
Also, at this time, as described above, the DSP core 51 does not need to keep writing / reading the value to / from the register during communication, so that the code size of the program for performing communication control is accordingly reduced. In other words, it can be reduced more than before.
[0058]
Further, in the present embodiment, the serial communication unit 1 a shown in FIG. 2 includes the serial communication switching register 13, the selector 18, and the selector 19. According to the value to be written, it is possible to switch between communication by the conventional GPIO function unit and communication by the serial communication unit 1a.
Since the selector 18 and the selector 19 are provided and the terminal t used for the GPIO function unit and the serial communication unit 1a is shared, the serial communication according to the present embodiment can be performed without increasing the terminal t. It is possible to do in.
[0059]
In the above-described embodiment, a case where the data processing device of the present invention is a DSP that performs digital audio signal processing provided in a recording / reproducing device corresponding to, for example, a CD, DVD, or other media will be described. However, the present invention can be suitably applied to a data processing device that performs other digital signal processing such as video signal processing.
[0060]
In the embodiment, the shift clock is transmitted at the terminal t1, the output data is communicated at the terminal t2, and the input data is communicated at the terminal t3. The configuration of the GPIO1 corresponding to this is exemplified. The shift register 7 may be added to deal with the increase in the number of output data, or the serial input data register 8 and the shift register 9 may be added to accommodate the increase in the number of input data. .
At this time, if the selector 18 (or the selector 19) is provided for all the terminals t, the terminal t with which the serial communication unit 1a performs communication can be selected.
[0061]
【The invention's effect】
As described above, according to the present invention, for example, a data input / output for performing data communication with an external device is provided in a data processing device having a processor for executing predetermined data processing and controlling the data communication. As a device, first, first data holding means for holding output data generated by the data processing, and second data holding serial data to be output by serial communication among data generated by the data processing. Data holding means.
And selectively outputting the output data held in the first data holding unit or the serial data held in the second data holding unit in response to a mode switching signal supplied from the processor. And first selecting means for performing the setting.
Then, a clock generation unit for generating a communication clock for serial communication and a second selection unit for selectively outputting the supplied general-purpose clock or the communication clock in response to the mode switching signal are provided. I have to.
[0062]
In the present invention as described above, the communication clock (shift clock) required for serial communication is generated and output on the data input / output device side, and thus the processor (core unit) in the data processing device in this case is used. In the case of (1), it is not necessary to continuously write the value to the register, for example, in order to sequentially output the value of the shift clock as in the related art.
Further, regarding the serial data output by serial communication, if the second data holding means can hold, for example, a plurality of bits of data, the processor can write the plurality of bits of data at one time. That is, in this case, the processor does not need to continuously write a value as serial data during serial communication.
[0063]
Thus, in the present invention, the processor can reduce the processing load for performing communication, and can obtain an idle time for processing during communication, and can perform other processing during communication. Become.
At this time, the description for executing the writing to the register as described above can be deleted from the communication control program, and the program code size can be made smaller than before.
[0064]
According to the present invention, general-purpose output data can be held by the first holding means. At this time, the first selection means is provided, so that the serial data and the general-purpose output data can be stored. Data can be selectively output. Further, the provision of the second selecting means enables a communication clock for serial communication and a general-purpose clock to be selectively output.
That is, according to the present invention, a function as a general-purpose interface similar to the related art can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an example of an internal configuration of a data processing device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram for describing an internal configuration example of a data input / output device as an embodiment of the present invention.
FIG. 3 is a diagram for explaining the function of each register included in the data input / output device according to the embodiment;
FIG. 4 is a circuit diagram showing a configuration of a conventional data input / output device.
[Explanation of symbols]
1 GPIO, 2 input / output control unit, 3 GPIO input data register, 4 GPIO output data register, 5 GPIO input / output control register, 6 serial output data register, 7, 9 shift register, 8 serial input data register, 10 serial communication mode Register, 11 shift clock generation circuit, 12 serial communication status register, serial communication switching register, 18, 19 selector, 50 DSP, 51 DSP core, 52 program memory, 53 data memory, 54 second bus, 55 first bus, 56 Bus controller, 57 timer, 58 ICU, 59 audio interface, 60 external memory interface, 61 host interface

Claims (6)

In a data input / output device for performing data communication with an external device,
First data holding means for holding output data;
Second data holding means for holding serial data output by serial communication;
A first selection for selectively outputting the output data held in the first data holding means or the serial data held in the second data holding means in response to the supplied mode switching signal. Means,
Clock generation means for generating a communication clock for serial communication,
Second selecting means for selectively outputting the supplied general-purpose clock or the communication clock according to the mode switching signal;
A data input / output device comprising: Further comprising a switching signal holding means for holding the supplied mode switching signal,
2. The data input / output device according to claim 1, wherein the mode switching signal held by the switching signal holding unit is supplied to the first and second selection units. A mode setting signal holding unit for holding a mode setting signal indicating the supplied serial communication condition,
2. The data input / output device according to claim 1, wherein the clock generation means generates the communication clock in accordance with the mode setting signal held in the mode setting signal holding means. A data processing device that performs data communication with an external device,
A processor that executes predetermined data processing and controls the data communication,
First data holding means for holding output data generated by the data processing;
Second holding means for holding serial data output by serial communication among data generated by the data processing;
A first output for selectively outputting the output data held in the first data holding means or the serial data held in the second holding means in response to a mode switching signal supplied from the processor; Means of selection,
Clock generation means for generating a communication clock for serial communication,
Second selecting means for selectively outputting the general-purpose clock or the communication clock supplied from the processor according to the mode switching signal;
A data processing device comprising: Further comprising a switching signal holding means for holding the mode switching signal supplied from the processor,
The data processing device according to claim 4, wherein the mode switching signal held by the switching signal holding unit is supplied to the first and second selection units. A mode setting signal holding unit that holds a mode setting signal indicating a condition of the serial communication supplied from the processor;
5. The data processing device according to claim 4, wherein the clock generation unit generates the communication clock in accordance with the mode setting signal held in the mode setting signal holding unit.

Images