JP2004349452A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently manufacture a cross point type Fe RAM. <P>SOLUTION: In this method of manufacturing semiconductor device, an auxiliary upper electrode layer 2C which becomes a dielectric capacitor forming area X is exposed on the top surface of an insulating layer 3 through a step of forming the insulating layer 3 on the whole top surface of an interlayer insulating layer 1 having a laminate, constituted by laminating a lower electrode layer 2A, a ferroelectric layer 2B, and the auxiliary upper electrode layer 2C upon another in this order, on its lower electrode forming area; a step of forming a mask pattern P used for forming a plurality of via holes V1 and V2 in the top surface of the insulating layer 3; and a step of etching back the whole surface of the insulating layer 3, under a condition where the via holes V2 formed in areas having smaller etching rates reach the top surface of the auxiliary upper electrode layer 2C after performing anisotropic dry etching on the insulating layer 3, under a condition where the via holes V1 formed in areas having larger etching rates reach the top surface of the auxiliary upper electrode layer 2C. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having a ferroelectric capacitor.
[0002]
[Prior art]
In recent years, with the high integration and miniaturization of semiconductor devices, as a semiconductor device having a ferroelectric capacitor, a plurality of semiconductor devices having a ferroelectric capacitor are provided at intersections between upper electrode layers arranged in rows and lower electrode layers arranged in columns. A cross-point type FeRAM in which ferroelectric capacitors are arranged has been attracting attention.
[0003]
FIG. 4 is a cross-sectional view showing one manufacturing process of a conventional semiconductor device. FIG. 4 is a cross-sectional view of the upper electrode layer formed in a row along the longitudinal direction.
First, as shown in FIG. 4A, a known method of manufacturing a cross-point type FeRAM is a known CVD (Chemical Vapor Deposition) method on the entire upper surface of a semiconductor substrate (not shown) on which MOS transistors and the like are formed. Is used to form the interlayer insulating layer 10.
[0004]
Next, a lower electrode layer 20A, a ferroelectric layer 20B, and an upper electrode auxiliary layer 20C are formed in this order on the upper surface of the interlayer insulating layer 10 by a known sputtering method to form a ferroelectric laminate. After that, using a known photolithography technique and etching technique, a plurality of the ferroelectric laminates are formed in rows in the lower electrode formation region.
Next, the insulating layer 30 is formed on the entire upper surface of the interlayer insulating layer 10 in which the ferroelectric laminate is formed in the lower electrode formation region by using a known CVD method.
[0005]
Next, as shown in FIG. 4B, the entire upper surface of the insulating layer 30 is etched back to expose the upper electrode auxiliary layer 20C of the ferroelectric laminate.
Next, an upper electrode layer 20D is formed on the entire upper surface of the insulating layer 30 exposing the upper electrode auxiliary layer 20C by using a known sputtering method, and then, by using a known photolithography technique and an etching technique, FIG. As shown in (c), a plurality of the upper electrode layers 20D are formed in rows in the upper electrode formation region. Here, at each intersection of the upper electrode layer 20D and the lower electrode layer 20A arranged in a lattice pattern, the upper electrode auxiliary layer 20C and the upper electrode layer 20D are connected via the connection holes H, and a plurality of strong electrodes are formed. The dielectric capacitor C can be formed.
[0006]
On the other hand, as another manufacturing method of the cross-point type FeRAM, following a general semiconductor process, after the process shown in FIG. 4A, the insulating layer 30 is formed using a known photolithography technique and etching technique. A connection hole (not shown) reaching the upper electrode auxiliary layer 20C from the upper surface of the substrate is formed, and the upper electrode auxiliary layer 20C and the upper electrode layer 20D are connected via this connection hole.
[0007]
[Problems to be solved by the invention]
However, in the above-described method of manufacturing the cross-point type FeRAM using the entire surface etch-back, the upper electrode auxiliary layer 20C is exposed by performing the entire surface etch back on the entire upper surface of the insulating layer 30. If the thickness and the overall etch back rate are not uniform, the amount of etching in the same wafer or the same chip is different, and there is a problem that deterioration of product performance is induced.
[0008]
Further, depending on the thickness of the insulating layer 30 and the overall etch back rate, the upper electrode auxiliary layer 20C may be over-etched (excessively etched). For this reason, it is necessary to restrict the conditions of the entire etch-back, and there is a problem that the work efficiency required for the entire etch-back is not good.
On the other hand, in the above-described other manufacturing method of the cross-point type FeRAM, a connection hole for connecting the upper electrode auxiliary layer 20C and the upper electrode layer 20D is formed by a ferroelectric material formed by fine processing close to the minimum processing line width. In the case of forming the capacitor on the capacitor C, it is necessary to form a fine hole near the processing limit in consideration of misalignment in the photolithography process. For this reason, there has been a problem that the photoresist process and the etching process for forming a connection hole for connecting the upper electrode auxiliary layer 20C and the upper electrode layer 20D are difficult.
[0009]
Therefore, the present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method of manufacturing a semiconductor device capable of efficiently manufacturing a cross-point type FeRAM and contributing to an improvement in product performance. I have.
[0010]
[Means for Solving the Problems]
In order to solve such a problem, a method of manufacturing a semiconductor device according to the present invention includes a method of disposing a ferroelectric capacitor at an intersection of a lower electrode layer extending in one direction and an upper electrode layer extending in another direction. Forming a lower electrode layer extending in one direction on a semiconductor substrate by laminating a lower electrode layer, a ferroelectric layer, and an upper electrode auxiliary layer in this order on the semiconductor substrate. Forming a linear pattern in a region, forming an insulating layer on the semiconductor substrate on which the laminated body is formed, and forming a mask pattern for forming a plurality of connection holes on the insulating layer. Performing the etching under the condition that at least a part of the plurality of connection holes does not reach the upper surface of the upper electrode auxiliary layer by using the mask pattern, and after performing the etching, Connection hole Te is characterized in that and a step of performing etching back the entire surface under the conditions to reach the upper surface of the upper electrode auxiliary layer.
[0011]
Further, in the method of manufacturing a semiconductor device according to the present invention, the etching is performed using a mask pattern in which the connection hole is formed with a hole diameter larger than the line width of the upper electrode auxiliary layer. It is.
Further, in the method of manufacturing a semiconductor device according to the present invention, the etching is terminated when a connection hole formed in a region having a high etching rate reaches the upper surface of the upper electrode auxiliary layer. It is.
[0012]
Further, in the method of manufacturing a semiconductor device according to the present invention, the etching is terminated when a connection hole formed in a region where the insulating layer has a small thickness reaches the upper surface of the upper electrode auxiliary layer. It is assumed that.
Further, in the method for manufacturing a semiconductor device according to the present invention, the etch back on the entire surface is performed under a condition that a corner of the connection hole can be formed.
[0013]
The conditions under which the corners of the connection holes can be formed are not particularly limited. For example, dry etching is performed by using a gas having a high composition ratio of an inert gas such as Ar and setting the gas pressure to a high value, for example. This can be realized by performing etching.
Further, in the method for manufacturing a semiconductor device according to the present invention, the overall etch back is performed under a condition that the bottom surface of the connection hole is not below the lower surface of the upper electrode auxiliary layer. .
[0014]
Further, in the method for manufacturing a semiconductor device according to the present invention, the entire surface etch-back is performed under a condition that the bottom surface of the connection hole formed by the entire etch back has a smaller hole diameter than the connection hole formed by the etching. It is characterized by performing.
Further, in the method of manufacturing a semiconductor device according to the present invention, the method further includes a step of forming an upper electrode layer extending in the other direction on the insulating layer after the entire surface is etched back. Things.
[0015]
As described above, according to the method of manufacturing a semiconductor device according to the present invention, the etching process is completed at a stage where all or at least a part of the plurality of connection holes does not reach the upper surface of the upper electrode auxiliary layer, and the mask pattern is removed. By switching to the whole back etch back, over-etching to the upper electrode auxiliary layer can be suppressed. Therefore, it is possible to improve the work efficiency required for exposing the upper electrode auxiliary layer and to improve the product performance of the semiconductor device.
[0016]
Further, since the entire insulating layer is etched by performing the etch back on the entire surface, the aspect ratio of the connection hole can be reduced.
Furthermore, according to the method for manufacturing a semiconductor device of the present invention, even if etching is performed using a mask pattern in which the connection hole is formed with a hole diameter larger than the line width of the upper electrode auxiliary layer, the entire surface is etched back. At this time, the dimension can be converted into a connection hole smaller than the diameter of the connection hole formed by etching. Therefore, even if the capacitor size is reduced due to recent high integration and miniaturization of semiconductor devices, the connection between the upper electrode layer auxiliary layer and the upper electrode layer can be easily performed without performing a difficult photolithography process and an etching process. And it can be performed reliably.
[0017]
Furthermore, according to the method of manufacturing a semiconductor device according to the present invention, the condition that the hole diameter of the bottom surface of the connection hole formed by etch back over the entire surface is smaller than the hole diameter of the connection hole formed by etching, specifically, the connection hole By performing etch back on the entire surface under the condition that the etching of the central portion is faster than the corner portion of the bottom surface, the coverage (coverage) of the upper electrode layer formed on the entire upper surface of the insulating layer where the upper electrode auxiliary layer is exposed is improved. Therefore, the product performance of the semiconductor device can be improved.
[0018]
Similarly, by performing etch back on the entire surface under the condition that the corner of the connection hole can be formed, etching proceeds at the center of the bottom of the connection hole, and the etching rate decreases as approaching the outer periphery of the bottom of the connection hole. It can be formed in a size smaller than the diameter of the connection hole. Therefore, even in the case of forming a ferroelectric capacitor formed by microfabrication close to the minimum processing line width, it is not necessary to perform a photolithography process and an etching process with high difficulty, thereby improving the manufacturing efficiency of a semiconductor device. It is possible to do.
[0019]
Further, according to the method of manufacturing a semiconductor device according to the present invention, the entire surface is etched back under the condition that the bottom surface of the connection hole does not go below the lower surface of the upper electrode auxiliary layer, thereby increasing the integration density of the semiconductor device in recent years. Also, with miniaturization, even when the capacitor size is smaller than the connection hole size, the connection between the upper electrode auxiliary layer and the upper electrode layer can be performed more reliably.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a plan view showing a configuration example of a semiconductor device according to the present invention. 2A and 2B show the semiconductor device shown in FIG. 1, wherein FIG. 2A is a cross-sectional view taken along line AA of FIG. 1, and FIG. 2B is a cross-sectional view taken along line BB of FIG.
[0021]
As shown in FIG. 1, the semiconductor device according to the present embodiment includes, on a semiconductor substrate (not shown), intersections of lower electrode layers 2A formed in columns and upper electrode layers 2D formed in rows. A cross-point type FeRAM including a plurality of ferroelectric capacitors C arranged in a section and a MOS transistor (not shown) connected to a part of the ferroelectric capacitor C is configured.
[0022]
As shown in FIG. 2, the ferroelectric capacitor C includes a lower electrode layer 2A, a ferroelectric layer 2B, and an upper electrode auxiliary layer formed on an upper surface of an interlayer insulating layer 1 formed on a semiconductor substrate (not shown). The layer 2C and the upper electrode layer 2D are stacked in this order, and the upper electrode auxiliary layer 2C and the upper electrode layer 2D are connected only in the ferroelectric capacitor forming region X.
[0023]
As shown in FIG. 2A, an insulating layer 3 is formed on the lower surface of the upper electrode layer 2D formed in a row except for the ferroelectric capacitor forming region X, as shown in FIG. On the other hand, among the lower electrode layers 2A formed in a row, a ferroelectric layer 2B is formed on the upper surface other than the ferroelectric capacitor formation region X, as shown in FIG. 2B.
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.
[0024]
FIG. 3 is a cross-sectional view showing one manufacturing process of the semiconductor device according to the present invention. FIG. 3 is a cross-sectional view of the semiconductor device shown in FIG. 1 as viewed from a cross-sectional direction along the line AA in each manufacturing process.
In the method of manufacturing a semiconductor device according to the present embodiment, first, an interlayer insulating layer 1 made of a silicon oxide film or the like is formed to a thickness of 1500 nm over the entire upper surface of a semiconductor substrate on which a MOS transistor is formed in advance using a known CVD method. It is formed so that it becomes.
[0025]
Next, as shown in FIG. 3A, a lower electrode layer 2A made of a metal film such as Pt and an SBT (SrBi ₂ Ta ₂ O) are formed on the entire upper surface of the interlayer insulating layer 1 by a known sputtering method or the like. ₉₎ or _{PZT (Pb (Zr X Ti 1} -X) O 3) ferroelectric ferroelectric layer 2B made of film, the upper electrode auxiliary layer 2C and the thickness of each 200nm made of a metal film such as Pt, such as Films are formed in this order so that
[0026]
Next, the lower electrode layer 2A, the ferroelectric layer 2B, and the upper electrode auxiliary layer 2C are collectively etched using a known photolithography technique and an etching technique, and the lower electrode layer 2A, the ferroelectric layer 2B, and A plurality of laminated bodies for a ferroelectric capacitor composed of three layers of the upper electrode auxiliary layer 2C are formed in a row in the lower electrode layer forming region.
Next, an insulating layer 3 made of a silicon oxide film or the like is formed to a thickness of 1000 nm on the entire upper surface of the interlayer insulating layer 1 in which the ferroelectric capacitor laminate is formed in the lower electrode layer forming region by a known CVD method. It forms so that it may become. Then, a mask pattern P is formed on the upper surface of the insulating layer 3 so as to expose the upper portion of the upper electrode auxiliary layer 2C and cover the other portions.
[0027]
Then, as shown in FIG. 3B, the via hole V1 formed in the region of the insulating layer 3 having a high etching rate reaches the upper surface of the upper electrode auxiliary layer 2C by using a known anisotropic dry etching. Etching is performed with a CF-based (fluorocarbon) gas so that the etching is completed at the point of time.
Here, in the insulating layer 3, the upper electrode auxiliary layer 2C is exposed on the bottom surface of the via hole V1 formed in the region having a high etching rate, and the via hole V2 formed in the region having a low etching rate is formed on the bottom surface. The interlayer insulating layer 1 is exposed.
[0028]
Next, after removing the mask pattern P formed on the upper surface of the insulating layer 3 by a known technique, as shown in FIG. 3C, the interlayer is formed by etching in a previous process using a known isotropic wet etching. The following conditions are set so that the portion where the insulating layer 1 remains, that is, the via hole V2 formed in the region of the interlayer insulating layer 1 where the etching rate is low reaches the upper surface of the upper electrode auxiliary layer 2C. Perform the whole etch back with. At this time, it is particularly preferable to adjust the overall etch-back condition so that the bottom surface of the via hole V1 formed in the region having a high etching rate does not go below the lower surface of the upper electrode auxiliary layer 2C. In addition, at the time of this whole etch back, the etching rate tends to be higher at the center of the bottom of the via holes V1 and V2 than at the corner, and the area of the bottom of the via holes V1 and V2 is reduced as shown in FIG. Will be. Further, it is preferable to terminate the entire etch-back when the corners of the via holes V1 and V2 are rounded.
[0029]
As a specific etching method, the cleaning is performed by spin cleaning using a 1:20 diluted hydrofluoric acid or a batch type wet etching, but other isotropic etching can also be performed.
Here, the upper surface of the upper electrode auxiliary layer 2C is exposed in all the via holes V1 and V2 regardless of the etching rate of the insulating layer 3.
[0030]
Next, as shown in FIG. 3 (e), the upper electrode made of Pt is formed on the entire upper surface of the insulating layer 3 where the upper electrode auxiliary layer 2C to be the ferroelectric capacitor forming region X is exposed by using a known sputtering method. The layer 2D is formed. Then, by using a known photolithography technique and etching, the upper surface of the upper electrode layer 2D formed in a region other than the ferroelectric capacitor formation region X is removed to a part of the film thickness of the ferroelectric upper electrode layer 2D, whereby the ferroelectric material is removed. The upper electrode auxiliary layer 2C is formed only in the dielectric capacitor formation region X, and the upper electrode layer 2D is formed in rows in the upper electrode layer formation region including the upper surface of the upper electrode auxiliary layer 2C.
[0031]
Here, the upper electrode layer 2D and the lower electrode layer 2A are arranged in a lattice pattern, and the upper electrode auxiliary layer 2C formed only at each intersection and the upper electrode layer 2D are connected. Is completed.
Then, the upper electrode layer 2D and the lower electrode layer 2A are connected to the MOS transistor to form a peripheral circuit, thereby completing a semiconductor device functioning as a cross-point type FeRAM. In this cross-point type FeRAM, by selecting the upper electrode layer 2D and the lower electrode layer 2A via the peripheral circuit, it is possible to perform writing / reading of the ferroelectric capacitor C disposed at the intersection. Become.
[0032]
As described above, according to the method for manufacturing a semiconductor device of the present embodiment, etching is performed under the condition that the via hole V1 formed in the insulating layer 3 in the region having a high etching rate reaches the upper surface of the upper electrode auxiliary layer 2C. After that, the entire surface is etched back under the condition that the via hole V2 formed in the region of the insulating layer 3 having a small etching rate reaches the upper surface of the upper electrode auxiliary layer 2C, so that the via hole V2 is formed in the same semiconductor substrate. The amount of etching can be made uniform, and over-etching of the upper electrode auxiliary layer 2C can be suppressed. Therefore, the work efficiency of exposing the upper electrode auxiliary layer 2C from the upper surface of the insulating layer 3 can be improved, and the product performance of the semiconductor device can be improved.
[0033]
Further, according to the method of manufacturing the semiconductor device according to the present embodiment, the entire surface is etched back under the condition that the corners of the via holes V1 and V2 are rounded at the time of etching back the entire surface. The coverage with the upper electrode layer 2C is improved, and the upper electrode auxiliary layer 2C and the upper electrode layer 2C can be reliably connected.
Further, by etching the center of the bottom of the via holes V1 and V2 faster than the corners of the bottom of the via holes, the diameters of the via holes V1 and V2 after the entire etch back are smaller than the diameters of the via holes V1 and V2 formed by etching. Become. For this reason, with the recent increase in the degree of integration and miniaturization of the semiconductor device, the capacitor size becomes smaller than the opening diameter of the via holes V1 and V2. Even so, the upper electrode auxiliary layer 2C and the upper electrode layer 2A can be easily and reliably connected without performing a difficult photolithography step and an etching step.
[0034]
Further, according to the method of manufacturing the semiconductor device according to the present embodiment, the entire surface is etched back under the condition that the bottom surfaces of the via holes V1 and V2 do not reach below the lower surface of the upper electrode auxiliary layer 2C. With the high integration and miniaturization of the semiconductor device, the capacitor size becomes smaller than the opening diameter of the via holes V1 and V2, and even if the bottom surfaces of the via holes V1 and V2 do not ride over the ferroelectric capacitor C, The connection between the electrode auxiliary layer 2C and the upper electrode layer 2D can be performed more reliably.
[0035]
In the present embodiment, the etching condition and the overall etch-back condition are determined in consideration of the in-plane distribution of the etching rate. However, all or at least a part of the plurality of via holes V1 and V2 are formed by the upper electrode. The method is not limited to this, as long as etching is performed under conditions that do not reach the upper surface of the auxiliary layer 2C, and then the entire surface is etched back until all of the plurality of via holes V1 and V2 reach the upper surface of the upper electrode auxiliary layer 2C. For example, the etching condition and the overall etch-back condition may be determined in consideration of the in-plane film thickness of the insulating layer 3, or both the in-plane film thickness of the insulating layer 3 and the in-plane distribution of the etching rate. May be determined in consideration of the above.
[0036]
In the present embodiment, when the upper electrode layer 2D is etched, the ferroelectric layer 2B is left on the upper surface of the lower electrode layer 2A other than the ferroelectric capacitor formation region X. The present invention is not limited to this as long as the upper electrode layer 2D other than the capacitor forming region X is removed. For example, by etching from the upper surface of the upper electrode layer 2D formed outside the ferroelectric capacitor formation region X to the upper surface of the lower electrode layer 2A, the lower electrode layer 2A other than the ferroelectric capacitor formation region X is etched. The lower electrode layer 2A may be exposed on the upper surface.
[0037]
Furthermore, in the present embodiment, the case where the MOS transistor is connected to the ferroelectric capacitor C has been described. However, the present invention is not limited to this and any other semiconductor device can be connected to the ferroelectric capacitor C. . Specifically, other MIS (Metal-Insulator-Semiconductor) transistors such as MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) transistors and the like can be given.
[Brief description of the drawings]
FIG. 1 is a plan view illustrating a configuration example of a semiconductor device according to an embodiment.
FIGS. 2A and 2B show the semiconductor device of FIG. 1, in which FIG. 2A is a cross-sectional view taken along line AA of FIG. 1, and FIG. 2B is a cross-sectional view taken along line BB of FIG.
FIG. 3 is a cross-sectional view showing one manufacturing step of the semiconductor device in the embodiment.
FIG. 4 is a cross-sectional view showing one manufacturing step of a conventional semiconductor device.
[Description of Signs] 1, 10 ... Interlayer insulating layers. 2A, 20A: Lower electrode layer. 2B, 20B: Ferroelectric layer. 2C, 20C: Upper electrode auxiliary layer. 2D, 20D: Upper electrode layer. 3, 30 ... an insulating layer. C: Ferroelectric capacitor. P: Mask pattern. V1, V2: Via holes. X: ferroelectric capacitor formation region

Claims (8)

In a method of manufacturing a semiconductor device, a ferroelectric capacitor is arranged at an intersection of a lower electrode layer extending in one direction and an upper electrode layer extending in another direction.
Forming a laminated body in which a lower electrode layer, a ferroelectric layer, and an upper electrode auxiliary layer are laminated in this order on a semiconductor substrate, in a linear manner in a lower electrode layer forming region extending in the one direction;
Forming an insulating layer on the semiconductor substrate on which the laminate is formed;
Forming a mask pattern for forming a plurality of connection holes on the insulating layer;
Using the mask pattern, performing a step of etching under conditions that at least a part of the plurality of connection holes does not reach the upper surface of the upper electrode auxiliary layer,
After performing the etching, all of the plurality of connection holes, a step of performing an entire etch-back under the condition of reaching the upper surface of the upper electrode auxiliary layer,
A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the etching is performed using a mask pattern in which the connection hole has a diameter larger than the line width of the upper electrode auxiliary layer. 3. 3. The method according to claim 1, wherein the etching is terminated when a connection hole formed in a region having a high etching rate reaches an upper surface of the upper electrode auxiliary layer. 4. 3. The semiconductor device according to claim 1, wherein the etching is completed when a connection hole formed in a region where the insulating layer has a small thickness reaches the upper surface of the upper electrode auxiliary layer. 4. Production method. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the entire surface is etched back under a condition that a corner of the connection hole can be formed. 6. 6. The semiconductor device according to claim 1, wherein the entire surface is etched back under a condition that a bottom surface of the connection hole does not go below a lower surface of the upper electrode auxiliary layer. 7. Production method. 7. The method according to claim 1, wherein the etch back is performed under the condition that the bottom surface of the connection hole formed by the etch back has a smaller hole diameter than the connection hole formed by the etching. 9. The method for manufacturing a semiconductor device according to claim 1. The method according to claim 1, further comprising: forming an upper electrode layer extending in the other direction on the insulating layer after the entire surface is etched back. A method for manufacturing a semiconductor device.

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