JP2004336624A - Circuit, method and program for processing signal, and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit that has a wide pull-in range even though a phase noise characteristic is satisfactory. <P>SOLUTION: This PLL circuit is provided with a voltage controlled oscillator (VCO) 10, a digital phase comparator 12 for outputting a signal that corresponds to a phase difference between an output signal and a reference signal, a digital loop filter 14 for making a low frequency component of an output of the digital phase comparator 12 pass through, a multiplier 22 for outputting a signal that corresponds to the phase difference between the output signal and the reference signal and whose allowable range for a phase difference is narrower than that of a first phase comparing means, an analog loop filter 24 for making a low frequency component of an output of the multiplier 22 pass through, a limiter circuit 26 for limiting the voltage of an output outputted by the analog loop filter 24 on the basis of the voltage of a signal outputted by the digital loop filter 14, and a switch 30 for switching a signal given to the voltage controlled oscillator 10 to either a signal outputted by the first low pass filter or a signal outputted by the second low pass filter. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to phase synchronization in a PLL (Phase Locked Loop) circuit.
[0002]
[Prior art]
Conventionally, a PLL (Phase Locked Loop) circuit has been used for a frequency multiplier or the like. The PLL circuit has a phase comparator. The phase comparator may use an analog multiplier or a digital circuit, that is, a logic circuit.
[0003]
Generally, when an analog multiplier is used for the phase comparator, the phase noise characteristics are good. However, the pull-in range (capture range) is narrow. On the other hand, when a logic circuit is used for the phase comparator, the pull-in range can be widened. However, the phase noise characteristic is worse than when an analog multiplier is used.
[0004]
Therefore, as disclosed in Patent Document 1, a PLL circuit that uses an analog multiplier and a logic circuit together in a phase comparator has been proposed. That is, the phase is synchronized using a digital phase comparator having a wide pull-in range, and the frequency of the voltage-controlled oscillation circuit is locked. After that, an analog phase comparator having a good phase noise characteristic is used.
[0005]
[Patent Document 1]
JP 2002-152039 A (abstract)
[Problems to be solved by the invention]
However, when the voltage-frequency sensitivity of the voltage-controlled oscillation circuit is high, when the used phase comparator is switched from the digital phase comparator to the analog phase comparator, an error voltage due to a phase difference is generated, and the voltage control type The difference between the output frequency of the oscillation circuit and the reference frequency to be locked may greatly deviate from the pull-in range of the analog phase comparator.
[0006]
Therefore, an object of the present invention is to provide a PLL circuit which has a good phase noise characteristic and a wide pull-in range.
[0007]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a voltage controlled oscillator for controlling a frequency of an output signal according to a voltage of an input signal, and a first signal for outputting a signal corresponding to a phase difference between the output signal and a reference signal. A phase comparison unit, a first low-pass filter that allows a low-frequency component of an output of the first phase comparison unit to pass, and a signal corresponding to a phase difference between the output signal and the reference signal, and an allowable range in which the phase difference can be allowed is A second phase comparison means narrower than the first phase comparison means, a second low-pass filter that passes a low-frequency component of an output of the second phase comparison means, and a voltage of a signal output from the second low-pass filter, Voltage limiting means for limiting based on the voltage of the signal output by the filter; and a signal applied to the voltage controlled oscillation means, one of a signal output from the first low-pass filter and a signal output from the second low-pass filter. Configured with a switching means for switching.
[0008]
According to the invention configured as described above, the voltage controlled oscillator controls the frequency of the output signal according to the voltage of the input signal. The first phase comparing means outputs a signal corresponding to a phase difference between the output signal and the reference signal. The first low-pass filter passes a low-frequency component of the output of the first phase comparison means. The second phase comparison means outputs a signal corresponding to the phase difference between the output signal and the reference signal, and the allowable range in which the phase difference can be allowed is smaller than that of the first phase comparison means. The second low-pass filter passes a low-frequency component of the output of the second phase comparison means. The voltage limiting means limits the voltage of the signal output from the second low-pass filter based on the voltage of the signal output from the first low-pass filter. The switching means switches a signal supplied to the voltage controlled oscillator to one of a signal output from the first low-pass filter and a signal output from the second low-pass filter.
[0009]
The invention according to claim 2 is the invention according to claim 1, wherein the first phase comparing means is configured to be constituted by a digital circuit.
[0010]
A third aspect of the present invention is the invention according to the first aspect, wherein the second phase comparing means is constituted by an analog circuit.
[0011]
According to a fourth aspect of the present invention, in the first aspect of the present invention, the voltage limiting means changes the voltage of the signal output from the second low-pass filter to the voltage of the signal output from the first low-pass filter. It is configured to limit the value added with the offset as the maximum value or the minimum value.
[0012]
According to a fifth aspect of the present invention, in the first aspect of the invention, the voltage limiting means converts the voltage of the signal output from the second low-pass filter to the voltage of the signal output from the first low-pass filter. It is configured to limit the value to be equal to or less than the value obtained by adding the first offset and to be equal to or more than the value obtained by adding the predetermined second offset.
[0013]
According to a sixth aspect of the present invention, in the first aspect of the present invention, the switching means supplies a signal output from the first low-pass filter to the voltage controlled oscillation means, and a phase difference between the output signal and the reference signal is provided. After falling within the predetermined range, the signal supplied to the voltage controlled oscillator is switched to the signal output from the second low-pass filter.
[0014]
According to a seventh aspect of the present invention, there is provided a voltage controlled oscillator for controlling a frequency of an output signal in accordance with a voltage of an input signal, and a first signal for outputting a signal corresponding to a phase difference between the output signal and a reference signal. A phase comparison unit, a first low-pass filter that allows a low-frequency component of an output of the first phase comparison unit to pass, and a signal corresponding to a phase difference between the output signal and the reference signal, and an allowable range in which the phase difference can be allowed is A second phase comparison means narrower than the first phase comparison means, a second low-pass filter that passes a low-frequency component of an output of the second phase comparison means, and a voltage of a signal output from the second low-pass filter, Voltage limiting means for limiting based on the voltage of the signal output by the filter; and a signal applied to the voltage controlled oscillation means, one of a signal output from the first low-pass filter and a signal output from the second low-pass filter. A signal processing method in a signal processing circuit comprising: a switching means for switching, wherein a step of providing a signal output from the first low-pass filter to the voltage controlled oscillating means, wherein a phase difference between the output signal and the reference signal is within a predetermined range. Switching the signal supplied to the voltage-controlled oscillating means to the signal output from the second low-pass filter.
[0015]
The invention according to claim 8 is a voltage controlled oscillator for controlling the frequency of the output signal in accordance with the voltage of the input signal, and a first signal for outputting a signal in accordance with the phase difference between the output signal and the reference signal. A phase comparison unit, a first low-pass filter that allows a low-frequency component of an output of the first phase comparison unit to pass, and a signal corresponding to a phase difference between the output signal and the reference signal, and an allowable range in which the phase difference can be allowed is A second phase comparison means narrower than the first phase comparison means, a second low-pass filter that passes a low-frequency component of an output of the second phase comparison means, and a voltage of a signal output from the second low-pass filter, Voltage limiting means for limiting based on the voltage of the signal output by the filter; and a signal applied to the voltage controlled oscillation means, one of a signal output from the first low-pass filter and a signal output from the second low-pass filter. A program for causing a computer to execute signal processing in a signal processing circuit including a switching unit, and a process of giving a signal output from the first low-pass filter to the voltage control oscillation unit, and A program for causing a computer to execute a process of switching a signal supplied to the voltage controlled oscillator to a signal output from the second low-pass filter after the phase difference falls within a predetermined range.
[0016]
According to a ninth aspect of the present invention, there is provided a voltage controlled oscillator for controlling a frequency of an output signal in accordance with a voltage of an input signal, and a first signal for outputting a signal corresponding to a phase difference between the output signal and a reference signal. A phase comparison unit, a first low-pass filter that allows a low-frequency component of an output of the first phase comparison unit to pass, and a signal corresponding to a phase difference between the output signal and the reference signal, and an allowable range in which the phase difference can be allowed is A second phase comparison means narrower than the first phase comparison means, a second low-pass filter that passes a low-frequency component of an output of the second phase comparison means, and a voltage of a signal output from the second low-pass filter, Voltage limiting means for limiting based on the voltage of the signal output by the filter; and a signal applied to the voltage controlled oscillation means, one of a signal output from the first low-pass filter and a signal output from the second low-pass filter. A computer-readable recording medium storing a program for causing a computer to execute signal processing in a signal processing circuit including a switching unit for switching, and providing a signal output from a first low-pass filter to a voltage-controlled oscillating unit. A program for causing a computer to execute a process and a process of switching a signal given to a voltage controlled oscillator to a signal output from a second low-pass filter after a phase difference between an output signal and a reference signal falls within a predetermined range. Is a recording medium that can be read by a computer that has recorded therein.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0018]
FIG. 1 is a block diagram illustrating a configuration of a PLL circuit 1 according to an embodiment of the present invention. The PLL circuit 1 includes a voltage controlled oscillator (VCO) 10, a digital phase comparator (first phase comparison unit) 12, a digital loop filter (first low-pass filter) 14, a multiplier (second phase comparison unit) 22, an analog Loop filter (second low-pass filter) 24, a limiter circuit (voltage limiting unit) 26, and a switch (switching unit) 30.
[0019]
A voltage controlled oscillator (VCO: Voltage Controlled Oscillator) 10 controls the frequency of the output signal according to the voltage of the input signal. The input terminal of the voltage controlled oscillator 10 is connected to the terminal 30c of the switch 30.
[0020]
The digital phase comparator (first phase comparing means) 12 outputs a signal corresponding to the phase difference between the output signal and the reference signal. The digital phase comparator 12 is configured by a digital circuit such as a logic circuit. For this reason, the pull-in range (capture range) is wider than that of the multiplier 22, but the phase noise characteristics are poor. When the phase difference between the output signal and the reference signal falls within a predetermined range, the digital phase comparator 12 supplies a lock detection signal to the limiter circuit 26 and the switch 30.
[0021]
The digital loop filter (first low-pass filter) 14 allows the low-frequency component of the output of the digital phase comparator 12 to pass. The output voltage of the digital loop filter 14 is called D-LOCK.
[0022]
FIG. 2 is a circuit diagram showing a configuration of the digital loop filter 14. The digital loop filter 14 has a resistor 14a, a differential amplifier 14b, a resistor 14c, and a capacitance element 14d. The resistor 14a receives the output of the digital phase comparator 12. The difference amplifier 14b receives the output of the digital phase comparator 12 via one resistor at its one input terminal. Note that the other input terminal of the difference amplifier 14b is grounded. The difference amplifier 14 b amplifies a signal obtained by subtracting the potential of the signal received at one input terminal from the potential of the signal received at the other input terminal, and outputs the amplified signal to the switch 30. The resistor 14c has one end connected between the resistor 14a and the differential amplifier 14b, and the other end connected to the capacitance element 14d. The capacitance element 14d has one end connected to the resistor 14c and the other end connected to the output side of the difference amplifier 14b.
[0023]
The multiplier (second phase comparing means) 22 is a multiplier, and outputs a signal corresponding to a phase difference between the output signal and the reference signal. However, the allowable range in which the phase difference can be allowed, that is, the pull-in range is smaller than that of the digital phase comparator 12. However, the phase noise characteristics are good.
[0024]
The analog loop filter (second low-pass filter) 24 allows the low-frequency component of the output of the multiplier 22 to pass. The output voltage of the analog loop filter 24 is called A-LOCK.
[0025]
FIG. 3 is a circuit diagram showing a configuration of the analog loop filter 24. The analog loop filter 24 has a resistor 24a, a differential amplifier 24b, a resistor 24c, and a capacitance element 24d. The resistor 24a receives the output of the multiplier 22. The difference amplifier 24b receives the output of the multiplier 22 via one end of the input terminal via the resistor 24a. The other input terminal of the difference amplifier 24b is grounded. The difference amplifier 24 b amplifies a signal obtained by subtracting the potential of the signal received at one input terminal from the potential of the signal received at the other input terminal, and outputs the amplified signal to the switch 30. The resistor 24c has one end connected to one input terminal of the differential amplifier 24b and the other end connected to a capacitance element 24d. Note that the resistor 24c receives a limit signal output from the limiter circuit 26 from one end thereof. The capacitance element 24d has one end connected to the resistor 24c and the other end connected to the output side of the difference amplifier 24b.
[0026]
The limiter circuit (voltage limiting means) 26 limits the voltage A-LOCK of the signal output from the analog loop filter 24 based on the voltage D-LOCK of the signal output from the digital loop filter 14. That is, D-LOCK + second offset voltage (referred to as BSH) ≦ A-LOCK ≦ D-LOCK + first offset voltage (referred to as ASH).
[0027]
FIG. 4 is a circuit diagram showing a configuration of the limiter circuit 26. The limiter circuit 26 has an S / H (sample / hold) section 26a, adders 26b and 26c, differential amplifiers 26d and 26e, switches 26f and g, and resistors 26h, j, and k.
[0028]
The S / H (sample / hold) unit 26a receives the D-LOCK during the sample period and outputs the D-LOCK during the hold period. Switching between the sample period and the hold period is performed by an S / H control signal applied to the S / H unit 26a. With the S / H control signal, the hold period is started from the time when the lock detection signal is received.
[0029]
The adder 26b outputs ASH obtained by adding a first offset voltage to D-LOCK output from the S / H unit 26a. The adder 26c outputs a BSH obtained by adding a second offset voltage to D-LOCK output from the S / H unit 26a.
[0030]
The difference amplifier 26d amplifies and outputs a voltage obtained by subtracting A-LOCK from the output voltage of the adder 26b. The difference amplifier 26e amplifies and outputs a voltage obtained by subtracting the output voltage of the adder 26c from A-LOCK.
[0031]
The switch 26f receives the output of the adder 26b and turns on when the output voltage of the adder 26b is negative. When the switch 26f is turned on, the switch 26f supplies a signal of a positive voltage + V1 to the analog loop filter 24 as a limit signal via the resistors 26h and 26k.
[0032]
The switch 26g receives the output of the adder 26c, and turns on when the output voltage of the adder 26c is negative. When the switch 26f is turned on, the switch 26f supplies a signal of the negative voltage −V2 to the analog loop filter 24 as a limit signal via the resistors 26j and 26k.
[0033]
The resistor 26h is a resistor that receives a signal of the positive voltage + V1. The resistor 26j is a resistor that receives a signal of the negative voltage −V2. The resistor 26k is a resistor that receives the signal of the positive voltage + V1 and the signal of the negative voltage −V2 and gives the signal to the analog loop filter 24.
[0034]
The switch (switching means) 30 has terminals 30a, b, and c. The terminal 30a is connected to the output of the analog loop filter 24, the terminal 30b is connected to the output of the digital loop filter 14, and the terminal 30c is connected to the input terminal of the voltage controlled oscillator 10. The switch 30 switches a terminal connected to the terminal 30c to one of the terminal 30a and the terminal 30b.
[0035]
The switch 30 has a terminal connected to the terminal 30c as a terminal 30b. That is, the output of the digital loop filter 14 is given to the voltage controlled oscillator 10. Then, a lock detection signal is received from the digital phase comparator 12. At that time, a terminal connected to the terminal 30c is referred to as a terminal 30a. That is, the output of the analog loop filter 24 is given to the voltage controlled oscillator 10.
[0036]
Next, the operation of the embodiment of the present invention will be described with reference to the timing chart of FIG.
[0037]
First, in the switch 30, a terminal connected to the terminal 30c is a terminal 30b. That is, the output of the digital loop filter 14 is given to the voltage controlled oscillator 10. The pull-in range (capture range) of the digital phase comparator 12 is wide. Therefore, even if the frequency of the output signal of the voltage controlled oscillator 10 is slightly different from the frequency of the reference signal, the frequency of the output signal of the voltage controlled oscillator 10 is eventually drawn to the frequency of the reference signal.
[0038]
At this time (see FIG. 5), since the lock detection signal has not yet been output, the switch 30 connects the terminals 30c and 30b. Then, the S / H control signal becomes High, and the S / H section 26a is in the sampling period. That is, the S / H unit 26a receives the D-LOCK.
[0039]
Eventually, in the digital phase comparator 12, when the phase difference between the output signal and the reference signal falls within a predetermined range, a lock detection signal is given to the limiter circuit 26 and the switch 30.
[0040]
Then, the switch 30 uses the terminal connected to the terminal 30c as the terminal 30a. That is, the output of the analog loop filter 24 is given to the voltage controlled oscillator 10. The multiplier 22 has a narrow pull-in range (capture range). However, since the output frequency of the voltage controlled oscillator 10 has already approached the reference frequency to some extent by using the digital phase comparator 12, the frequency of the output signal of the voltage controlled oscillator 10 is It can be drawn in with high accuracy. This is because the multiplier 22 has good phase noise characteristics.
[0041]
When the limiter circuit 26 receives the lock detection signal, the S / H control signal goes low, and the S / H section 26a is in the hold period. That is, the S / H unit 26a outputs D-LOCK. Then, A-LOCK is compared with ASH and BSH by the difference amplifiers 26d and 26e.
[0042]
When A-LOCK exceeds ASH, the voltage output from the difference amplifier 26d becomes negative, and the switch 26f is turned on. Then, a signal of the positive voltage + V1 is given to the analog loop filter 24 as a limit signal via the resistors 26h and k. As a result, the voltage input to the analog loop filter 24 decreases.
[0043]
When A-LOCK becomes less than BSH, the voltage output from the difference amplifier 26e becomes negative, and the switch 26g is turned on. Then, a signal of the negative voltage −V2 is given as a limit signal to the analog loop filter 24 via the resistors 26j and 26k. As a result, the voltage input to the analog loop filter 24 increases.
[0044]
Referring to FIG. 5, it is assumed that the voltage applied to voltage controlled oscillator 10 slightly exceeds ASH immediately before the lock detection signal is output. However, it should be noted here that the voltage applied to the voltage controlled oscillator 10 does not greatly deviate from D-LOCK. This is because the output frequency of the voltage controlled oscillator 10 is locked. The slight deviation from D-LOCK is due to an error or noise.
[0045]
When the lock detection signal is output, the limiter circuit 26 provides a signal of the positive voltage + V1 to the analog loop filter 24 as a limit signal via the resistors 26h and 26k. Therefore, the voltage input to the analog loop filter 24 decreases. Then, the voltage drops too much, and the voltage applied to the voltage controlled oscillator 10 falls slightly below BSH. Then, the limiter circuit 26 gives a signal of the negative voltage −V2 to the analog loop filter 24 as a limit signal via the resistors 26j and 26k. Therefore, the voltage input to the analog loop filter 24 increases. In this manner, the frequency of the output signal of the voltage controlled oscillator 10 can be more accurately drawn from the multiplier 22 to the frequency of the reference signal.
[0046]
According to an embodiment of the present invention, a digital phase comparator 12 with a wide pull-in range is used to achieve phase synchronization and lock the frequency of a voltage controlled oscillator (VCO) 10. After that, the multiplier 22 having good phase noise characteristics is used.
[0047]
This enables precise phase synchronization using the multiplier 22 having a narrow pull-in range.
[0048]
In addition, the limiter circuit 26 converts the voltage A-LOCK of the signal output from the analog loop filter 24 into D-LOCK + second offset voltage (BSH) ≦ A-LOCK ≦ D-LOCK + first offset voltage (ASH). And
[0049]
As described above, since the A-LOCK is limited to a range near the D-LOCK, the frequency output from the voltage controlled oscillator 10 becomes larger than the frequency of the reference signal due to a temperature change of the voltage controlled oscillator (VCO) 10 or the like. Even if they are far apart, the frequency of the voltage controlled oscillator (VCO) 10 can be pulled. Further, the frequency of the voltage controlled oscillator 10 can be pulled in without greatly changing the A-LOCK.
[0050]
The above advantage is an example where the A-LOCK is limited to the range of the voltage applied to the voltage controlled oscillator 10 when the frequency of the voltage controlled oscillator 10 is in the range near the frequency of the reference signal. If you suppose and compare, it becomes clearer.
[0051]
That is, it is assumed that the frequency of the voltage controlled oscillator 10 has largely deviated from the frequency of the reference signal due to a temperature change of the voltage controlled oscillator 10 or the like. Then, when switching to use the multiplier 22 (connecting the terminals 30a and 30c), the output voltage of the analog loop filter 24 is set so that the frequency of the voltage controlled oscillator 10 is in a range near the frequency of the reference signal. , Greatly deviates from the range of the voltage applied to the voltage controlled oscillator 10. Therefore, even if an attempt is made to limit the A-LOCK to the range of the voltage applied to the voltage controlled oscillator 10 when the frequency of the voltage controlled oscillator 10 is in the range near the frequency of the reference signal, the multiplier 22 does not operate. It doesn't work because the drawing-in range is narrow. In addition, if the A-LOCK is to be restricted within such a range, the A-LOCK must be largely changed.
[0052]
Further, the above embodiment can be realized as follows. A media reading device for a computer having a CPU, a hard disk, and a medium (a floppy (registered trademark) disk, a CD-ROM, etc.) reading device stores a medium recording a program for realizing switching control of the switch 30 described above. Read it and install it on your hard disk. Even with such a method, the above function can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a PLL circuit 1 according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a digital loop filter 14.
FIG. 3 is a circuit diagram showing a configuration of an analog loop filter 24.
FIG. 4 is a circuit diagram showing a configuration of a limiter circuit 26;
FIG. 5 is a timing chart showing the operation of the embodiment of the present invention.
[Explanation of symbols]
1 PLL circuit 10 Voltage controlled oscillator (VCO)
12. Digital phase comparator (first phase comparison means)
14 Digital loop filter (first low-pass filter)
22 Multiplier (second phase comparison means)
24 Analog loop filter (second low-pass filter)
26 Limiter circuit (voltage limiting means)
30 switches (switching means)

Claims (9)

Voltage-controlled oscillating means for controlling the frequency of the output signal according to the voltage of the input signal;
First phase comparing means for outputting a signal corresponding to the phase difference between the output signal and the reference signal,
A first low-pass filter that passes a low-frequency component of the output of the first phase comparison means,
A signal corresponding to the phase difference between the output signal and the reference signal is output, and an allowable range in which the phase difference is allowable is smaller than the first phase comparing means.
A second low-pass filter that passes a low-frequency component of the output of the second phase comparison means,
Voltage limiting means for limiting the voltage of the signal output from the second low-pass filter based on the voltage of the signal output from the first low-pass filter,
A switching unit that switches a signal to be applied to the voltage control oscillation unit to one of a signal output from the first low-pass filter and a signal output from the second low-pass filter;
A signal processing circuit comprising: The signal processing circuit according to claim 1,
The first phase comparison means is configured by a digital circuit,
Signal processing circuit. The signal processing circuit according to claim 1,
The second phase comparison means is configured by an analog circuit,
Signal processing circuit. The signal processing circuit according to claim 1,
The voltage limiting unit limits the voltage of the signal output from the second low-pass filter to a value obtained by adding a predetermined offset to the voltage of the signal output from the first low-pass filter as a maximum value or a minimum value,
Signal processing circuit. The signal processing circuit according to claim 1,
The voltage limiting unit sets a voltage of a signal output from the second low-pass filter to a value equal to or less than a value obtained by adding a predetermined first offset to a voltage of a signal output from the first low-pass filter, and adds a predetermined second offset. Limit as
Signal processing circuit. The signal processing circuit according to claim 1,
The switching means,
Giving a signal output from the first low-pass filter to the voltage-controlled oscillating means,
After the phase difference between the output signal and the reference signal falls within a predetermined range, a signal given to the voltage controlled oscillator is switched to a signal output from the second low-pass filter.
Signal processing circuit. Voltage-controlled oscillating means for controlling the frequency of the output signal according to the voltage of the input signal; first phase comparing means for outputting a signal corresponding to the phase difference between the output signal and the reference signal; A first low-pass filter that allows a low-frequency component of the output of the phase comparison means to pass therethrough, and outputs a signal corresponding to a phase difference between the output signal and a reference signal; A second phase comparison means narrower than the means, a second low-pass filter that passes a low-frequency component of the output of the second phase comparison means, and a voltage of a signal output from the second low-pass filter, the first low-pass filter Voltage limiting means for limiting based on the voltage of the signal output by the first and second low-pass filters; and a signal to be supplied to the voltage-controlled oscillating means. A signal processing method in the signal processing circuit provided with a switching means for switching to one of the that signal,
Providing a signal output from the first low-pass filter to the voltage-controlled oscillation means,
After the phase difference between the output signal and the reference signal falls within a predetermined range, a signal to be supplied to the voltage-controlled oscillating means, a step of switching to a signal output from the second low-pass filter,
A signal processing method comprising: Voltage-controlled oscillating means for controlling the frequency of the output signal according to the voltage of the input signal; first phase comparing means for outputting a signal corresponding to the phase difference between the output signal and the reference signal; A first low-pass filter that allows a low-frequency component of the output of the phase comparison means to pass therethrough, and outputs a signal corresponding to a phase difference between the output signal and a reference signal; A second phase comparison means narrower than the means, a second low-pass filter that passes a low-frequency component of the output of the second phase comparison means, and a voltage of a signal output from the second low-pass filter, the first low-pass filter Voltage limiting means for limiting based on the voltage of the signal output by the first and second low-pass filters; and a signal to be supplied to the voltage-controlled oscillating means. A program for executing signal processing in a computer in the signal processing circuit provided with a switching means for switching to one of the that signal,
A process of giving a signal output from the first low-pass filter to the voltage-controlled oscillation means,
After the phase difference between the output signal and the reference signal falls within a predetermined range, a process of switching a signal given to the voltage controlled oscillator to a signal output by the second low-pass filter,
A program for causing a computer to execute. Voltage-controlled oscillating means for controlling the frequency of the output signal according to the voltage of the input signal; first phase comparing means for outputting a signal corresponding to the phase difference between the output signal and the reference signal; A first low-pass filter that allows a low-frequency component of the output of the phase comparison means to pass therethrough, and outputs a signal corresponding to a phase difference between the output signal and a reference signal; A second phase comparison means narrower than the means, a second low-pass filter that passes a low-frequency component of the output of the second phase comparison means, and a voltage of a signal output from the second low-pass filter, the first low-pass filter Voltage limiting means for limiting based on the voltage of the signal output by the first and second low-pass filters; and a signal to be supplied to the voltage-controlled oscillating means. A recording medium readable by the recording a computer program for executing the signal processing on a computer in the signal processing circuit provided with a switching means for switching to one of the that signal,
A process of giving a signal output from the first low-pass filter to the voltage-controlled oscillation means,
After the phase difference between the output signal and the reference signal falls within a predetermined range, a process of switching a signal given to the voltage controlled oscillator to a signal output by the second low-pass filter,
And a computer-readable recording medium recording a program for causing a computer to execute the program.

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