JP2004327723A - Multilayer substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To match the impedance for internal stripline as seen from an input/output terminal to be a predetermined impedance, even if the space, between a line conductor connected to the input/output terminal and ground electrodes lying above and below the line conductor, is narrowed and the characteristic impedance of the stripline is lowered. <P>SOLUTION: Although, stripline is constituted, by forming ground electrodes GNDb, GNDa in the lower layer and the upper layer of the line conductor ML in an electrode pattern, a ground electrode non-forming part A for reducing the capacity generated between input/output terminals 13in, 13out on the rear surface electrically continuous with the line conductor and the ground electrode is provided. According to this constitution, a series inductance component is increased, and a parallel capacitance component is reduced to facilitate impedance matching, when the impedance matching between an external standard impedance; and the low impedance of the stripline in a multilayer substrate is contrived in the input/output terminal part. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multilayer substrate formed by laminating a plurality of insulating sheets on which electrode patterns are formed, and more particularly to a multilayer substrate having a strip line and input / output terminals.
[0002]
[Prior art]
Conventionally, in a high-frequency component using a multi-layer substrate, a strip conductor having a triplate structure in which a linear conductor is provided in an inner layer and ground electrodes are arranged in a lower layer and an upper layer, respectively, is configured, and its end is connected to an input / output terminal. There was a case where a structure was adopted. The characteristic impedance of the strip line is determined by the dielectric constant of the insulating layer formed by the insulating sheet, the width of the linear conductor (hereinafter, referred to as "line conductor"), and the distance between the line conductor and the upper and lower ground electrodes.
[0003]
In general, as the height of high-frequency components is reduced, the thickness of the multilayer substrate itself is also required to be reduced. Therefore, the distance between the line conductor and the ground electrodes above and below the line conductor also tends to be narrow.
[0004]
[Problems to be solved by the invention]
In general, ideally, the characteristic impedance of the strip line connected to the input / output terminal is adjusted to 50Ω which is an external standard impedance. However, since the dielectric constant of the insulating sheet cannot be changed basically, as the distance between the line conductor and the ground electrode above and below it becomes smaller, if the characteristic impedance is to be kept at 50Ω, the line width of the line conductor also needs to be reduced. There is. However, from the viewpoint of increasing the conductor loss of the strip line and the precision of forming the electrode pattern, there is a limit in reducing the line width of the line conductor. As a result, the characteristics of the strip line connected to the input / output terminals are reduced. The impedance must be lower than 50Ω.
[0005]
The input / output terminal is formed so that the end of the line conductor is drawn out to the side surface of the multilayer substrate, extends downward from that portion via the side surface of the multilayer substrate, and further extends around the rear surface side of the multilayer substrate. Is common. In order to match the impedance when viewing the internal stripline having a characteristic impedance lower than 50Ω from such an input / output terminal to 50Ω within a predetermined frequency range, it is conceivable to increase the inductivity of the input / output terminal portion. .
[0006]
However, in the input / output terminal having the above-described structure, a capacitance is generated between the input / output terminal (rear surface land) formed to extend to the rear surface side of the multilayer substrate and the ground electrode located below the line conductor. This capacitance offsets the inductive properties of the input / output terminal portion. As a result, there arises a problem that the input / output impedance of the input / output terminal cannot be matched to 50Ω.
[0007]
Therefore, an object of the present invention is to provide an internal strip line from an input / output terminal even if the distance between the line conductor connected to the input / output terminal and the ground electrode above and below the line conductor is reduced and the characteristic impedance of the strip line is reduced. It is an object of the present invention to provide a multi-layer substrate capable of matching the impedance when viewed to a predetermined impedance.
[0008]
[Means for Solving the Problems]
The present invention provides, in a multilayer substrate formed by laminating a plurality of insulating sheets on which an electrode pattern is formed, a ground electrode arranged at least in a lower layer of a line conductor formed by the electrode pattern to constitute a strip line, and a lower portion than the lower layer. A back surface is provided with an input / output terminal that is electrically connected to the line conductor, and a ground electrode on a lower layer formed with a ground electrode is provided at a position facing the input / output terminal to reduce a capacitance generated between the input / output terminal and the ground electrode. It is characterized in that a non-formed portion is provided.
[0009]
With this structure, the capacitance (parallel capacitance component) generated between the input / output terminal provided on the back surface of the multilayer substrate and the ground electrode below the line conductor is reduced, and the series inductance component of the input / output terminal is increased. As a result, even if the distance between the line conductor connected to the input / output terminal and the ground electrode above and below the line conductor is narrowed and the characteristic impedance of the strip line is low, the impedance seen from the input / output terminal to the strip line is the standard impedance. (50Ω).
[0010]
Further, according to the present invention, a ground electrode is also disposed on the layer above the line conductor, and a ground electrode non-formed portion is provided at a position facing the ground electrode non-formed portion in the upper layer where the ground electrode is disposed. Thereby, the opposing area between the input / output terminal and the ground electrode can be more efficiently suppressed.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
The multilayer substrate according to the first embodiment will be described with reference to FIGS.
FIG. 1 is an exploded perspective view of a main part of the multilayer substrate, and FIG. 2 is a partial cross-sectional view in a state where a high-frequency component including the multilayer substrate is mounted on a mounting substrate. In FIG. 1, various electrode patterns are formed on each of the insulating sheets 10i, 10j, 10k, and 10L. Various terminals including input / output terminals 13in, 13out and a ground terminal G are formed on the back surface of the insulating sheet 10i. A ground electrode GNDb is formed on the upper surface of the insulating sheet 10j. Line conductors ML and SL are formed on the upper surface of the insulating sheet 10k. A ground electrode GNDa is formed on the upper surface of the insulating sheet 10L. The line conductors ML, SL and the upper and lower ground electrodes GNDa, GNDb constitute a strip line having a triplate structure. The former acts as the main track of the coupler, and the latter acts as its sub track.
[0012]
In FIG. 2, the multilayer substrate 100 is formed by laminating insulating sheets each having an electrode pattern formed thereon as shown in FIG. On the side surface of the multilayer substrate 100, a side electrode 12 which is electrically connected to the internal electrode 11 (in this case, the line conductor ML of the main line) is formed. On the back surface, a back electrode 13out which is electrically connected to the side electrode 12 is formed. A wiring pattern 111 is formed on the upper surface of the mounting substrate 101, and a high-frequency component made of the multilayer substrate 100 is surface-mounted so that the back electrode 13out is bonded to a predetermined position of the wiring pattern 111.
[0013]
Since the lower ground electrode GNDb and the back electrode 13out face each other via the insulating layers 10i and 10j, a capacitance is generated therebetween. However, as shown in FIG. 1, since the ground electrode non-forming portion A is provided in the layer where the lower layer ground electrode GNDb is formed opposite to the back surface electrode 13out, the ground electrode GNDb and the input / output terminals 13in and 13out are not provided. Are substantially reduced, and the capacitance component therebetween is reduced. Further, also in the upper layer on which the ground electrode GNDa is formed, by providing the ground electrode non-formed portion A, the capacitance component generated between the ground electrode GNDa and the input / output terminals 13in and 13out can be suppressed. Note that the upper-layer ground electrode non-formed portion is not essential.
[0014]
Thereby, when impedance matching is performed by the side surface electrode 12 and the back surface electrode 13 as input / output terminals, the series inductance component by the input / output terminals is increased, and the parallel capacitance component is reduced, so that the internal strip line can be connected from the input / output terminals. The seen impedance can be easily matched to a predetermined standard impedance.
[0015]
Next, the configuration of a high-frequency component using the multilayer board according to the second embodiment will be described with reference to FIGS.
FIG. 3 is a plan view of each layer of the multilayer substrate constituting the high-frequency component. Here, the numbers in parentheses represent the layer numbers. The smaller the value, the lower the layer. The lower layer corresponds to (1) and the upper layer corresponds to (10). In the names of the terminals shown in (1), G is a ground terminal, IN is an input terminal, and OUT is an output terminal. The lower layer ground electrode GNDb is formed in the layer (2). No electrode pattern is formed on the layers (3), (5) and (7). In the layer (4), a line conductor ML of the main line and a line conductor SL of the sub line are formed. In the layer of (6), an upper ground electrode GNDa is formed. Several line conductors are formed in the layers (8) and (9). The mounting component P is mounted on the uppermost layer indicated by (10).
[0016]
FIG. 5 shows a configuration example of a high-frequency component using a conventional multilayer substrate shown in comparison with FIG. The lower ground electrode GNDb formed on the layer (2) and the upper ground electrode GNDa formed on the layer (6) in FIG. 5 are formed over substantially the entire surface so as not to reach the side surface of the substrate. In such a structure, large capacitance components are generated between the back electrodes 13in, 13out and the ground electrodes GNDa, GNDb, respectively.
[0017]
On the other hand, in the example shown in FIG. 3, the layer (2) on which the lower-layer ground electrode GNDb is formed has a ground electrode non-forming portion A at a position facing the input / output terminals 13in, 13out, 13c, and 13d on the back surface. Is provided. In the layer (6) on which the upper layer ground electrode GNDa is formed, a ground electrode non-formed portion A is provided at a position facing the input / output terminals 13in and 13out on the back surface.
In this way, the capacitance generated between the back electrodes 13in, 13out and the ground electrodes GNDa, GNDb can be reduced.
[0018]
Next, the configuration of a high-frequency component using the multilayer board according to the third embodiment will be described with reference to FIG.
The multilayer substrate of this high-frequency component has a total of 11 layers different from the example shown in FIG. 3, and the line conductor ML of the main line and the line conductor SL of the sub line are formed in different layers. Others are basically the same as those shown in FIG. In the example shown in FIG. 4, the layer (2) on which the lower layer ground electrode GNDb is formed is provided with a ground electrode non-forming portion A at a position facing the input / output terminals 13in and 13out on the back surface. In the layer (8) on which the upper ground electrode GNDa is formed, a ground electrode non-formed portion A is provided at a position facing the input / output terminals 13in and 13out on the back surface.
In this way, the capacitance generated between the back electrodes 13in, 13out and the ground electrodes GNDa, GNDb can be reduced.
[0019]
【The invention's effect】
According to the present invention, the capacitance (parallel capacitance component) generated between the input / output terminal provided on the back surface of the multilayer substrate and the ground electrode on the lower side of the line conductor inside the multilayer substrate is reduced, and the series inductance component of the input / output terminal is reduced. Increase. As a result, even if the distance between the line conductor connected to the input / output terminal and the ground electrode above and below the line conductor is narrowed and the characteristic impedance of the strip line is low, the impedance seen from the input / output terminal to the strip line is the standard impedance. (50Ω). Thereby, loss due to impedance mismatch at the input / output terminal can be suppressed.
[0020]
Further, according to the present invention, by providing the ground electrode non-formed portion also in the upper layer opposite to the ground electrode non-formed portion in the lower layer than the strip line, the facing area between the input / output terminal and the ground electrode can be more efficiently increased. Can be suppressed. Further, since the upper and lower portions of the linear conductor are symmetrical at the input / output terminal portion, the vertical symmetry of the strip line is maintained, and the occurrence of spurious modes is suppressed.
[Brief description of the drawings]
FIG. 1 is an exploded perspective view showing a configuration of a multilayer board according to a first embodiment; FIG. 2 is a partial cross-sectional view of a main part in a state where the multilayer board is mounted on a mounting board; FIG. FIG. 4 is a plan view of each layer of the high-frequency component according to the third embodiment. FIG. 5 is a plan view of each layer of the high-frequency component according to the second embodiment. Plan view [Explanation of reference numerals]
10-Insulating sheet 11-Internal electrode 12-Side electrode 13-Back electrode 100-Multilayer substrate 101-Mounting substrate 111-Wiring pattern IN-Input terminal OUT-Output terminal G-Ground terminal GND-Ground electrode A-No ground electrode Part ML-line conductor SL of main line-line conductor P of sub-line-mounting component

Claims (2)

In a multilayer substrate formed by laminating a plurality of insulating sheets on which an electrode pattern is formed,
A ground electrode is arranged on at least a lower layer of the line conductor by the electrode pattern to constitute a strip line, and an input / output terminal for conducting to the line conductor is provided on a back surface further below the lower layer,
A multilayer substrate in which a layer on which a lower ground electrode is formed is provided with a ground electrode non-forming portion at a position facing the input / output terminal to reduce a capacitance generated between the input / output terminal and the input / output terminal. 2. The multilayer substrate according to claim 1, wherein a ground electrode is also arranged on an upper layer of the line conductor, and a ground electrode non-formation portion is provided at a position facing the ground electrode non-formation portion in the upper layer where the ground electrode is arranged.

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