JP2004319809A - Semiconductor chip and its manufacturing method - Google Patents

Semiconductor chip and its manufacturing method Download PDF

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Publication number
JP2004319809A
JP2004319809A JP2003112476A JP2003112476A JP2004319809A JP 2004319809 A JP2004319809 A JP 2004319809A JP 2003112476 A JP2003112476 A JP 2003112476A JP 2003112476 A JP2003112476 A JP 2003112476A JP 2004319809 A JP2004319809 A JP 2004319809A
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Prior art keywords
semiconductor chip
chip
bonding pads
pad
forming
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Shingo Shimoaze
真吾 下畦
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Renesas Technology Corp
Renesas Design Corp
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Renesas Technology Corp
Renesas Design Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor chip capable of contracting the chip size thereof. <P>SOLUTION: In the semiconductor chip 1 equipped with a multitude of bonding pads 100, 101 arrayed in one row on the peripheral parts of the chip as input-and-output interfaces, an up-and-down stage difference is provided between neighbored bonding pads 100, 101. Further, the bonding pads 100 formed on the upper stage are arranged so as to be deviated toward inside of the semiconductor chip 1 compared with the bonding pads 101 formed on the lower stage. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
この発明は、半導体集積回路チップ（以下、半導体チップという。）に関するものであり、特に、チップサイズの縮小化に寄与するものである。
【０００２】
【従来の技術】
従来の半導体チップは、入出力インターフェースとしての多数のボンディングパッドをチップ四辺に一列に並べて形成しており、隣り合うパッド同士の短絡を防ぐため隣り合うパッド間には数ミクロンの隙間を設けている（たとえば、特許文献１参照）。また、短絡を防ぐためパッドをチップ四辺に千鳥状に配置（二列配置）しているものもある。
【０００３】
【特許文献１】
特開２０００−１３８２１７号公報
【０００４】
【発明が解決しようとする課題】
ボンディングパッドをチップ四辺に一列に並べて形成し、パッド間を分離するために数ミクロンの隙間を設ける場合、パッド数が増えると隙間の数も増え、チップサイズが増大する。また、パッドをチップ四辺に千鳥状に交互に配置（二列配置）するものは、パッド間の隙間を無くそうとするものであるが、パッドを二列配置するので必然的に各辺パッド一列分チップサイズが増大する。
【０００５】
この発明は、上記の課題を解決するためになされたもので、従来に比べチップサイズを縮小することができる半導体チップを提供することを目的とする。
【０００６】
【課題を解決するための手段】
上記目的を達成するために、この発明に係る半導体チップは、チップ周辺部に入出力インターフェースとして一列に並べて形成した多数のボンディングパッドを備えた半導体チップにおいて、隣り合う前記ボンディングパッドの間に上下段差を設けたものである。
【０００７】
【発明の実施の形態】
以下に、添付図面を参照してこの発明に係る半導体チップの好適な実施の形態を詳細に説明する。
【０００８】
実施の形態１．
図１を用いて、この発明の実施の形態１を説明する。図１（ａ）はこの発明の実施の形態１の半導体チップの上面図、（ｂ）は（ａ）のア部拡大上面図、（ｃ）はア部拡大正面図、（ｄ）はア部拡大斜視図である。
【０００９】
図において、半導体チップ１は、チップ周辺の四辺に入出力インターフェースとして一列に並べて形成したボンディングパッド１００、１０１を備えている。図１（ｃ）、（ｄ）に示すようにチップ周辺部には、等間隔に平部１ａと溝部１ｂが形成され、平部１ａの端部には上段部パッド１００が形成され、溝部１ｂの端部には下段部パッド１０１が形成されている。
【００１０】
平部１ａと溝部１ｂの段差は下段部パッド１０１の厚さよりも大きくなっていて、上段部パッド１００は平部１ａの幅いっぱいに、下段部パッド１０１は溝部１ｂの幅いっぱいに設けられていても両者が短絡することはない。従って、パッド１００とパッド１０１の間に幅方向の隙間を設ける必要はない。
【００１１】
次に図２を用いて、この発明の半導体チップの製造方法を説明する。図２はこの発明の実施の形態１の半導体チップの製造工程を示す図である。
【００１２】
第１の工程として、図２（ａ）に示すように、半導体チップウエハの４層配線プロセスの場合、３層配線形成時に下段パッド１０１を、チップ周辺部にパッド幅と同じ幅の隙間を空けて一列に並べて形成する（最上層の下の層に下段パッド１０１を形成する。）。
【００１３】
第２の工程として、図２（ｂ）に示すように、３層配線と４層配線を分離するための層間絶縁膜１０２を堆積させる。この層間絶縁膜１０２の厚さは下段パッド１０１の厚さよりも厚い。
【００１４】
第３の工程として、図２（ｃ）に示すように、層間絶縁膜１０２上に４層配線を形成する時に上段パッド１００を、チップ周辺部の下段パッド１０１の隙間上に位置するように一列に並べて形成する。
【００１５】
第４の工程として、図２（ｄ）に示すように、チップ周辺部の上段パッド１００列形成部の内側領域全面にエッチングマスクとしてレジスト１０３を塗布する。
【００１６】
第５の工程として、図２（ｅ）に示すように、パッド１００、１０１材質と層間絶縁膜２０１材質との高選択比をもつエッチング（ドライエッチング）を施すことにより、レジスト１０３及び上段パッド１００をマスクとして層間絶縁膜１０２のみをエッチングし、下段パッド１０１を露出させる。
【００１７】
第６の工程として、図２（ｆ）に示すように、レジスト１０３を除去する。これらの工程によりパッド部の段差構造が形成される。
【００１８】
実施の形態２．
図３を用いて、この発明の実施の形態２を説明する。図３（ａ）はこの発明の実施の形態２の半導体チップの上面図、（ｂ）は（ａ）のイ部拡大上面図、（ｃ）はイ部拡大正面図、（ｄ）はイ部拡大斜視図である。
【００１９】
図において、半導体チップ２は、チップ周辺の四辺に入出力インターフェースとして一列に並べて形成したボンディングパッド２００、２０１を備えている。図２（ｂ）、（ｃ）、（ｄ）に示すようにチップ周辺部には、等間隔に平部２ａと溝部２ｂが形成され、平部２ａの端部には上段部パッド２００が形成され、溝部２ｂの端部には下段部パッド２０１が形成されている。
【００２０】
平部２ａと溝部２ｂの段差は下段部パッド２０１の厚さよりも大きくなっていて、上段部パッド２００は平部２ａの幅いっぱいに、下段部パッド２０１は溝部２ｂの幅いっぱいに設けられていても両者が短絡することはない。従って、パッド２００とパッド２０１の間に幅方向の隙間を設ける必要はない。
【００２１】
この実施の形態２の半導体チップ２が実施の形態１の半導体チップ１と異なるところは、図２（ｂ）、（ｄ）に示すように、上段部パッド２００の列及び平部２ａを下段部パッド２０１の列よりも半導体チップ２の内側にずれ量２ｃだけずらして形成したことである。
【００２２】
このような構造にすると、下段部パッド２０１に斜め方向からボンディングされたワイヤが上段部パッド２００の端部に接触して短絡するようなことを防ぐことができる。
【００２３】
実施の形態２の半導体チップ２を製造するには、実施の形態１の半導体チップ１の製造方法の第３の工程で、層間絶縁膜１０２上の最上層配線形成時に、上段ボンディングパッド１００（２００）を、チップ周辺部の下段ボンディングパッド１０１（２０１）の隙間上のチップ内側に、ずれ量２ｃだけずらした位置に一列に並べて形成すればよい。
【００２４】
【発明の効果】
この発明によれば、チップ周辺部に入出力インターフェースとして一列に並べて形成した多数のボンディングパッドを備えた半導体チップにおいて、隣り合うボンディングパッドの間に上下段差を設けたので、隣り合うボンディングパッド同士が短絡することはなく、隣り合うボンディングパッドの間に幅方向の隙間を設ける必要がないので、半導体チップのサイズを縮小することができる。
【図面の簡単な説明】
【図１】この発明の実施の形態１の半導体チップの外観図である。
【図２】この発明の実施の形態１の半導体チップの製造工程を示す図である。
【図３】この発明の実施の形態２の半導体チップの外観図である。
【符号の説明】
１，２ 半導体チップ、１００，２００ 上段ボンディングパッド、１０１，２０１ 下段ボンディングパッド、１ａ，２ａ 平部、１ｂ，２ｂ 溝部、２ｃ
ずれ量、１０２ 層間絶縁膜、１０３ レジスト。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit chip (hereinafter, referred to as a semiconductor chip), and particularly to a reduction in chip size.
[0002]
[Prior art]
In a conventional semiconductor chip, a number of bonding pads as input / output interfaces are formed in a line on four sides of the chip, and a gap of several microns is provided between adjacent pads to prevent a short circuit between adjacent pads. (For example, see Patent Document 1). In some cases, pads are arranged in a staggered manner (two rows) on four sides of the chip to prevent short circuits.
[0003]
[Patent Document 1]
JP 2000-138217 A
[Problems to be solved by the invention]
When bonding pads are formed in a line on four sides of a chip and a gap of several microns is provided to separate the pads, the number of gaps increases as the number of pads increases, and the chip size increases. In the case where pads are alternately arranged on two sides of the chip in a staggered manner (in two rows), an attempt is made to eliminate a gap between the pads. The chip size increases by an amount.
[0005]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide a semiconductor chip capable of reducing the chip size as compared with the related art.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor chip according to the present invention includes a semiconductor chip having a large number of bonding pads formed in a line as an input / output interface in a peripheral portion of the chip. Is provided.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of a semiconductor chip according to the present invention will be described in detail with reference to the accompanying drawings.
[0008]
Embodiment 1 FIG.
Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1A is a top view of a semiconductor chip according to a first embodiment of the present invention, FIG. 1B is an enlarged top view of a portion A of FIG. 1, FIG. 1C is an enlarged front view of a portion A, and FIG. It is an expansion perspective view.
[0009]
In the figure, a semiconductor chip 1 includes bonding pads 100 and 101 formed in a line as input / output interfaces on four sides around the chip. As shown in FIGS. 1 (c) and 1 (d), flat portions 1a and grooves 1b are formed at equal intervals around the chip, and upper-stage pads 100 are formed at the ends of the flat portions 1a. Is formed with a lower-stage pad 101 at the end of the lower part.
[0010]
The level difference between the flat portion 1a and the groove portion 1b is larger than the thickness of the lower portion pad 101, the upper portion pad 100 is provided to fill the width of the flat portion 1a, and the lower portion pad 101 is provided to fill the width of the groove portion 1b. Also, there is no short circuit between them. Therefore, it is not necessary to provide a gap in the width direction between the pad 100 and the pad 101.
[0011]
Next, a method for manufacturing a semiconductor chip according to the present invention will be described with reference to FIG. FIG. 2 is a diagram showing a manufacturing process of the semiconductor chip according to the first embodiment of the present invention.
[0012]
As a first step, as shown in FIG. 2A, in the case of a four-layer wiring process for a semiconductor chip wafer, a lower pad 101 is formed at the time of forming three-layer wiring, and a gap having the same width as the pad width is formed around the chip. (The lower pad 101 is formed in a layer below the uppermost layer.)
[0013]
As a second step, as shown in FIG. 2B, an interlayer insulating film 102 for separating the three-layer wiring and the four-layer wiring is deposited. The thickness of the interlayer insulating film 102 is larger than the thickness of the lower pad 101.
[0014]
As a third step, as shown in FIG. 2C, when a four-layer wiring is formed on the interlayer insulating film 102, the upper pads 100 are arranged in a line so as to be located above the gaps between the lower pads 101 in the peripheral portion of the chip. Formed side by side.
[0015]
As a fourth step, as shown in FIG. 2D, a resist 103 is applied as an etching mask on the entire surface of the inside area of the upper row of pads 100 formed around the chip.
[0016]
As a fifth step, as shown in FIG. 2E, etching (dry etching) having a high selectivity between the material of the pads 100 and 101 and the material of the interlayer insulating film 201 is performed, so that the resist 103 and the upper pad 100 are formed. Is used as a mask to etch only the interlayer insulating film 102 to expose the lower pad 101.
[0017]
As a sixth step, the resist 103 is removed as shown in FIG. By these steps, a step structure of the pad portion is formed.
[0018]
Embodiment 2 FIG.
Embodiment 2 of the present invention will be described with reference to FIG. FIG. 3A is a top view of a semiconductor chip according to a second embodiment of the present invention, FIG. 3B is an enlarged top view of part A of FIG. 3A, FIG. 3C is an enlarged front view of part A, and FIG. It is an expansion perspective view.
[0019]
In the figure, a semiconductor chip 2 has bonding pads 200 and 201 formed in a line as input / output interfaces on four sides around the chip. As shown in FIGS. 2 (b), 2 (c) and 2 (d), flat portions 2a and grooves 2b are formed at equal intervals around the chip, and upper step pads 200 are formed at the ends of the flat portions 2a. The lower step pad 201 is formed at the end of the groove 2b.
[0020]
The level difference between the flat portion 2a and the groove portion 2b is larger than the thickness of the lower portion pad 201, the upper portion pad 200 is provided to fill the width of the flat portion 2a, and the lower portion pad 201 is provided to fill the width of the groove portion 2b. Also, there is no short circuit between them. Therefore, it is not necessary to provide a gap in the width direction between the pad 200 and the pad 201.
[0021]
The difference between the semiconductor chip 2 of the second embodiment and the semiconductor chip 1 of the first embodiment is that, as shown in FIGS. 2B and 2D, the rows of the upper-stage pads 200 and the flat portions 2a are changed to the lower-stage portions. That is, the pad 201 is formed inside the semiconductor chip 2 with a shift amount of 2c from the row of the pads 201.
[0022]
With such a structure, it is possible to prevent the wire bonded to the lower pad 201 from an oblique direction from coming into contact with the end of the upper pad 200 and causing a short circuit.
[0023]
To manufacture the semiconductor chip 2 of the second embodiment, in the third step of the method of manufacturing the semiconductor chip 1 of the first embodiment, when forming the uppermost layer wiring on the interlayer insulating film 102, the upper bonding pads 100 (200 ) May be formed in a row at a position shifted by a shift amount 2c inside the chip above the gap between the lower bonding pads 101 (201) at the periphery of the chip.
[0024]
【The invention's effect】
According to the present invention, in a semiconductor chip having a large number of bonding pads formed in a line as an input / output interface in the periphery of the chip, an upper and lower step is provided between adjacent bonding pads, so that adjacent bonding pads are There is no short circuit and there is no need to provide a gap in the width direction between adjacent bonding pads, so that the size of the semiconductor chip can be reduced.
[Brief description of the drawings]
FIG. 1 is an external view of a semiconductor chip according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a manufacturing process of the semiconductor chip according to the first embodiment of the present invention;
FIG. 3 is an external view of a semiconductor chip according to a second embodiment of the present invention.
[Explanation of symbols]
1, 2, semiconductor chip, 100, 200 upper bonding pad, 101, 201 lower bonding pad, 1a, 2a flat portion, 1b, 2b groove portion, 2c
Displacement amount, 102 interlayer insulating film, 103 resist.

Claims (4)

チップ周辺部に入出力インターフェースとして一列に並べて形成した多数のボンディングパッドを備えた半導体チップにおいて、
隣り合う前記ボンディングパッドの間に上下段差を設けたことを特徴とする半導体チップ。In a semiconductor chip having a large number of bonding pads formed in a line as an input / output interface in a peripheral portion of the chip,
A semiconductor chip, wherein upper and lower steps are provided between adjacent bonding pads. 前記上段に形成したボンディングパッドを前記下段に形成したボンディングパッドよりも前記半導体チップの内側にずらして配置したことを特徴とする請求項１に記載の半導体チップ。2. The semiconductor chip according to claim 1, wherein the bonding pads formed on the upper stage are shifted from the bonding pads formed on the lower stage inside the semiconductor chip. 3. 半導体チップウエハの最上層の下の層の配線形成時に、下段ボンディングパッドを、チップ周辺部にパッド幅と同じ幅の隙間を設けて一列に並べて形成する第１の工程と、
最上層配線とその下の層の配線とを分離するための層間絶縁膜を前記ウエハに堆積させる第２の工程と、
前記層間絶縁膜上の前記最上層配線形成時に、上段ボンディングパッドを、前記チップ周辺部の前記下段ボンディングパッドの隙間上に位置するように一列に並べて形成する第３の工程と、
前記チップ周辺部の前記上段ボンディングパッド列形成部の内側領域にレジストを塗布する第４の工程と、
前記レジスト及び前記上段ボンディングパッドをマスクとして前記層間絶縁膜をエッチングして下段ボンディングパッドを露出させる第５の工程と、
前記レジストを除去する第６の工程と、
を含む半導体チップの製造方法。A first step of forming lower bonding pads in a row with a gap having the same width as the pad width in the periphery of the chip when forming wiring in a layer below the uppermost layer of the semiconductor chip wafer;
A second step of depositing an interlayer insulating film on the wafer for separating an uppermost layer wiring and a wiring of a layer thereunder;
A third step of forming upper-layer bonding pads in a line so as to be positioned above a gap between the lower-layer bonding pads in a peripheral portion of the chip when forming the uppermost layer wiring on the interlayer insulating film;
A fourth step of applying a resist to an inner area of the upper bonding pad row forming portion around the chip;
A fifth step of exposing the lower bonding pad by etching the interlayer insulating film using the resist and the upper bonding pad as a mask;
A sixth step of removing the resist,
A method for manufacturing a semiconductor chip including: 前記第３の工程において、前記層間絶縁膜上の前記最上層配線形成時に、上段ボンディングパッドを、前記チップ周辺部の下段ボンディングパッドの隙間上のチップ内側にずらした位置に一列に並べて形成することを特徴とする請求項３に記載の半導体チップの製造方法。In the third step, when forming the uppermost layer wiring on the interlayer insulating film, the upper bonding pads are formed in a line at a position shifted toward the inside of the chip above a gap between the lower bonding pads on the periphery of the chip. The method for manufacturing a semiconductor chip according to claim 3, wherein:
JP2003112476A 2003-04-17 2003-04-17 Semiconductor chip and its manufacturing method Pending JP2004319809A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102853108A (en) * 2011-06-29 2013-01-02 株式会社鹭宫制作所 Brazing structure body and brazing method of piping components

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102853108A (en) * 2011-06-29 2013-01-02 株式会社鹭宫制作所 Brazing structure body and brazing method of piping components
JP2013010121A (en) * 2011-06-29 2013-01-17 Saginomiya Seisakusho Inc Brazed structure and brazing method of piping member

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