JP2004315261A - Method of forming ferroelectric thin film - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To lower crystallization temperature and to improve electric characteristics or the like with excellent reproductivity in a method of forming a ferroelectric thin film. <P>SOLUTION: The ferroelectric thin film is formed by applying a material prepared by adding water into a sol gel solution containing a ferroelectric material and silicate, applying on a substrate, then, drying and firing. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【００３０】
図４（ｅ）参照
次いで、この工程を必要とする回数、例えば、２回繰り返すことによって、厚さが、７０ｎｍのＰＺＴ焼成膜１６を形成する。
【００３１】
図４（ｆ）参照
次いで、ＲＴＡ（ラピッドサーマルアニール）によって、Ｏ_２ 雰囲気中で結晶化が起こる温度、例えば、７００℃で１分間結晶化アニールを行ってペロブスカイト構造のＰＺＴ膜１７とする。
【００３２】
図４（ｇ）参照
次いで、スパッタ法によって、ＰＺＴ膜１７上に厚さが、例えば、１００ｎｍのＰｔ上部電極１８を形成したのち、Ｏ_２ 雰囲気中で、例えば、７００℃で回復アニールを行うことによって強誘電体キャパシタの基本構造が完成する。
なお、この回復アニールによって、スパッタ工程においてＰＺＴ膜１７が受けたダメージを回復する。
【００３３】
図５参照
図５は、上記の工程において、水の添加量を１００ｍｏｌ％とした時の強誘電体キャパシタのＱ_ｓｗ−Ｖ特性のＰｂＳｉＯ_３ 添加量依存性の説明図であり、２ｍｏｌ％までの添加量では、Ｑ_ｓｗ−Ｖ特性が向上する。
【００３４】
また、走査型電子顕微鏡写真からは、４ｍｏｌ％の添加量までは、無添加の場合と比較して結晶粒径が大きく且つ表面が平坦になっており、電気特性においてもリーク電流が低下が期待される。
【００３５】
図６参照
図６は、上記の工程において、２ｍｏｌ％のＰｂＳｉＯ_３ を添加した時の強誘電体キャパシタのＱ_ｓｗ−Ｖ特性の水添加量依存性の説明図であり、２００ｍｏｌ％を超える添加量では、Ｑ_ｓｗ−Ｖ特性の低下が予想される。
【００３６】
図７（ａ）及び（ｂ）参照
図７（ａ）は、２ｍｏｌ％のＰｂＳｉＯ_３ を添加した水無添加のＰＺＴ（１１５／４０／６０）ゾルゲル溶液の塗布−乾燥−焼成を３回繰り返した後、結晶化アニールを行った場合の強誘電体キャパシタのヒステリシス特性図であり、一方、図７（ｂ）は、２ｍｏｌ％のＰｂＳｉＯ_３ と１００ｍｏｌ％の水を添加したＰＺＴ（１１５／４０／６０）ゾルゲル溶液の塗布−乾燥−焼成を３回繰り返した後、結晶化アニールを行った場合の強誘電体キャパシタのヒステリシス特性図である。
【００３７】
図から明らかなように、水を添加しない場合の自発分極は、６Ｖ印加した場合の自発分極は、Ｐ≒２０μＣ／ｃｍ^２ であるのに対して、水を添加した場合には、６Ｖ印加した場合の自発分極は、Ｐ≒３０μＣ／ｃｍ^２ であり、３Ｖ印加においてもＰ≒２３μＣ／ｃｍ^２ となり、大幅な特性向上が見られた。
【００３８】
図８参照
図８は、Ｑ_ｓｗ−Ｖ特性の水添加依存性の説明図であり、図７（ａ）及び（ｂ）に示した結果を定量的に示したものであり、水の添加によりＱ_ｓｗが大幅に改善されていることが理解される。
【００３９】
図９参照
図９は、ＸＲＤ（Ｘ線回折）パターンの説明図であり、水を添加した場合の強誘電体膜の回折強度が高くなっており、水を添加することによって結晶性が向上していることが理解される。
【００４０】
次に、図１０を参照して、具体的なＦｅＲＡＭ関する本発明の第２の実施の形態を説明する。
図１０（ａ）参照
図１０（ａ）は本発明の第２の実施の形態に係るプレーナ型ＦｅＲＡＭの概略的要部断面図であり、まず、ｎ型シリコン基板２１の所定領域にｐ型ウエル領域２２を形成するとともに、ｎ型シリコン基板２１を選択酸化することによって素子分離酸化膜２３を形成し、次いで、素子形成領域にゲート絶縁膜２４を介してＷＳｉからなるゲート電極２５を形成し、このゲート電極２５をマスクとしてＡｓ等のイオンを注入することによってｎ⁻ 型ＬＤＤ領域２６を形成する。
【００４１】
次いで、全面にＳｉＯ_２ 膜等を堆積させ、異方性エッチングを施すことによってサイドウォール２７を形成したのち、再び、Ａｓ等をイオン注入することによってｎ^＋ 型ドレイン領域２８及びｎ^＋ 型ソース領域２９を形成し、次いで、ＴＥＯＳ（Ｔｅｔｒａ−Ｅｔｈｙｌ−Ｏｒｔｈｏ−Ｓｉｌｉｃａｔｅ）−ＮＳＧ膜等の厚いＳｉＯ_２ 膜からなる第１層間絶縁膜３０を形成したのち、ｎ^＋ 型ドレイン領域２８及びｎ^＋ 型ソース領域２９に達するコンタクトホールを形成し、このコンタクトホールをＷで埋め込むことによってＷプラグ３１，３２を形成する。
【００４２】
次いで、ＣＶＤ法を用いて全面に薄いＳｉＮ膜３３及びＳｉＯ_２ 膜３４を堆積させたのち、スパッタ法によって厚さが、例えば、１５０ｎｍのＰｔからなる下部電極３５を形成し、次いで、ゾルゲル法を用いて上記の第１の実施の形態と全く同様な工程でＰＺＴ膜３６を形成する。
【００４３】
次いで、再び、スパッタ法を用いてＰＺＴ膜３６上に厚さが、例えば、１５０ｎｍのＰｔからなる上部電極３７を形成したのち、大気圧酸素雰囲気中において７００℃で２０分程度の熱処理を行なってＰＺＴ膜３６が受けた損傷を回復し、次いで、上部電極３７乃至下部電極３５をパターニングすることによって強誘電体キャパシタを形成する。
【００４４】
次いで、全面に薄いＡｌ_２ Ｏ_３ からなる第２層間絶縁膜３８を設けたのち、Ｗプラグ３２に達するコンタクトホールを形成するとともに、上部電極３７に対するコンタクトホールを設け、次いで、全面にＴｉＮ膜を堆積させてパターニングすることによって局所内部配線３９を形成する。
【００４５】
最後に、全面に厚さが、例えば、１．５μｍのＴＥＯＳ−ＮＳＧ膜を堆積させたのちＣＭＰ（化学機械研磨）法によって平坦化して第３層間絶縁膜４０としたのち、Ｗプラグ３１に達するコンタクトホールを形成し、次いで、全面に、ＴｉＮ膜、Ａｌ膜、Ｔｉ膜、及び、ＴｉＮ膜を順次堆積させたのちパターニングしてｎ^＋ 型ドレイン領域２８に接続するビット線４１を形成することによってプレーナ型のＦｅＲＡＭの１メモリセルの基本構造が完成する。
【００４６】
図１０（ｂ）参照
図１０（ｂ）は、図１０（ａ）に示したメモリセルの等価回路図であり、ゲート電極２５はワード線４２に連なり、一方、強誘電体キャパシタは、ｎ^＋ 型ソース領域２９と下部電極３５との間に接続され、下部電極３５は下部電極３５を構成するＰｔ配線層を介してプレート線（接地線）４３に接続されている。
【００４７】
本発明の第２の実施の形態においては、ＦｅＲＡＭのメモリセルを構成するキャパシタを、シリケートを含み且つ水を添加したゾルゲル溶液を用いて形成しているので、キャパシタ特性を向上することができるとともに、再現性を高めることができ、ＦｅＲＡＭの信頼性を向上することができる。
【００４８】
また、シリケートを含み且つ水を添加したゾルゲル溶液を用いて形成しているので、ＰＺＴ膜の表面平坦化及びリーク電流の低減が可能になり、それによって、キャパシタの小型化が可能になるのでＦｅＲＡＭの集積度を向上することができる。
【００４９】
また、シリケートを添加することによって、結晶化アニール温度の低温化が可能になり、スタック型キャパシタを備えたＦｅＲＡＭの実現が可能になる。
【００５０】
以上、本発明の各実施の形態を説明してきたが、本発明は各実施の形態に記載した構成に限られるものではなく、各種の変更が可能である。
例えば、上記の各実施の形態においては、強誘電体膜をＰＺＴ（ＰｂＺｒ_ｘ Ｔｉ_１−ｘ Ｏ_３ ）で構成しているが、ＰＺＴに限られるものではなく、ＰＺＴにＬａを添加したＰＬＺＴ〔Ｐｂ_１−ｙ Ｌａ_ｙ （Ｚｒ_ｘ Ｔｉ_１−ｘ ）_{１−ｙ／４} Ｏ_３ 〕等の他のＰｂ系ペロブスカイト強誘電体、即ち、Ｐｂ_１−ｙ Ａ_ｙ （Ｚｒ_ｘ Ｔｉ_１−ｘ ）_{１−ｙ／４} Ｏ_３ （Ａは、Ｌａ，Ｃａ，Ｓｒ）を用いても良いものである。
【００５１】
さらには、ＳｒＢｉ_２ Ｔａ_２ Ｏ_９ （ＳＢＴ）またはＢｉ_４ Ｔｉ_３ Ｏ_１２（ＢＩＴ）、若しくは、ＳＢＴ或いはＢＩＴにＬａ，Ｐｒ，Ｎｄ，Ｃａ等を含んだ強誘電体材料を用いても良いものである。
【００５２】
また、上記の実施の形態においては、添加するシリケートとして、ＰｂＯ：ＳｉＯ_２ ＝１：１組成のゾルゲル溶液を用いているが、組成比は任意である。
【００５３】
また、上記の実施の形態においては、添加するシリケートとして、鉛シリケートを用いているが、鉛シリケートに限られるものではなく、ランタンシリケート或いはカルシウムシリケート等の他のシリケートを用いても良いものであり、さらには、ＳｉＯ_２ 単体でも良いものである。
【００５４】
また、上記の実施の形態においては、市販のＰＺＴゾルゲル溶液を用いているが、各金属元素の前駆体を混合して任意のゾルゲル溶液を作成しても良いものである。
例えば、Ｐｂ源としてのＰｂ（ＣＨ_３ ＣＯＯ）_２ ・３Ｈ_２ Ｏ〔酢酸鉛〕、Ｔｉ源としてのＴｉ（ｉ−ＯＣ_３ Ｈ_７ ）_４ 〔チタニウムイソプロポキシド〕、Ｚｒ源としてのＺｒ（ｉ−ＯＣ_３ Ｈ_７ ）_４ 〔ジルコニウムイソプロポキシド〕、及び、安定剤としてのＣＨ_３ ＣＯＣＨ_２ ＣＯＣＨ_３ （２，４−ペンタンジオン）を溶剤であるＣＨ_３ ＯＣ_２ Ｈ_４ ＯＨ〔メトキシエタノール〕で希釈した溶液を用いれば良い。
【００５５】
また、上記の各実施の形態においては下部電極及び上部電極としてＰｔを用いているが、Ｉｒ或いはＩｒＯ_ｘ 等を単層或いは多層構造として用いても良いものである。
【００５６】
また、上記の各実施の形態においては、１Ｔｒ＋１Ｃ型の強誘電体メモリ装置を前提に説明しているが、２Ｔｒ＋２Ｃ型の強誘電体メモリ装置にも適用されることは言うまでもない。
【００５７】
また、上記の各実施の形態においては、強誘電体メモリ装置のメモリセルを構成する強誘電体キャパシタを前提として説明しているが、強誘電体メモリ装置に限られるものではなく、一般の半導体集積回路装置内の薄膜キャパシタ或いは圧電素子、光素子としても良いものである。
【００５８】
ここで、再び、図１を参照して、改めて本発明の詳細な特徴を説明する。
再び、図１参照
（付記１） 強誘電体材料およびシリケートを含むゾルゲル溶液に水を添加したものを基板上に塗布したのち、乾燥・焼成することを特徴とする強誘電体薄膜の形成方法。
（付記２） 上記強誘電体材料が、少なくともＰｂ，Ｚｒ，Ｔｉを含む酸化物であることを特徴とする付記１記載の強誘電体薄膜の形成方法。
（付記３） 上記少なくともＰｂ，Ｚｒ，Ｔｉを含む酸化物が、Ｐｂ_１−ｙ Ａ_ｙ （Ｚｒ_ｘ Ｔｉ_１−ｘ ）_{１−ｙ／４} Ｏ_３ （但し、Ａは、Ｌａ，Ｃａ，Ｓｒ）であることを特徴とする付記２記載の強誘電体薄膜の形成方法。
（付記４） 上記シリケートが、鉛シリケートであることを特徴とする付記２または３に記載の強誘電体薄膜の形成方法。
（付記５） 上記強誘電体材料に対するシリケート及び水の混合比が、それぞれ０．２〜４ｍｏｌ％及び２０〜２００ｍｏｌ％であることを特徴とする付記２乃至４のいずれか１に記載の強誘電体薄膜の形成方法。
（付記６） 上記ゾルゲル溶液に水を添加したものを基板上に塗布したのち、体積収縮を起こす温度よりも低温で一定時間乾燥させ、次いで、体積収縮を起こす温度で焼成を行うことを特徴とする付記１乃至５のいずれか１に記載の強誘電体薄膜の形成方法。
（付記７） 上記乾燥の温度が、７０℃〜２５０℃であることを特徴とする付記６記載の強誘電体薄膜の形成方法。
【００５９】
【発明の効果】
本発明によれば、シリケートを含むゾルゲル溶液に水を添加して塗布しているので、強誘電体膜の表面状態を改善し、しかも強誘電体としての電気特性を再現性良く向上させることができ、ひいては、強誘電体メモリ装置をはじめとする強誘電体キャパシタを構成要素とする電子デバイスの信頼性の向上或いは特性の向上に寄与するところが大きい。
【図面の簡単な説明】
【図１】本発明の原理的構成の製造フロー図である。
【図２】本発明の第１の実施の形態の製造フロー図である。
【図３】本発明の第１の実施の形態の強誘電体キャパシタの途中までの製造工程の説明図である。
【図４】本発明の第１の実施の形態の強誘電体キャパシタの図３以降の製造工程の説明図である。
【図５】Ｑ_ｓｗ−Ｖ特性のＰｂＳｉＯ_３ 添加量依存性の説明図である。
【図６】Ｑ_ｓｗ−Ｖ特性の水添加量依存性の説明図である。
【図７】強誘電体キャパシタのヒステリシス特性図である。
【図８】強誘電体キャパシタのＱ_ｓｗ−Ｖ特性の水添加依存性の説明図である。
【図９】ＸＲＤパターンの説明図である。
【図１０】本発明の第２の実施の形態のプレーナ型ＦｅＲＡＭの説明図である。
【符号の説明】
１１ シリコン基板
１２ ＳｉＯ_２ 膜
１３ Ｐｔ下部電極
１４ ＰＺＴ塗布膜
１５ ＰＺＴ焼成薄膜
１６ ＰＺＴ焼成膜
１７ ＰＺＴ膜
１８ Ｐｔ上部電極
２１ ｎ型シリコン基板
２２ ｐ型ウエル領域
２３ 素子分離酸化膜
２４ ゲート絶縁膜
２５ ゲート電極
２６ ｎ⁻ 型ＬＤＤ領域
２７ サイドウォール
２８ ｎ^＋ 型ドレイン領域
２９ ｎ^＋ 型ソース領域
３０ 第１層間絶縁膜
３１ Ｗプラグ
３２ Ｗプラグ
３３ ＳｉＮ膜
３４ ＳｉＯ_２ 膜
３５ 下部電極
３６ ＰＺＴ膜
３７ 上部電極
３８ 第２層間絶縁膜
３９ 局所内部配線
４０ 第３層間絶縁膜
４１ ビット線
４２ ワード線
４３ プレート線[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for forming a ferroelectric thin film, and more particularly to improving the reproducibility of electrical characteristics when adding a silicate to a Pb-based perovskite ferroelectric film to reduce the crystallization temperature. The present invention relates to a method for forming a ferroelectric thin film having a characteristic structure.
[0002]
[Prior art]
Flash memories and ferroelectric memories are known as nonvolatile memories that can retain information even when the power is turned off. Among them, the flash memory is a gate insulating film of an insulated gate field effect transistor (IGFET). It has a floating gate embedded inside and stores information by accumulating charges representing stored information in the floating gate.To write or erase information, a tunnel current passing through the insulating film must be passed. Requires relatively high voltages.
[0003]
On the other hand, a ferroelectric memory (FeRAM: Ferroelectric Random Access Memory) stores information using a hysteresis characteristic of a ferroelectric, and has a ferroelectric film as a capacitor dielectric between a pair of electrodes. The ferroelectric capacitor generates polarization according to the applied voltage between the electrodes, has spontaneous polarization even when the applied voltage is removed, and if the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed.
[0004]
Since the information can be read by detecting the spontaneous polarization, the ferroelectric memory operates at a lower voltage than the flash memory, and has a feature of being able to perform high-speed writing with low power consumption.
[0005]
As the film formation method of the ferroelectric film, a sputtering method, MOCVD method, or it sol-gel method is known, in the sol-gel _{method, PZT (PbZr x Ti 1-} x O 3) metal oxides such as The ratio at which the thermally decomposable organometallic compound, hydrolyzable organometallic compound, partial hydrolyzate and / or polycondensate of each metal constituting the above metal gives the metal atom ratio of the metal oxide of the desired composition And a solution dissolved in an organic solvent such as butanol (for example, see Patent Document 1).
[0006]
In such a ferroelectric capacitor, a polycrystalline ferroelectric film is used. However, in the polycrystalline ferroelectric film, irregularities on the surface and large voids at the crystal grain boundaries are likely to be generated, and the interface between the electrode and the electrode is formed. It is easy to form a metamorphic layer.
[0007]
In addition, with the recent demand for higher integration, the ferroelectric film must be made thinner in order to cope with low-voltage driving. However, as the ferroelectric film becomes thinner, surface irregularities and crystallinity increase. There is a problem that a leakage current increases because a conduction path is formed along the grain boundary.
[0008]
In order to improve the degree of integration, it is necessary to adopt a stack structure in which a capacitor is arranged on a cell transistor. However, in a high-temperature and oxidizing atmosphere, conduction cannot be achieved due to oxidation of a junction between the electrode and the transistor. It is necessary to crystallize the ferroelectric film at a low temperature of 500 ° C. or less.
[0009]
Therefore, in recent years, it has been proposed to add a silicate or the like to the sol-gel PZT in order to reduce the film formation temperature of the ferroelectric film (for example, Patent Document 1, Non-Patent Document 1, or Non-Patent Document 2). ), The effect of improving the crystallinity or improving the electrical characteristics as well as lowering the crystallization temperature has been reported.
[0010]
[Patent Document 1]
JP-A-11-292626 [Patent Document 2]
JP 2003-002647 [Non-Patent Document 1]
Jpn. J. Appl. Phys. , Vol. 41, p. L716, 2002
[Non-patent document 2]
Nikkei Electronics, pp. 137-148, 2002.05.20
[0011]
[Problems to be solved by the invention]
As described above, the addition of the silicate clearly improves the electrical characteristics, such as a decrease in the leak current, but has a problem that the amount of inversion charge is often small and the reproducibility is poor.
There is also a problem that the characteristics are greatly different depending on processes such as the upper electrode structure.
[0012]
Accordingly, an object of the present invention is to reduce the crystallization temperature and to improve electrical characteristics and the like with good reproducibility.
[0013]
[Means for Solving the Problems]
FIG. 1 is a manufacturing flow chart of the principle configuration of the present invention. Here, means for solving the problems in the present invention will be described with reference to FIG.
Referring to FIG. 1, in order to achieve the above object, the present invention relates to a method for forming a ferroelectric thin film, wherein a sol-gel solution containing a ferroelectric material and a silicate to which water is added is applied onto a substrate and then dried. -It is characterized by firing.
[0014]
Thus, {circle around (1)} By adding water to the sol-gel solution containing the ferroelectric material and the silicate, the hydrolysis and dehydration condensation of the sol molecules of the silicate causes the desorption of the organic component and the formation of the Si—O—Si network. As the formation proceeds, the density of the gel including the molecules constituting the ferroelectric increases due to the volume shrinkage, and the gel is easily crystallized. Therefore, both a decrease in the crystallization temperature and an improvement in reproducibility can be achieved.
[0015]
Also, by adding water, the density of the gel also increases, the ferroelectric thin film after firing becomes denser, the surface flatness is improved, and as a result, electric characteristics such as a reduction in leak current are improved. Can be.
In a commercially available sol-gel solution, water generated during the manufacturing process is removed and purified as impurities.
[0016]
The ferroelectric material in this case, oxides containing at least Pb, Zr, and Ti, for _{example, Pb 1-y A y Zr} x Ti 1-x O 3 ( where, A is, La, Ca, Sr), etc. Pb-based perovskite ferroelectric, or SrBi ₂ Ta ₂ O ₉ (SBT) or Bi ₄ Ti ₃ O ₁₂ (BIT), or a ferroelectric containing La, Pr, Nd, Ca or the like in SBT or BIT Materials can be used.
[0017]
In addition, SiO ₂ may be used as the silicate, but lead silicate (PbSiO ₃ ) or the like is typical for improving the ferroelectric characteristics.
In this case, the silicate is added in the form of a sol-gel solution using a precursor.
[0018]
The mixing ratio of silicate and water to the ferroelectric material is preferably 0.2 to 4 mol%, more preferably 0.2 to 2 mol%, and 20 to 200 mol%.
[0019]
That is, in order to improve the Q _sw properties by the addition of silicate, although the addition amount of the silicate is preferably in the range of 0.2 to 2 mol%, the effect of reducing leakage current by improving the film quality of the surface flattening is 0. It is obtained in the range of 2-4 mol%.
In order to obtain an improvement in Q _sw characteristics and spontaneous polarization by the addition of water, the amount of water added is preferably 20～200Mol%, when no water is added, the spontaneous polarization is significantly reduced.
[0020]
In this case, after a solution obtained by adding water to the sol-gel solution is applied onto the substrate, drying is performed at a temperature lower than the temperature causing the volume shrinkage for a certain period of time, and then firing is performed at the temperature causing the volume shrinkage. It is desirable.
[0021]
That is, (2) when the film is not dried at a temperature lower than the temperature at which volume contraction occurs for a certain period of time, and (3) when calcined, the chemical reaction and the evaporation of the solvent occur simultaneously, so that the film density cannot be increased. (2) If (4) crystallization annealing is performed immediately after drying, a coarse film is obtained.
[0022]
The drying temperature in this case is 70 ° C. to 250 ° C., and varies depending on the composition of the sol-gel solution.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Here, the manufacturing process of the ferroelectric capacitor according to the first embodiment of the present invention will be described with reference to FIGS. 2 to 4. FIG. 2 is a manufacturing flow according to the first embodiment of the present invention. FIG.
2 and 3A, a Pt lower electrode 13 having a thickness of, for example, 150 nm is provided on a silicon substrate 11 via a SiO ₂ film 12 by a sputtering method.
[0024]
Next, as shown in FIG. 3B, a PZT coating film 14 is formed by applying a sol-gel PZT solution to which water and lead silicate are added, for example, in a 40% humidity atmosphere at room temperature at a rotation speed of 5000 rpm for 30 seconds. And
[0025]
At this time, as the sol-gel solution for PZT, a sol-gel solution for forming a ferroelectric thin film composed of, for example, a 10% by weight butanol solution mixed with each precursor at a molar ratio according to the required PZT composition (Mitsubishi Materials, http: //Www.mmc.co.jp/adv/ele/electric5.html).
Here, a sol-gel solution having a composition from which PZT having a composition of Pb: Zr: Ti: = 115: 40: 60 is obtained.
[0026]
Further, as the sol-gel solution for lead silicate, Pb (CH ₃ COO) ₂ .3H ₂ O [lead acetate] serving as a Pb source and TEOS (tetraethoxysilane) serving as a Si source are, for example, PbO: SiO ₂ Using a 10% by weight butanol solution mixed at a ratio of = 1: 1, 0.2 to 4 mol% is added to the sol-gel solution for PZT.
Water is added, for example, at 100 mol% to the sol-gel solution for PZT.
At this time, ethanol may be added to improve the mixing.
[0027]
Next, immediately after coating, the PZT coating film 14 is dried by baking at a temperature lower than the temperature at which volume contraction occurs in an O ₂ atmosphere at atmospheric pressure, for example, at 200 ° C. for 5 minutes.
In this drying step, butanol as a solvent evaporates.
[0028]
Next, as shown in FIG. 3D, baking is performed at a temperature that causes volume shrinkage in an O ₂ atmosphere at atmospheric pressure, for example, 230 ° C. for 5 minutes, followed by baking to obtain a PZT fired thin film 15.
[0029]
In this baking step, as shown in the following chemical reaction formula, desorption of organic components and formation of a Si—O—Si network proceed by hydrolysis and dehydration condensation of silicate sol molecules, and a ferroelectric substance is formed by volume shrinkage. The density of the gel including the molecules constituting the gel increases, and the gel is easily crystallized.
Embedded image

[0030]
Referring to FIG. 4E, the PZT fired film 16 having a thickness of 70 nm is formed by repeating this step a required number of times, for example, twice.
[0031]
Next, as shown in FIG. 4F, crystallization annealing is performed by RTA (rapid thermal annealing) at a temperature at which crystallization occurs in an O ₂ atmosphere, for example, at 700 ° C. for 1 minute to form a PZT film 17 having a perovskite structure.
[0032]
Referring to FIG. 4 (g), after forming a Pt upper electrode 18 having a thickness of, for example, 100 nm on the PZT film 17 by sputtering, recovery annealing is performed at, for example, 700 ° C. in an O ₂ atmosphere. Thereby, the basic structure of the ferroelectric capacitor is completed.
In addition, the damage that the PZT film 17 receives in the sputtering process is recovered by the recovery annealing.
[0033]
See Figure 5. Figure 5 in the above step is an explanatory view of a PbSiO ₃ amount dependency of _Q sw -V characteristics of the ferroelectric capacitor when the amount of water added was set to 100 mol%, up to 2 mol% With the added amount, the _Qsw- V characteristics are improved.
[0034]
From the scanning electron micrograph, up to 4 mol%, the crystal grain size is large and the surface is flat as compared with the case where no additive is added, and the leak current is expected to decrease in the electric characteristics. Is done.
[0035]
FIG. 6 is an explanatory diagram showing the dependence of the _Qsw- V characteristic of the ferroelectric capacitor on the amount of water added when 2 mol% of PbSiO ₃ is added in the above-described process. In this case, it is expected that the Q _sw -V characteristic will be reduced.
[0036]
FIGS. 7 (a) and (b) refer to FIG. 7 (a), application of 2 mol% of PZT (115/40/60) of added Mizunashi added PbSiO ₃ sol-gel solution - drying - was repeated three times fired FIG. 7B is a hysteresis characteristic diagram of the ferroelectric capacitor when crystallization annealing is performed later, while FIG. 7B shows PZT (115/40/60) to which 2 mol% of PbSiO ₃ and 100 mol% of water are added. FIG. 3 is a hysteresis characteristic diagram of a ferroelectric capacitor when crystallization annealing is performed after repeating application-drying-firing of a sol-gel solution three times.
[0037]
As is clear from the figure, the spontaneous polarization when no water is added is 6 ≒ C / cm ² , whereas the spontaneous polarization when 6 V is applied is 6 μC / cm ² when water is added. In this case, the spontaneous polarization was P ≒ 30 μC / cm ² , and even when 3 V was applied, P ≒ 23 μC / cm ² , indicating a significant improvement in characteristics.
[0038]
FIG. 8 is an explanatory diagram of the dependence of the Q _sw -V characteristic on water addition, and quantitatively shows the results shown in FIGS. 7A and 7B. It can be seen that Q _sw is greatly improved.
[0039]
FIG. 9 is an explanatory view of an XRD (X-ray diffraction) pattern. The diffraction intensity of the ferroelectric film when water is added is high, and the crystallinity is improved by adding water. It is understood that.
[0040]
Next, a second embodiment of the present invention relating to a specific FeRAM will be described with reference to FIG.
FIG. 10A is a schematic sectional view of a principal part of a planar type FeRAM according to a second embodiment of the present invention. First, a p-type well is formed in a predetermined region of an n-type silicon substrate 21. Forming a region 22 and selectively oxidizing the n-type silicon substrate 21 to form an element isolation oxide film 23, and then forming a gate electrode 25 made of WSi via a gate insulating film 24 in an element forming region, Using the gate electrode 25 as a mask, ions such as As are implanted to form an n ⁻ type LDD region 26.
[0041]
Next, a SiO ₂ film or the like is deposited on the entire surface, and a sidewall 27 is formed by performing anisotropic etching. Then, ion implantation of As or the like is performed again to thereby form the n ⁺ -type drain region 28 and the n ⁺ -type source region. After forming a first interlayer insulating film 30 made of a thick SiO ₂ film such as a TEOS (Tetra-Ethyl-Ortho-Silicate) -NSG film, the n ⁺ -type drain region 28 and the n ⁺ -type source A contact hole reaching the region 29 is formed, and this contact hole is filled with W to form W plugs 31 and 32.
[0042]
Next, after depositing a thin SiN film 33 and a SiO ₂ film 34 on the entire surface by the CVD method, a lower electrode 35 made of Pt having a thickness of, for example, 150 nm is formed by the sputtering method, and then the sol-gel method is performed. The PZT film 36 is formed in the same process as in the first embodiment.
[0043]
Next, after the upper electrode 37 made of Pt having a thickness of, for example, 150 nm is formed on the PZT film 36 again by the sputtering method, a heat treatment is performed at 700 ° C. for about 20 minutes in an atmospheric oxygen atmosphere. After the damage of the PZT film 36 is recovered, the upper electrode 37 to the lower electrode 35 are patterned to form a ferroelectric capacitor.
[0044]
Next, after a second interlayer insulating film 38 made of thin Al ₂ O ₃ is provided on the entire surface, a contact hole reaching the W plug 32 is formed, a contact hole for the upper electrode 37 is provided, and a TiN film is formed on the entire surface. The local internal wiring 39 is formed by depositing and patterning.
[0045]
Lastly, a TEOS-NSG film having a thickness of, for example, 1.5 μm is deposited on the entire surface, planarized by a CMP (chemical mechanical polishing) method to form a third interlayer insulating film 40, and then reaches the W plug 31. A contact hole is formed, and then a TiN film, an Al film, a Ti film, and a TiN film are sequentially deposited on the entire surface and then patterned to form a bit line 41 connected to the n ⁺ type drain region 28. The basic structure of one memory cell of the planar type FeRAM is completed.
[0046]
FIG. 10B is an equivalent circuit diagram of the memory cell shown in FIG. 10A, in which the gate electrode 25 is connected to the word line 42, while the ferroelectric capacitor is n ⁺ The lower electrode 35 is connected between the mold source region 29 and the lower electrode 35, and is connected to a plate line (ground line) 43 via a Pt wiring layer constituting the lower electrode 35.
[0047]
In the second embodiment of the present invention, since the capacitor constituting the memory cell of the FeRAM is formed using a sol-gel solution containing silicate and adding water, the capacitor characteristics can be improved. , The reproducibility can be improved, and the reliability of the FeRAM can be improved.
[0048]
In addition, since the PZT film is formed using a sol-gel solution containing silicate and to which water is added, the surface of the PZT film can be flattened and the leakage current can be reduced, thereby making it possible to reduce the size of the capacitor. Can be improved.
[0049]
Further, by adding silicate, the crystallization annealing temperature can be lowered, and an FeRAM having a stacked capacitor can be realized.
[0050]
The embodiments of the present invention have been described above. However, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible.
For example, PLZT in the above embodiments, although the ferroelectric film _{PZT (PbZr x Ti 1-x} O 3), is not limited to PZT, the addition of La to PZT [ _{Pb 1-y La y (Zr} x Ti 1-x) 1-y / 4 O 3 ] other Pb-based perovskite ferroelectrics such, _{i.e., Pb 1-y a y (} Zr x Ti 1-x) 1 _-y / _{4 O} 3 (a is, La, Ca, Sr) those may be used.
[0051]
Further, SrBi ₂ Ta ₂ O ₉ (SBT) or Bi ₄ Ti ₃ O ₁₂ (BIT), or a ferroelectric material containing SBT or BIT containing La, Pr, Nd, Ca, or the like may be used. It is.
[0052]
In the above embodiment, a sol-gel solution having a PbO: SiO ₂ = 1: 1 composition is used as the silicate to be added, but the composition ratio is arbitrary.
[0053]
In the above embodiment, lead silicate is used as a silicate to be added.However, the present invention is not limited to lead silicate, and other silicates such as lanthanum silicate or calcium silicate may be used. Further, SiO ₂ alone may be used.
[0054]
Further, in the above embodiment, a commercially available PZT sol-gel solution is used, but an arbitrary sol-gel solution may be prepared by mixing precursors of each metal element.
For example, _Pb of the Pb source _{(CH 3 COO) 2 · 3H} 2 O [lead acetate], Ti as Ti source _{(i-OC 3 H 7)} 4 [titanium isopropoxide], Zr as Zr source (i -OC ₃ H _{7) 4} [zirconium isopropoxide], and, in _{CH 3} COCH ₂ COCH 3 as stabilizer (2,4-pentanedione) is a solvent _CH 3 _OC 2 _H 4 OH [methoxyethanol] A diluted solution may be used.
[0055]
Further, in the above embodiments is used to Pt as the lower electrode and the upper electrode, but may be used Ir or IrO _x or the like as a single layer or a multilayer structure.
[0056]
Further, in each of the above embodiments, description has been made on the premise that a 1Tr + 1C type ferroelectric memory device is used, but it goes without saying that the present invention is also applied to a 2Tr + 2C type ferroelectric memory device.
[0057]
Further, in each of the above-described embodiments, the description has been made on the assumption that the ferroelectric capacitor constituting the memory cell of the ferroelectric memory device is used. It may be a thin film capacitor, a piezoelectric element, or an optical element in an integrated circuit device.
[0058]
Here, the detailed features of the present invention will be described again with reference to FIG. 1 again.
Again referring to FIG. 1 (Appendix 1) A method for forming a ferroelectric thin film, comprising applying a water to a sol-gel solution containing a ferroelectric material and a silicate to a substrate, followed by drying and firing.
(Supplementary Note 2) The method for forming a ferroelectric thin film according to Supplementary Note 1, wherein the ferroelectric material is an oxide containing at least Pb, Zr, and Ti.
(Supplementary Note 3) The oxide containing at least Pb, Zr, and Ti is Pb _1-y A _y (Zr _x Ti _1-x ) _{1-y / 4} O ₃ (where A is La, Ca, and Sr). 3. The method for forming a ferroelectric thin film according to claim 2, wherein
(Supplementary note 4) The method for forming a ferroelectric thin film according to supplementary note 2 or 3, wherein the silicate is a lead silicate.
(Supplementary note 5) The ferroelectric substance according to any one of Supplementary notes 2 to 4, wherein a mixing ratio of silicate and water to the ferroelectric material is 0.2 to 4 mol% and 20 to 200 mol%, respectively. Method of forming body thin film.
(Supplementary Note 6) After applying a solution obtained by adding water to the sol-gel solution onto a substrate, drying the solution at a temperature lower than a temperature at which volume shrinkage occurs, and then performing baking at a temperature at which volume shrinkage occurs. 6. The method for forming a ferroelectric thin film according to any one of supplementary notes 1 to 5.
(Supplementary note 7) The method for forming a ferroelectric thin film according to supplementary note 6, wherein the drying temperature is 70 ° C to 250 ° C.
[0059]
【The invention's effect】
According to the present invention, since the water is added to the sol-gel solution containing silicate and applied, the surface state of the ferroelectric film can be improved, and the electric characteristics as the ferroelectric can be improved with good reproducibility. This greatly contributes to the improvement of the reliability or characteristics of electronic devices including ferroelectric capacitors such as ferroelectric memory devices as constituent elements.
[Brief description of the drawings]
FIG. 1 is a manufacturing flow chart of the principle configuration of the present invention.
FIG. 2 is a manufacturing flow chart according to the first embodiment of the present invention.
FIG. 3 is an explanatory diagram of a manufacturing process of the ferroelectric capacitor according to the first embodiment of the present invention halfway;
FIG. 4 is an explanatory diagram of a manufacturing process of the ferroelectric capacitor according to the first embodiment of the present invention after FIG. 3;
FIG. 5 is an explanatory diagram of the dependence of Q _sw -V characteristics on the added amount of PbSiO ₃ .
FIG. 6 is an explanatory diagram of the dependence of Q _sw -V characteristics on the amount of water added.
FIG. 7 is a diagram showing hysteresis characteristics of a ferroelectric capacitor.
FIG. 8 is an explanatory diagram of the dependence of Q _sw -V characteristics of a ferroelectric capacitor on water addition.
FIG. 9 is an explanatory diagram of an XRD pattern.
FIG. 10 is an explanatory diagram of a planar type FeRAM according to a second embodiment of the present invention.
[Explanation of symbols]
Reference Signs List 11 silicon substrate 12 SiO ₂ film 13 Pt lower electrode 14 PZT coating film 15 PZT fired thin film 16 PZT fired film 17 PZT film 18 Pt upper electrode 21 n-type silicon substrate 22 p-type well region 23 element isolation oxide film 24 gate insulating film 25 Gate electrode 26 n ⁻ type LDD region 27 Side wall 28 n ⁺ type drain region 29 n ⁺ type source region 30 First interlayer insulating film 31 W plug 32 W plug 33 SiN film 34 SiO ₂ film 35 Lower electrode 36 PZT film 37 Upper part Electrode 38 Second interlayer insulating film 39 Local internal wiring 40 Third interlayer insulating film 41 Bit line 42 Word line 43 Plate line

Claims (5)

A method for forming a ferroelectric thin film, comprising: applying a solution obtained by adding water to a sol-gel solution containing a ferroelectric material and a silicate to a substrate, followed by drying and firing. 2. The method according to claim 1, wherein the ferroelectric material is an oxide containing at least Pb, Zr, and Ti. 3. The method for forming a ferroelectric thin film according to claim 2, wherein a mixing ratio of silicate and water to the ferroelectric material is 0.2 to 4 mol% and 20 to 200 mol%, respectively. 2. The method according to claim 1, wherein said sol-gel solution to which water is added is applied onto a substrate, dried for a certain time at a temperature lower than a temperature at which volume shrinkage occurs, and then fired at a temperature at which volume shrinkage occurs. 4. The method for forming a ferroelectric thin film according to claim 1. The method for forming a ferroelectric thin film according to claim 4, wherein the drying temperature is 70C to 250C.

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