JP2004311785A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high density and multilayer structured semiconductor device by thinning the thickness of a laminated structure in arranging a wiring board or a semiconductor element in a laminated positional relation. <P>SOLUTION: The semiconductor device 1 is mainly composed of a wiring board 2 provided by a wiring layer 2a, a first semiconductor element 3, and a second semiconductor element 4. An opening 2b to which the second semiconductor element 4 is arranged and to be an adjusting part for a lamination thickness is formed at the predetermined position of the wiring board 2. It is set that the thickness of the wiring board 2 is A &mu;m, the thickness of the first semiconductor element 3 is B &mu;m, the thickness of the second semiconductor element 4 is, for instance thinner than that of the wiring board 2, C &mu;m, and the diameter of a projected electrode 5 is D &mu;m. The second semiconductor element 4 having a thickness of C &mu;m is arranged in the opening 2b formed in the wiring board 2 in the semiconductor device 1. This does not reflect the thickness of the second semiconductor element 4 to the thickness (X) of the lamination position of the semiconductor device 1. That is, X=(A+B+D) &mu;m. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device in which a plurality of semiconductor elements are mounted on a wiring board in a stacked positional relationship.
[0002]
[Prior art]
2. Description of the Related Art In recent years, a wiring board used for an electronic device has been reduced in size and size of a semiconductor device and various electronic components with the miniaturization of the device body.
[0003]
For example, in the hybrid integrated circuit disclosed in Japanese Patent No. 2841825, in order to increase the mounting density of the semiconductor elements, in a hybrid integrated circuit in which a plurality of semiconductor elements are mounted on a wiring board, at least one semiconductor element is connected by wire bonding. A structure is shown in which the semiconductor device is mounted on one surface of a wiring board by technology and at least one other semiconductor element is mounted on the surface on the side opposite to the wiring substrate by flip chip technology.
[0004]
[Patent Document 1] Japanese Patent No. 2841825 (Page 2, FIGS. 1 and 2)
[0005]
[Problems to be solved by the invention]
However, in the hybrid integrated circuit disclosed in Japanese Patent No. 2841825, although the mounting density per unit area is improved, when realizing higher-density lamination, the thickness of the wiring board itself and the thickness of the semiconductor element are increased. It will be an obstacle to conversion.
[0006]
The present invention has been made in view of the above circumstances, and when arranging a wiring substrate or a semiconductor element in a stacking positional relationship, the thickness of the stacked state is configured to be thinner, and a semiconductor device having a high-density stacked structure is realized. It is intended to provide.
[0007]
[Means for Solving the Problems]
A semiconductor device according to a first aspect of the present invention is a semiconductor device in which a plurality of semiconductor elements are mounted in a stacked positional relationship on a wiring board provided with a wiring layer,
At least one of the semiconductor elements or the wiring board provided with the wiring layer arranged in the stacking positional relationship, the thickness of the actual stacked state, the thickness of the plurality of semiconductor elements and the thickness of the wiring board, A lamination thickness adjusting unit for making the lamination thickness smaller than the total value is provided.
According to this configuration, by providing the stacked thickness adjusting unit and arranging the plurality of semiconductor elements on the wiring board in a stacked manner, the thickness of the semiconductor device configured in this stacked state is reduced by the plurality of semiconductor elements. Is smaller than the sum of the thickness of the wiring board and the thickness of the wiring board.
[0008]
A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the lamination thickness adjusting section is an opening provided at a predetermined position of the wiring board.
According to this configuration, one semiconductor element is arranged on one surface side of the wiring board so as to cover the opening of the wiring board, and another semiconductor element is arranged in the opening, and a plurality of semiconductor elements are arranged on the wiring board. On the other hand, in a stacked arrangement state, the thickness dimension of the semiconductor device configured in this stacked arrangement state is smaller than the sum of the thickness dimensions of the plurality of semiconductor elements and the wiring board.
[0009]
The semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first aspect, wherein the laminated thickness adjusting section is a recess having a predetermined depth dimension formed in one semiconductor element.
According to this configuration, when the plurality of semiconductor elements are stacked on the wiring substrate in a state where another semiconductor element is arranged in the recess of one semiconductor element, the thickness of the semiconductor device configured in this stacked arrangement is The height dimension is smaller than the sum of the thickness dimensions of the plurality of semiconductor elements and the wiring board.
[0010]
A semiconductor device according to a fourth aspect is a semiconductor device in which a plurality of semiconductor elements are mounted in a stacked positional relationship with respect to a semiconductor element provided with a wiring layer,
A concave portion serving as a laminated thickness adjusting section is formed in one of the semiconductor elements arranged in a laminated positional relationship.
According to this configuration, when the plurality of semiconductor elements are stacked on the semiconductor element provided with the wiring layer in a state in which another semiconductor element is arranged in the concave portion of one semiconductor element, the semiconductor device is configured in this stacked arrangement state. The thickness of the semiconductor device thus obtained is smaller than the sum of the thickness of the plurality of semiconductor elements and the thickness of the wiring board.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(1st Embodiment)
1 to 3 relate to a first embodiment of the present invention. FIG. 1 is a view for explaining a semiconductor device in which an opening is formed in a wiring board as a lamination thickness adjuster. FIG. FIG. 3 is a diagram illustrating an example of a configuration when the semiconductor device is stacked and arranged without providing a thickness adjusting unit. FIG. 3 is a diagram illustrating another example of a configuration of a semiconductor device.
[0012]
FIG. 3A is a diagram showing a semiconductor device in which an electrical connection portion through a through hole and flip-chip connection are combined, and FIG. 3B is a semiconductor device in which flip-chip connection and connection by wire bonding are combined. FIG. 3C is a diagram showing a semiconductor device in which a flip-chip connection provided with a wiring region is combined with a wire bonding connection. FIG. 3D is a semiconductor device provided with a wiring region provided by a flip-chip connection. FIG. 3E shows a semiconductor device in which connection by wire bonding and flip-chip connection are combined, and FIG. 3F shows a semiconductor device in which connection by wire bonding is performed. FIG. 3G shows a semiconductor device in which an optical member is arranged, and FIG. 3H shows three semiconductor elements provided for connection by wire bonding. It is a diagram showing a semiconductor device of a combination of a lip-chip connection.
[0013]
As shown in FIG. 1, a semiconductor device 1 of the present embodiment has a wiring board 2 having a wiring layer 2 a formed on one or both sides by a wiring pattern (not shown) on a surface portion, and a wiring layer 2 a of the wiring board 2. It is mainly constituted by a first semiconductor element 3 that is electrically connected and a second semiconductor element 4 that is electrically connected to the first semiconductor element 3. At a predetermined position of the wiring substrate 2, an opening 2b having a predetermined shape to be a lamination thickness adjusting portion in which the second semiconductor element 4 is arranged is formed.
[0014]
The electrical connection between the wiring layer 2a provided on the wiring board 2 and the first semiconductor element 3 and the electrical connection between the first semiconductor element 3 and the second semiconductor element 4 are made of, for example, gold or solder. This is achieved by flip-chip connection via the formed protruding electrodes 5. Then, the fixing of the flip chip connection portion is performed by the adhesive 9.
[0015]
The thickness of the wiring board 2 is A μm, the thickness of the first semiconductor element 3 is B μm, the thickness of the second semiconductor element 4 is, for example, C μm smaller than the thickness of the wiring board 2, Is set to D μm.
[0016]
The thickness dimension (X) of the semiconductor device 1 configured as described above will be described.
As shown in FIG. 2, the first semiconductor element 3 and the second semiconductor element 4 are arranged on both sides of a wiring board 2A having a thickness of A μm without an opening serving as a lamination thickness adjustment part in a lamination positional relationship. When the semiconductor device 20 is configured as described above, the thickness dimension (Y) at the lamination position is a value obtained by adding the thickness dimensions of the respective members. Reference numeral 6 denotes a wire formed of a thin metal wire for wire bonding.
That is, Y = (A + B + C + D) μm.
[0017]
On the other hand, in the semiconductor device 1 shown in FIG. 1 of the present embodiment, the second semiconductor element 4 whose thickness is set to C μm is arranged in the opening 2 b formed in the wiring board 2. You. Therefore, the thickness dimension of the second semiconductor element 4 is not reflected on the thickness dimension (X) at the stacking position of the semiconductor device 1.
[0018]
That is, X = (A + B + D) μm.
[0019]
Therefore, the thickness (X) of the semiconductor device 1 of the present embodiment at the stacking position is formed to be smaller than the thickness (Y) of the semiconductor device 20 at the stacking position.
[0020]
As described above, the opening is provided in the wiring board as the stack thickness adjusting section, and one of the semiconductor elements arranged in the stacking positional relationship is arranged in the opening, so that the semiconductor device is configured to be stacked and arranged. Can be made smaller than the total value of the plurality of semiconductor elements and the wiring board. This makes it possible to reduce the size and thickness of the semiconductor device having a laminated structure and achieve high-density mounting without complicating the structure of the wiring board.
[0021]
In the present embodiment, the electrical connection between the wiring board 2 and the first semiconductor element 3 and the electrical connection between the first semiconductor element 3 and the second semiconductor element 4 are made by flip-chip connection via the bump electrodes 5. However, the electrical connection is not limited to the flip-chip connection, and the following electrical connection may be performed to configure the semiconductor device. This makes it possible to reduce the size and thickness of the semiconductor device having a laminated structure and achieve high-density mounting.
[0022]
In the semiconductor device 1A shown in FIG. 3A, the first semiconductor element 3 is provided with a through-hole 3a extending from the front surface to the back surface of the element, and the through-hole 3a and the wiring layer 2a are formed via the bump electrode 5. Are electrically connected, and the first semiconductor element 3 and the second semiconductor element 4 are electrically connected by flip-chip connection via the protruding electrodes 5. Then, the bonding of the flip chip connection portion is performed by the adhesive 9.
[0023]
In the semiconductor device 1B shown in FIG. 3B, a through hole 3a is provided in the first semiconductor element 3, and the through hole 3a is electrically connected to the wiring layer 2a via the protruding electrode 5. The electrical connection between the second semiconductor element 4 and the wiring board 2 is performed by wire bonding via a wire 6 which is a thin metal wire.
[0024]
In the semiconductor device 1B shown in this figure, when connecting the through-hole 3a and the wiring layer 2a via the protruding electrode 5, electrical and mechanical connection is performed using ultrasonic waves, thermocompression bonding, soldering or the like. ing. Further, the first semiconductor element 3 and the second semiconductor element 4 are die-bonded with an insulating or conductive adhesive 9 in a back-to-back relationship. Then, the die bonding of the second semiconductor element 4 and the fixing of the first semiconductor element 3 and the wiring board 2 with the adhesive 9 are performed simultaneously, and thereafter, the second semiconductor element 4 is electrically connected to the wiring board 2 by wire bonding. ing.
[0025]
In the semiconductor device 1C shown in FIG. 3C, a wiring region 3b is provided in the first semiconductor element 3 from the element surface to the element side surface to the element back surface. Then, while the wiring region 3b and the wiring layer 2a are flip-chip connected via the protruding electrodes 5, the second semiconductor element 4 and the wiring substrate 2 are electrically connected by wire bonding via the wires 6. Is going.
[0026]
In addition, as shown in the semiconductor device 1D of FIG. 3D, the wiring region 3b is extended to the position where the second semiconductor element 4 is arranged, and the electrical connection between the wiring region 3b and the wiring layer 2a and the connection between the wiring region 3b and the wiring layer 2a are performed. The electrical connection between the first semiconductor element 3 and the second semiconductor element 4 may be both performed by flip-chip connection via the bump electrodes 5.
[0027]
In the semiconductor device 1E shown in FIG. 3E, the first semiconductor element 3 is electrically connected to the wiring layer 2a of the wiring board 2 by wire bonding via the wires 6, while the second semiconductor element 4 is connected to the first semiconductor element. The electrical connection with the element 3 is made by flip-chip connection.
[0028]
In the semiconductor device 1F shown in FIG. 3F, the electrical connection between the first semiconductor element 3 and the wiring layer 2a of the wiring board 2 and the electrical connection between the second semiconductor element 4 and the wiring layer 2a of the wiring board 2 are made. This is performed by wire bonding via the wire 6.
[0029]
In the semiconductor device 1F of this figure, the first semiconductor element 3 is die-bonded to the wiring board 2 with an insulating or conductive adhesive 9, and then the second semiconductor element 4 is dropped into the opening 2b. The second semiconductor element 4 is die-bonded to the back surface of the first semiconductor element 3 with an insulating or conductive adhesive 9. The first semiconductor element 3 and the second semiconductor element 4 are electrically connected to each other by wire bonding via wires 6.
[0030]
In the semiconductor device 1G shown in FIG. 3G, the optical member 7 is arranged on the first semiconductor element 3 or on at least one of the wiring board 2. At this time, when the first semiconductor element 3 is specifically an imaging element, the optical member 7 is an optical component such as a glass lid, a lens, a filter, and a prism. In the present embodiment, since the electrical connection between the second semiconductor element 4 and the wiring layer 2a of the wiring board 2 is performed by wire bonding via the wire 6, the wire 6 comes into contact with the optical member 7. In order to prevent this, the wiring board 2 is provided with a step 2c having a predetermined height for preventing contact.
[0031]
In the semiconductor device 1H shown in FIG. 3H, the third semiconductor element 8 is arranged on the first semiconductor element 3, and the optical member 7 is arranged on the wiring board 2 having the step 2c. Then, the first semiconductor element 3 is electrically connected to the wiring layer 2a of the wiring board 2 by flip-chip connection, and the third semiconductor element 8 is electrically connected to the wiring layer 2a of the wiring board 2 via the wire 6. Wire bonding.
[0032]
It should be noted that the semiconductor device 1H of this drawing has a three-chip configuration using three semiconductor elements, and the three chips are formed in a stack structure from the surface of the wiring board. After the first semiconductor element 3 is electrically connected to the wiring board 2 by flip-chip connection, the second semiconductor element 4 is die-bonded to the back surface of the first semiconductor element 3 with an adhesive 9. At this time, the adhesive 9 also serves to fix the flip chip connection portion of the first semiconductor element 3. Then, the second semiconductor element 4 and the wiring board 2 are electrically connected by wire bonding via the wires 6, and the third semiconductor element 8 is stacked on the upper surface of the first semiconductor element 3 by die bonding. The third semiconductor element 8 is electrically connected to the wiring board 2 by wire bonding via the wires 6.
Further, a three-chip configuration may be adopted by forming a stack structure from the back surface of the wiring board.
[0033]
(2nd Embodiment) ◎
4 to 7 relate to a second embodiment of the present invention. FIG. 4 is a view for explaining a semiconductor device in which a concave portion is provided in a semiconductor element as a laminated thickness adjusting portion. FIG. FIG. 6 is a diagram illustrating an example of a configuration in which components are stacked and arranged without providing an adjustment unit, FIG. 6 is a diagram illustrating a semiconductor device having another configuration, and FIG. 7 is a diagram illustrating a semiconductor device having another configuration.
FIG. 4A is a diagram illustrating a semiconductor device in which an opening serving as a laminated thickness adjusting unit is provided in a wiring substrate, and FIG. 4B is a diagram illustrating a semiconductor device in which a laminated thickness adjusting unit is not formed. FIG. 4 is a diagram illustrating a semiconductor device in which semiconductor elements are arranged in a stacked positional relationship.
As shown in FIG. 4A, a semiconductor device 10 of the present embodiment includes a wiring board 2 having a thickness of A μm provided with a wiring layer 2a and an opening 2b by a wiring pattern (not shown) on the surface, for example. The first semiconductor element 11 having a thickness of E μm electrically connected to the wiring layer 2a of the wiring board 2 via the wire 6 and electrically connected to the wiring layer 2a of the wiring board 2 by the wire bonding via the wire 6. And a second semiconductor element 12 having a thickness of F μm.
[0034]
At a predetermined position of the first semiconductor element 11, a concave portion 11a having a depth dimension of a predetermined dimension b μm serving as a lamination thickness adjusting section to which the second semiconductor element 12 is die-bonded by the adhesive 9 is formed by, for example, etching. ing.
[0035]
The thickness dimension of the semiconductor device 10 configured as described above will be described.
First, as shown in FIG. 5, the first semiconductor element 11 and the second semiconductor are arranged on both sides of a wiring board 2A having a thickness of A μm without an opening and a recess serving as a lamination thickness adjusting section in a lamination positional relationship. When the semiconductor device 20A is configured by disposing the elements 12, the thickness dimension (YA) at the lamination position is a value obtained by adding the thickness dimensions of the respective members.
[0036]
That is, YA = (A + E + F) μm.
[0037]
On the other hand, in the semiconductor device 10 of the present embodiment, as shown in FIG. 4A, the depth dimension in which the second semiconductor element 12 having the thickness dimension of F μm is formed in the first semiconductor element 11. Are fixed to the bottom surface of the recess 11a of b μm, and are disposed in the opening 2b in this state.
[0038]
Therefore, the second semiconductor element 12 fixed to the recess 11a of the first semiconductor element 11 is arranged without protruding from the opening 2b. As a result, the thickness dimension of the second semiconductor element 12 is not reflected on the thickness dimension (hereinafter, referred to as XA) of the stacked positional relationship of the semiconductor device 10.
That is, XA = (A + E) μm.
Thus, the thickness (XA) at the stacking position of the semiconductor device 10 of the present embodiment is formed smaller than the thickness (YA) at the stacking position of the semiconductor device 20A.
[0039]
As described above, a concave portion having a predetermined depth is provided as a laminated thickness adjusting portion in one of the semiconductor elements configured in the laminated positional relationship, and the other semiconductor element is fixedly disposed on the bottom surface of the concave portion, thereby achieving a laminated arrangement. The thickness dimension of the semiconductor device configured in the state can be made smaller than the total value of the plurality of semiconductor elements and the wiring board.
[0040]
Note that, even in the case where the opening 2b is not provided in the wiring board 2 as shown in FIG. 4B, a recess 11a having a predetermined depth is formed in the first semiconductor element 11, and the recess 11a is formed. When the semiconductor device 10A is configured by disposing the second semiconductor element 12 therein, the thickness F of the second semiconductor element 12 is not reflected in the thickness (XB) at the lamination position of the semiconductor device 10A. The thickness dimension (XB) of the semiconductor device 10A at the lamination position can be made smaller than the value obtained by adding the plurality of semiconductor elements and the wiring board and the like.
[0041]
Further, instead of mounting a plurality of semiconductor elements on a wiring board to form a semiconductor device, as shown in FIG. 6, at least one surface side of the third semiconductor element 13 is formed of an insulating resin layer using, for example, a polyimide resin or the like. The rewiring layer 14 is provided. Then, the second semiconductor element 12 and the third semiconductor element 13 are electrically and mechanically connected via the protruding electrodes 5, and the second semiconductor element 12 is disposed in the recess 11 a of the first semiconductor element 11. In this state, the first semiconductor element 11 is electrically and mechanically connected to the third semiconductor element 13 via the protruding electrode 5 to form a semiconductor device 10B.
Thus, the thickness dimension of the semiconductor device 10B at the lamination position can be made smaller than the total value of the plurality of semiconductor elements and the wiring board and the like.
[0042]
Note that the first semiconductor element 11 and the third semiconductor element 13 may be connected to each other after the second semiconductor element 12 is mounted on the third semiconductor element 13.
[0043]
In the first and second embodiments, for example, a redistribution layer 14 is formed in advance on the second semiconductor elements 4 and 12 as shown in FIG. The semiconductor device 10C may be configured by mounting the peripheral circuit components 15 such as a ceramic capacitor, a resistor, an inductor, and an oscillator. This makes it possible to reduce the size and thickness of the semiconductor device, reduce the number of assembly steps, and reduce the number of parts.
[0044]
It should be noted that the present invention is not limited to only the above-described embodiments, and various modifications can be made without departing from the spirit of the invention.
[0045]
[Appendix]
According to the above-described embodiment of the present invention as described in detail above, the following configuration can be obtained.
[0046]
(1) In a semiconductor device in which a plurality of semiconductor elements are mounted in a stacked positional relationship with respect to a wiring board provided with a wiring layer,
At least one of the semiconductor elements or the wiring board provided with the wiring layer arranged in the stacking positional relationship, the thickness of the actual stacked state, the thickness of the plurality of semiconductor elements and the thickness of the wiring board, A semiconductor device provided with a lamination thickness adjustment unit that makes the sum smaller than the sum.
[0047]
(2) The semiconductor device according to Supplementary Note 1, wherein the stacked thickness adjusting unit is an opening provided at a predetermined position of the wiring board.
[0048]
(3) The semiconductor device according to Supplementary Note 1, wherein the lamination thickness adjusting section is a recess formed in one semiconductor element.
[0049]
(4) In a semiconductor device in which a plurality of semiconductor elements are mounted in a stacked positional relationship with respect to a semiconductor element provided with a wiring layer,
A semiconductor device in which a concave portion serving as a laminated thickness adjusting portion is formed in one of semiconductor elements arranged in a laminated positional relationship.
[0050]
(5) The semiconductor device according to any one of supplementary notes 1 to 4, wherein the electrical connection between the semiconductor element and the wiring board or the electrical connection between the semiconductors is performed by a lip-chip connection.
[0051]
(6) The semiconductor device according to any one of supplementary notes 1 to 4, wherein electrical connection between the semiconductor element and the wiring board is performed by wire bonding connection.
[0052]
(7) The semiconductor device according to any one of supplementary notes 1 to 5, wherein a through-hole is provided in the semiconductor element from the front surface of the semiconductor element to the back surface of the semiconductor element, and electrical connection between the wiring substrate and the semiconductor element is performed via a protruding electrode. 13. The semiconductor device according to claim 1.
[0053]
(8) The semiconductor element is provided with a wiring region extending from the front surface of the semiconductor element to the back surface of the semiconductor element through the side surface of the semiconductor element, and electrically connecting the wiring substrate to the semiconductor element via the protruding electrode. 6. The semiconductor device according to any of supplementary notes 5.
[0054]
(9) The semiconductor device according to any one of supplementary notes 5 to 8, wherein an optical component or a peripheral circuit component is mounted on the semiconductor element or the wiring board.
[0055]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a semiconductor device having a high-density stacked structure by arranging a thinner layer in a stacked state when arranging wiring substrates or semiconductor elements in a stacked positional relationship. Can be.
[Brief description of the drawings]
FIGS. 1 to 3 relate to a first embodiment of the present invention, and FIG. 1 is a view for explaining a semiconductor device in which an opening is formed in a wiring board as a laminated thickness adjusting section. FIG. 3 is a diagram illustrating a configuration example when a semiconductor element is stacked without providing a stack thickness adjustment unit. FIG. 3 is a diagram illustrating another configuration example of a semiconductor device. FIG. FIG. 4 is a diagram illustrating a semiconductor device in which a recess is formed in a semiconductor element as a lamination thickness adjusting unit. FIG. 5 is a diagram illustrating a lamination without providing a lamination thickness adjusting unit in a wiring board and a semiconductor element. FIG. 6 illustrates a configuration example when arranged. FIG. 6 illustrates a semiconductor device having another configuration. FIG. 7 illustrates a semiconductor device having another configuration.
DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Wiring board 2a ... Wiring layer 2b ... Opening 3 ... 1st semiconductor element 4 ... 2nd semiconductor element

Claims (4)

In a semiconductor device in which a plurality of semiconductor elements are mounted in a stacked positional relationship with respect to a wiring board provided with a wiring layer,
At least one of the semiconductor elements or the wiring board provided with the wiring layer arranged in the stacking positional relationship, the thickness of the actual stacked state, the thickness of the plurality of semiconductor elements and the thickness of the wiring board, A semiconductor device provided with a lamination thickness adjusting section for making the lamination thickness smaller than the sum. 2. The semiconductor device according to claim 1, wherein the lamination thickness adjustment unit is an opening provided at a predetermined position on the wiring board. 3. 2. The semiconductor device according to claim 1, wherein the stacked thickness adjusting section is a recess having a predetermined depth dimension formed in one semiconductor element. 3. In a semiconductor device in which a plurality of semiconductor elements are mounted in a stacked positional relationship with respect to a semiconductor element provided with a wiring layer,
A semiconductor device, wherein a concave portion serving as a laminated thickness adjusting portion is formed in one of semiconductor elements arranged in a laminated positional relationship.

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