JP2004304855A - Image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image forming apparatus provided with an image processing apparatus capable of executing other data processing by allowing other CPU and other DMAC to use other data bus even when one CPU and one DMAC exclusively use a data bus. <P>SOLUTION: A first interface control section controls a first FIFO memory and a memory control section controls a third FIFO memory to attain transfer of data from a scanner section or a communication control section to the memories and a second interface control section controls a second FIFO memory and the memory control section controls the third FIFO memory to attain transfer of data from the memories to a printer section or the communication control section so as to allow the memories to access the first and second data buses in time series. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image forming apparatus such as a copying machine, a printer, and a facsimile.

  In recent years, digital copiers that form images based on image data obtained from document images have been used. In this type of copier, image information of a document is read by a scanner or the like, and the image information of the document is temporarily stored in an image memory. The image information stored in the image memory is subjected to image processing such as reduction, enlargement, and rotation of the image in response to a user request. Thus, the image of the original can be copied onto a predetermined transfer sheet based on the image data on which the image processing has been performed.

  In this type of digital copying machine, a large-capacity memory is provided for temporarily storing image information of a document, and a technique for efficiently transferring the image information is required.

  FIG. 7 is a block diagram showing a configuration example of a conventional image forming apparatus 500 using this type of image memory. This image forming apparatus 500 has a CPU bus 1 shown in FIG. The CPU bus 1 is connected to a system control unit 2, an image memory 3, a direct memory access controller (hereinafter simply referred to as a DMAC) 4, an image acquisition unit 5, and an image reproduction unit 6.

  The system control means 2 connected to the CPU bus 1 has a CPU 2a, a ROM 2b, a RAM 2c, and an operation unit 2d. The CPU 2a is an IC that controls the entire image forming apparatus 500, and its control program is stored in the ROM 2b. The RAM 2c is a memory temporarily used when the CPU 2a performs an operation, and is necessary for executing a control program.

  For example, when a control instruction such as a start instruction is output to the image acquisition unit 5 or the image reproduction unit 6, the control instruction is written into the RAM 2 c by the CPU 2 a, and thereafter, when a write end notification of the image data is given, It is checked whether it is for the control command.

  The operation unit 2d is necessary for an interface between the user and the apparatus, and the CPU 2a executes predetermined data processing according to the instruction. The image memory 3 connected to the CPU bus 1 is a relatively large-capacity memory having a capacity for a plurality of pages. Although not shown, code data is accumulated by performing an encoding process. The DMAC 4 performs data transfer between devices without the intervention of the CPU 2a, and can perform data transfer at a higher speed than the CPU 2a.

  The image acquisition unit 5 connected to the CPU bus 1 has a scanner interface 5a, a scanner unit 5b, and a page memory 5c. The scanner interface 5a controls the driving of the scanner unit 5b and controls the writing and reading of image data (DATA) in the page memory 5c. The page memory 5c is a memory for storing one page of image data from the scanner unit 5b, and is necessary for matching the data transfer speed between the scanner unit 5b and the CPU 2a and improving the use efficiency of the CPU bus 1.

  Further, the image reproducing means 6 connected to the CPU bus 1 has a printer interface 6a, a page memory 6b, and a printer section 6c. The printer interface 6a controls the driving of the printer unit 6c and controls the writing and reading of image data in the page memory 6b. The page memory 6b is a memory for storing one page of data to be written to the printer unit 6c, and is necessary for matching the data transfer speed between the printer 6c and the CPU 2a and improving the use efficiency of the CPU bus 1.

  Next, the operation of the image forming apparatus 500 will be described. First, a copy operation for a single original will be described. First, when a one-page copy instruction is received from the operation unit 2d, the CPU 2a instructs the image acquisition unit 5 to drive the scanner. Upon receiving this instruction, the scanner interface 5a drives the scanner section 5b, acquires image data of the document from the scanner section 5b, and sequentially stores the image data in the page memory 5c. When one page of image data is stored in the page memory 5c, the scanner interface 5a notifies the CPU 2a of the end of reading the image data.

  The CPU 2a receiving this notification instructs the DMAC 4 to transfer image data from the scanner interface 5a to the printer interface 6a. Then, the image data for one page is transferred from the page memory 5c for the scanner to the page memory 6b for the printer. When the transfer of the image data of one page is completed, the DMAC 4 notifies the CPU 2a of the completion of the transfer. The CPU 2a receiving this notification instructs the image reproducing means 6 to drive the printer. The image data is read from the page memory 6b by the printer interface 6a receiving this instruction, and the image data is output to the printer unit 6c. The printer unit 6c can copy the image of the document on a transfer paper or the like based on the image data of one page.

  Next, the operation when copying a plurality of copies of a plurality of documents will be described. First, the CPU 2a that has received the instruction from the operation unit 2d instructs the image acquisition unit 5 to drive the scanner. In the scanner interface 5a receiving this instruction, the image data for one page acquired by the scanner unit 5b is stored in the page memory 5c, and then the image data for one page is sent from the scanner interface 5a to the CPU 2a. The end of reading is notified. The CPU 2a that has received this notification instructs the DMAC 4 to transfer data, so that the image data stored in the page memory 5c is transferred to the image memory 3.

  This series of operations is repeated by the number of documents, and all image data is stored in the image memory 3. Thereafter, the stored image data is transferred to the printer interface 6a according to an instruction from the CPU 2a. At this time, when one page of image data is stored in the printer page memory 6d from the image memory 3 by the DMAC 4, the CPU 2a instructs the printer interface 6a to start the printer.

  When one page of image data is output to the printer unit 6c by the printer interface 6a receiving this instruction, the CPU 2a is notified of the end of printing. The CPU 2a having received the notification instructs the DMAC 4 to transfer the image data of the next page, and the printing is started.

  This series of operations is repeated by the number of documents, so that the first copy is completed. In this example, since multiple copies are instructed to the CPU 2a, the DMAC 4 is instructed to transfer the image data of the first page from the image memory 3 to the printer interface 6a again. Thereafter, the same operation is repeated for the set number of copies, so that a plurality of copies can be made.

  By the way, according to the conventional image forming apparatus 10, there is a demand for a data processing apparatus in which a printer and a facsimile function are combined with a copying function by adding communication means to the apparatus. In response to this request, the image memory 3 must be used efficiently for performing so-called memory communication or broadcast communication. However, in the conventional method, the image memory 3, the DMCA 4, the image acquisition unit 5 and the image reproduction unit 6 are connected to one CPU bus 1, and the page memories 5 c and 6 b are connected to each of the units 5 and 6. I have.

  Therefore, since the page memories 5c and 6b for the scanner and the printer are not used except during the operation of the scanner unit 5c and the printer unit 6c, there is a problem in system construction that the memory use efficiency is deteriorated. Incidentally, the page memories 5c and 6b have a capacity for recording image data of the largest document size (for example, A3 size). As a result, when copying a document smaller than the A3 size, an unused memory area is generated, and the memory use efficiency is reduced.

  Further, when copying a plurality of copies of a plurality of originals, that is, when reading one page of image data and then simultaneously performing a plurality of copies while printing out the first page of the original, the DMAC 4 is used for a scanner. Image data must be transferred from the page memory 5c to both the image memory 3 and the page memory 6b for the printer. Therefore, the image data must be transferred twice, which is about twice as long as the data transfer time for a single original.

  Further, since the transfer speed of the DMAC 4 connected to the CPU bus 1 changes depending on the bus occupancy of the CPU 2a, the DMAC 4 may overwrite the image data of the previous page with the image data of the next page. This is because, when the transfer speed of the DMAC 4 is reduced due to a change in the bus occupancy of the CPU 2a, the image data of the next page is not transferred before all the image data of one page is transferred from the page memory 5a to the image memory 3. Occurs when the reading of a has started.

  Similarly, if an instruction to start up the printer is given before the image data for one page is stored in the page memory 6b, an underflow of the image data may occur and the upper part of the document may not be copied. If the DMAC (hereinafter also referred to as an external device) 4 is made to occupy the CPU bus 1 in preference to the CPU 2a in order to avoid such a state, the processing speed of the CPU 2a is reduced or the CPU bus (hereinafter also referred to as a data bus) is used. 1) and a facsimile process using an image memory (hereinafter also referred to as data memory) 3 by a CPU (hereinafter referred to as an external device) 2a.

  In view of the above, the present invention has solved the above-described problem. Even when one external device occupies a data bus, the other external device executes another data process using another data bus. It is another object of the present invention to provide an image forming apparatus including a data processing device capable of chronologically sharing a data memory with an external device connected to each data bus.

The invention according to claim 1 includes a first data bus,
A communication control unit connected to the first data bus;
A second data bus;
A printer unit connected to the second data bus and performing image formation based on data;
Memory for data,
Writing and reading data between the memory and the first data bus, writing and reading data between the memory and the second data bus, and And three-way interface means for performing data transfer between the first data bus and the second data bus.
The three-way interface means includes:
A first interface unit connected to the first data bus;
A second interface unit connected to the second data bus;
Memory control means for controlling writing and reading of data to and from the memory,
A first FIFO memory for temporarily storing data input from the first interface unit;
A second FIFO memory for temporarily storing data output to the second interface unit;
A third FIFO memory for temporarily storing data to be written and read by the memory control means;
By controlling the first interface unit and the memory control unit, it is possible to transfer data from the communication control unit to the memory,
By controlling the first interface unit and the memory control unit, it is possible to transfer data from the memory to the printer unit,
An image forming apparatus, comprising: a control unit that controls the first data bus and the second data bus so as to be able to access the memory in a time-series manner.

The invention according to claim 2 is an image forming apparatus having a printer unit that forms an image based on data,
A first data bus;
A communication control unit connected to the first data bus;
A second data bus;
A scanner unit connected to the second data bus;
A memory for the data;
Writing and reading data between the memory and the first data bus, writing and reading data between the memory and the second data bus, and Three-way interface means for performing data transfer between a data bus and the second data bus,
The three-way interface means includes:
A first interface unit connected to the first data bus;
A second interface unit connected to the second data bus;
Memory control means for controlling writing and reading of data to and from the memory,
A first FIFO memory for temporarily storing data output to the first interface unit;
A second FIFO memory for temporarily storing data input from the second interface unit;
A third FIFO memory for temporarily storing data to be written and read by the memory control means;
By controlling a second interface unit and the memory control unit, it is possible to transfer data from the scanner unit to the memory,
By controlling the first interface unit and the memory control unit, it is possible to transfer data from the memory to the communication control unit,
An image forming apparatus, comprising: a control unit that controls the first data bus and the second data bus so as to be able to access the memory in a time-series manner.

  The invention according to claim 3, wherein a control command for input / output control of the first interface unit, the second interface unit, and the memory control unit, and the first, second, and third FIFO memories 3. The image forming apparatus according to claim 1, further comprising a control memory for temporarily storing a control command for performing the data write / read control. 4.

  According to the present invention, since the memory can be shared by the scanner unit and the printer unit, a page memory as in the conventional system is not required, and the use efficiency of the memory is improved.

  In addition, since data transfer control in which one data bus is divided into two can be performed, for example, an external device connected to the first data bus writes and reads data to and from a data memory. The data writing / reading between the second data bus and the data memory is stopped, or the same data read from the data memory is transferred to the second data bus. Or you can.

  Therefore, when an external device connected to the first data bus is writing and reading data to and from the data memory, the second data bus can be opened to another external device. . At the same time, an external device connected to the first data bus and an external device connected to the second data bus can share a data memory in chronological order or simultaneously.

  Further, according to the present invention, it is possible to divide one data bus into two and perform data transfer between the two data buses, and to place an excessive control burden on a higher-level control device or the like. It is possible to construct a data processing system that does not run.

  Hereinafter, a data processing device and a system construction method according to an embodiment of the present invention will be described with reference to the drawings.

(1) Configuration Example of Interface Device FIG. 1 is a diagram illustrating a configuration example of an interface device applied to a data processing device according to this embodiment.

  In the present embodiment, a three-way interface is connected to a data memory and a data bus divided into two, and an external device connected to one data bus is connected to the data memory. When writing / reading data at the same time, the other data bus can be opened to other external devices, and the data memory can be stored in time series or simultaneously by external devices connected to each data bus. It is designed to be shared.

  The interface device 100 is used by being connected between the first data bus 11 and the second data bus 12 shown in FIG. A bidirectional first interface unit 13 is connected to the data bus 11, and data is input and output to and from the data bus 11. A FIFO memory 14a as a first data memory is connected to an output stage to the inside of the interface unit 13, and data input from the data bus 11 is temporarily recorded. The FIFO memory 14a is required to match the data transfer speed between the two data buses. Data from the FIFO memory 14a is output first from the first input.

  A second interface unit 16 is connected to an output stage of the FIFO memory 14a via an internal data bus 15a. A data bus 12 is connected to an output stage to the outside of the interface unit 16, and data from the data bus 11 is output to the data bus 12.

  Further, a FIFO memory 14b as a second memory for data is connected to an output stage to the inside of the interface unit 16, and the data input from the data bus 12 is temporarily recorded for the above-described reason. This data is output first from the first input. The interface section 13 is connected to an output stage of the FIFO memory 14b via an internal data bus 15b. A data bus 11 is connected to an output stage to the outside of the interface unit 13, and data from the data bus 12 is output to the data bus 11.

  Further, a control memory 17 is connected between the two interface units 13 and 16. For example, when a data processing system including this interface device 100 is constructed, control from a higher-level control device or the like is performed. The command D1 is temporarily recorded. In this example, the control memory 17 has a command register 17a and a status register 17b. The control command D1 described above is recorded in the command register 17a.

  As a method of accessing the interface device 100, a method using a uniquely determined chip select signal, a method using an address decoding method, and the like can be considered. In the address decoding method, when an address Add mapped in advance to a ROM or the like is accessed, the address is driven onto the data bus 11 by a control device or the like at the time of access. This is a method of setting an address register in the interface device 100 and receiving an access by decoding the address in the interface device 100. In the following description, the latter case will be described.

  For example, an interface control unit 18 is provided in the interface unit 13 or the interface unit 16, and performs data write / read control of the FIFO memories 14a and 14b based on a control command D1 recorded in a command register 17a. Input / output of the units 13, 16 and the internal data buses 15a, 15b is controlled.

  The interface control unit 18 includes an address register 18a, a decoder 18b, a timing generation circuit 18c, and the like shown in FIG. An address addressed to the interface device 100 is set in the address register 18a at the time of access. Whether the access is addressed to the interface device 100 is determined by decoding the address by the decoder 18b. This decoder 18b is also used for decoding the control instruction D1. The switch control signals S1 to S4 are generated in the timing generation circuit 18c based on the decoding result of the control instruction D1.

  The switch control signal S1 is used for bus switching of the interface unit 13, and the switch control signal S2 is used for bus switching of the interface unit 16. The memory control signal S3 is used for writing and reading of the FIFO memory 14a, and the memory control signal S4 is used for writing and reading of the FIFO memory 14b.

  Control notification information is temporarily recorded in the status register 17b. The control notification information is such as end status data D2 indicating the result of data transfer executed with respect to the control command D1, and the control device or the like in the upper system receives the end status data D2, and then receives the interface status first. It can be determined whether the data processing for the control command D1 given to the device 100 has been completed.

  Next, the operation of the interface device 100 will be described with reference to FIG. In this example, when data is transferred between the data buses 11 and 12, the control command D1 is written in the command register 17a.

  For example, when data is transferred from the data bus 11 to the data bus 12, a control instruction D1 to that effect is written to the command register 17a. When the control command D1 is received by the interface control unit 18, the control command D1 is decoded by the interface control unit 18, and the data bus 11 is connected to the internal data The internal data bus 15a is connected to the data bus 12 in the interface unit 16 based on the switch control signal S2.

  Then, the data input from the data bus 11 is temporarily recorded in the FIFO memory 14a based on the memory control signal S3. This is to match the data transfer speed on the data bus 11 with the data transfer speed on the data bus 12. The data is first read out from the FIFO memory 14a in order based on the memory control signal S3, and is output to the data bus 12 through the interface unit 16.

  When data is transferred from the data bus 12 to the data bus 11, a control instruction D1 to that effect is written to the command register 17a. When the control command D1 is received by the interface control unit 18, the data bus 11 is connected to the internal data bus 15b in the interface unit 13 based on the switch control signal S1 decoded by the interface control unit 18, and the interface unit 16 Internal data bus 15b is connected to data bus 12 based on switch control signal S2. Then, the data input from the data bus 12 is temporarily recorded in the FIFO memory 14b based on the memory control signal S4, and the data transfer speeds of the data buses 11 and 12 are matched. The data is first read out from the FIFO memory 14b based on the memory control signal S4, and is output to the data bus 11 through the interface unit 13 in order.

  When this data transfer is completed, the end status data D2 is written into the status register 17b. It is to be noted that the end status data D2 of the interface device 100 itself is written into the status register 17b, and a large number of such interface devices 100 are arranged at nodes at which the data bus is divided, thereby constructing a data processing system. Then, the end status data D2 from another interface device 100 is also recorded.

  By doing so, by confirming the recorded contents of the status register 17b of the interface device 100 arranged closest to the control device of the system, the control given to the interface device 100 close to the terminal device in the data processing system can be confirmed. It is possible to easily determine whether the data processing for the instruction D1 has been completed.

  As described above, according to the interface device 100 according to the present embodiment, after the control command D1 is once written in the command register 17a, the interface units 13, 16 and the internal data bus 15a are based on the control command D1. , 15b, and write / read control of the FIFO memories 14a, 14b, so that data can be transferred between the data buses 11, 12 independently of a higher-level control device connected to the interface device 100. can do.

  Therefore, after writing the control command D1, the control device does not need to manage the input / output of the interface device 100 itself, so that the data processing load on the control device can be reduced.

  Further, in the present embodiment, the end status data D2 indicating the data transfer result executed with respect to the control command D1 is temporarily recorded in the status register 17b. Therefore, by reading the data D2 from the command register 17b, the control command D1 is read. Can easily confirm the result of data transfer executed for. Therefore, data processing by handshaking can be performed between the control device and the interface device 100, and data processing by handshaking can be performed between the plurality of interface devices 100.

  Next, the three-way interface device 200 according to the present embodiment will be described. FIG. 3 is a block diagram illustrating a configuration example of a three-way interface device 200 according to the present embodiment.

  In this embodiment, a branch data bus branched from the internal data buses 15a and 15b is connected, a memory control means is connected to the branch data bus, and data input and output by the interface units 13 and 16 are based on the control instruction D1. In this case, writing and reading are controlled. Note that the components having the same reference numerals and the same names as those of the interface device 100 have the same functions, and the description thereof is omitted.

  The three-way interface device 200 is provided with an internal bus selector 21 shown in FIG. The internal bus selector 21 has a switch circuit 21a for selecting two circuits and one switch circuits 21b and 21c shown in FIG. Of course, these switch circuits 21a to 21c may use a transistor circuit integrated by a field effect transistor, a bipolar transistor, or the like.

  The point a of the switch circuit 21a is connected to the internal data bus 15a of the output stage of the FIFO memory 14a, and the point b is connected to the internal data bus 15b of the output stage of the FIFO memory 14b. The neutral point n of the switch circuit 21a is connected to a write memory bus 22a as a branch data bus. The memory bus 22a is connected to a FIFO memory 23a as a third memory for data, and temporarily stores write data branched from the internal data bus 15a or 15b. A memory control unit 24 is connected to an output stage of the FIFO memory 23a, and controls writing and reading of data branched from the internal data bus 15a or 15b. A data memory such as the image memory 3 is connected to an output stage to the outside of the memory control means 24.

  In addition, a FIFO memory 23b is connected to an output stage to the inside of the memory control means 24, and read data to be output to the internal data bus 15a or 15b is temporarily stored. A read memory bus 22b is connected to an output stage of the FIFO memory 23b. This memory bus 22b is connected to the contact n of the switch circuits 21b and 21c. The point a of the switch circuit 21b is connected to the input stage of the interface unit 16 via the internal data bus 15a, and the point b of the switch circuit 21c is connected to the input stage of the interface unit 13 via the internal data bus 15b.

  An interface control unit 28 is provided in the interface unit 13 or 16 in place of the interface control unit 18. The interface control unit 28 has an address register 28a, a decoder 28b and a timing generation circuit 28c, and these functions are almost the same as those of the address register 18a, the decoder 18b and the timing generation circuit 18c of the interface control unit 18. The interface control unit 28 controls the data writing and reading of the FIFO memories 14a and 14b and 23a and 23b based on the control command D1 recorded in the command register 17a, and controls the input and output of the interface units 13 and 16 and the internal data buses 15a and 15b. Output control and switch control of the switch circuits 21a to 21c are performed.

  The interface control unit 28 decodes the control command D1 to generate the switch control signals S1 to S4 in the same manner as the interface control unit 18, and also uses the timing generation circuit 28c to switch the switch control signal used for switching the bus of the switch circuit 21a. S5, a switch control signal S6 used for switching the bus of the switch circuit 21b, a memory control signal S7 used for writing and reading in the FIFO memory 23a, and a memory control signal S8 used for writing and reading in the FIFO memory 23b. , A switch control signal S9 used for short-circuiting the bus of the switch circuit 21c and the like are generated.

Next, the operation of the interface device 200 will be described with reference to FIG. In this example, a control instruction D1 relating to the following nine data transfer events is written in the command register 17a. This data transfer event
(1) When transferring data (data through) from the data bus 11 to the data bus 12,
(2) When writing data from the data bus 11 to the image memory 3,
(3) When writing data from the data bus 11 to the image memory 3 and simultaneously transferring the same data to the data bus 12,
(4) When transferring data from the data bus 12 to the data bus 11 (data through),
(5) When writing data from the data bus 12 to the image memory 3,
(6) When writing data from the data bus 12 to the image memory 3 and simultaneously transferring the same data to the data bus 11,
(7) When reading data from the image memory 3 to the data bus 11,
(8) Reading data from the image memory 3 to the data bus 12, and (9) Reading the same data from the image memory 3 to the data bus 11 and the data bus 12.

  For example, when the control command D1 relating to the data transfer event (1) is written in the command register 17a, when the control command D1 is received by the interface control unit 28, the control command D1 is decoded by the interface control unit 28. The data bus 11 is connected to the internal data bus 15a in the interface unit 13 based on the switch control signal S1, which is the decoding result, and the internal data bus 15a is connected to the data bus 12 in the interface unit 16 based on the switch control signal S2. Connected.

  In the switch circuit 21a, the memory bus 22a is disconnected from the internal data bus 15a based on the switch control signal S5. Similarly, in the switch circuit 21a, the memory bus 22b is disconnected from the internal data bus 15b based on the switch control signal S6. Then, the data input from the data bus 11 is temporarily recorded in the FIFO memory 14a based on the memory control signal S3. The data is first read out from the FIFO memory 14a in order based on the memory control signal S3, and is output to the data bus 12 through the interface unit 16. Thereby, data can be transferred (data through) from the data bus 11 to the data bus 12. When the control command D1 relating to the data transfer event (2) is written in the command register 17a, the data bus 11 is connected to the internal data bus 15a based on the switch control signal S1 decoded by the interface control unit 28. In the switch circuit 21a, the memory bus 22a and the internal data bus 15a are connected based on the switch control signal S5.

  Then, the data input from the data bus 11 is temporarily recorded in the FIFO memory 14a based on the memory control signal S3. The data recorded first in the FIFO memory 14a is sequentially recorded in the FIFO memory 23a. The data recorded in the FIFO memory 23a is read out based on the memory control signal S7 and written in the image memory 3.

  At this time, the memory bus 22b remains disconnected from the internal data bus 15b. In this case, the data bus 12 and the internal data buses 15a and 15b may be connected in any manner. Thereby, data can be written from the data bus 11 to the image memory 3.

  Further, when the control command D1 related to the data transfer event (3) is written in the command register 17a, the data bus 11 is connected to the internal data bus 15a based on the switch control signal S1 decoded by the interface control unit 28. The internal data bus 15a is connected to the data bus 12 based on the switch control signal S2. In the switch circuit 21a, the memory bus 22a and the internal data bus 15a are connected based on the switch control signal S5.

  Then, the data input from the data bus 11 is temporarily recorded in the FIFO memory 14a based on the memory control signal S3. The data recorded first in the FIFO memory 14a is sequentially recorded in the FIFO memory 23a. At the same time, data recorded in the FIFO memory 14a is output to the data bus 12. The data recorded in the FIFO memory 23a is read out based on the memory control signal S7 and written in the image memory 3. Thereby, the same data can be transferred from the data bus 11 to the image memory 3 and transferred to the data bus 12 at the same time.

  When the control command D1 relating to the data transfer event (4) is written in the command register 17a, the data bus 11 is connected to the internal data bus 15b based on the switch control signal S1 decoded by the interface control unit 28. The internal data bus 15b is connected to the data bus 12 based on the switch control signal S2.

  In the switch circuit 21a, the memory bus 22a is disconnected from the internal data bus 15a based on the switch control signal S5. Similarly, in the switch circuit 21a, the memory bus 22b is disconnected from the internal data bus 15b based on the switch control signal S6. Then, the data input from the data bus 12 is temporarily recorded in the FIFO memory 14b based on the memory control signal S4. The data is first read out from the FIFO memory 14b based on the memory control signal S4, and is output to the data bus 11 through the interface unit 13 in order. As a result, data can be transferred from the data bus 12 to the data bus 11 (data through). Next, when the control command D1 relating to the data transfer event (5) is written into the command register 17a, the data bus 12 is connected to the internal data bus 15b based on the switch control signal S2 decoded by the interface control unit 28. In the switch circuit 21a, the memory bus 22a and the internal data bus 15a are connected based on the switch control signal S5.

  Then, the data input from the data bus 12 is temporarily recorded in the FIFO memory 14b based on the memory control signal S4. The data recorded first in the FIFO memory 14b are sequentially recorded in the FIFO memory 23a. The data recorded in the FIFO memory 23a is read out based on the memory control signal S7 and written in the image memory 3.

  At this time, the memory bus 22b remains disconnected from the internal data bus 15b. In this case, the data bus 11 and the internal data buses 15a and 15b may be connected in any manner. Thereby, data can be written from the data bus 12 to the image memory 3.

  When the control command D1 related to the data transfer event (6) is written in the command register 17a, the data bus 11 is connected to the internal data bus 15b based on the switch control signal S1 decoded by the interface control unit 28, and Internal data bus 15b is connected to data bus 12 based on control signal S2. In the switch circuit 21a, the memory bus 22a and the internal data bus 15a are connected based on the switch control signal S5.

  Then, the data input from the data bus 12 is temporarily recorded in the FIFO memory 14b based on the memory control signal S4. The data recorded first in the FIFO memory 14b are sequentially recorded in the FIFO memory 23a. At the same time, the data recorded in the FIFO memory 14b is output to the data bus 11. The data recorded in the FIFO memory 23a is read out based on the memory control signal S7 and written in the image memory 3. Thus, the same data can be transferred from the data bus 12 to the image memory 3 and transferred to the data bus 11 at the same time.

  When the control command D1 related to the data transfer event (7) is written in the command register 17a, the data bus 11 is connected to the internal data bus 15b based on the switch control signal S1 decoded by the interface control unit 28, and the switch In the circuit 21b, the memory bus 22b and the internal data bus 15b are connected based on the switch control signal S6. In this example, the switch circuit 21c is turned on by the switch control signal S9.

  Then, the data read from the image memory 3 is temporarily recorded in the FIFO memory 23b based on the memory control signal S8. The data recorded first in the FIFO memory 23b is output to the data bus 11 through the interface unit 13 in order from the first. At this time, the memory bus 22a is disconnected from the internal data bus 15b. In this case, the internal data bus 15b is separated from the data bus 12 based on the switch control signal S2. Thus, data can be read from the image memory 3 to the data bus 11.

  When the control command D1 relating to the data transfer event (8) is written in the command register 17a, the data bus 11 is disconnected from the internal data bus 15a based on the switch control signal S1 decoded by the interface control unit 28, and In the circuit 21b, the memory bus 22b and the internal data bus 15a are connected based on the switch control signal S6.

  Then, the data read from the image memory 3 is temporarily recorded in the FIFO memory 23b based on the memory control signal S8. The data recorded in the FIFO memory 23b is output to the data bus 12 through the interface unit 16 in order from the data recorded first. At this time, the memory bus 22a is disconnected from the internal data bus 15b. In this case, the internal data bus 15a is separated from the data bus 11 based on the switch control signal S1. Thus, data can be read from the image memory 3 to the data bus 12. When the control command D1 relating to the data transfer events (1) to (6) and (8) is executed, the switch circuit 21c is kept off by the switch control signal S9.

  When the control command D1 relating to (9) is written into the command register 17a, the data bus 11 is connected to the internal data bus 15b based on the switch control signal S1 decoded by the interface control unit 28, and the switch control is performed. Data bus 12 is connected to internal data bus 15a based on signal S2. Moreover, in the switch circuit 21b, the memory bus 22b and the internal data bus 15a are connected based on the switch control signal S6, and the switch circuit 21c is turned on based on the switch control signal S9, and the internal data buses 15a and 15b are short-circuited. .

  Then, the data read from the image memory 3 is temporarily recorded in the FIFO memory 23b based on the memory control signal S8. The data recorded first in the FIFO memory 23b is sequentially output to the data bus 11 through the interface unit 13 and is output to the data bus 12 through the interface unit 16. At this time, the memory bus 22a is disconnected from the internal data buses 15a and 15b. Thereby, the same data can be read from the image memory 3 to the data bus 11 and the data bus 12. When any of these data transfer events (1) to (9) ends, end status data D2 is written to the status register 17b to notify the result of the data transfer.

  As described above, according to the three-way interface device 200 of the present embodiment, after the control command D1 is written from the control device of the system to the command register 17a, the data bus 11 is connected independently of the control device. Data can be written to the image memory 3 or the like, and data can be read from the image memory 3 onto the data bus 12.

  Therefore, when a data processing system such as an office computer system or an image forming apparatus is constructed, one data bus is divided into two, and data is transferred between the two data buses 11 and 12. The bidirectional interface device 100 according to the present embodiment is designed to be arranged between the two data buses 11 and 12.

  In addition, data can be written and read between the only image memory 3 and the data bus 11, data can be written and read between the image memory 3 and the data bus 12, and , And 12, the three-way interface device 200 according to the present embodiment is arranged between the image memory 3 and the data buses 11 and 12. A command register 17a may be provided in each of the interface devices 100 and 200, and the control command D1 may be written in the command register 17a to control the input and output of the interface devices 100 and 200.

  Subsequently, a data processing device using the interface devices 100 and 200 will be described.

(2) Configuration Example of Data Processing Device FIG. 5 is a block diagram illustrating a configuration example of the data processing device 300 according to the present embodiment.

  In this embodiment, a three-way interface device 200 is connected between a main storage device 30 shown in FIG. 5 and two divided data buses A and B, and a terminal device connected to one data bus B. When the data writing / reading is performed between the main control device 40 and the main storage device 30, the other data bus A can be opened to the main control device 10, and the data bus A is connected to each data bus A or B. The main storage device 30 can be shared in time series or simultaneously by the main control device 10, the sub-control device 20, the terminal devices 40, 50, and the like.

  The data processing device 300 is provided with a main storage device 30 shown in FIG. 5 as a data memory. The above-described three-way interface device 200 is connected to the main storage device 30, and data is transferred between the main storage device 30 and the data bus A by a control command D1 written in a command register 17a therein. Writing and reading are performed, data is written and read between the main storage device 30 and the data bus B, and data transfer is performed between the two data buses A and B.

  In this example, the data bus A is provided with two bidirectional interface devices 101 and 102. One interface device 101 is connected to the data bus A, to the other interface device 102 and the three-way interface device 200, and to the main control device 10 as an external device through the CPU bus 1a.

  Similarly, the other interface device 102 is connected to the data bus A to be connected to the three-way interface device 200, and is also connected to the sub-control device 20 as an external device through the CPU bus 1b. Further, a bus arbitration unit 60 as a first arbitration unit is connected to the data bus A, and arbitration of the right to use the bus of the interface devices 101 and 102 is performed so that data collision does not occur.

  The data bus B is also provided with two bidirectional interface devices 103 and 104. One interface device 103 is connected to the data bus B, to the other interface device 104 and the three-way interface device 200, and to the terminal device 40 as an external device through the terminal bus 40a.

  Similarly, the other interface device 104 is connected to the data bus B and connected to the three-way interface device 200, and is also connected to the terminal device 50 as an external device through the terminal bus 50a. Further, a bus arbitration unit 70 as a second arbitration unit is connected to the data bus B, and arbitration of the bus use right of the interface devices 103 and 104 is performed.

  As the interface devices 101 to 104 described above, the bidirectional interface device 100 according to the present embodiment is used, and data transfer control is performed by a control command D1 written in a command register 17a provided therein. . In this example, at least when data is transferred between the data bus A and the main storage device 30, when data is transferred between the main storage device 30 and the data bus B, or when data is transferred between the data buses A and B. When performing the transfer, the control command D1 is written to the command register 17a in the interface device 200. The control command D1 is written by the main control device 10 or the sub control device 20.

  Next, the operation of the data processing device 300 will be described. For example, the description will be made on the assumption that data is written from the terminal device 40 to the main storage device 30. In this case, the control command D1 related to the data transfer event (5) described above is written in the command register 17a of the interface device 200.

  Prior to this, first, a control command D1 relating to the data transfer event (1) is written from the main controller 10 to a command register 17a (not shown) in the interface device 101 and a command register 17a (not shown) in the interface device 200. . Next, the control command D1 related to the data transfer event (4) is written from the main control device 10 to the interface device 103, and then the control command D1 related to the data transfer event (5) is written to the interface device 200.

  When each of the control commands D1 is decoded by the interface devices 101, 200, and 103, the data bus B and the terminal bus 40a are connected in the interface device 103, and the data bus B and the memory bus 30a are connected in the interface device 200. Connected. The operation inside each of the interface devices 101, 200 and 103 is as described above. For example, data can be written from the terminal device 40 to the main storage device 30 via the data bus B by the connection operation of the interface devices 103 and 200.

  In this example, when data is being written from the terminal device 40 to the main storage device 30 and when data is being read from the main storage device 30 to the terminal device 50, the data bus A is output by the three-way interface device 200. Is separated from the data bus B, so that the data bus A can be opened to the main control device 10 and the sub control device 20. Thereby, the main control device 10 connected to the data bus A can exchange other data with the sub-control device 20 through the interface devices 101 and 102.

  Further, the same data read from the main storage device 30 based on the control command D1 relating to the data transfer event (9) described above can be transferred to the main control device 10, the sub-control device 20, the terminal device 50, and the like. it can. Thereby, the main storage device 30 can be shared in time series or simultaneously between the main control device 10 and the sub control device 20 connected to the data bus A and the terminal devices 40 and 50 connected to the data bus B. .

  As described above, according to the data processing device 300 of the present embodiment, the two data buses A and B are input / output controlled in time series by the bidirectional interface devices 101 to 104 and the three-directional interface device 200. Therefore, it is possible to perform data transfer control in which one CPU bus 1 is divided into two as in the conventional image forming apparatus 500.

  Next, an image forming apparatus to which the data processing apparatus 300 is applied will be described.

(3) Application Example of Data Processing Apparatus FIG. 6 is a block diagram illustrating a configuration example of an image forming apparatus 400 according to the present embodiment. In this embodiment, a memory bus bridge 201 is connected to the image memory 3 shown in FIG. 7 and the two divided data buses A and B, and after a control command D1 is given to this bus bridge 201, The control unit D1 controls the scanner unit 42 and the printer unit 52 to control the input and output in a time-series manner independently of the CPU 2a, during which the CPU 2a can execute other data processing.

  This image forming apparatus 400 is provided with a bus bridge 201 shown in FIG. 6 as three-way interface means. For the bus bridge 201, the three-way interface device 200 according to the present embodiment is used.

  The bus bridge 201 is connected to the image memory 3 and temporarily stores image data such as a document. In this example, image data can be written and read between the image memory 3 and the data bus A by the control command D1 written in the command register 17a in the bus bridge 201. , And image data is transferred between the two data buses A and B.

  In this example, the data bus A is provided with two bidirectional bus bridges 31 and 32. One bus bridge 31 is connected to the data bus A and connected to the other bus bridge 32 and the memory bus bridge 201, and is also connected to the CPU 2a through the CPU bus 1a. The ROM 2b, the RAM 2c, and the operation unit 2d are connected to the CPU 2a in the same manner as in the conventional method, and the entire control of the image forming apparatus 400 is performed. The description of these functions is omitted (see FIG. 7).

  The other bus bridge 32 is connected to the data bus A and connected to the bus bridge 201, and is also connected to the CPU 25 that controls a communication modem and the like via the CPU bus 1b. The ROM 26 and the RAM 27 connected to the CPU bus 1b support the CPU 25. Further, a bus arbiter 61 as first arbitration means is connected to the data bus A, and arbitration of the bus use right of the bus bridge 31 and the bus bridge 32 is performed so that data collision does not occur.

  The data bus B is also provided with two bidirectional bus bridges 33 and 34. The one bus bridge 33 is connected to the data bus B and connected to the other bus bridge 34 and the bus bridge 201, and is connected to a scanner unit 42 as an image acquisition unit through a scanner bus 41. The scanner unit 41 acquires an image of the document based on the input control of the bus bridge 33, and outputs image data of the document.

  Similarly, the other bus bridge 34 is connected to the data bus B and is connected to the bus bridge 201, and is also connected to the printer section 52 as image reproducing means through the printer bus 51. In the printer unit 52, image data is given based on output control of the bus bridge 34, and an image of a document is reproduced based on the image data. Further, a bus arbiter 71 as second arbitration means is connected to the data bus B, and arbitration of the right to use the buses of the bus bridges 33 and 34 is performed.

  In each of the bus bridges 101 to 104 described above, the bidirectional interface device 100 according to the present embodiment is used, and data transfer is controlled by a control command D1 written in a command register 17a provided therein. . In this example, at least when data is transferred between the data bus A and the image memory 3, when data is transferred between the image memory 3 and the data bus B, or when data is transferred between the data buses A and B. When performing, the control command D1 is written to the command register 17a in the bus bridge 201.

  In this example, after the control command D1 is written into the bus bridge 201 by the CPU 2a or the CPU 25, the scanner unit 42 and the printer unit 52 are controlled to input and output in time series by the control command D1.

  Next, an operation of the image forming apparatus 400 according to the present embodiment will be described. First, a case of copying a single (one page) document will be described. In this example, it is assumed that the image data of the document obtained by the scanner unit 42 is temporarily transferred to the image memory 3, and then the image data is read from the image memory 3 and supplied to the printer unit 52. I do.

  For example, when the operation unit 2d instructs the CPU 2a to copy one page, the CPU 2a instructs the bus bridge 33 to drive the scanner to drive the scanner unit. At this time, since the bus bridge 33 and the CPU 2a are not directly connected to the data buses A and B, a scanner driving instruction is sent via the bus bridge 31 and the bus bridge 201.

  At the time of this scanner driving instruction, a control command D1 is sent from the CPU 2a to the bus bridge 31. At this time, the address generated by the CPU 2a indicates the bus bridge 31 mapped in advance. Therefore, the bus bridge 31 drives the control command D1 and the address onto the data bus A. In the bus bridge 201 connected to the data bus A, since the address assigned to the control instruction D1 specifies the bus bridge 33 connected to the data bus B, the control instruction D1 and the address are assigned to the data bus B. Driven. Thus, the bus bridge 33 receives the control command D1 and the address from the bus bridge 201, and controls the driving of the scanner unit 42.

  Next, the destination of the image data output from the scanner unit 42, the number of transfer bytes, and the like are instructed from the CPU 2a to the bus bridge 33. At this time, as described above, the CPU 2a drives the control command D1 for instructing the address of the bus bridge 33, the storage location of the image data, and the like on the data bus A via the CPU bus 1a. Thereby, the control command D1 is transferred to the bus bridge 33 through the bus bridge 31 and the bus bridge 201. The bus bridge 33 that has received the control command D1 starts preparations for writing the image data from the scanner unit 42 to the specified address of the image memory 3.

  At the time of this writing, the bus bridge 33 requests the bus arbiter 71 to use the data bus B. The bus arbiter 71 permits the use of the data bus B in response to the highest-priority bus use request at that time according to a predetermined algorithm contained therein. In this case, since no bus use request has been made from the bus bridge 201 and the bus bridge 34, the use of the data bus B is permitted to the bus bridge 33. In the bus bridge 33 having the permission, the specified address of the image memory 3 is driven to the data bus B.

  The bus bridge 201 receiving the address of the image memory 3 decodes the control command D1 to detect that the access is to the image memory 3. Therefore, the image data driven on the data bus B is stored in the image memory 3 through the above-described internal data bus 15b of the bus bridge 201 and the FIFO memory 23a (see FIG. 4).

  Here, if the address of the image memory 3 and the address of the bus bridge 34 are set to the same value on the address map of the CPU 2a, the image data from the scanner unit 42 is stored in the image memory 3 while the document Can be printed out.

  While the image data of the transfer byte number specified by the CPU 2a is stored in the image memory 3 by the bus bridge 33, the CPU bus 1a and the data bus A are not used for the transfer of the image data. The CPU 25 and the like can process a job such as a newly designated communication process.

  When the transfer of the specified number of bytes of image data is completed, the bus bridge 33 notifies the CPU 2a of the end of the data transfer. At this time, in the bus bridge 33, the data bus B is driven to indicate the address of the bus bridge 31 in order to record the end status data D2 in the status register 17b in the bus bridge 31.

  Since the data bus B is driven, the address is decoded in the bus bridge 201, and the address of the bus bridge 31 and the end status data D2 are driven to the data bus A. Thus, in the bus bridge 31, since the address addressed to the bus bridge itself is driven, the end status data D2 is stored in the status register 17b.

  Since the contents of the status register 17b change in the bus bridge 31, the contents are notified to the CPU 2a. Therefore, by reading the register 17b of the bus bridge 31, the CPU 2a can detect that the transfer of the image data from the scanner unit 42 to the image memory 3 has been completed.

  The CPU 2a that has received the data transfer end notification instructs the bus bridge 34 to start the printer unit 52. At this time, the address driven on the CPU bus 1a indicates the bus bridge 34. Accordingly, the control command D1 for the bus bridge 34 passes through the bus bridge 31 and the bus bridge 201 and is stored in the command register 17a of the bus bridge 34. Thereafter, the CPU 2a instructs the bus bridge 34 on the storage source of the image data and the number of bytes, and prepares for the start of printing.

  The bus bridge 34 requires the bus arbiter 71 to use the data bus B for data transfer. Upon receiving this request, the bus arbiter 71 is given permission for the highest priority bus use request according to a predetermined algorithm. In this case, since there is no bus use request from the bus bridge 201 and the bus bridge 33, the bus bridge 34 is given permission to use the data bus B. In the bus bridge 34 having received the permission, the address of the image memory 3 is driven to the data bus B.

  In the bus bridge 201 receiving the address of the image memory 3, the address is decoded, and an access to the image memory 3 is detected based on the decoded result. Thus, in the bus bridge 201, the image data is read from the image memory 3 at the address specified by the CPU 2a, and the image data is driven onto the data bus B. The image data driven on the data bus B is captured by the bus bridge 34, and the image data is output to the printer unit 52.

  In the bus bridge 34, when the specified bytes have been printed out, the transfer end status is stored in the status register 17b in the bus bridge 31 described above. In this manner, the CPU bus 1a and the data bus A can be used for the next job of the CPU 2a from the time when the start command is sent to the bus bridge 33 until the end of copying one page of the document.

  Next, a case where a plurality of documents are copied on a plurality of copies of transfer paper will be described. Also in this case, the CPU 2a sends a control command D1 for controlling the drive of the scanner unit 42 to the bus bridge 33 in response to an instruction from the operation unit 2d. Further, the storage destination address and the number of read bytes of the image data read by the scanner unit 42 are set, and reading of the image data is started. At this time, by setting the address of the bus bridge 34 to be the same as the address of the image memory 3 as described above, the read image data can be stored in the image memory 3 while being printed out.

  In this example, when the reading of the image data of the first page of the document is completed, the CPU 2a instructs the bus bridge 34 to start the printer unit 52. At this time, if there is free space in the memory area for one page in the image memory 3, the CPU 2a instructs the bus bridge 33 to start reading the second page. Each of the bridges 33 and 34 requests the bus arbiter 71 to use the data bus B. The bus bridge 33 or 34 receiving this permission performs the data transfer as described above. When the same operation described above is performed for the number of originals on the first page, one copy of the original on the first page is completed. In order to copy a plurality of copies, the bus bridge 34 is sequentially activated, and the copy of a preset number of copies is completed.

  As described above, according to the image forming apparatus 400 of the present embodiment, the input / output control of the image data can be performed by the bus bridge 201 dedicated to the memory independently of the CPU 2a. While writing the image data in the memory 3, the image of the original can be copied by the printer unit 42 based on the image data from the scanner unit 42 at the same time. Therefore, after the control command D1 is given from the CPU 2a to the bus bridge 201, the CPU 2a can execute other data processing such as communication processing.

  In this example, the communication unit 38 is connected to the CPU 25, and the image data of the original by the scanner unit 42 is transmitted to the communication line 39, or the image data of the original transmitted by using the communication line 39 is received. The image data of the document received by the communication unit 38 may be reproduced and output by the printer unit 52.

  Note that the CPU 2a and the CPU 25 may be the same. When the CPU 2a and the CPU 25 are the same, the bus bridge 31 and the bus bridge 32 can have the same configuration. The contents of the address map provided in the ROM 2b and the like are simplified.

  In the present embodiment, since the image memory 3 can be shared by the scanner unit 42, the printer unit 52, and the like, the page memory unlike the conventional method is not required, and the use efficiency of the image memory 3 is improved.

  Further, since one data bus can be divided into two, A and B, as in the conventional system, the DMAC can be introduced without concern about the influence on the CPU 2a. Therefore, by providing the interface control unit 18 in the bus bridges 31 to 34 and the interface control unit 28 in the bus bridge 201 with the DMAC function, the transfer speed of image data and the like can be increased.

FIG. 1 is a block diagram illustrating a configuration example of an interface device 100 according to an embodiment of the present invention. FIG. 2 is a configuration diagram illustrating an operation example of the interface apparatus. FIG. 1 is a block diagram illustrating a configuration example of a three-way interface device 200 according to an embodiment of the present invention. FIG. 4 is a configuration diagram illustrating an operation example of the interface apparatus 200. FIG. 1 is a block diagram illustrating a configuration example of a data processing device 300 according to an embodiment of the present invention. FIG. 1 is a block diagram illustrating a configuration example of an image forming apparatus according to an embodiment of the present invention. FIG. 5 is a block diagram illustrating a configuration example of a conventional image forming apparatus 500.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 CPU bus 2 System control means 3 Image memory 5 Image acquisition means 6 Image reproduction means 10 Main control unit 13, 16 Interface unit 17 Control memory 17a Command register 17b Status register 20 Sub-control unit 21 Internal bus selector 24 Memory control unit 28 Interface control unit 30 Main storage device 31-34, 201 Bus bridge 60, 70 Bus arbitration means 100, 200 Interface device

Claims (3)

A first data bus;
A communication control unit connected to the first data bus;
A second data bus;
A printer unit connected to the second data bus and performing image formation based on data;
Memory for data,
Writing and reading data between the memory and the first data bus, writing and reading data between the memory and the second data bus, and And three-way interface means for performing data transfer between the first data bus and the second data bus.
The three-way interface means includes:
A first interface unit connected to the first data bus;
A second interface unit connected to the second data bus;
Memory control means for controlling writing and reading of data to and from the memory,
A first FIFO memory for temporarily storing data input from the first interface unit;
A second FIFO memory for temporarily storing data output to the second interface unit;
A third FIFO memory for temporarily storing data to be written and read by the memory control means;
By controlling the first interface unit and the memory control unit, it is possible to transfer data from the communication control unit to the memory,
By controlling the first interface unit and the memory control unit, it is possible to transfer data from the memory to the printer unit,
An image forming apparatus, comprising: a control unit that controls the first data bus and the second data bus so that the memory can be accessed in time series. In an image forming apparatus having a printer unit that forms an image based on data,
A first data bus;
A communication control unit connected to the first data bus;
A second data bus;
A scanner unit connected to the second data bus;
A memory for the data;
Writing and reading data between the memory and the first data bus, writing and reading data between the memory and the second data bus, and Three-way interface means for performing data transfer between a data bus and the second data bus,
The three-way interface means includes:
A first interface unit connected to the first data bus;
A second interface unit connected to the second data bus;
Memory control means for controlling writing and reading of data to and from the memory,
A first FIFO memory for temporarily storing data output to the first interface unit;
A second FIFO memory for temporarily storing data input from the second interface unit;
A third FIFO memory for temporarily storing data to be written and read by the memory control means;
By controlling a second interface unit and the memory control unit, it is possible to transfer data from the scanner unit to the memory,
By controlling the first interface unit and the memory control unit, it is possible to transfer data from the memory to the communication control unit,
An image forming apparatus, comprising: a control unit that controls the first data bus and the second data bus so that the memory can be accessed in time series. A control command for controlling input / output of the first interface unit, the second interface unit, and the memory control unit; and a control command for controlling data writing and reading of the first, second and third FIFO memories. 3. The image forming apparatus according to claim 1, further comprising a control memory for temporarily storing a control command.

Images