JP2004304390A - Signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processor capable of reducing the number of frame memories by making frame memories to be used for IP conversion adapted to motion and an overdrive in common. <P>SOLUTION: In the case of executing the IP conversion adapted to motion, the gradation value of a pixel at the same position of the previous field necessary for an overdrive operation is simultaneously operated to thereby reduce a data transfer amount to the frame memories, reducing the number of the frame memories. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a signal processing apparatus for processing a video signal for a display device using a liquid crystal element, an organic EL element plasma, or the like, and in particular, in the signal processing apparatus, converts an interlaced video signal into a progressive video signal. The present invention relates to interlace-progressive conversion and overdrive control for improving the response speed of a display element.
[0002]
[Prior art]
When displaying an interlaced video signal on a display device such as a liquid crystal panel which displays a video in a progressive format, it is necessary to perform an interlace-progressive conversion for converting the interlaced video signal into a progressive video signal. Conventionally, as a method of interlace-progressive conversion, for example, as disclosed in Japanese Patent Application Laid-Open No. 2000-152246, an inter-image interpolation signal formed from an image signal of a frame or a field different from an interpolation target and an interpolation method Means for mixing an object with an intra-image interpolation signal formed from an image signal of the same frame or field are known. Here, a field delay device is used to form an inter-image interpolation signal.
[0003]
Further, in a liquid crystal display device, a frame memory is used, for example, as disclosed in Japanese Patent Application Laid-Open No. 2001-125067, in order to solve an afterimage phenomenon due to a long response time in which a liquid crystal responds to a voltage change. There is known a means for shortening the response time by using a data emphasis unit to emphasize and convert the display data so as to increase the change when the display data is changed.
[0004]
[Patent Document 1]
JP 2000-152246 A
[Patent Document 2]
JP 2001-125067 A
[0005]
[Problems to be solved by the invention]
In a display device using a liquid crystal element or the like, when performing interlace-progressive conversion (hereinafter, referred to as IP conversion) adapted to motion, it is necessary to use a field delay device such as a frame memory. The frame memory is also used when implementing the above-described data emphasis means (hereinafter referred to as overdrive). That is, if the IP conversion and the overdrive are to be performed separately, two frame memories are required, which leads to an increase in the cost of the display device.
[0006]
An object of the present invention is to provide a signal processing device that reduces the number of frame memories by sharing a frame memory used for IP conversion and overdrive adapted to motion.
[0007]
[Means for Solving the Problems]
The present invention relates to a signal processing device for a display device, wherein a timing control unit, a field determination unit, a frame memory control unit, a line memory, a line memory control unit, a line memory selection unit, an overdrive compatible IP conversion And an overdrive unit, wherein the field determination unit includes means for determining whether data of the input video signal is data of an odd field or data of an even field, and data of the input video signal. For determining whether the data is data of an odd-numbered line or data of an even-numbered line. The overdrive-compatible IP conversion unit is provided with a motion detection IP conversion unit for performing IP conversion adapted to motion by using a frame memory based on the discrimination data in the field determination unit. In addition to means for calculating the gradation value of the previous field of the target pixel by calculation, means for simultaneously calculating data of the previous field of the same pixel for overdrive is provided. Further, the overdrive unit includes a correction value determination unit for performing overdrive control based on the current field grayscale value and the previous field grayscale value, and uses the correction value as a current field grayscale value. Means are provided for adding overdrive control.
[0008]
Therefore, the amount of access to the frame memory can be reduced as compared with the case where the two operations of the IP conversion and the overdrive adapted to the motion are separately processed. As a result, the frame memory connected to the signal processing apparatus can be reduced. This has the effect of reducing the number of chips.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
[0010]
As described above, when a moving image such as a television image is displayed on a display device using a liquid crystal element or the like, it is effective to mount the IP conversion and the overdrive in order to improve the image quality.
[0011]
The IP conversion is a function of converting an interlaced (interlaced scanning) signal into a progressive (sequential scanning) signal. For example, the present invention is applied to a case where an interlaced video signal such as NTSC, PAL, D1, or D3 is displayed on a display device such as a liquid crystal panel which performs progressive video display.
[0012]
On the other hand, the overdrive function is a function of improving the response speed of the liquid crystal panel to reduce moving image blur when displaying a moving image.
[0013]
The present invention provides a signal processing device that realizes two functions of IP conversion and overdrive for a display device using a liquid crystal display device or the like.
[0014]
Before describing the operation of the signal processing device of the present invention, an overview of IP conversion and overdrive will be described.
[0015]
First, the IP conversion will be described.
[0016]
Both the progressive signal and the interlace signal are in the form of a video signal.
[0017]
FIG. 1 shows a schematic diagram of a progressive signal, and FIG. 2 shows a schematic diagram of a positional relationship of data constituting an interlace signal.
[0018]
As shown in FIG. 1, the progressive signal forms one frame of data for one screen at a certain sampling time, and sequentially scans all data in the same frame from the upper left to the lower right of the screen in units of horizontal lines. This is a signal composed of For example, a signal such as D2 or D4 of the video signal standard is composed of about 60 frames per second.
[0019]
On the other hand, as shown in FIG. 2, the interlaced signal alternately forms odd fields and even fields at each sampling time, and displays only odd-numbered horizontal lines in odd fields and only even-numbered horizontal lines in even fields. Is a signal formed by performing interlaced scanning in horizontal line units from the upper left to the lower right. For example, in a signal such as NTSC, D1, D3, etc., about 30 odd-numbered fields and about 30 even-numbered fields are formed in one second, each consisting of about 60 fields.
[0020]
The IP conversion is a process of interpolating a signal that is not included in the interlace signal, that is, data of an even line of an odd field and data of an odd line of an even field.
[0021]
In the present invention, as a method of IP conversion, motion detection IP conversion excellent in image quality is performed. Next, the motion detection IP conversion will be described.
[0022]
IP conversion methods include, for example, an intra-field interpolation method for interpolating with line data in the same field, and an inter-field interpolation method for interpolating data between fields by referring to data between a plurality of fields.
[0023]
FIG. 3 is a schematic diagram illustrating a mutual positional relationship between a line to be interpolated by IP conversion and a line used as reference data for interpolation.
[0024]
In the intra-field interpolation, for example, when obtaining the gradation value of the pixel included in the line C301 shown in FIG. 3, the interpolation is performed using the data of the lines U302 and L303 above and below the line C301. As an interpolation method at this time, for example, the data of the line U302 can be used as it is (line doubler method), or the average value of the gradation value of the line U302 and the gradation value of L303 can be used (linear interpolation method). . In each case, the resolution in the vertical direction is reduced as compared with the original progressive signal.
[0025]
In the inter-field interpolation, for example, when obtaining the value of the line C301 shown in FIG. 3, the interpolation is performed using the data of the lines P304 and N305 at the same position in the fields before and after the line C. As the interpolation method at this time, for example, the data of the line N305 can be used as it is, or the average value of the gradation value of the line P304 and the gradation value of the line N305 can be used. Unlike the intra-field interpolation, the inter-field interpolation does not cause a reduction in the vertical resolution. However, since images having different sampling times are synthesized every other line, if there is motion in the image during the period between the line P304 and the line N305, striped noise may occur in the horizontal direction.
[0026]
As described above, when only one of the intra-field interpolation and the inter-field interpolation is used, the resolution is reduced and the image quality is deteriorated due to the generation of noise.
[0027]
In order to solve these problems, the motion detection IP conversion is a method that combines the advantages of intra-field interpolation for moving images and inter-field interpolation for still images, and detects motion of an image. This is a method that uses intra-field interpolation and inter-field interpolation in a portion where there is no motion. Since optimum data can be appropriately selected according to the image, a high-quality image can be obtained.
[0028]
The motion detection IP conversion has been described above. Next, overdrive will be described.
[0029]
Overdrive is a function that improves the response speed of the liquid crystal panel and reduces moving image blur.
[0030]
Using a frame memory, the gradation difference of the same position pixel between frames is detected, and a correction value according to the amount of change is added to the pixel having a change in gradation to the original gradation value, thereby obtaining a liquid crystal display. The response time of the panel can be reduced.
[0031]
FIG. 5 shows a schematic diagram of shortening the luminance response time of the display element by overdrive.
[0032]
In order to obtain a target luminance value in the j-th frame at a specific pixel, the input gradation value of the j-th frame and the input gradation value of the j-th frame are used to change the luminance value from the luminance value of the j-1 frame. The example in which the gradation correction value obtained from the difference value of (1) is added to the gradation data of the j-frame.
[0033]
If there is no correction by the overdrive, the response time exceeds one frame period, so that it takes a plurality of frame periods to reach the target luminance of the j frame. The response period and the lack of effective luminance due to the blunted waveform may be recognized as moving image blur. On the other hand, when overdriving is performed, the response time until the target luminance is reached can be reduced, and the moving image blur phenomenon can be improved.
[0034]
FIG. 4 is a schematic diagram showing the mutual positional relationship of lines used for overdrive.
[0035]
The grayscale value I (O) after overdrive is applied to the grayscale value I (C) of the pixel included in the line 401 at the position C in FIG. Using the adjustment value I (P), it can be calculated, for example, as in equation (1).
[0036]
I (O) = I (C) + α (I (C) I (P)) (1)
Here, α is an overdrive coefficient, and an appropriate value is determined according to the characteristics of the liquid crystal panel so that the response speed is improved.
[0037]
The motion detection IP conversion and the overdrive have been described above. Since the motion detection IP conversion and the overdrive require data of a plurality of fields for the calculation as described above, the frame memory for storing the field data is used respectively. There is a need to.
[0038]
For this reason, the configuration sharing of a display device using a conventional liquid crystal element is, for example, as shown in FIG.
[0039]
The display device 601 includes, for example, an interface module 602 and a liquid crystal panel module 603.
[0040]
The interface module 602 includes, for example, a tuner 604, input terminals 605, 606, 607, a Y / C separation device 608, an RGB conversion device 608, a signal processing device 610, and a frame memory 611.
[0041]
The tuner 604 has a function of, for example, selecting a channel from a television broadcast radio wave and extracting an NTSC signal, for example.
[0042]
The input terminals 605, 606, and 607 are terminals for inputting various video signals from an external device (not shown) such as a video deck, a DVD player, and a PC (personal computer). For example, there are a composite terminal, an S terminal, a D terminal, a D-Sub terminal, a DVI terminal, a component terminal, and the like. Although the configuration example in which three input terminals are provided is shown in the drawing, a different configuration may be employed.
[0043]
The Y / C separation device 608 generates a luminance signal when a signal input from the tuner 604 or the input terminals 605, 606, and 607 is a signal obtained by combining a luminance signal and a color signal, such as an NTSC signal. It has the function of separating signals and color signals.
[0044]
When the input video signal is a signal composed of a luminance signal and a chrominance signal, the RGB conversion device 609 converts the input signal into gradation value data of each of an R component, a G component, and a B component. Has functions.
[0045]
The signal processing device 610 has at least means 617 for performing IP conversion on the input signal.
[0046]
The frame memory 611 is used to store frame data necessary for the IP conversion means 617 executed by the signal processing device 610.
[0047]
The liquid crystal panel module 603 includes, for example, a timing control unit 612, a frame memory 613, drivers 614 and 615, a liquid crystal panel 616, and the like.
[0048]
The drivers 614 and 615 have a function of applying a predetermined voltage to drive a predetermined liquid crystal element of the liquid crystal panel 616.
[0049]
The timing control unit 612 has a function of transferring input data to the drivers 614 and 615 at a predetermined timing. Further, an overdrive unit 618 for applying data modulation by overdrive to the input data is provided.
[0050]
The frame memory 613 is used to store necessary frame data in the overdrive unit 618 executed by the timing control unit 612.
[0051]
As shown in the example here, the conventional IP conversion means 617 is implemented in the signal processing device 610 of the interface module 602, and the overdrive means 618 is implemented in the timing control unit 612 of the liquid crystal panel module 603. Since the memories 611 and 613 were individually mounted on separate modules, the number of parts increased, which led to an increase in the cost of the system.
[0052]
Thus, in the present invention, the frame memory for IP conversion and the frame memory for overdrive are shared, thereby reducing the number of components and reducing the cost of the display device.
[0053]
FIG. 7 is a diagram illustrating a configuration example of a display device 701 to which an embodiment of the present invention has been applied.
[0054]
In the configuration of FIG. 6, there are two frame memories 611 and 613, whereas in the configuration of FIG. 7, only one frame memory 711 is used.
[0055]
Also, in the configuration of FIG. 6, the IP conversion unit 617 is mounted on the signal processing device 610 of the interface module 612, and the overdrive unit 618 is mounted on the liquid crystal panel module 613, whereas in the configuration of FIG. The difference lies in that two of the conversion means 717 and the overdrive means 718 are mounted in the signal processing device 718 of the interface module 702.
[0056]
However, in the configuration of FIG. 7, simply using a common frame memory causes two memory accesses to one frame memory 711 at the same time, a memory access by the IP conversion unit and a memory access by the overdrive. In other words, depending on the combination of the input video signal and the output video signal, the amount of data transferred per unit time may increase, possibly causing a case where the operable speed of the frame memory is exceeded.
[0057]
Therefore, in the present invention, in addition to the common use of the frame memory shown in FIG. 7, the amount of data transferred to the frame memory is reduced by performing the processing in cooperation with the IP conversion and overdrive. By reducing the data transfer amount, the frame memory can be reduced.
[0058]
Next, a method of reducing the data transfer amount will be described.
[0059]
In this method, the processing used for both motion detection IP conversion and overdrive is cooperated by utilizing the fact that the lines used have commonality. By using a part of the motion detection IP conversion processing for the operation for overdrive, the data transfer amount is reduced.
[0060]
FIG. 8 and FIG. 9 are diagrams showing the outline of the mutual positional relationship of the lines respectively used in the motion detection IP conversion and the overdrive in the present method.
[0061]
Here, the method of calculating the gradation value is as follows: (1) a case of calculating an odd line of an odd field or an even line of an even field; and (2) a case of calculating an even line of an odd field or an odd line of an even field. And two cases.
[0062]
FIG. 8 shows an example of a calculation method for displaying an odd line of an odd field or an even line of an even field.
[0063]
When calculating the gradation value of the pixel included in the line C801, the gradation value of the current field can be used as it is without performing the interpolation processing because the corresponding actual data already exists in the input video signal. On the other hand, the gradation value of the pixel of the line P802 of the previous field necessary for overdrive is determined by U′803, L′ 804, P ′ by the above-described motion detection IP conversion because there is no actual data in the input video signal. '805, interpolation is performed from the pixels included in the line at the position of C801.
[0064]
FIG. 9 shows an example of a calculation method for displaying an even line of an odd field or an odd line of an even field.
[0065]
When calculating the gradation values of the pixels included in the line C901, since the corresponding actual data does not exist in the input video signal, the gradation values of the current field are calculated using the above-described motion detection IP conversion. Interpolation is performed from the pixels included in the line at positions P904 and N905. On the other hand, the gradation value of the pixel of the line P904 in the previous field necessary for overdrive can be used as it is without performing the interpolation processing because the corresponding actual data exists in the input video signal.
[0066]
As described above with reference to FIGS. 8 and 9, the lines used for motion detection IP conversion and overdrive have commonality.
[0067]
FIG. 10 is a table summarizing a method of calculating the gradation values of the pixels of the previous field and the gradation values of the pixels of the current field based on the combinations of the fields and the lines described above.
[0068]
The current field gradation value and the previous field gradation value can be selected according to the type of the field and the line.
[0069]
I (C) 1001 and 1007 are the gradation values of the current field of line C801, and I (S ') 1002 and 1008 are obtained from lines U'803, L'804, P'805, and C801 by motion detection IP conversion. This is the gradation value of the previous field.
[0070]
On the other hand, I (S) 1003 and 1005 are the gradation values of the current field obtained by the motion detection IP conversion from the lines U902, L903, P904 and N905, and I (P) 1004 and 1006 are the gradation values of the previous field of the line C901. It is.
[0071]
As described above, the method of realizing the IP conversion and the overdrive while cooperating the two operations to reduce the data transfer amount and share the frame memory has been described. Next, a configuration example of a logic circuit that realizes the above method will be described.
[0072]
FIG. 11 shows a configuration example of an overdrive-compatible IP conversion unit 1100 for realizing the above-described data transfer amount reduction method.
[0073]
The overdrive-compatible IP conversion unit 1100 includes a motion detection IP conversion unit 1101 and a selector 1102.
[0074]
The motion detection IP conversion unit 1101 includes an intra-field interpolation unit 1103, an inter-field interpolation unit 1104, a motion detection unit 1105, and a selector 1106.
[0075]
The intra-field interpolation unit 1103 performs intra-field interpolation using pixel data of lines above and below the interpolation target pixel.
[0076]
The inter-field interpolation unit 1104 performs inter-field interpolation using pixel data of a line of a field before and after the interpolation target pixel.
[0077]
The motion detection unit 1105 compares the previous field with the next field to detect whether or not the interpolation target pixel has a motion. When the motion is detected, the motion detection unit 1105 generates a motion detection signal. For example, a method of calculating a difference value between the gradation value of the previous field and the gradation value of the next field, and determining that there is a motion when the difference value is equal to or larger than a predetermined threshold value, may be adopted. it can. Alternatively, a method may be adopted in which pattern matching is performed around the pixel to be interpolated to detect movement.
[0078]
The selector 1106 appropriately selects, based on the motion detection signal, data of an interpolation target pixel obtained as a result of intra-field interpolation and data of an interpolation target pixel obtained as a result of inter-field interpolation.
[0079]
By the operation of the selector 1106, the motion detection IP conversion combining the intra-field interpolation and the inter-field interpolation can be executed.
[0080]
The selector 1107 performs a condition determination using the field determination signal and the line determination signal based on the determination conditions illustrated in FIG. 10, thereby obtaining the gradation value of the motion detection IP conversion result, the gradation value of the line of the previous field, The current field gradation value and the previous field gradation value are respectively selected from the gradation values of the line of the next field.
[0081]
The field determination signal is a signal that indicates at any time whether the data to be interpolated by the overdrive compatible IP conversion unit 1100 is data of an odd field or even field.
[0082]
The line discrimination signal is a signal that indicates at any time whether the data to be interpolated by the overdrive-compatible IP conversion unit 1100 is odd-numbered line data or even-numbered line data.
[0083]
Here, the motion detection IP conversion unit 1101 is used to calculate the gradation value of the current field in the odd lines of the even lines / even lines of the even fields, and in the odd lines of the odd fields / even lines of the even fields. The same motion detection IP conversion unit 1101 is time-divisionally used by alternately switching the role for each line for two purposes, such as calculating the gradation value of the previous field for overdrive. Thus, it can be used for another purpose, and the circuit scale can be reduced.
[0084]
FIG. 12 shows a configuration example of the overdrive unit 1200.
[0085]
The overdrive unit 1200 includes a correction value determination unit 1201 and an addition unit 1202.
[0086]
The correction value determination unit 1201 calculates a correction value from the gradation value of the current field, the gradation value of the previous field, and the overdrive coefficient α.
[0087]
The adder 1202 adds the correction value determined by the correction value determiner 1201 to the current field gradation value.
[0088]
The correction value determination unit 1201 has a configuration in which, for example, α in Expression (1) is held in a register or the like, and a calculation is performed as needed from the current field grayscale value and the previous field grayscale value to determine an overdrive correction value. be able to. Alternatively, for example, a table in which the combination of the current field gradation value and the previous field gradation and the overdrive value corresponding to the combination are set in a matrix is provided, and the table is referred to using a RAM or a ROM. May be used to determine the correction value.
[0089]
FIG. 13 is a diagram illustrating an example of a method of configuring a logic circuit to which the present invention is applied.
[0090]
The signal processing device 1300 includes, for example, a timing control unit 1301, a field determination unit 1302, an S / P unit 1303, a frame memory control unit 1304, line memories 1305 to 1310, P / S units 1311 to 1316, a line memory control unit 1317, It comprises a memory selector 1318, an overdrive compatible IP converter 1319, and an overdrive unit 1320.
[0091]
The timing control unit 1301 has a function of generating a vertical synchronizing signal, a horizontal synchronizing signal, and a data valid signal for liquid crystal panel output from a vertical synchronizing signal, a horizontal synchronizing signal, and a data valid signal of an input video signal.
[0092]
The field determination unit 1302 has a function of determining whether an input signal is data of an odd field or data of an even field, and generating a field determination signal.
[0093]
In addition, the field determination unit 1302 has a function of determining whether an input signal is data of an odd line or data of an even line, and generating a line determination signal.
[0094]
The frame memory control unit 1304 controls data access to the frame memory 1321. Here, for the frame memory 1321, for example, an SDRAM can be used. The frame memory 1321 is provided with at least two areas in which data for one frame can be stored, that is, storage areas for two frames, and arbitration is performed in each area so that reading from the frame memory and writing access do not collide.
[0095]
S / P section 1303 performs serial-parallel conversion of data.
[0096]
Further, P / S sections 1311 to 1316 perform parallel-to-serial conversion of data in order to restore the signal converted in parallel by S / P section 1303 to the original state.
[0097]
The S / P unit 1303 and the P / S units 1311 to 1316 are provided to execute data access to a plurality of pixels at one time in order to improve the efficiency of data transfer to the frame memory 1321. For example, when the input data is a 24-bit signal configured by allocating 8 bits to each of the R component, the G component, and the B component, if the data bus width of the frame memory 1321 is 48 bits, data of two pixels is transmitted once. Can be transferred by memory access.
[0098]
The line memories 1305 to 1310 have a function of storing data read from the frame memory 1321 in units of horizontal lines. The line memories 1305 to 1310 have a buffer function for adjusting input and output timings. In addition, the line memories 1305 to 1310 read the data of the line from the frame memory 1321 when the data of the same line is used a plurality of times over the calculation of a plurality of lines in the calculation in the overdrive-compatible IP conversion unit 1319. After the data is used for one operation, the data is discarded immediately, and the same line data is not read out and stored again from the frame memory 1321 in the next operation, but is stored in the frame memory 1321 once. The read and stored data is stored in the line memories 1305 to 1310 at least for a period in which the data is required for the operation of the overdrive-compatible IP conversion unit 1319. Using the data stored in 1310 By row, it used to reduce the number of accesses to the frame memory 1321.
[0099]
The line memory control unit 1318 controls data transfer from the frame memory 1321 to the line memories 1305 to 1310. In order to accurately perform IP conversion and overdrive, necessary data must be input to the arithmetic circuit unit when necessary. Therefore, the line memory control unit 1318 instructs the frame memory control unit 1304 to transfer the data stored in the frame memory 1321 to the line memories 1305 to 1310 at appropriate timing. Upon receiving the instruction, the frame memory control unit 1314 replaces the data specified by the instruction among the frame data stored in the frame memory 1321 with the data specified by the instruction among the line memories 1305 to 1310. Store in line memory.
[0100]
The line memory selecting unit 1318 outputs U, L, P, N (or U ′, L ′, P ′, C) necessary for the operation of the overdrive-compatible IP conversion unit 1319 from the plurality of line memories 1305 to 1310. It has a function of selecting a line memory storing the line data of a book. The line memory control unit 1317 manages information indicating which line memory stores which line data, and the line memory control unit 1317 sends the four line data to the line memory selection unit 1318 based on the information. Is transmitted to specify the four line memories storing the line data. Note that the frame memory control unit 1304 and the line memory control unit have write access for transferring the data from the frame memory 1321 to the line memories 1305 to 1310 and write access to transfer the data stored in the line memories 1305 to 1310. A function is provided to prevent two accesses to the same line memory from colliding at the same time in a read access for reading by the drive-compatible IP conversion unit 1319.
[0101]
The frame memory 1321 has a function of storing an input video signal as frame data. The frame memory 1321 can be configured using, for example, an SDRAM. The frame memory 1321 may be configured to be externally attached to the signal processing device 1300, or may be configured to be built in the signal processing device 1300.
[0102]
The frame memory control unit 1304 manages information on which line of which frame is stored in which address of the frame memory 1321.
[0103]
The frame memory 1321 and the frame memory control unit 1304 are connected using a data bus having a bus width of a predetermined number of bits. Here, if the bus width of the data bus is increased, an improvement in the data transfer rate can be expected. However, problems such as an increase in the number of chips constituting the frame memory 1321 and an increase in power consumption occur. Therefore, it is necessary to select an appropriate bus width.
[0104]
For example, when the gradation value per pixel is represented by a total of 24-bit signals of 8 bits for each of the R component, the G component, and the B component, when storing data in the frame memory 1321, the data bus width is 24 bits. It is desirable to be a multiple of.
[0105]
On the other hand, when an SDRAM chip having a data bus width of, for example, 16 bits or 32 bits per chip is used as a memory chip constituting the frame memory 1321, a plurality of SDRAM chips are connected in parallel to increase the data bus width. Considering a configuration for improving the transfer speed, the data bus width is desirably a multiple of 16.
[0106]
Considering the above two points, it is appropriate that the data bus width be a common multiple of 16 and 24, for example, a value of 48 bits or 96 bits.
[0107]
However, for example, when the data bus width is set to 48 bits, the frame memory 1321 can be configured by using three SDRAM chips having a bus width of 16 bits, whereas when the data bus width is set to 96 bits. In the case where the frame memory 1321 is configured using an SDRAM chip having a bus width of 16 bits, it is necessary to use six SDRAM chips, or the frame memory 1321 is configured using an SDRAM chip having a bus width of 32 bits. In this case, it is necessary to use three SDRAM chips, and the number of SDRAM chips used is increased as compared with the case where the data bus width of the frame memory 1321 is configured to be 48 bits. This leads to an increase in the cost of the display device 701 used. That.
[0108]
For the above reasons, it is considered appropriate that the data bus width of the frame memory 1321 is, for example, 48 bits. As described above, when the data bus width of the frame memory 1321 is 48 bits, the frame memory 1321 can be configured by connecting three SDRAM chips having a data bus width of 16 bits per chip in parallel, for example.
[0109]
However, the above-described resolution per pixel, data format, type of memory chip, data bus width, and the like are merely examples, and other combinations may be employed.
[0110]
The application example of the present invention has been described above.
[0111]
【The invention's effect】
As described above, according to the present invention, in a signal processing device for processing a video signal for a display device, a frame memory is realized by performing common operations in both systems while realizing IP conversion and overdrive adapted to motion. Can be reduced, and as a result, the number of frame memories used for the calculation can be reduced, so that the cost of the display device using the present signal processing device can be reduced. .
[0112]
Further, when the amount of data transferred between the signal processing device and the frame memory is reduced, it is possible to obtain an effect that the operating frequency of the frame memory can be reduced and that the power consumption can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing a progressive video signal.
FIG. 2 is a diagram schematically illustrating an interlaced video signal.
FIG. 3 is a diagram schematically illustrating an example of interlace-progressive conversion in a signal processing device to which the present invention has been applied.
FIG. 4 is a diagram schematically illustrating an example of overdrive in a signal processing device to which the present invention has been applied.
FIG. 5 is a diagram illustrating an example of a reduction in response time due to overdrive in a signal processing device to which the present invention has been applied.
FIG. 6 is a diagram illustrating an example of a schematic configuration of a display device using a liquid crystal element or the like.
FIG. 7 is a diagram illustrating an example of a schematic configuration of a display device using a liquid crystal element or the like to which the present invention is applied.
FIG. 8 is a diagram schematically illustrating an example of overdrive-compatible IP conversion of a signal processing device to which the present invention has been applied.
FIG. 9 is a diagram schematically illustrating an example of overdrive-compatible IP conversion of a signal processing device to which the present invention has been applied.
FIG. 10 is a diagram illustrating an example of a method of calculating a tone value of a pixel to be interpolated in overdrive-compatible IP conversion of a signal processing device to which the present invention has been applied.
FIG. 11 is a diagram illustrating an example of a schematic configuration of an overdrive-capable IP conversion unit in a signal processing device to which the present invention has been applied.
FIG. 12 is a diagram illustrating an example of a schematic configuration of an overdrive unit in a signal processing device to which the present invention has been applied.
FIG. 13 is a diagram illustrating an example of a schematic configuration of a signal processing device to which the present invention has been applied.
[Explanation of symbols]
301,801,901 ... interpolation target line, 302,803,902 ... upper line of interpolation target line, 303,804,903 ... lower line of interpolation target line, 304,805,904 ... previous field of interpolation target line Lines, 305, 905: lines in the next field of the line to be interpolated, 401: lines to be overdriven, 401, 802: lines in the field before the line to be overdriven, 601, 701: display device, 602, 702: interface module, 603, 703: liquid crystal panel module; 604, 704: tuner; 605, 606, 607, 705, 706, 707: input terminal; ... Signal processing devices, 611, 613, 7 DESCRIPTION OF SYMBOLS 1 ... Frame memory, 612, 712 ... Timing control device, 614, 615, 714, 715 ... Driver, 616, 716 ... Liquid crystal panel, 1100, 1319 ... Overdrive compatible IP conversion unit, 1101 ... Motion detection IP conversion unit, 1102 , 1106... Selector, 1103... Intra-field interpolation unit, 1104... Inter-field interpolation unit, 1105... Motion detection unit, 1200, 1320... Overdrive unit, 1201. , 1301 ... signal processing device, 1302 ... field determination unit, 1303 ... S / P unit, 1304 ... frame memory control unit, 1305, 1306, 1307, 1308, 1309, 1310 ... line memory, 1311, 1312, 1313, 1314 1315, 1316 ... / S unit, 1317 ... line memory control unit, 1318 ... line memory selection unit.

Claims (7)

What is claimed is: 1. A signal processing device for performing signal processing of a video signal for a display device, comprising: means for connecting a frame memory; a video signal stored in the frame memory as frame data; Means for performing the conversion, and means for performing overdrive for controlling the response speed of the luminance value of the display element, the interlace-progressive conversion means calculates the gradation value of the current field of the pixel to be interpolated, A signal processing device for calculating a gradation value of a previous field. 2. The signal processing device according to claim 1, further comprising at least one line memory capable of storing the frame data stored in the frame memory in units of horizontal lines, wherein the interlace-progressive conversion and Signal processing characterized in that in executing the overdrive operation, it is possible to reduce the amount of data transferred to the frame memory per unit time by using data stored in the line memory. apparatus. 2. The signal processing apparatus according to claim 1, wherein the execution target of the operation corresponds to at least one video signal among video signal standards of NTSC, PAL, D1, D2, D3, and D4. A signal processing device. 2. The signal processing device according to claim 1, wherein an SDRAM is used as the frame memory. 2. The signal processing device according to claim 1, wherein three memory chips each having a data bus width of 16 bits per chip are connected in parallel and used as a frame memory having a data bus width of 48 bits. Characteristic signal processing device. An interface module for a display device having a function of performing signal processing of a video signal for a display device, comprising: input means for a video signal using a tuner and an input terminal; and output means for outputting the signal processing result. An interface module for a display device, wherein the interface module is configured using the signal processing device according to claim 1. A display device comprising the signal processing device according to claim 1.

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