JPH05336477A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To full-line drive a delta arrangement liquid crystal panel in a pseudo interlace system by adding the minimum number of systems compared with the liquid crystal panel of the normal driving system and to prevent the deterioration of pictures such as the generation of spuriousness or the like. CONSTITUTION:The X driver output (the output of output buffers 38 and 48) of the two systems provided with a high impedance function independently corresponding to the upper and lower lines of the delta arrangement respectively are parallelly connected to a liquid crystal panel X side input pad 40 connected to the source of the TFT 45 of a delta arrangement liquid crystal cell 44 and the output buffer 48 is turned to a high impedance state during the output of the output buffer 38. Thus, when displaying optional two lines within a horizontal period, writing the first line during the first half of a horizontal video information write period and writing the remaining line in the remaining half of the write period are enabled, so that time base compression processing corresponding to the increase of the systems and the generation of the spuriousness is unnecessitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device such as a liquid crystal television receiver.

[0002]

2. Description of the Related Art In a liquid crystal display device, various AC driving methods are used for the purpose of maintaining the quality of liquid crystal. When a liquid crystal cell that is not an ideal element is AC-driven, a brightness difference, that is, flicker, occurs when the polarity of the same signal is inverted. Although various means for preventing image quality deterioration due to flicker have been developed, the main methods can be roughly classified into the following three.

(1) Higher flicker frequency (2) Correction processing by various signal operations (3) Improvement of element itself These are under development and improvement in parallel. In particular, the method of (1) Since the change becomes a permissible level at about 30 Hz, in normal television image display, the H inversion drive method in which the polarity is inverted every horizontal period (1H) is
Due to its feasibility, it is now the mainstream.

On the other hand, some full-line driving methods for liquid crystal display devices have already been developed as means for realizing high-definition display in the vertical direction, and some have been commercialized as high-definition large-size liquid crystal display devices. The main ones are shown below.

(4) Interlace drive (5) Simultaneous 2-line drive (6) Double speed scanning by time-axis conversion of video signals Interlace drive is standard NTSC from the viewpoint of scanning.
There is no difference from a cathode ray tube (CRT) display method for signals, and even lines are displayed in even fields and odd lines are displayed in odd fields.

[0006] This method does not require video signal processing for full line driving, and a very simple full line system can be constructed. However, if only one line is focused on, the image is written in the liquid crystal cell only once in 1/30 second, which causes a double image with a blurred outline in a rapidly moving image. Since it is necessary to invert the polarity in the situation that the data is written only once, the polarity frequency becomes 15 Hz, and there is a problem that flicker becomes noticeable.

The 2-line simultaneous drive system and the double speed scanning system by time-axis conversion of video signals are called pseudo full line drive system.

FIG. 7 shows an outline of display by the two-line simultaneous drive system. The red, green, and blue primary color signals R, G, B, which are image information, are input to the X drivers 1 and 2, and the pulses CPH1 to CPH3 and CPH4 are arbitrarily matched with the pixel arrangement.
.About.CPH6, the sampling and holding circuits 3 and 4 are sequentially sampled and sent to the output buffers 5 and 6.

The output buffers 5 and 6 are thin film transistors (TFTs) arranged in the respective R, G and B liquid crystal cells 11 according to arbitrary output timing control pulses OE1 and OE2.
It is output to 12 source input terminals.

On the other hand, the gate input of the TFT 12 is the buffers 9 and 1 of the Y drivers 7 and 8 which are separated into right and left every other line.
As shown in FIG. 8, the gate pulse is simultaneously output to two adjacent and different lines for each odd / even field. For example, for the N line, (G
1, G2), (G3, G4), ... output gate pulses simultaneously to two adjacent lines, and (N + 1) line, G1, (G2, G3), (G4, G5), ...
The gate pulse is output simultaneously to two adjacent lines.

As shown in FIG. 7, if the pixel array of the color liquid crystal is a stripe array, the outputs X1, X2, X3, ... Of the X drivers 1 and 2 are B, R, G ... Since the output terminals and display colors have a one-to-one correspondence and are not displaced in the horizontal direction, there is no problem even if two adjacent vertical lines are displayed simultaneously.

Therefore, as shown in FIG. 8, two times as many scanning lines as normal field scanning lines are prepared to display one line information over two lines, and in the next field, two lines to be displayed are displayed. By arbitrarily changing the combination, one line is shifted for each field while satisfying the condition of changing the applied voltage to the liquid crystal cell 11 once every 1/60 second, and therefore, it is about 1.5 times. It is possible to obtain vertical resolution.

However, in the method (5), it is an absolute condition that the pixel arrangement is a stripe arrangement, so
Compared with the case of delta arrangement, especially in the television image,
There is a problem that the horizontal resolution deteriorates.

FIG. 9 shows a basic configuration of a full line drive system by time-axis conversion of a video signal.

In FIG. 9, input video signals R, G and B are input to an analog / digital converter (A / D) 21,
Selected by a selector 22 which is digitally converted by a sampling clock (clock frequency N × fH) that is N times (N is an arbitrary frequency) times the horizontal synchronizing frequency fH locked with the video signal and then switched every horizontal period (1H). It is written in the memory 23 or 24 that has been written. The two memories 23 and 24 operate so that reading and writing are alternately performed in the respective memories.

At this time, the other memory not selected by the selector 22 already stores the information of one line before, and the selector 22 selects the other memory not selected by the output selector 25. , At the frequency twice the write clock (2N × fH), the information for one line compressed in half on the time axis continues for 2
Read once and digital / analog converter (D / A)
26 is output.

The digital / analog converter 26 has a double clock frequency (2N ×
fH), it is converted back to an analog signal and the time axis is 1 /
The video signals WR, WG, and WB that are compressed to 2 and are exclusively used for double speed are output. The output video signals WR, WG, WB have a time delay of 1H with respect to the input video signals R, G, B.

The interpolation method in full line drive signal processing by the double speed scanning method by time-axis conversion of the video signal is as follows:
In addition to the same-signal double-reading method described above, several methods are conceivable, and the main methods and configurations thereof can be roughly classified into the following two ways.

(7) Interpolation calculation is performed from the upper and lower lines using a plurality of line memories.

(8) Using a plurality of line memories and a plurality of field memories, interpolation calculation is performed from the video information of the upper and lower lines and the field one field before.

Since the method (6) is a method that enables full line display in a delta array liquid crystal display device, the method (7), which is a simple method, has the advantages of the delta array (5). It is possible to display with the advantages of).

However, there are some problems caused by using the method (6), and the main ones are as follows.

The first problem is that the system becomes complicated and large in scale, and cannot be mounted on a system having restrictions in terms of space and cost.

The second problem is that all horizontal processing is 2
Since it is necessary to double the processing speed, the double frequency characteristic is required for all liquid crystal drive processing systems including the X driver.

The third problem is that unnecessary radiation (spurious) becomes large because the A / D, the memory, the address counter, and the D / A operate at a considerably high speed.

The fourth problem is the increase in power consumption and heat generation due to the addition of A / D, memory, address counter, and D / A.

Thus, prior art full-line techniques either have to sacrifice horizontal resolution or tolerate a significant increase in system size, and
Even if the structure was recognized, its use range and application range were very narrow.

[0028]

As described above, in the conventional liquid crystal display device, when it is attempted to realize the pseudo full line driving system to enable high definition display, firstly, the horizontal resolution deterioration due to the stripe arrangement is caused. Or, secondly,
With the addition of A / D, D / A, memory, and address counter, the increase in system scale and the increase in unnecessary radiation had to be tolerated.

In view of the above problems, the present invention requires a minimum system addition and spurious and other image quality when a delta array liquid crystal panel is driven in pseudo full line, as compared with a normal drive type liquid crystal panel. It is an object of the present invention to provide a liquid crystal display device which can be driven without causing deterioration and which can be applied to a wider range as a high definition display system.

[0030]

According to the present invention, the video information of one horizontal line of a certain field is displayed over any two adjacent lines, and in the next field, the display information of one line is displayed in the previous field. In a liquid crystal display device of a pseudo interlaced display system using a liquid crystal panel of a delta arrangement, which displays in two adjacent lines in a different combination from
For each of the X-side input pads for inputting the horizontal information of the delta array liquid crystal panel for display, two lines of driver output are provided, which independently correspond to the upper and lower lines of the delta array and have both independent drive and high impedance functions. By connecting in parallel, while one driver is outputting, the other driver is in a high impedance state, so that video information is written alternately to each of the upper and lower lines X
A driver and two arbitrary lines of a liquid crystal panel for displaying within a certain horizontal period are sequentially driven in correspondence with the writing of the upper and lower lines of the X driver. In one half of one horizontal video information writing period. Y for performing serial write operation, writing information in one line and writing information in the remaining one line in the remaining half writing period.
And a driver.

[0031]

According to the present invention, it becomes possible to write the first line in the half of the normal writing period and the remaining one line in the remaining half of the writing period. Different information for two lines can be performed by a temporal serial write operation. As a result, it is not necessary to perform the time-axis compression processing of the video signal as in the prior art, so that a minimum system addition is sufficient and image quality deterioration such as spurious does not occur.

[0032]

EXAMPLES Examples will be described with reference to the drawings. FIG. 1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention. Here, a case will be described in which R, G, and B color liquid crystal pixels are arranged in a delta array and these pixels are driven in pseudo full line.

In FIG. 1, reference numerals 31 and 32 are X drivers, 33 and 34 are Y drivers (TFT gate drivers), 35 is a color liquid crystal panel, 36 is a sample hold circuit, 37 is a shifter register, 38 is an output buffer,
39 is an X driver output terminal, 40 is a video information input pad, 41 is a shift register, 42 is an output buffer, 43
Is a scan pulse input pad, 44 is a liquid crystal cell, and 45 is a TF
T and 46 are sample and hold timing pulses, and 48 is an output buffer.

In each liquid crystal cell 44 of the color liquid crystal panel 35, a TFT 45 is arbitrarily arranged and wired.
The source input of the FT 45 is connected to the input pad 40 arranged on the upper and lower sides of the panel for one pixel, and the gate input of the TFT 45 is the input pad 4 arranged on the left and right sides of the panel for each line.
It is connected to 3.

The X drivers 31 and 32 include liquid crystal RGB
Timing pulses CPH1 to CPH corresponding to the cell 44
6 and the horizontal display timing pulse STH are input, and these and the shift register 37 supply the sample hold timing pulse 46 corresponding to all the liquid crystal cells of two lines to the sample hold circuit 36.

The sample and hold circuit 36 samples the two hot water image information according to each hold timing, and holds this value with respect to the inputs of the output buffers 38 and 48.

Adjacent output buffers 38 and 48, which have a one-to-one correspondence with each liquid crystal cell 44 and have pixel information for two lines.
Since the output is short-circuited with respect to the X-side pad 40, the cell enable information OE1 and OE2 is used to select the cell information of an arbitrary line at an arbitrary timing while the information is input to the source input of the TFT 45 of each liquid crystal cell 44. Can be transmitted.

On the other hand, regarding the structure and drive timing of the Y drivers 33 and 34, in this embodiment, since the video information display for two lines to be displayed needs to be serially written within one horizontal period, the output enable pulse is required. OE1, OE
By performing timing control by the four oil enable signals CLR1 and CLR2 corresponding to 2, it becomes possible to sequentially write information to the liquid crystal cells within one horizontal period.

FIG. 2 shows the arrangement of the pixels R, G and B and the timing pulse CPH corresponding to the pixels R, G and B. CPH1 to CPH6 belong to the driver 31,
CPH1 'to CPH6' belong to the driver 32.
STH is a horizontal display timing pulse, and STH1
Is for the driver 31, and STH2 is for the driver 32.

FIG. 3 shows a timing chart related to the output enable pulse. In order to serially write the writing period 51 by the normal non-interface driving method into the upper and lower two lines, the X drivers 31 and 32 have the output enable pulses OE1 and OE2 dedicated to the upper and lower sides, respectively.
The video information to be displayed on the lower line and the upper line is output in the periods 52 and 53, respectively.

Corresponding to this, Y driver output pulse 5
Also for 4, 55, the gate voltage is applied 56, 57 only at the output timing of 52, 53.
Output enable signals CLR1 and CLR
2 obtains the gate voltage at the timings of 58 and 59. Here, 60 is a video signal display period.

By the way, the X driver output time of the non-interlaced liquid crystal panel, which is currently mainstream, is usually 15 times.
About μs, the Y driver output time is almost 1H period (63
μs). When the serial writing full line drive according to the present invention is performed, only half the writing time can be given. Therefore, depending on the type and structure of the TFT liquid crystal, due to the output capacity of the driver, the current limitation of the TFT, etc.,
It is conceivable that problems such as deterioration of contrast due to insufficient writing time may occur.

FIG. 4 shows another embodiment of the present invention. FIG. 4 (a) is an overall view, and FIG. 4 (b) shows the configuration of the X driver. In this embodiment, reference numeral 71 is a circuit having a function of generating RGB detection, horizontal synchronizing signal HD and vertical synchronizing signal VD, 72 and 73 are liquid crystal drive circuits, 74 is a control circuit, 75 is a PLL circuit, and 76 is an inversion circuit. Circuit, 7
9 is a liquid crystal drive video signal, 80 is an X driver control timing pulse, 81 and 82 are X drivers, 83 is a signal switching circuit, 85 is a Y driver control timing pulse, 86 is a Y driver, 87 is a liquid crystal module,
Reference numerals 88 and 90 are sample hold circuits, and 89 is an output buffer.

In the present embodiment, another stage of the sample and hold circuit 90 is added between the sample and hold circuit 88 of the X drivers 81 and 82 and the output buffer 89 to form a two-stage latch configuration, so that X, 30μ for both Y driver
s or more is ensured to avoid the above-mentioned trouble (writing time shortage).

This state is shown in FIG. As a matter of course, this is not necessary in the liquid crystal panel in which the writing time is guaranteed to be about 7 μs.

The video signal input to the input terminal (VIDEO-IN) is an RGB detection, HD, VD generation circuit (for example, TA8695 manufactured by Toshiba Corporation) 71, and R, G, B signals and horizontal and vertical synchronization pulses. The R, G, B signals are restored to (HD, VD) and the liquid crystal drive circuit (for example,
Toshiba TA8696) 72, 73 input, HD, V
The D signal is input to the liquid crystal module 87. The PLL circuit 75 receives the HD pulse output from the circuit 71,
A system clock pulse synchronized with this is created and output to the control circuit 74.

The control circuit 74 generates arbitrary liquid crystal drive pulses including CPH, STH and Q1H from HD, VD and system clock pulses to control the X drivers 81 and 82 and the Y driver 86, and Timing pulses Q1H that are mutually inverted are output to the liquid crystal drive circuits 72 and 73.

The liquid crystal drive circuits 72 and 73 are the circuit 71.
The RGB signal received from the liquid crystal drive signal Vsig
, -Vsig and output to the liquid crystal module 87.

Here, switching between Vsig and -Vsig is performed by X
The X driver 8 is performed in response to the input switching circuit 83 of the drivers 81 and 82, and when the liquid crystal drive circuits 72 and 73 perform any inversion method and color signal switching.
If the signal switching circuit 83 for 1 and 82 is not necessary and conversely all switching is performed by the signal switching circuit 83,
The liquid crystal drive circuits 72 and 73 always convert only to Vsig or -Vsig.

The liquid crystal drive video signal 79, the X driver control timing pulse 80, obtained as described above,
With the Y driver control timing pulse 85, pseudo interlaced full line driving can be performed without performing time axis conversion.

Here, the behavior of the Y driver is similar to the time axis drive method described in FIG. 9 in the output timing, but the operation is the same as the two line simultaneous drive method described in FIG. An operation combining the signal operations described in FIG. 3 is performed, and its output waveform is as shown in FIG.

FIG. 6 shows an embodiment for obtaining the same effect as that of the embodiment of FIG. 4 by using a conventional X driver in place of the X driver 82 having the structure shown in FIG. 4 (b). Is.

Two normal X drivers 101 and 102 are mounted on one double-sided mountable substrate 103, and the respective output lines are mounted.
Output patterns 107 on the respective boards are provided by making the output terminals 104 and 105 correspond to each other and providing through holes 106 at the corresponding points by making the wires 104 and 105 on both sides of the board using patterns. In contrast, the output lines of the two independent X drivers 101 and 102 are wired in parallel, and
An operation equivalent to that of the X driver described in 1) is possible.

This configuration is similar to the conventional X drivers 101 and 102.
There is no problem even if the two are doubled on the substrate to reduce the occupied area. Also, even if a normally mounted substrate is double-bonded, an operation equivalent to that in FIG. 4 can be performed.

In the above-described embodiment, in the embodiment of FIG. 4, only one liquid crystal drive IC is added and the X driver and the controller are changed, and the pseudo interlace system is used without changing the time axis of the video signal. Full line drive becomes possible.

The size of the liquid crystal drive IC is 15 mm × 12 mm for Toshiba IC (TA8696F).
It is about 2.5 mm, and the increase in the system of the video board is very small. Even for the liquid crystal module 87, the controller 74 can be realized only by changing the content, and the size of the X driver itself is also the same. Toshiba I
Since it is about 8 mm × 5.5 mm × 1 mm at C (T6A00), the expansion of the entire module does not matter regardless of whether the double latch configuration (FIG. 4), the parallel configuration (FIG. 6) or the double configuration is used. It becomes a degree.

In particular, compared with the case of using the time axis conversion method, two line memories for analog / digital conversion, read / write, a digital / analog converter, and an address counter IC are required for each of RGB. In order to drive these at high speed, it is necessary to take proper measures against spurious. In contrast,
The method of the present invention is very advantageous in terms of spuriousness because the digital signal exists only in the liquid crystal module shielded from the beginning and there is no need to digitally process the video signal.

Further, in FIG. 9, since the video signal is time-compressed to half, the video information band on the display is 4M.
In order to secure the Hz, the frequency band of 8 MHz, which is twice that, is required for the D / A converter, the liquid crystal drive circuit, and the X driver. In other words, when the same liquid crystal drive circuit is used, it becomes possible to obtain the characteristics excellent in frequency characteristics of the present invention. That is, the use of the present invention is advantageous in circuit design considering frequency characteristics.

[0059]

As described above, according to the present invention, when the liquid crystal panel of the delta array is driven by the full line of the pseudo interlace system, it can be realized with the minimum system addition as compared with the liquid crystal panel of the normal drive system. In addition, spurious and other image quality deterioration does not occur. This enables a wider range of applications as a high-definition display system.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing the relationship between CPH pulses and delta array liquid crystal pixels used in the embodiment of FIG.

FIG. 3 is a diagram showing drive timings and output timings of the X and Y drivers in the embodiment of FIG.

FIG. 4 is a configuration diagram showing a liquid crystal display device of another embodiment of the present invention.

5 is a diagram showing drive timings and output timings of the X and Y drivers in the embodiment of FIG.

6 is a configuration diagram showing another embodiment of the X driver configuration of FIG.

FIG. 7 is a configuration diagram showing a conventional full-line driving type liquid crystal display device by simultaneous driving of two lines.

8 is a diagram showing drive timing and output timing of the X and Y drivers in FIG.

FIG. 9 is a diagram showing a basic configuration of a conventional full line drive system by time-axis conversion of a video signal.

[Explanation of symbols]

 31, 32 ... X driver 33, 34 ... Y driver 35 ... Liquid crystal panel 36 ... Sample hold circuit 37 ... Shifter register 40, 43 ... Input pad 44 ... Liquid crystal cell 45 ... Thin film transistor (TFT)

[Procedure amendment]

[Submission date] June 25, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Fig. 2]

[Figure 3]

[Figure 1]

[Figure 4]

[Figure 5]

[Figure 6]

[Figure 7]

[Figure 8]

[Figure 9]

Claims (1)

[Claims] 1. Video information of one horizontal line of a certain field is displayed over any two adjacent lines, and in the next field, the display information of one line is displayed in a combination different from that of the previous field. In a pseudo interlaced display type liquid crystal display device using a delta array liquid crystal panel that is displayed in line, a delta array is provided for each X-side input pad that inputs horizontal information of the delta array liquid crystal panel that performs display. By connecting the driver outputs of two systems, which correspond to the upper and lower lines independently, and have both independent drive and high impedance function in parallel, while one driver is outputting, the other driver is in the high impedance state. X for writing video information alternately for each line
A driver and two arbitrary lines of a liquid crystal panel for displaying within a certain horizontal period are sequentially driven in correspondence with the upper and lower line writing of the X driver. A liquid crystal display device, comprising: a Y driver for performing serial write operation of writing information in one line and writing information in the remaining one line in the remaining half writing period.