JP2004303989A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which alleviates the possibility of disconnection remarkably about an electric connection to a memory peripheral circuit in a cross point type ferroelectric RAM, and to provide a method for manufacturing the same. <P>SOLUTION: An interlayer insulating film 15 and a silicon nitride film 16 are laminated on a predetermined region of a semiconductor substrate 11 surrounded by an element isolation insulating film 12, and a lower electrode 17 is formed in a stripe shape on this silicon nitride film 16. An upper electrode 19 is formed in a stripe shape above the lower electrode 17 so as to intersect the lower electrode 17. A ferroelectric thin film 18 is arranged between the lower electrode 17 and the upper electrode 19, the intersection area of both the electrodes is arranged in a matrix shape in a memory cell structure to constitute a memory 20. An interlayer insulating film 21 is formed to cover the memory part 20. The thickness of the interlayer insulating film L1 can be suppressed to low. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention particularly relates to a semiconductor device including a semiconductor integrated circuit having a cross-point type FeRAM (Ferroelectric Random Access Memory) cell and a method of manufacturing the same.
[0002]
[Prior art]
An FeRAM, a so-called ferroelectric memory, is one of the non-volatile memories having high speed, low power consumption, high integration, and excellent rewriting resistance. The ferroelectric memory can perform high-speed rewriting using the hysteresis characteristic of the ferroelectric thin film, that is, high-speed polarization inversion and its remanent polarization. In particular, a cross-point type FeRAM has a configuration in which memory cells having a structure in which a lower electrode and an upper electrode intersect via a ferroelectric thin film are arranged in a matrix, and is excellent in high integration.
[0003]
FIG. 3 is a cross-sectional view showing a part of a memory part and its periphery in a conventional cross-point type FeRAM. An element isolation insulating film 32 is formed on a semiconductor substrate 31, and a MOS element 34 serving as a peripheral circuit of a memory section is formed in an adjacent element region 33. An interlayer insulating film 35 is formed on the entire surface including on the MOS element 34. The interlayer insulating film 35 is planarized by using a CMP (chemical mechanical polishing) technique or the like, and a silicon nitride film 36 is formed on the interlayer insulating film 35. The silicon nitride film 36 functions as a barrier film provided at least in the memory unit 40 described later. That is, the silicon nitride film 36 is formed of oxygen during recovery annealing in an O ₂ atmosphere, which is performed after etching of a ferroelectric such as PZT (Pb (Zr, Ti) O ₃ ) or SBT (SrBi ₂ Ta ₂ O ₉ ). Is formed for the purpose of preventing the diffusion into the transistor element (gate oxide film, diffusion layer, etc.).
[0004]
A lower electrode 37 is formed in a stripe shape on the silicon nitride film 36 above the element isolation insulating film 32 in a predetermined region. Above the lower electrode 37, an upper electrode 39 is formed in a stripe shape so as to intersect. A ferroelectric thin film 38 is provided between the lower electrode 37 and the upper electrode 39, and a memory cell structure in which the intersecting regions of the two electrodes are arranged in a matrix form constitutes a memory section 40. An interlayer insulating film 41 is formed so as to cover the memory section 40.
[0005]
In the cross-point type FeRAM, the relationship between the sub-bit line potential of the lower electrode 37 and the word line potential of the upper electrode 39 is controlled, and the ferroelectric capacitors each having the ferroelectric thin film 38 are moved in a predetermined applied electric field direction. Polarize. The selected memory cell has a sub-bit line potential corresponding to the polarization state of the ferroelectric capacitor, and is transmitted to a selection transistor and a bit line (not shown). Such a cross-point type FeRAM is disclosed in Patent Document 1, for example.
[0006]
[Patent Document 1]
JP-A-9-116107 (pages 5 to 10)
[0007]
[Problems to be solved by the invention]
In FIG. 3, for example, an interlayer insulating film IL2 having a relatively large total thickness of an interlayer insulating film 35, a silicon nitride film 36, and an interlayer insulating film 41 is formed on a MOS element 34 serving as a peripheral circuit of a memory section. I have. In order to electrically connect to the MOS element 34, it is necessary to open a contact hole HL2 that reaches a target region from above the interlayer insulating film IL2 and to connect a wiring with a conductive member.
[0008]
According to the above configuration, the memory unit is provided on the element isolation insulating film 32 via the interlayer insulating film 35 and the silicon nitride film 36. As a result, the peripheral circuit of the memory section, for example, the contact hole HL2 to the MOS element 34 has a high aspect ratio, and there is a concern about disconnection of the aluminum wiring. In order to avoid such a problem of step coverage, use of a W (tungsten) plug may be considered. However, the ferroelectric memory requires oxygen annealing (heat treatment) for obtaining a stable hysteresis characteristic of the ferroelectric thin film 38, which is called recovery annealing as described above. As a result, when a W plug is used, oxidation proceeds on the upper surface of the W plug, and the wiring resistance increases. Therefore, we want to avoid using W plugs.
[0009]
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a semiconductor device and a method of manufacturing the same which greatly reduces the risk of disconnection in electrical connection to a peripheral circuit of a memory section in a cross-point type FeRAM. It is assumed that.
[0010]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes an element isolation insulating film on a semiconductor substrate, and an insulating film having a smaller thickness than the element isolation insulating film formed on a predetermined region of the semiconductor substrate surrounded by the element isolation insulating film. And a memory unit provided on the insulating film, in which memory cells having a ferroelectric thin film between the intersecting lower electrode and upper electrode are arranged in a matrix.
[0011]
According to the semiconductor device of the present invention, the memory section is provided on a predetermined region of the semiconductor substrate via an insulating film having a smaller thickness than the element isolation insulating film. Thereby, the height of the memory area is improved in a direction in which the difference in film thickness between adjacent interlayer insulating films is reduced.
[0012]
In the above-described semiconductor device according to the present invention, the insulating film is formed of a laminated film including a barrier film for the lower electrode.
Further, a MOS type device related to a peripheral circuit having a connection with the memory portion is further provided in an element region on the semiconductor substrate near the memory portion.
Further, the semiconductor device further includes a MOS type device related to a peripheral circuit having a connection with the memory portion in an element region on the semiconductor substrate near the memory portion, wherein the insulating film is an interlayer insulating film on the MOS type device. It is characterized by having.
Due to the above-described features, the aspect ratio of the contact hole when the MOS element is electrically connected to the memory portion is improved in a lower direction, and a mode of preventing disconnection can be obtained.
[0013]
The method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation insulating film on a semiconductor substrate, and a step of forming an element isolation insulating film on a predetermined region of the semiconductor substrate surrounded by the element isolation insulating film. Forming an insulating film having a thickness, and forming a memory portion on the insulating film in which memory cells having a ferroelectric thin film between a lower electrode and an upper electrode to be crossed are arranged in a matrix. And a step of performing
[0014]
According to the method of manufacturing a semiconductor device according to the present invention, the memory unit is provided on the predetermined region of the semiconductor substrate via the insulating film having a smaller thickness than the element isolation insulating film. Thereby, the height of the memory area is improved in a direction in which the difference in film thickness between adjacent interlayer insulating films is reduced.
[0015]
In the method of manufacturing a semiconductor device according to the present invention, the insulating film is a laminated film, and a barrier film for the lower electrode is formed on the insulating film.
The method may further include a step of forming a MOS element related to a peripheral circuit having a connection with the memory section in an element region on the semiconductor substrate near the memory section.
The method may further include forming a MOS type device related to a peripheral circuit having a connection with the memory portion in an element region on the semiconductor substrate near the memory portion, wherein the insulating film is formed by the MOS type device. It is achieved by the same process as the formation of the interlayer insulating film thereon.
With the features described above, the aspect ratio of the contact hole when electrically connecting the MOS element and the memory unit can be improved in a lower direction.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention, showing a part of a memory part and its periphery in a cross-point type FeRAM. FIG. 2 is a sectional view showing an intermediate step for realizing the configuration of FIG.
An element isolation insulating film 12 is formed on a semiconductor substrate 11, and a MOS element 14 serving as a peripheral circuit of a memory section is formed in an adjacent element region 13. An interlayer insulating film 15 is formed on the entire surface including the MOS element 14. On the interlayer insulating film 15, a silicon nitride film 16 is formed. As described above, the silicon nitride film 16 functions as a barrier film for preventing oxygen diffusion at the time of recovery annealing required at least when forming the memory portion.
[0017]
In this embodiment, an interlayer insulating film 15 and a silicon nitride film 16 are laminated on a predetermined region of a semiconductor substrate 11 surrounded by an element isolation insulating film 12, and a lower electrode 17 is formed in a stripe on the silicon nitride film 16. ing. The lower electrode 17 is, for example, Pt having a thickness of about 100 nm. Above the lower electrode 17, an upper electrode 19 is formed in a stripe shape so as to intersect. The upper electrode 19 is also made of, for example, Pt having a thickness of about 100 nm. The ferroelectric thin film 18 is provided between the lower electrode 17 and the upper electrode 19. Various types of the ferroelectric thin film 18 are conceivable. For example, the ferroelectric thin film 18 is selected from a PZT (Pb (Zr, Ti) O ₃ ) -based compound, a Bi-based compound having a layered structure (SBT (SrBi ₂ Ta ₂ O ₉ )) and the like. To adopt. The thickness of the ferroelectric thin film 18 is about 100 to 200 nm. As a result, a memory cell structure in which the intersecting regions of the lower electrode 17 and the upper electrode 19 are arranged in a matrix is formed, and the memory section 20 is formed. An interlayer insulating film 21 is formed so as to cover the memory section 20.
[0018]
That is, as shown in FIG. 2, the interlayer insulating film 15 and the silicon nitride film 16 after the formation of the MOS element 14 are laminated on the same semiconductor substrate 11 as the element region where the element isolation insulating film is not formed, and A base region is formed. The interlayer insulating film 15 is a SiO ₂ film having a thickness of about 100 nm and corresponds to a post-oxide film or the like. The silicon nitride film 16 has a thickness of about 50 nm and is configured as a barrier film and a protective film for the device. The memory unit 20 is formed in such a base region.
[0019]
For example, an interlayer insulating film IL1 having a total thickness of the interlayer insulating film 15, the silicon nitride film 16, and the interlayer insulating film 21 is formed on the MOS element 14 serving as a peripheral circuit of the memory unit 20. However, compared to the conventional technique, the thickness of the interlayer insulating film IL1 can be reduced. That is, since the memory section 20 is not formed above the element isolation insulating film 12, the thickness of the interlayer insulating film IL1 is generally smaller by a height corresponding to about half the thickness of the element isolation insulating film 12. can do.
[0020]
For electrical connection to a peripheral circuit of the memory section, for example, to the MOS element 14, it is necessary to open a contact hole HL1 which reaches a target region from above the interlayer insulating film IL1 and to wire it with a conductive member. Since the thickness of the interlayer insulating film IL1 is small, the aspect ratio of the contact hole HL1 is smaller than that of the conventional configuration, and the possibility of disconnection of the aluminum wiring is greatly reduced.
[0021]
According to the above-described embodiment and method, the memory unit 20 is provided on the predetermined region of the semiconductor substrate 11 via the insulating film (the lamination of the interlayer insulating film 15 and the silicon nitride film 16) having a smaller thickness than the element isolation insulating film 12. It is a form that can be done. Thereby, the height of the region of the memory unit 20 is improved in a direction in which the difference in thickness between the adjacent interlayer insulating films IL1 is reduced. As a wiring member filling the inside of the contact hole HL1, for example, an aluminum wiring is used as a main wiring layer. The aluminum wiring contains at least Cu in Al or a small amount of Si. By improving the aspect ratio of the contact hole HL1, the risk of disconnection in the aluminum wiring is greatly reduced.
[0022]
In addition, the interlayer insulating film IL1 has conventionally required a flattening process such as CMP to secure DOF (depth of focus). However, the aspect ratio of the contact hole HL1 becomes small, so that the CMP is not necessarily required. do not do. Thereby, an advantage of shortening the process can be expected.
[0023]
As described above, according to the present invention, the memory unit is provided on the predetermined region of the semiconductor substrate via the insulating film having a smaller thickness than the element isolation insulating film. Thereby, the height of the region of the memory portion is improved in a direction in which the difference in film thickness between adjacent interlayer insulating films is reduced. As a result, it is possible to provide a semiconductor device and a method of manufacturing the same that greatly reduce the possibility of disconnection in electrical connection to a peripheral circuit of a memory unit in a cross-point type FeRAM.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention, showing a part of a memory part and a periphery thereof in a cross-point type FeRAM.
FIG. 2 is a sectional view showing an intermediate step for realizing the configuration of FIG. 1;
FIG. 3 is a cross-sectional view showing a part of a memory part and its periphery in a conventional cross-point type FeRAM.
[Explanation of symbols]
11, 31: semiconductor substrate, 12, 32: element isolation insulating film, 13, 33: element region, 14, 34: MOS element, 15, 35: interlayer insulating film, 16, 36: silicon nitride film, 17, 37 ... Lower electrode, 18, 38... Ferroelectric thin film, 19, 39... Upper electrode, 20, 40.

Claims (8)

An element isolation insulating film on a semiconductor substrate,
An insulating film having a thickness smaller than that of the element isolation insulating film formed on a predetermined region of the semiconductor substrate surrounded by the element isolation insulating film;
A memory unit provided on the insulating film, in which memory cells having a ferroelectric thin film between the intersecting lower electrode and upper electrode are arranged in a matrix,
A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein the insulating film is formed of a laminated film including a barrier film for the lower electrode. 3. The semiconductor device according to claim 1, further comprising a MOS element related to a peripheral circuit having a connection with the memory unit in an element region on the semiconductor substrate near the memory unit. The semiconductor device further includes a MOS element related to a peripheral circuit having a connection with the memory section in an element region on the semiconductor substrate near the memory section, and the insulating film is an interlayer insulating film on the MOS element. 3. The semiconductor device according to claim 1, wherein: Forming an element isolation insulating film on the semiconductor substrate;
Forming an insulating film having a thickness smaller than that of the element isolation insulating film on a predetermined region of the semiconductor substrate surrounded by the element isolation insulating film;
Forming a memory portion on the insulating film, in which memory cells having a ferroelectric thin film between a lower electrode and an upper electrode to intersect are arranged in a matrix;
A method for manufacturing a semiconductor device, comprising: 6. The method according to claim 5, wherein the insulating film is a laminated film, and a barrier film for the lower electrode is formed thereon. 7. The semiconductor according to claim 5, further comprising a step of forming a MOS-type element related to a peripheral circuit having a connection with the memory section in an element region on the semiconductor substrate near the memory section. apparatus. Forming a MOS-type device related to a peripheral circuit having a connection with the memory portion in an element region on the semiconductor substrate near the memory portion; and forming the insulating film on the MOS-type device. 7. The method for manufacturing a semiconductor device according to claim 5, wherein the method is achieved in the same step as the formation of the interlayer insulating film.

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