JP2004303985A - Ferroelectric memory device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To incorporate a sufficient adhesion force in a region disposed on an insulating layer in the upper electrode of a ferroelectric capacitor and to prevent a hydrogen invaded from the upper electrode from reaching a ferroelectric layer. <P>SOLUTION: An adhesion layer is disposed at least on the bottom of the upper electrode, and a material having a hydrogen barrier performance is used as this adhesion layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a ferroelectric memory device including a memory cell array and a method for manufacturing the same.
[0002]
[Prior art]
In manufacturing a ferroelectric memory device, after a ferroelectric layer is formed, the ferroelectric layer may be exposed to a hydrogen atmosphere in a step of forming an interlayer insulating layer, a dry etching step, or the like. The ferroelectric layer generally comprises a metal oxide. Therefore, when the ferroelectric layer is exposed to hydrogen, oxygen constituting the ferroelectric layer is reduced by hydrogen. As a result, the ferroelectric layer is damaged. For example, if the ferroelectric layer is made of SBT (SrBi ₂ Ta ₂ O ₉ ), When the SBT is reduced by hydrogen, metal Bi is generated at the grain boundary, and the upper electrode and the lower electrode are short-circuited. In order to prevent this, a protective film called a hydrogen barrier film is coated on the ferroelectric capacitor. Various oxides have been studied as hydrogen barrier films. ₂ O ₃ Is attracting attention as a promising candidate material because it exhibits excellent hydrogen barrier performance. These materials are generally formed by a sputtering method or the like. However, when the step coverage is poor, the hydrogen barrier is not formed with a sufficient film thickness on the side wall depending on the shape of the upper electrode. For this reason, there has been a problem that the ferroelectric layer is reduced by hydrogen penetrating from the side wall of the upper electrode, and the ferroelectric performance is significantly deteriorated.
[0003]
When the upper electrode of the ferroelectric capacitor is used as a wiring and connected to an element driving transistor and other peripheral circuits formed outside the capacitor region, the upper electrode is formed not only on the ferroelectric layer but also on the capacitor. It is also arranged on the peripheral interlayer insulating film. However, depending on the material of the interlayer insulating film, sufficient adhesion between the upper electrode and the upper electrode cannot be obtained, and the upper electrode peels off from the interlayer insulating film due to an external stress caused by a process or an internal stress of the upper electrode itself. There was a problem that it would. A similar phenomenon occurs between the upper electrode and the interlayer insulating film coated thereon.
[0004]
[Problems to be solved by the invention]
An object of the present invention is to provide a ferroelectric capacitor that secures adhesion between an upper electrode and an interlayer insulating film and, at the same time, prevents hydrogen penetrating from a side wall of the upper electrode from reaching a ferroelectric layer. I have.
[0005]
[Means for Solving the Problems]
(1) In the ferroelectric memory element of the present invention, memory cells are arranged in a matrix, and a lower electrode, an upper electrode arranged in a direction intersecting the lower electrode, at least the upper electrode and the lower electrode, In a ferroelectric memory element in which a ferroelectric layer disposed in an intersection region of and a ferroelectric memory element in which an interlayer insulating layer including a hydrogen barrier film is formed on at least a memory cell array, an adhesion layer is disposed on a bottom surface or an upper surface of the upper electrode. It is characterized by having been done.
According to the above configuration, there is an effect that the adhesion between the upper electrode and the interlayer insulating film deposited thereunder or the adhesion between the upper electrode and the interlayer insulating film coated thereon can be improved.
[0006]
(2) In the ferroelectric memory element of the present invention, the memory cells are arranged in a matrix, and a lower electrode, an upper electrode arranged in a direction intersecting the lower electrode, at least the upper electrode and the lower electrode, And a ferroelectric memory element in which an interlayer insulating layer including a hydrogen barrier layer is formed on at least the memory cell array, and an adhesion layer on both the bottom and top surfaces of the upper electrode. Are arranged.
According to the above configuration, it is possible to improve the adhesion between the upper electrode and the interlayer insulating film deposited thereunder simultaneously with the adhesion between the upper electrode and the interlayer insulating film deposited thereunder. Have.
[0007]
(3) In the ferroelectric memory device according to the present invention, the ferroelectric layer is provided in an intersection region between the lower electrode and the upper electrode, and an intermediate portion is provided between the ferroelectric layer and the upper electrode. An electrode is provided.
According to the above configuration, there is an effect that an insulating material can be used as the adhesion layer.
[0008]
(4) The ferroelectric memory element according to the present invention is characterized in that the adhesion layer is made of a material having a hydrogen barrier property. According to the above configuration, there is an effect that it is possible to prevent hydrogen invading from above the upper electrode or from the side wall of the upper electrode from reaching the ferroelectric layer.
[0009]
(5) The ferroelectric memory element according to the present invention is characterized in that the adhesion layer provided on the bottom surface of the upper electrode is not formed only in an intersection region between the upper electrode and the lower electrode.
According to the above configuration, there is an effect that an insulating material can be used as the adhesion layer.
[0010]
(6) In the ferroelectric memory element according to the present invention, in the adhesion layer provided on the bottom surface of the upper electrode, an opening smaller than the area of the intersection region in the intersection region between the upper electrode and the lower electrode is provided. Is provided.
According to the above configuration, there is an effect that the amount of hydrogen that enters from directly above the ferroelectric layer can be minimized.
[0011]
(7) The ferroelectric memory element according to the present invention is characterized in that the material having the hydrogen barrier performance is an oxide.
According to the above configuration, there is an effect that the adhesion between the upper electrode and the interlayer insulating layer can be made extremely strong.
[0012]
(8) The ferroelectric memory element according to the present invention is characterized in that the material having the hydrogen barrier performance is a conductive material.
According to the above configuration, it is not necessary to provide an opening for connecting the intermediate electrode and the upper electrode in the adhesion layer, and the process is simplified.
[0013]
(9) The ferroelectric memory element according to the present invention is characterized in that the conductive material is an iridium oxide film.
According to the above configuration, there is an effect that the hydrogen invading from the upper portion of the upper electrode or the hydrogen invading from the side wall portion of the upper electrode can be more efficiently shielded and the characteristic deterioration of the ferroelectric can be prevented.
[0014]
(10) In the ferroelectric memory element of the present invention, the oxide is Al ₂ O ₃ Characterized by containing an oxide represented by the following chemical formula:
According to the above configuration, since the adhesion layer exerts extremely excellent hydrogen barrier performance, there is an effect that hydrogen entering from above the upper electrode or the side wall of the upper electrode can be cut off from the ferroelectric layer.
[0015]
(11) A ferroelectric memory element according to the present invention includes a peripheral circuit section for selectively writing or reading information to or from the memory cell, and the hydrogen barrier film is provided on the peripheral circuit section. Is not formed.
According to the above configuration, since the hydrogen barrier film is not formed on the peripheral circuit portion, hydrogen can enter the peripheral circuit portion, so that the peripheral circuit portion can be recovered by hydrogen. That is, there is an effect that the peripheral circuit portion can be recovered by hydrogen while suppressing the reduction of the ferroelectric layer of the memory cell array by hydrogen.
[0016]
(12) A ferroelectric memory element according to the present invention includes a peripheral circuit portion for selectively writing or reading information to or from the memory cell, and the adhesion layer is formed on the peripheral circuit portion. It is not formed.
According to the above configuration, since the adhesion layer is not formed on the peripheral circuit portion, hydrogen can enter the peripheral circuit portion, so that the peripheral circuit portion can be recovered by hydrogen. In other words, in the area of the memory cell array, there is an effect that the peripheral circuit portion can be recovered by hydrogen while securing the adhesion between the upper electrode and the insulating layer.
[0017]
(13) A method of manufacturing a ferroelectric memory element according to the present invention is a method of manufacturing a ferroelectric memory element including a memory cell array in which memory cells each formed of a ferroelectric capacitor are arranged in a matrix. Process.
(A) forming a first conductive layer on a substrate;
(B) forming a ferroelectric layer on the first conductive layer;
(C) forming a second conductive layer on the ferroelectric layer.
(D) a step of patterning at least the ferroelectric layer and the second conductive layer.
(E) forming an insulating layer on the substrate so as to cover a stacked body including the first conductive layer, the ferroelectric layer, and the second conductive layer.
(F) forming a thin film having hydrogen barrier performance as an adhesion layer on the insulating layer;
(G) forming an opening having a desired shape in the adhesion layer at a position overlapping with the ferroelectric layer;
(H) forming a third conductive layer of a desired pattern connected to the second conductive layer through the opening;
According to the above method, the third conductive layer is connected to the second conductive layer through the opening of the adhesion layer, and in the other area, the third conductive layer is disposed on the insulating layer through the adhesion layer. A sufficient adhesive force is obtained between the conductive layer and the substrate, which has an effect that the third conductive layer does not peel off. According to the above method, a hydrogen barrier is also formed in the lower region of the third conductive layer. Therefore, it is possible to prevent hydrogen invading from the upper portion or the side wall of the third conductive layer from reaching the ferroelectric layer. It has the effect of being able to.
[0018]
(14) The method of manufacturing a ferroelectric memory element according to the present invention is characterized in that the opening formed in the step (g) is formed smaller than the area of the ferroelectric layer.
According to the above method, there is an effect that the amount of hydrogen entering from the opening can be minimized.
[0019]
(15) The method of manufacturing a ferroelectric memory element according to the present invention is characterized in that in the step (e), after forming an insulating layer, the insulating layer is exposed to oxygen plasma.
According to the above method, since moisture contained in the insulating layer can be efficiently removed, there is an effect that deterioration of the film quality of the thin film having a hydrogen barrier function formed thereon can be prevented.
[0020]
(16) A method of manufacturing a ferroelectric memory element according to the present invention is characterized in that in the step (h), the third conductive layer is exposed to an oxygen plasma atmosphere.
According to the above method, there is an effect that an oxide film as an adhesion layer also having a hydrogen barrier performance can be formed on the upper surface of the third conductive layer in a self-aligned manner.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
1.1 Device structure
FIG. 1 is a diagram schematically showing a ferroelectric memory device, and FIG. 2 is a cross-sectional view schematically showing a part of the ferroelectric memory device along line AA in FIG. FIG. 3 is a sectional view schematically showing a part of the ferroelectric memory device along the line BB in FIG. FIG. 4 is an enlarged schematic cross-sectional view of the memory cell array in FIG. FIG. 5 is an enlarged schematic cross-sectional view of the memory cell array in FIG. 3, and FIG. 5 is an enlarged schematic cross-sectional view of the memory cell array in FIG.
[0022]
The ferroelectric memory device 1000 has a memory cell array 100 and a peripheral circuit section 200. The memory cell array 100 and the peripheral circuit section 200 are formed in different layers. The peripheral circuit section 200 is formed in a region outside the memory cell array 100. Specifically, the peripheral circuit portion formation region A200 is provided in a region outside the memory cell array formation region A100. In this example, a peripheral circuit section 200 is formed in a lower layer, and a memory cell array 100 is formed in an upper layer. Specific examples of the peripheral circuit unit 200 include a Y gate, a sense amplifier, an input / output buffer, an X address decoder, a Y address decoder, and an address buffer.
[0023]
In the memory cell array 100, a lower electrode (word line) 12 for selecting a row and an upper electrode (bit line) 16 for selecting a column are arranged so as to be orthogonal to each other. That is, the lower electrodes 12 are arranged at a predetermined pitch along the X direction, and the lower electrodes are arranged at a predetermined pitch along the Y direction orthogonal to the X direction. Note that the lower electrode 12 may be a bit line and the upper electrode may be a word line.
[0024]
The memory cell array 100 is provided on the first interlayer insulating layer 10, as shown in FIGS. As shown in FIGS. 4 and 5, the memory cell array 100 has a lower electrode 12, a ferroelectric layer 14 constituting a ferroelectric capacitor, an intermediate electrode 18, and an upper electrode (upper electrode) on a first interlayer insulating layer 10. ) 16 are stacked. The ferroelectric layer 14 and the intermediate electrode 18 are provided in the intersection region between the lower electrode 12 and the upper electrode 16. That is, a memory cell including the ferroelectric capacitor 20 is formed in a region where the lower electrode 12 and the upper electrode 16 intersect.
[0025]
As shown in FIG. 5, an insulating layer 72 is formed so as to cover at least the lower electrode 12 of the ferroelectric capacitor 20. By providing the insulating layer 72, a short circuit between the lower electrode 12 and the intermediate electrode 18 or the upper electrode 16 is prevented. As the insulating layer 72, ozone TEOS-SiO having good step coverage is used. ₂ It is desirable to use a membrane. A first hydrogen barrier film 42 is formed thereon. Thereby, the groove between the adjacent ferroelectric capacitors is filled.
[0026]
As shown in FIGS. 4 and 5, an adhesion layer 40 is formed on at least the bottom surface of the upper electrode 16 in order to increase the adhesion with the insulating layer 72. In the present example, an oxide of titanium was applied as the adhesion layer. Since this is an insulating material, an opening is provided above the ferroelectric capacitor. The upper electrode 16 is connected to the intermediate electrode 18 through this opening.
[0027]
A second hydrogen barrier film 44 is formed to cover the entire surface of memory cell array 100. By forming the second hydrogen barrier film 44, the ferroelectric layer 14 of the ferroelectric capacitor 20 is reduced by hydrogen generated in a process after the formation of the second hydrogen barrier film 44 (for example, a passivation film forming process). Can be suppressed. Here, the material of the first hydrogen barrier film 42 or the second hydrogen barrier film 44 is not particularly limited as long as it has a hydrogen barrier function. However, in order to prevent a short circuit between the upper electrode and the lower electrode of the ferroelectric capacitor, the first hydrogen barrier film 42 needs to use an insulating material. Possible materials include aluminum oxide, magnesium oxide, zirconium oxide, titanium oxide, and hafnium oxide. On the other hand, the second hydrogen barrier film may be not only an insulating material but also a conductive material as long as the material has a hydrogen barrier performance.
[0028]
The first hydrogen barrier film 42 may not be formed in the formation region A200 of the peripheral circuit portion. Thus, the peripheral circuit section 200 can be recovered with hydrogen while suppressing the ferroelectric layer 16 in the memory cell array 100 from being reduced by hydrogen.
[0029]
As shown in FIGS. 2 and 3, a first protective layer 36 is formed on the first interlayer insulating layer 10 so as to cover the memory cell array 100. Further, an insulating second protection layer 38 is even formed on the first protection layer 36 so as to cover the wiring layer 19.
[0030]
A second hydrogen barrier film 44 is formed between the first protective layer 36 and the second protective layer 38. The second hydrogen barrier film 44 can be formed at least in the memory cell array region A100. By forming the second hydrogen barrier film 44, the ferroelectric layer 14 in the memory cell array 100 is reduced by hydrogen by hydrogen generated in a process after the formation of the second hydrogen barrier film 44 (for example, a passivation film forming process). Can be suppressed more reliably. The material of the second hydrogen barrier film 44 is not particularly limited as long as it has a hydrogen barrier function, and may be insulating or non-insulating. When the second hydrogen barrier film 44 is made of an insulating material, the material of the second hydrogen barrier film 44 may be the same as that of the first hydrogen barrier film 42. When the second hydrogen barrier film 44 is made of a conductive material, examples of the material of the second hydrogen barrier film 44 include titanium, iridium oxide, titanium nitride, and aluminum.
[0031]
Further, the second hydrogen barrier film 44 may not be formed in the peripheral circuit region A200. This makes it possible to recover the peripheral circuit portion with hydrogen while suppressing reduction of the ferroelectric layer 14 in the memory cell array 100 by hydrogen.
[0032]
As shown in FIG. 1, the peripheral circuit section 200 includes various circuits for selectively writing or reading information to or from the memory cell, and includes, for example, a first circuit for selectively controlling the lower electrode 12. One drive circuit 50, a second drive circuit 52 for selectively controlling the upper electrode 34, and a signal detection circuit (not shown) such as a sense amplifier are included.
[0033]
Further, the peripheral circuit section 200 includes a MOS transistor 112 formed on the semiconductor substrate 110 as shown in FIG. The MOS transistor 112 has a gate insulating layer 112a, a gate electrode 112b, and source / drain regions 112c. Each MOS transistor 112 is isolated by an element isolation region 114. On the semiconductor substrate 110 on which the MOS transistor 112 is formed, the first interlayer insulating layer 10 is formed. The peripheral circuit section 200 and the memory cell array 100 are electrically connected by the wiring layer 19.
[0034]
Next, an example of writing and reading operations in the ferroelectric memory device 1000 will be described.
[0035]
First, in the read operation, the read voltage “V” is applied to the capacitor of the selected cell. ₀ Is applied. This also serves as a write operation of “0” at the same time. At this time, the current flowing through the selected bit line or the potential when the bit line is set to high impedance is read by the sense amplifier. At this time, a predetermined voltage is applied to the capacitors of the non-selected cells in order to prevent crosstalk during reading.
[0036]
In the write operation, when writing “1”, “−V” is applied to the capacitor of the selected cell. ₀ Is applied. In the case of writing “0”, a voltage that does not reverse the polarization of the selected cell is applied to the capacitor of the selected cell, and the “0” state written during the read operation is maintained. At this time, a predetermined voltage is applied to the capacitors of the non-selected cells in order to prevent crosstalk during writing.
[0037]
1.2 Effects
Hereinafter, the function and effect of the ferroelectric memory device 1000 will be described.
(1) In the present embodiment, the adhesion layer 40 is disposed on the bottom surface of the upper electrode 16. The material of the adhesive layer is not limited as long as it is a material that improves the adhesive strength between the insulating layer 72 and the upper electrode 16. An oxide is preferable in consideration of compatibility with the insulating layer. This makes it possible to sufficiently increase the adhesive force between the upper electrode 16 and the interlayer insulating film 72, thereby improving the mechanical strength of the element.
[0038]
(2) In the present embodiment, the first hydrogen barrier film 42 is provided so as to cover at least the entire surface of the memory cell array 100. Therefore, the following operation and effect can be obtained.
[0039]
By providing the first hydrogen barrier film 42, reduction of the ferroelectric layer 14 by hydrogen generated in a process after the formation of the first hydrogen barrier film 42 can be suppressed.
[0040]
Further, since the first hydrogen barrier film 42 is formed on the entire surface, it is not necessary to pattern the first hydrogen barrier film 42 into a fine pattern. Therefore, patterning of the first hydrogen barrier film 42 becomes easy.
[0041]
(3) In the present embodiment, the second hydrogen barrier film 44 is provided on the first protective layer 36 at least in the memory cell array formation region A100. For this reason, the same operation and effect as those described in the first hydrogen barrier film 42 can be obtained.
[0042]
(4) The ferroelectric layer 14 is formed in a region where the upper electrode 16 and the lower electrode 12 intersect. Therefore, it is possible to suppress the lines of electric force from protruding outside from the capacitor. As a result, the electric field in the ferroelectric layer 14 can be strengthened, so that the voltage required to make the ferroelectric layer 14 have a constant polarization value can be suppressed. Therefore, the hysteresis loop can be approximated to a square. As a result, according to the ferroelectric memory device 1000, the characteristics of the ferroelectric capacitor 20 can be improved.
[0043]
1.3 Process
Next, an example of a method for manufacturing the above-described ferroelectric memory device will be described. 6 to 14 are cross-sectional views schematically showing manufacturing steps of the ferroelectric memory device 1000. 7 to 17 are cross-sectional views showing only the memory cell array region.
[0044]
As shown in FIG. 6, a peripheral circuit 200 is formed using a known LSI process. Specifically, the MOS transistor 112 is formed on the semiconductor substrate 110. For example, the MOS transistor 112 is formed over the semiconductor substrate 110. For example, an element isolation region 114 is formed in a predetermined region on the semiconductor substrate 110 by using a trench isolation method, a LOCOS method, or the like, a gate insulating layer 112a and a gate electrode 112b are formed, and then the semiconductor substrate 110 is doped with impurities. By doing so, the source / drain region 112c is formed. Thus, the peripheral circuit section 200 including various circuits such as the drive circuits 50 and 52 and the signal detection circuit 54 is formed. Next, the first interlayer insulating layer 10 is formed by a known method.
Next, the memory cell array 100 is formed on the first interlayer insulating layer 10. Hereinafter, a method for forming the memory cell array 100 will be described with reference to FIGS.
[0045]
First, as shown in FIG. 7, a first conductive layer 12a for the lower electrode 12 is formed on the first interlayer insulating layer 10. The material of the first conductive layer 12a is not particularly limited as long as it can be an electrode of a ferroelectric capacitor. As a material of the first conductive layer 12a, for example, Ir, IrO _x , Pt, RuO _x , SrRuO _x , LaSrCoO _x And the like. Further, as the first conductive layer 12a, a single layer or a stacked layer of a plurality of layers can be used. As a method for forming the first conductive layer 12a, a method such as sputtering, vacuum deposition, or CVD can be used.
[0046]
Next, a ferroelectric layer 14a is formed on the first conductive layer 12a. As the material of the ferroelectric layer 14a, any composition can be applied as long as it exhibits ferroelectricity and can be used as a capacitor insulating layer. As such a ferroelectric, for example, PZT (PbZr _z Ti _1-z O ₃ ), SBT (SrBi ₂ Ta ₂ O ₉ ), And those obtained by adding elements such as niobium, nickel, and magnesium to these materials can be applied. Examples of the method of forming the ferroelectric layer 14a include a spin coating method using a sol-gel material or a MOD material, a dipping method, a sputtering method, an MOCVD method, and a laser ablation method.
[0047]
Next, a second conductive layer 18a for the intermediate electrode 18 is formed on the ferroelectric layer 14a. As the material and the forming method of the second conductive layer 18a, the same material as that of the first conductive layer 12a can be applied.
[0048]
Next, a mask layer 60 is formed on the entire surface, and the mask layer is patterned by lithography and etching. That is, the mask layer 60 is formed on a region where the lower electrode 12 is to be formed. The material of the mask layer 60 is not particularly limited as long as it can function as a mask when the second conductive layer 18a, the ferroelectric layer 14a and the first conductive layer 12a are etched. For example, silicon nitride, silicon oxide And titanium nitride. The mask layer 60 can be formed by, for example, a CVD method.
[0049]
Next, as shown in FIG. 8, using the mask layer 60 as a mask, the second conductive layer 18a, the ferroelectric layer 14a and the first conductive layer 12a are etched, and the second conductive layer 18a, the ferroelectric layer 14a and The first conductive layer 12a is patterned. By patterning the first conductive layer 12a, the lower electrode 12 having a predetermined pattern is formed. Examples of the etching method include RIE, sputter etching, and plasma etching.
[0050]
Next, as shown in FIG. 9, an insulating layer 72 is formed on the entire surface. The material of the insulating layer 72 is not particularly limited as long as the same etching rate as that of the mask layer 60 can be obtained in a later etch-back step of the first insulating layer. If coverage performance is prioritized for the purpose of embedding between capacitors, ozone TEOS-SiO ₂ Preferably, a membrane is used. As a method for forming the insulating layer 72, for example, a CVD method can be given. When the material and the forming method of the insulating layer 72 are the same as the material and the forming method of the mask layer 60, the etching rates of the insulating layer 72 and the mask layer 60 are easily made the same. The insulating layer 72 is formed so as to cover a stacked body (hereinafter, referred to as a “stacked body”) of the lower electrode 12, the ferroelectric layer 14a, the second conductive layer 18a, and the mask layer 60, and to fill the space between the stacked bodies. Is done.
[0051]
Next, as shown in FIG. 10, a resist layer R1 is formed on the insulating layer 72. The resist layer R1 is formed so that its upper surface is flat. The resist layer R1 can be formed by a spin coating method. The thickness of the resist layer R1 can be about twice (for example, 0.8 μm) the depth of the concave portion formed in the insulating layer 72. When an insulating layer having a flat upper surface is formed by using a coating method, the resist layer R1 may not be formed. Specifically, when the insulating layer 72 is made of an SOG (Spin On Glass) layer, the resist layer R1 may not be formed.
[0052]
Next, as shown in FIG. 11, the insulating layer 72 and the resist layer R1 are etched back. Simultaneously with this etch-back, the mask layer 60 is removed and exposed on the upper surface of the second conductive layer 18a. The etching method can be performed by dry etching such as RIE. In addition, the etching rates of the resist layer R1 and the insulating layer 72 can be the same. For example, as an etching etchant, CHF ₃ And O ₂ Can be applied, and the selectivity between the resist layer R1 and the insulating layer 72 is CHF ₃ And O ₂ Can be controlled by the mixing ratio with During this etch back, the insulating layer 72 covers at least the side wall of the lower electrode 12.
[0053]
Next, as shown in FIG. 12, an adhesion layer 40a is deposited on the entire surface. In this embodiment, an oxide of titanium is used as the adhesion layer 40a. Next, an opening H1 having a desired shape is provided at a desired position of the adhesion layer. This opening is provided at a position overlapping with the ferroelectric layer 14a and serves as a contact area with the second conductive layer 18a.
[0054]
Next, as shown in FIG. 13, the third conductive layer 16a is formed on the adhesion layer 40a. As a result, the third conductive layer is connected to the second conductive layer 18a through the opening H1. A resist R2 having a predetermined pattern is formed on the third conductive layer 16a. The resist layer R2 is formed on a region where the upper electrode 16 is to be formed.
[0055]
Next, the third conductive layer 16a, the adhesion layer 40a, the second conductive layer 18a, the ferroelectric layer 14a, and the insulating layer 72 are etched using the resist layer R2 as a mask. Thus, as shown in FIGS. 14 and 15, the upper electrode 16 is formed by patterning the third conductive layer 16a. Further, by patterning the second conductive layer 18a and the ferroelectric layer 14a, the intermediate electrode 18 and the ferroelectric layer 14 are formed in the intersection region between the upper electrode 16 and the lower electrode 12. Note that the adhesive layer 40 and the insulating layer 72 remain under the upper electrode 16 except for the region where the upper electrode 16 and the lower electrode 12 intersect. Thus, the memory cell array 100 is formed.
[0056]
Next, as shown in FIGS. 1 and 16, a first hydrogen barrier film 42 is formed. Here, the material of the first hydrogen barrier 42 is not particularly limited as long as it has a hydrogen barrier function. However, it is necessary to use an insulating material for the first hydrogen barrier film 42 in order to prevent a short circuit between the upper electrode and the lower electrode of the ferroelectric capacitor. Possible materials include aluminum oxide, magnesium oxide, zirconium oxide, titanium oxide, hafnium oxide, and the like. As a film formation method, a sputtering method, an MOCVD method, a laser ablation method, or the like can be used. The first hydrogen barrier film 42 is patterned so as to cover at least the entire surface of the memory cell array 100.
[0057]
Next, the first protective layer 36 is formed on the first hydrogen barrier film 42 by a known method. Next, the first protective layer 36 is planarized as necessary.
[0058]
Next, a second hydrogen barrier film 44 is formed on the first protection layer 36. As a method for forming the second hydrogen barrier film 44, the method described for the first hydrogen barrier film 42 can be used. The second hydrogen barrier film 44 is patterned so as to cover at least the entire surface of the memory cell array 100. Next, a second protective layer 38 is formed on the first protective layer 36 and the second hydrogen barrier film 44.
[0059]
1.4 Process effects
When the third conductive layer 16a is formed directly on the insulating layer 72, the adhesion between the third conductive layer 16a and the insulating layer 72 is weak, and the third conductive layer 16a is formed during the process after the patterning step of the third conductive layer. There is a problem that separation occurs between the layer and the insulating layer. In particular, when the upper electrode of the ferroelectric capacitor is used also as a wiring for connecting to a peripheral drive circuit portion as in the ferroelectric memory element of the present invention, the third conductive layer (upper electrode) is an interlayer insulating film. The area arranged on the layer becomes larger. If peeling or the like occurs at this portion, disconnection will occur.
[0060]
By arranging the adhesion layer on the bottom surface of the third conductive layer (upper electrode) as in the above-described process shown in this embodiment, the adhesion to the underlying insulating layer is significantly improved. If the internal stress of the third conductive layer itself and an adhesive force that can withstand the external stress caused by the hydrogen barrier film or other insulating film coated thereon can be obtained, peeling and disconnection of the upper electrode during the process can be prevented. be able to.
[0061]
(Embodiment 2)
As the adhesion layer 40 described in the first embodiment, an oxide material having a hydrogen barrier performance was used. In this example, an aluminum oxide having extremely excellent hydrogen barrier performance was applied. Except for changing the material, the structure and process of the element are the same as those of the first embodiment. As shown in FIG. 5, when a material having a hydrogen barrier function as the adhesion layer is used, the adhesion between the upper electrode 16 and the insulating layer 72 can be improved, and at the same time, the upper surface or the side wall of the upper electrode 16 can be improved. Hydrogen invading from the portion can be prevented from reaching the ferroelectric layer 14. Preventing the intrusion of hydrogen from the upper electrode region is extremely important for maintaining the film quality of the ferroelectric layer 14. Platinum is often used as a material for the upper electrode, and this platinum has a very large catalytic effect. Therefore, the hydrogen that has invaded the upper electrode is activated here. The activated hydrogen has a stronger reducing action, and when it reaches the ferroelectric layer, the crystallinity of the ferroelectric crystal is significantly impaired. In order to investigate the effect of this on the characteristics of the ferroelectric capacitor, a contrasting sample was prepared and the characteristics were evaluated. The results are shown in FIGS.
[0062]
FIG. 17 shows the ferroelectric characteristics measured in the memory cell after the second protective layer 38 is formed by applying a titanium oxide as the adhesion layer 40. Significant deterioration of the hysteresis loop was observed, and the amount of remanent polarization was greatly reduced. On the other hand, FIG. 18 shows the result when an oxide of aluminum is used as the adhesion layer 40. As is clear from comparison with FIG. 17, the hysteresis loop maintains the initial shape, and a large amount of remanent polarization is obtained.
[0063]
In view of the above, a material having a hydrogen barrier property is used for the adhesion layer between the upper electrode 16 and the insulating layer 72, and the function of the hydrogen barrier is simultaneously provided while securing the adhesion force, so that the hydrogen resistance of the ferroelectric capacitor is improved. Was found to improve dramatically.
[0064]
(Embodiment 3)
In the second embodiment, the adhesion layer 40 (aluminum oxide) having a hydrogen barrier property is disposed only on the bottom surface of the upper electrode 16. In the present embodiment, this is also arranged on the upper surface of the upper electrode 16. As a result, as a countermeasure against hydrogen generated when the first protective layer 36 or the second protective layer 38 is formed, the hydrogen barrier function above the upper electrode can be more focused. In addition, since the adhesion between the first hydrogen barrier film 42 and the upper electrode 16 can be improved, it is possible to increase the mechanical strength of the element.
[0065]
When aluminum or iridium is used as the upper electrode, an aluminum or iridium oxide film can be formed on the upper surface of the upper electrode by exposing the upper electrode to oxygen plasma. This oxide film can be used as the above-mentioned adhesion layer also serving as a hydrogen barrier. By exposing the upper electrode to a plasma atmosphere after patterning, an oxide film can be formed on the upper surface or the side surface of the upper electrode in a self-aligned manner, so that the patterning process can be simplified and the process can be made more efficient.
[0066]
(Embodiment 4)
In the second embodiment, an insulating material is used as the adhesion layer 40 having the hydrogen barrier performance. In this embodiment, an oxide film of iridium, which is a conductive material, is used as the adhesion layer 40. When the conductive material is used as the adhesion layer in this manner, it is not necessary to form the opening H1 in FIG. 12 described in the first embodiment. After the formation of the adhesion layer 40, the third conductive layer 16a can be continuously formed, so that the process can be simplified.
[0067]
The use of an iridium oxide film as the adhesion layer as in this embodiment is extremely effective as a countermeasure against process-induced hydrogen, as described in the second embodiment. FIG. 19 shows ferroelectric characteristics measured in a memory cell after forming the second protective layer 38 by applying an iridium oxide film as the adhesion layer 40.
[0068]
It can be seen that the same hysteresis characteristics as in the case of applying the aluminum oxide film as the adhesion layer in the third embodiment are obtained. Since the iridium oxide film exhibits extremely excellent hydrogen barrier performance, it has become possible to prevent hydrogen that has entered from above or on the side wall of the upper electrode 16 from reaching the ferroelectric layer.
[0069]
(Embodiment 5)
A ferroelectric memory element was manufactured in the same configuration as in the first embodiment. In this embodiment, as shown in FIG. 11, the insulating layer 72 is made of ozone TEOS-SiO. ₂ The film was exposed to an oxygen plasma atmosphere for an appropriate time. Thereafter, the steps after the formation of the adhesion layer 40 are the same as those in the first embodiment. FIG. 20 shows the ferroelectric characteristics obtained in the memory cell after the formation of the second protective layer 38.
[0070]
Compared with the result of FIG. 17 measured in the second embodiment, it can be seen that significantly superior ferroelectric characteristics are obtained. Since the structure of the finally obtained ferroelectric memory element is the same between the second embodiment and the present embodiment, it is considered that the difference in the process appeared as a characteristic difference.
[0071]
In the method of the present embodiment, a step of exposing to oxygen plasma after the formation of the insulating layer 72 is added. The step of exposing to this plasma is ozone TEOS-SiO ₂ It is extremely effective for removing water from the film. Even if there is a thermal process in the subsequent process, no water evaporation occurs at this point. Since the penetration of moisture into the ferroelectric layer 14 was suppressed, deterioration of the capacitor characteristics was suppressed. The same phenomenon is common to the material formed on the insulating layer 72. Here, it is considered that the deterioration of crystallinity due to moisture was suppressed in the titanium oxide used as the adhesion layer 40. Thus, the oxide of titanium realizes a function as a hydrogen barrier in addition to a function as an adhesion layer. As a result, even if hydrogen generated during formation of the protective layer enters the upper electrode, it is prevented from reaching the ferroelectric layer. For this reason, the initial crystallinity of the ferroelectric layer is maintained, and extremely excellent capacitor characteristics are promised.
[0072]
(Embodiment 6)
In the device structure shown in the first embodiment, as a modified example, the adhesion layer can have the following structure.
[0073]
First, even when a conductive material such as the iridium oxide film described in Embodiment 4 is used as the adhesion layer, the upper electrode is in contact with the intermediate electrode through the opening provided in the adhesion layer as shown in FIG. It can be taken as a form. Since a direct contact is secured between the upper electrode and the intermediate electrode, the wiring resistance can be reduced accordingly. In addition, depending on the material of the intermediate electrode, there is a problem that the adhesion between the intermediate electrode and the iridium oxide film cannot be ensured, but this can be avoided. At this time, the shape or area of the opening can be arbitrarily changed. For example, as shown in FIG. 21, the entire area where the upper electrode and the lower electrode intersect may be opened. As a result, the upper electrode material can be reliably embedded in the opening independently of the film formation method and material of the upper electrode.
[0074]
On the other hand, when an insulating material (for example, the above-described aluminum oxide film) is used as the adhesion layer, the area of the opening is preferably smaller. Since the upper electrode and the intermediate electrode need to be in direct contact, the hydrogen barrier performance of the adhesion layer cannot be expected in this region. Therefore, in order to suppress the intrusion of hydrogen, it is necessary to reduce the area of the opening.
[Brief description of the drawings]
FIG. 1 is a plan view schematically showing a ferroelectric memory device according to a first embodiment.
FIG. 2 is a cross-sectional view schematically showing a part of the ferroelectric memory device along the line AA in FIG.
FIG. 3 is a cross-sectional view schematically showing a part of the ferroelectric memory device along the line BB in FIG. 1;
FIG. 4 is an enlarged schematic cross-sectional view of the memory cell array in FIG. 2;
FIG. 5 is an enlarged schematic cross-sectional view of the memory cell array in FIG. 3;
FIG. 6 is a diagram schematically showing a manufacturing process of the ferroelectric memory device.
FIG. 7 is a diagram schematically showing a manufacturing process of the ferroelectric memory device.
FIG. 8 is a diagram schematically showing a manufacturing process of the ferroelectric memory device.
FIG. 9 is a view schematically showing a manufacturing process of the ferroelectric memory device.
FIG. 10 is a diagram schematically showing a manufacturing process of the ferroelectric memory device.
FIG. 11 is a diagram schematically showing a manufacturing process of the ferroelectric memory device.
FIG. 12 is a diagram schematically showing a manufacturing process of the ferroelectric memory device.
FIG. 13 is a diagram schematically showing a manufacturing process of the ferroelectric memory device.
FIG. 14 is a diagram schematically showing a manufacturing process of the ferroelectric memory device.
FIG. 15 is a diagram schematically showing a manufacturing process of the ferroelectric memory device.
FIG. 16 is a diagram schematically showing a manufacturing process of the ferroelectric memory device.
FIG. 17 is a diagram showing characteristics of a ferroelectric memory element after a second protective layer is formed, obtained when titanium oxide is applied as an adhesion layer according to the second embodiment.
FIG. 18 is a diagram illustrating characteristics of a ferroelectric memory element after a second protective layer is formed, which is obtained when an oxide of aluminum is used as an adhesion layer according to the second embodiment.
FIG. 19 is a diagram showing characteristics of a ferroelectric memory element after a second protective layer is formed, which is obtained when an iridium oxide is used as an adhesion layer according to a fourth embodiment.
FIG. 20 is a diagram illustrating characteristics of a ferroelectric memory element after a second protective layer is formed, which is obtained when the insulating layer is exposed to oxygen plasma according to the fifth embodiment.
FIG. 21 is a diagram showing a modification of FIG. 12;
[Explanation of symbols]
10 First interlayer insulating layer
12 lower electrode
14 Ferroelectric layer
16 Upper electrode
18 Intermediate electrode layer
19 Wiring layer
36 First protective layer (plasma TEOS-SiO ₂ film)
38 Second protective layer (plasma Si ₃ N ₄ film)
40 Adhesion layer
42 First hydrogen barrier film
44 Second hydrogen barrier film
50 First drive circuit
52 Second drive circuit
60 Mask layer
72 Insulation layer
100 memory cell array
110 semiconductor substrate
112 MOS transistor
112a Gate insulating layer
112b Gate electrode
112c source / drain region
114 Element isolation region
200 Peripheral circuit
1000 Ferroelectric memory device

Claims (16)

Memory cells are arranged in a matrix, a lower electrode, an upper electrode arranged in a direction intersecting with the lower electrode, a ferroelectric layer disposed at least in an intersection region of the upper electrode and the lower electrode, A ferroelectric memory device having an interlayer insulating layer including a hydrogen barrier film formed on at least a memory cell array, wherein an adhesion layer is disposed on a bottom surface or an upper surface of the upper electrode. . Memory cells are arranged in a matrix, a lower electrode, an upper electrode arranged in a direction intersecting the lower electrode, a ferroelectric layer arranged at least in an intersection region of the upper electrode and the lower electrode, In a ferroelectric memory element in which an interlayer insulating layer including a hydrogen barrier film is formed at least on a memory cell array, an adhesion layer is disposed on both a bottom surface and an upper surface of the upper electrode. Memory element. The ferroelectric layer is provided in an intersection region between the lower electrode and the upper electrode, and an intermediate electrode is provided between the ferroelectric layer and the upper electrode. 3. The ferroelectric memory device according to 1 or 2. 4. The ferroelectric memory device according to claim 1, wherein the adhesion layer is made of a material having a hydrogen barrier performance. 5. The ferroelectric memory device according to claim 4, wherein the adhesion layer provided on the bottom surface of the upper electrode is not formed only in an intersection region between the upper electrode and the lower electrode. 5. The adhesion layer provided on the bottom surface of the upper electrode, wherein an opening smaller than the area of the intersection region is provided in an intersection region between the upper electrode and the lower electrode. 3. The ferroelectric memory element according to claim 1. 7. The ferroelectric memory device according to claim 4, wherein the material having the hydrogen barrier performance is an oxide. 7. The ferroelectric memory device according to claim 4, wherein the material having the hydrogen barrier performance is a conductive material. 9. The ferroelectric memory device according to claim 8, wherein the conductive material is an iridium oxide film. The ferroelectric memory device according to claim 7, characterized by containing an oxide in which the oxide is titled by the chemical formula Al ₂ O _3. 2. The semiconductor device according to claim 1, further comprising a peripheral circuit portion for selectively writing or reading information to or from said memory cell, wherein said hydrogen barrier film is not formed on said peripheral circuit portion. 11. The ferroelectric memory element according to any one of claims 10 to 10. 5. The semiconductor device according to claim 4, further comprising a peripheral circuit for selectively writing or reading information to or from said memory cell, wherein said adhesion layer is not formed on said peripheral circuit. 12. The ferroelectric memory element according to any of 11. A method for manufacturing a ferroelectric memory element including a memory cell array in which memory cells formed of ferroelectric capacitors are arranged in a matrix, comprising the following steps.
(A) forming a first conductive layer on a substrate;
(B) forming a ferroelectric layer on the first conductive layer;
(C) forming a second conductive layer on the ferroelectric layer.
(D) a step of patterning at least the ferroelectric layer and the second conductive layer.
(E) forming an insulating layer on the substrate so as to cover a stacked body including the first conductive layer, the ferroelectric layer, and the second conductive layer.
(F) forming a thin film having hydrogen barrier performance as an adhesion layer on the insulating layer;
(G) forming an opening having a desired shape in the adhesion layer at a position overlapping with the ferroelectric layer;
(H) forming a third conductive layer of a desired pattern connected to the second conductive layer through the opening; 14. The method according to claim 13, wherein an opening formed in the step (g) is formed smaller than an area of the ferroelectric layer. 14. The method according to claim 13, wherein in the step (e), after forming the insulating layer, exposing the insulating layer to oxygen plasma. 14. The method according to claim 13, wherein in the step (h), the third conductive layer is exposed to an oxygen plasma atmosphere.

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