JP2004297054A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2004297054A
JP2004297054A JP2004064828A JP2004064828A JP2004297054A JP 2004297054 A JP2004297054 A JP 2004297054A JP 2004064828 A JP2004064828 A JP 2004064828A JP 2004064828 A JP2004064828 A JP 2004064828A JP 2004297054 A JP2004297054 A JP 2004297054A
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semiconductor device
wiring
shielding film
circuit element
manufacturing
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JP4020874B2 (en
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Ryosuke Usui
良輔 臼井
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a countermeasure against noise for a semiconductor device by a simple method. <P>SOLUTION: This semiconductor device comprises an interlayer insulating film 405 and an insulating film 409, interconnect lines 407, 408a and 408b embedded in the insulating film 409, circuit components 410a and 410b mounted on the insulating film 409, a sealing film 415 formed so that circuit components 410a and 410b may be covered, and a conductive shielding film 416 formed so that the sealing film 415 may be covered. The interconnect lines 408a and 408b are configured to be electrically connected to the shielding film 416. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、回路素子を搭載した半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device having a circuit element mounted thereon and a method for manufacturing the same.

近年、携帯電話、ＰＤＡ、ＤＶＣ、ＤＳＣといったポータブルエレクトロニクス機器の高機能化が加速している。これに伴い、これらのエレクトロニクス機器に使用されるＬＳＩに対しても高機能化、高性能化が要求されている。このため、ＬＳＩの動作クロックも高周波となっている。また、このようなエレクトロニクス機器が市場で受け入れられるためには、小型・軽量化が必須となっており、それを実現するために高集積のＬＳＩが求められている。   In recent years, portable electronic devices such as mobile phones, PDAs, DVCs, and DSCs have become increasingly sophisticated. Accordingly, higher functions and higher performance are also required for LSIs used in these electronic devices. For this reason, the operation clock of the LSI has a high frequency. Further, in order for such electronic devices to be accepted in the market, reduction in size and weight is indispensable, and a highly integrated LSI is required to realize such.

このように、高周波のＬＳＩを小型に実装するため、半導体チップ間の距離が短くなり高密度となり、ノイズの影響が大きくなるという問題がある。従来、ノイズ対策として、半導体装置のパッケージを金属の封止材で覆う技術が開示されている（たとえば特許文献１）。   As described above, since the high-frequency LSI is mounted in a small size, there is a problem that the distance between the semiconductor chips is shortened, the density is increased, and the influence of noise is increased. 2. Description of the Related Art As a countermeasure against noise, a technique of covering a package of a semiconductor device with a metal sealing material has been disclosed (for example, Patent Document 1).

ところで、従来、高周波用ＬＳＩを小型でパッケージ化する技術として、ＣＳＰが知られている（たとえば特許文献２）。同公報には、高周波用ＬＳＩを搭載するシステム・イン・パッケージが開示されている。このパッケージは、ベース基板上に、多層配線構造が形成され、その上に高周波用ＬＳＩをはじめとする回路素子が形成されている。多層配線構造は、コア基板や樹脂付銅箔などが積層された構造となっている。
特開平５−４７９６２号公報 特開２００２−９４２４７号公報 特開２００２−１１０７１７号公報 By the way, a CSP is conventionally known as a technology for packaging a high-frequency LSI in a small size (for example, Patent Document 2). This publication discloses a system-in-package on which a high-frequency LSI is mounted. In this package, a multilayer wiring structure is formed on a base substrate, and circuit elements such as a high-frequency LSI are formed thereon. The multilayer wiring structure has a structure in which a core substrate, a resin-coated copper foil, and the like are stacked.
JP-A-5-47962 JP-A-2002-94247 JP-A-2002-110717

しかしながら、これら従来のＣＳＰでは、ポータブルエレクトロニクス機器等において現在望まれているような水準の小型化、薄型化、軽量化を実現することは難しかった。   However, it has been difficult for these conventional CSPs to achieve the levels of miniaturization, thinning, and lightening that are currently desired in portable electronic devices and the like.

また、上述した特許文献１で開示された、半導体装置のパッケージを金属の封止材で覆う技術では、半導体装置とは別部品として、プリント基板に封止材を実装しているため、封止材形成後のパッケージのサイズが大きくなり小型化が図れないと問題があった。また、封止材を半導体装置と別部品として形成するため、生産性が低いという問題もあった。   Further, in the technology disclosed in Patent Document 1 described above, a package of a semiconductor device is covered with a metal sealing material, since the sealing material is mounted on a printed circuit board as a separate component from the semiconductor device. There is a problem if the size of the package after forming the material becomes large and miniaturization cannot be achieved. Further, since the encapsulant is formed as a separate component from the semiconductor device, there is a problem that productivity is low.

本発明は、上記事情に鑑みなされたものであり、その目的は、簡易な方法で半導体装置のノイズ対策を行う技術を提供することにある。   The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a technique for taking measures against noise in a semiconductor device by a simple method.

ところで、本出願人は、ＩＳＢ（Ｉｎｔｅｇｒａｔｅｄ Ｓｙｓｔｅｍ ｉｎ Ｂｏａｒｄ；登録商標）とよばれる新規なパッケージを開発した。ＩＳＢとは、半導体ベアチップを中心とする電子回路のパッケージングにおいて、銅による配線パターンを持ちながら回路部品を支持するためのコア(基材)を使用しない独自のコアレスシステム・イン・パッケージである。特許文献３には、こうしたシステム・イン・パッケージが記載されている。   By the way, the present applicant has developed a new package called ISB (Integrated System in Board; registered trademark). ISB is a unique coreless system-in-package that does not use a core (base material) for supporting circuit components while having a wiring pattern made of copper in the packaging of electronic circuits centering on semiconductor bare chips. Patent Literature 3 describes such a system-in-package.

図１はＩＳＢの一例を示す概略構成図である。ここではＩＳＢの全体構造をわかりやすくするため、単一の配線層のみ示しているが、実際には、複数の配線層が積層した構造となっている。このＩＳＢでは、ＬＳＩベアチップ２０１、Ｔｒベアチップ２０２およびチップＣＲ２０３が銅パターン２０５からなる配線により結線された構造となっている。ＬＳＩベアチップ２０１は、引き出し電極や配線と金線ボンディング２０４を介して導通されている。ＬＳＩベアチップ２０１の直下には、導電性ペースト２０６が設けられ、これを介してＩＳＢがプリント配線基板に実装される。ＩＳＢ全体はエポキシ樹脂などからなる樹脂パッケージ２０７により封止された構造となっている。   FIG. 1 is a schematic configuration diagram showing an example of the ISB. Although only a single wiring layer is shown here for easy understanding of the entire structure of the ISB, it is actually a structure in which a plurality of wiring layers are stacked. The ISB has a structure in which an LSI bare chip 201, a Tr bare chip 202, and a chip CR 203 are connected by wiring made of a copper pattern 205. The LSI bare chip 201 is electrically connected to a lead electrode or a wiring via a gold wire bonding 204. A conductive paste 206 is provided directly below the LSI bare chip 201, and the ISB is mounted on the printed wiring board via the conductive paste 206. The entire ISB has a structure sealed with a resin package 207 made of epoxy resin or the like.

このパッケージによれば、以下の利点が得られる。
（i）コアレスで実装できるため、トランジスタ、ＩＣ、ＬＳＩの小型・薄型化を実現できる。
（ii）トランジスタからシステムＬＳＩ、さらにチップタイプのコンデンサや抵抗を回路形成し、パッケージングすることができるため、高度なＳｉＰ（Ｓｙｓｔｅｍ ｉｎ Ｐａｃｋａｇｅ）を実現できる。
（iii）現有の半導体チップを組み合わせできるため、システムＬＳＩを短期間に開発できる。
（iv）半導体ベアチップの下にコア材がないため、良好な放熱性を得ることができる。
（ｖ）回路配線が銅材でありコア材がないため、低誘電率の回路配線となり、高速データ転送や高周波回路で優れた特性を発揮する。
（vi）電極がパッケージの内部に埋め込まれる構造のため、電極材料のパーティクルコンタミの発生を抑制できる。
（vii）パッケージサイズはフリーであり、１個あたりの廃材を６４ピンのＳＱＦＰパッケージと比較すると、約１／１０の量となるため、環境負荷を低減できる。
（viii）部品を載せるプリント回路基板から、機能の入った回路基板へと、新しい概念のシステム構成を実現できる。
（ix）ＩＳＢのパターン設計は、プリント回路基板のパターン設計と同じように容易であり、セットメーカーのエンジニアが自ら設計できる。 According to this package, the following advantages can be obtained.
(I) Since it can be mounted without a core, transistors, ICs, and LSIs can be reduced in size and thickness.
(Ii) A high-level SiP (System in Package) can be realized because a circuit can be formed from a transistor to a system LSI, and furthermore, a chip type capacitor or resistor can be formed and packaged.
(Iii) Since existing semiconductor chips can be combined, a system LSI can be developed in a short time.
(Iv) Since there is no core material under the semiconductor bare chip, good heat dissipation can be obtained.
(V) Since the circuit wiring is a copper material and has no core material, the circuit wiring has a low dielectric constant, and exhibits excellent characteristics in high-speed data transfer and high-frequency circuits.
(Vi) Since the electrodes are embedded in the package, generation of particle contamination of the electrode material can be suppressed.
(Vii) The package size is free, and the amount of waste material per package is about 1/10 that of a 64-pin SQFP package, so that the environmental load can be reduced.
(Viii) A new concept system configuration can be realized from a printed circuit board on which components are mounted to a circuit board having functions.
(Ix) The pattern design of the ISB is as easy as the pattern design of the printed circuit board, and the engineer of the set maker can design by himself.

本発明は、以上のようなＩＳＢはもちろん、ＣＳＰやＳｉＰに好適な技術である。   The present invention is a technique suitable for CSP and SiP as well as ISB as described above.

本発明によれば、絶縁層と、絶縁層内に埋設された配線と、絶縁層上に搭載された回路素子と、回路素子を覆うように形成された封止層と、封止層を覆うように形成された導電性の遮蔽膜と、を含み、配線と遮蔽膜とが電気的に接続していることを特徴とする半導体装置が提供される。ここで、遮蔽膜は電磁波を遮蔽する機能を有する。これにより、ノイズの影響を低減することができる。遮蔽膜に電気的に接続された配線は接地することができる。これにより、遮蔽膜をも接地することができ、電磁波を遮蔽することができる。   According to the present invention, an insulating layer, wiring embedded in the insulating layer, a circuit element mounted on the insulating layer, a sealing layer formed to cover the circuit element, and covering the sealing layer And a conductive shielding film formed as described above, wherein the wiring and the shielding film are electrically connected to each other. Here, the shielding film has a function of shielding electromagnetic waves. Thereby, the influence of noise can be reduced. The wiring electrically connected to the shielding film can be grounded. Thereby, the shielding film can also be grounded, and the electromagnetic wave can be shielded.

遮蔽膜は、配線と同じ材料により構成することができる。遮蔽膜は、たとえば銅を主成分として構成することができる。また、配線は、回路素子にも電気的に接続して構成することができる。半導体装置をＩＳＢで構成した場合、回路素子に電気的に接続された配線のいずれかは接地される。本発明の半導体装置において、遮蔽膜が、このように接地される配線と電気的に接続されるように構成することができる。   The shielding film can be made of the same material as the wiring. The shielding film can be composed of, for example, copper as a main component. In addition, the wiring can be configured to be electrically connected to a circuit element. In the case where the semiconductor device is configured by ISB, one of the wirings electrically connected to the circuit element is grounded. In the semiconductor device of the present invention, the shielding film can be configured to be electrically connected to the wiring grounded as described above.

本発明の半導体装置は、遮蔽膜を覆うように形成され、遮蔽膜を構成する材料よりも腐食耐性の高い材料により構成された保護膜をさらに含むことができる。保護膜は、たとえばニッケルや金等により構成することができる。   The semiconductor device of the present invention can further include a protective film formed so as to cover the shielding film and made of a material having higher corrosion resistance than the material forming the shielding film. The protective film can be made of, for example, nickel or gold.

このようにすれば、遮蔽膜により半導体装置を遮蔽することができるとともに、遮蔽膜表面を腐食耐性の高い保護膜により保護することができるので、遮蔽膜の機能を長期間維持することができる。   With this configuration, the semiconductor device can be shielded by the shielding film, and the surface of the shielding film can be protected by the protective film having high corrosion resistance, so that the function of the shielding film can be maintained for a long time.

本発明によれば、絶縁層と、絶縁層内に埋設された配線と、絶縁層表面に搭載され、配線に電気的に接続された回路素子と、回路素子を覆うように形成された封止層と、を含む積層体を分割して回路素子を含む半導体装置を製造する方法が提供される。この半導体装置の製造方法は、上記積層体の表面に分割溝を形成して配線の側面を露出させる工程と、積層体の表面側を導電性材料で覆い、配線と電気的に接続した遮蔽膜を形成する工程と、積層体を裏面から分割溝に沿って切断し、当該積層体の回路素子を他の領域から分割する工程と、を含む。   According to the present invention, an insulating layer, wiring buried in the insulating layer, a circuit element mounted on the surface of the insulating layer and electrically connected to the wiring, and a seal formed to cover the circuit element And a method for manufacturing a semiconductor device including a circuit element by dividing a stacked body including the layers. This method of manufacturing a semiconductor device includes a step of forming a dividing groove on the surface of the laminate to expose a side surface of the wiring, and a shielding film that covers the surface of the laminate with a conductive material and is electrically connected to the wiring. And a step of cutting the laminate from the back surface along the dividing groove to divide the circuit element of the laminate from another region.

このようにすれば、回路素子を他の領域から分割する工程と組み合わせて遮蔽膜を形成することができるので、簡易な方法で半導体装置のノイズ対策を行うことができる。これにより、半導体装置の生産性を向上することができる。   With this configuration, the shielding film can be formed in combination with the step of dividing the circuit element from another region, so that a noise countermeasure for the semiconductor device can be taken by a simple method. Thereby, the productivity of the semiconductor device can be improved.

本発明の半導体装置の製造方法において、配線を接地させる工程をさらに含むことができる。配線は、回路素子にも電気的に接続して構成することができる。   The method for manufacturing a semiconductor device of the present invention may further include a step of grounding the wiring. The wiring can be configured to be electrically connected to a circuit element.

本発明の半導体装置の製造方法において、絶縁層上には複数の回路素子が搭載されてよく、配線の側面を露出させる工程の前において、配線は複数の回路素子に接続して設けられてよく、配線の側面を露出させる工程において、配線を分割し、当該分割された各配線が各回路素子にそれぞれ接続されるように分割溝を形成することができる。   In the method for manufacturing a semiconductor device of the present invention, a plurality of circuit elements may be mounted on the insulating layer, and the wiring may be provided in connection with the plurality of circuit elements before the step of exposing the side surface of the wiring. In the step of exposing the side surface of the wiring, the wiring may be divided, and the dividing groove may be formed such that each of the divided wirings is connected to each circuit element.

本発明の半導体装置の製造方法において、導電性材料は銅を主成分とすることができる。   In the method of manufacturing a semiconductor device according to the present invention, the conductive material may be mainly composed of copper.

本発明の半導体装置の製造方法において、めっき法により遮蔽膜を形成することができる。また、遮蔽膜は、スクリーン印刷法を用いて導電性ペーストを付着させることにより形成することもできる。   In the method for manufacturing a semiconductor device according to the present invention, the shielding film can be formed by plating. The shielding film can also be formed by attaching a conductive paste by using a screen printing method.

本発明の半導体装置の製造方法において、遮蔽膜を、当該遮蔽膜を構成する材料よりも腐食耐性の高い材料により構成された保護膜で覆う工程をさらに含むことができる。   The method for manufacturing a semiconductor device of the present invention may further include a step of covering the shielding film with a protective film made of a material having higher corrosion resistance than the material forming the shielding film.

以上説明したように本発明によれば、簡易な方法で半導体装置のノイズ対策を行うことができる。   As described above, according to the present invention, it is possible to take a countermeasure against noise of a semiconductor device by a simple method.

図２は、本発明の実施の形態における半導体装置の製造方法を示す工程断面図である。   FIG. 2 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

図２（ａ）は、半導体装置の製造途中における積層体を示す。ここで、積層体は、金属箔４０２と、その上に形成された多層配線構造４５５と、その上に形成された第一の回路素子４１０ａおよび第二の回路素子４１０ｂと、回路素子４１０ａおよび回路素子４１０ｂを覆うように形成された封止膜４１５とを含む。多層配線構造４５５は、層間絶縁膜４０５と、層間絶縁膜４０５に設けられたビア４０３と、ビア４０３に電気的に接続された配線４０７および被切断配線４０８と、配線４０７および被切断配線４０８を覆うように形成された絶縁膜４０９とを有する。ここでは、多層配線構造４５５を省略して記載しているが、多層配線構造４５５は、複数のビア、配線、および絶縁膜が積層した構造を有する。   FIG. 2A shows a stacked body during the manufacture of the semiconductor device. Here, the laminate includes a metal foil 402, a multilayer wiring structure 455 formed thereon, a first circuit element 410a and a second circuit element 410b formed thereon, a circuit element 410a and a circuit A sealing film 415 formed so as to cover the element 410b. The multilayer wiring structure 455 includes an interlayer insulating film 405, a via 403 provided in the interlayer insulating film 405, a wiring 407 electrically connected to the via 403, a wiring 408 to be cut, and a wiring 407 and a wiring 408 to be cut. An insulating film 409 formed so as to cover it. Although the multilayer wiring structure 455 is omitted here, the multilayer wiring structure 455 has a structure in which a plurality of vias, wirings, and insulating films are stacked.

第一の回路素子４１０ａおよび第二の回路素子４１０ｂは、たとえば、トランジスタ、ダイオード、ＩＣチップ等の半導体素子、チップコンデンサ、チップ抵抗等の受動素子である。第一の回路素子４１０ａおよび第二の回路素子４１０ｂは、ワイヤ４１２により配線４０７および被切断配線４０８に適宜電気的に接続される。ここで、被切断配線４０８は、第一の回路素子４１０ａおよび第二の回路素子４１０ｂに共通に接続されている。多層配線構造４５５の詳細な構造およびこの段階までの積層体の製造方法については後述する。   The first circuit element 410a and the second circuit element 410b are, for example, transistors, diodes, semiconductor elements such as IC chips, and passive elements such as chip capacitors and chip resistors. The first circuit element 410a and the second circuit element 410b are appropriately electrically connected to the wiring 407 and the wiring to be cut 408 by wires 412. Here, the wiring to be cut 408 is commonly connected to the first circuit element 410a and the second circuit element 410b. The detailed structure of the multilayer wiring structure 455 and the method of manufacturing the laminate up to this stage will be described later.

以下、このように構成された積層体を分割して半導体装置を製造する工程を説明する。
まず、積層体を、表面側（図中上側）から層間絶縁膜４０５の途中までダイシングして分割溝４１１を形成する（図２（ｂ））。これにより、被切断配線４０８は第一の回路素子４１０ａに接続した配線４０８ａと第二の回路素子４１０ｂに接続した配線４０８ｂとに分割され、配線４０８ａおよび配線４０８ｂともに分割溝４１１の側面に露出する。 Hereinafter, a process of manufacturing a semiconductor device by dividing the stacked body configured as described above will be described.
First, the laminated body is diced from the front side (upper side in the figure) to the middle of the interlayer insulating film 405 to form the dividing grooves 411 (FIG. 2B). As a result, the wiring 408 to be cut is divided into the wiring 408a connected to the first circuit element 410a and the wiring 408b connected to the second circuit element 410b, and both the wiring 408a and the wiring 408b are exposed on the side surfaces of the division groove 411. .

つづいて、半導体装置の表面を覆うように遮蔽膜４１６を形成する（図２（ｃ））。遮蔽膜４１６は、配線４０７および被切断配線４０８を構成する金属と同じ材料により構成することができる。遮蔽膜４１６は、たとえば銅や銀等の比較的低抵抗な金属により構成される。また、遮蔽膜４１６は、半導体装置を構成する他の構成要素、たとえば封止膜４１５、配線４０７、層間絶縁膜４０５、絶縁膜４０９等と線膨張係数の差が少ない材料により構成されるのが好ましい。遮蔽膜４１６は、たとえばめっき法、スパッタリング法、ＣＶＤ法等で形成することができる。めっき法で遮蔽膜４１６を形成する場合、たとえば硫酸銅等の化学銅を用いて無電解めっきを行い半導体装置の表面に銅の薄膜を形成した後、電解めっきする。電解めっきは、たとえば半導体装置の表面側を液温約２５℃の硫酸銅水溶液に浸漬して行うことができる。遮蔽膜４１６は、配線４０８ａおよび配線４０８ｂと電気的に接続するように形成される。遮蔽膜４１６は、半導体装置全体を覆うように形成した後、裏面側をパターニングして不要な遮蔽膜４１６を除去して形成することもでき、また半導体装置の表面側のみをめっき液に浸漬して形成することもできる。また、遮蔽膜４１６は、スクリーン印刷法を用いて導電性ペーストを付着させることにより形成することもできる。   Subsequently, a shielding film 416 is formed so as to cover the surface of the semiconductor device (FIG. 2C). The shielding film 416 can be formed of the same material as the metal forming the wiring 407 and the wiring 408 to be cut. The shielding film 416 is made of a relatively low-resistance metal such as copper or silver. Further, the shielding film 416 is made of a material having a small difference in linear expansion coefficient from other components of the semiconductor device, for example, the sealing film 415, the wiring 407, the interlayer insulating film 405, the insulating film 409, and the like. preferable. The shielding film 416 can be formed by, for example, a plating method, a sputtering method, a CVD method, or the like. In the case where the shielding film 416 is formed by plating, for example, electroless plating is performed using chemical copper such as copper sulfate to form a thin copper film on the surface of the semiconductor device, and then electrolytic plating is performed. Electroplating can be performed, for example, by immersing the surface side of the semiconductor device in an aqueous solution of copper sulfate at a liquid temperature of about 25 ° C. The shielding film 416 is formed so as to be electrically connected to the wirings 408a and 408b. The shielding film 416 can be formed so as to cover the entire semiconductor device, and thereafter, the back surface side is patterned to remove an unnecessary shielding film 416, or only the front surface side of the semiconductor device is immersed in a plating solution. It can also be formed. Further, the shielding film 416 can also be formed by attaching a conductive paste using a screen printing method.

その後、金属箔４０２を除去する。金属箔４０２の除去は、研磨、研削、エッチング、レーザの金属蒸発等により行うことができる。つづいて露出したビア４０３に半田等の導電材を被着して多層配線構造４５５の裏面に半田ボール４２０を形成する（図２（ｄ））。配線４０８ａおよび配線４０８ｂに接続された半田ボール４２０は接地される。これにより、遮蔽膜４１６をも接地することができ、半導体装置のノイズを遮断する機能を担保することができる。   After that, the metal foil 402 is removed. The removal of the metal foil 402 can be performed by polishing, grinding, etching, laser evaporation of the metal, or the like. Subsequently, a conductive material such as solder is applied to the exposed via 403 to form a solder ball 420 on the back surface of the multilayer wiring structure 455 (FIG. 2D). The solder balls 420 connected to the wirings 408a and 408b are grounded. Accordingly, the shielding film 416 can also be grounded, and the function of blocking noise of the semiconductor device can be secured.

つづいて、分割溝４１１に沿って、半導体装置の裏面側から再びダイシングして半導体装置を分割する（図２（ｅ））。ここで、裏面側からのダイシングは、各半導体装置において、遮蔽膜４１６がそれぞれ配線４０８ａおよび配線４０８ｂと接続した状態を保つように行う。これにより半導体装置が完成する。   Subsequently, dicing is again performed from the back surface side of the semiconductor device along the dividing groove 411 to divide the semiconductor device (FIG. 2E). Here, the dicing from the back surface side is performed in each semiconductor device so as to maintain a state where the shielding film 416 is connected to the wiring 408a and the wiring 408b, respectively. Thereby, the semiconductor device is completed.

本実施の形態において、図２（ｄ）に示した金属箔４０２の除去工程を行うまでは、金属箔４０２が支持基板となる。金属箔４０２は、ビア４０３、配線４０７、および被切断配線４０８形成時や遮蔽膜４１６形成時の電解めっき工程において電極としても利用される。また、封止膜４１５をモールドする際にも、金型への搬送、金型への実装の作業性を良好にすることができる。   In the present embodiment, the metal foil 402 becomes a support substrate until the step of removing the metal foil 402 shown in FIG. 2D is performed. The metal foil 402 is also used as an electrode in the electrolytic plating step when forming the via 403, the wiring 407, and the wiring to be cut 408 and when forming the shielding film 416. In addition, even when the sealing film 415 is molded, the workability of the transfer to the mold and the mounting to the mold can be improved.

以上のように、本発明によれば、半導体装置の製造途中で、簡易な方法で半導体装置表面に遮蔽膜４１６を形成することができ、ノイズ対策を行うことができる。これにより、半導体装置の生産性を向上することもできる。また、本発明によれば、回路素子がモールドされている封止膜４１５表面に直接遮蔽膜４１６が形成されるので、半導体装置を小型・軽量化することができる。   As described above, according to the present invention, it is possible to form the shielding film 416 on the surface of the semiconductor device by a simple method during the manufacture of the semiconductor device, and to take measures against noise. Thereby, the productivity of the semiconductor device can be improved. Further, according to the present invention, since the shielding film 416 is formed directly on the surface of the sealing film 415 where the circuit element is molded, the semiconductor device can be reduced in size and weight.

遮蔽膜４１６は、図３に示すように、保護膜４１８で覆われた構成とすることもできる。図２（ｃ）を参照して説明したのと同様に遮蔽膜４１６を形成した後、遮蔽膜４１６上にたとえばめっき法、スパッタリング法、ＣＶＤ法により保護膜４１８を形成する（図３（ａ））。保護膜４１８は、遮蔽膜４１６を構成する金属よりも腐食耐性の高い材料により構成される。このような材料として、たとえばニッケルや金等が例示される。つづいて、金属箔４０２を除去して半田ボール４２０を形成する（図３（ｂ））。その後、半導体装置の裏面側からダイシングして半導体装置を分割する（図３（ｃ））。   The shielding film 416 may be configured to be covered with a protective film 418 as shown in FIG. After forming the shielding film 416 in the same manner as described with reference to FIG. 2C, a protective film 418 is formed on the shielding film 416 by, for example, a plating method, a sputtering method, or a CVD method (FIG. 3A). ). The protective film 418 is made of a material having higher corrosion resistance than the metal forming the shielding film 416. Examples of such a material include nickel and gold. Subsequently, the solder ball 420 is formed by removing the metal foil 402 (FIG. 3B). Thereafter, the semiconductor device is divided by dicing from the back surface side of the semiconductor device (FIG. 3C).

このようにすれば、遮蔽膜４１６により半導体装置の第一の回路素子４１０ａおよび第二の回路素子４１０ｂを遮蔽することができるとともに、遮蔽膜４１６表面を腐食耐性の高い保護膜４１８により保護することができるので、遮蔽膜４１６の機能を長期間維持することができる。   In this manner, the first circuit element 410a and the second circuit element 410b of the semiconductor device can be shielded by the shielding film 416, and the surface of the shielding film 416 can be protected by the protective film 418 having high corrosion resistance. Therefore, the function of the shielding film 416 can be maintained for a long time.

図４は、図２に示した多層配線構造４５５部分を詳細に示す半導体装置の断面図である。図２では、多層配線構造４５５を省略して記載したが、多層配線構造４５５は、層間絶縁膜４０５および配線４０７からなる配線層が複数層積層した多層配線構造体より構成されている。   FIG. 4 is a cross-sectional view of the semiconductor device showing in detail the portion of the multilayer wiring structure 455 shown in FIG. Although the multilayer wiring structure 455 is omitted in FIG. 2, the multilayer wiring structure 455 is configured by a multilayer wiring structure in which a plurality of wiring layers including an interlayer insulating film 405 and a wiring 407 are stacked.

以下、図５および図２（ａ）を参照して、図２（ａ）に示した段階までの積層体の製造方法を説明する。
まず、金属箔４０２表面上の所定の領域に選択的に導電被膜４２２を形成する（図５（ａ））。具体的には、フォトレジスト（不図示）で金属箔４０２を被覆した後、所定の領域のフォトレジストを除去して金属箔４０２表面の一部を露出させる、つづいて、電解めっき法により、金属箔４０２の露出面に導電被膜４２２を形成する。導電被膜４２２の膜厚は、例えば１〜１０μｍ程度とする。この導電被膜４２２は、最終的に半導体装置の裏面電極となるので、半田等のロウ材との接着性の良い金、または銀を用いて形成することが好ましい。 金属箔４０２の主材料は、Ｃｕ、Ａｌ、Ｆｅ−Ｎｉ等の合金等とすることが好ましい。ロウ材の付着性やめっき性が良好だからである。金属箔４０２の厚さは、特に制限はないが、たとえば１０μｍ〜３００μｍ程度とすることができる。 Hereinafter, with reference to FIG. 5 and FIG. 2A, a method of manufacturing a laminated body up to the stage illustrated in FIG. 2A will be described.
First, a conductive film 422 is selectively formed in a predetermined region on the surface of the metal foil 402 (FIG. 5A). Specifically, after covering the metal foil 402 with a photoresist (not shown), the photoresist in a predetermined region is removed to expose a part of the surface of the metal foil 402. A conductive film 422 is formed on the exposed surface of the foil 402. The thickness of the conductive film 422 is, for example, about 1 to 10 μm. Since the conductive film 422 eventually becomes a back electrode of the semiconductor device, it is preferable to form the conductive film 422 using gold or silver having good adhesiveness to a brazing material such as solder. The main material of the metal foil 402 is preferably an alloy such as Cu, Al, and Fe-Ni. This is because the brazing material has good adhesion and plating properties. The thickness of the metal foil 402 is not particularly limited, but may be, for example, about 10 μm to 300 μm.

導電被膜４２２の形成に用いたレジストを除去した後、金属箔４０２上に、第一層目の配線パターンを形成する。まず金属箔４０２を化学研磨して表面のクリーニングと表面粗化を行う。次に、金属箔４０２上に熱硬化性樹脂を堆積して導電被膜４２２全面を覆い、加熱硬化させて平坦な表面を有する層間絶縁膜４０５を形成する。層間絶縁膜４０５を構成する樹脂材料としては、ＢＴレジン等のメラミン誘導体、液晶ポリマー、エポキシ樹脂、ＰＰＥ樹脂、ポリイミド樹脂、フッ素樹脂、フェノール樹脂、ポリアミドビスマレイミド等の熱硬化性樹脂が例示される。このうち、高周波特性に優れる液晶ポリマー、エポキシ樹脂、ＢＴレジン等のメラミン誘導体が好適に用いられる。これらの樹脂とともに、適宜、フィラーや添加剤を添加してもよい。   After removing the resist used to form the conductive film 422, a first-layer wiring pattern is formed on the metal foil 402. First, the metal foil 402 is chemically polished to perform surface cleaning and surface roughening. Next, a thermosetting resin is deposited on the metal foil 402, covers the entire surface of the conductive film 422, and is cured by heating to form an interlayer insulating film 405 having a flat surface. Examples of the resin material forming the interlayer insulating film 405 include melamine derivatives such as BT resin, liquid crystal polymers, epoxy resins, PPE resins, polyimide resins, fluorine resins, phenol resins, and thermosetting resins such as polyamide bismaleimide. . Among them, a liquid crystal polymer, an epoxy resin, and a melamine derivative such as BT resin having excellent high-frequency characteristics are preferably used. A filler or an additive may be appropriately added together with these resins.

つづいて、層間絶縁膜４０５中にたとえば炭酸ガスレーザー、機械加工、薬液による化学エッチング加工、プラズマを用いたドライエッチング法等によりビアホール４２４を形成する。その後、エキシマレーザーを照射してエッチング滓を除去し、つづいて、ビアホール４２４を埋め込むように全面に銅めっき層を形成する。この銅めっき層はビアホール４２４の段差で断線しないように、まず無電解銅めっきにより全面に０．５μｍ程度の薄膜を形成した後、電解めっきにより約２０μｍ程度の厚みに形成する。無電解めっき用触媒は、通常パラジウムを用いることが多く、可とう性の絶縁基材に無電解用めっき用触媒を付着させるには、パラジウムを錯体の状態で水溶液に含ませ、可とう性の絶縁基材を浸漬して表面にパラジウム錯体を付着させ、そのまま、還元剤を用いて、金属パラジウムに還元することによって可とう性の絶縁基材表面にめっきを開始するための核を形成することができる。通常は、このような操作をするために、被めっき物を、アルコールや酸で洗浄し、表面に付着した油分を除去しておく。   Subsequently, a via hole 424 is formed in the interlayer insulating film 405 by, for example, carbon dioxide laser, mechanical processing, chemical etching using a chemical solution, dry etching using plasma, or the like. After that, the etching residue is removed by irradiating an excimer laser, and then a copper plating layer is formed on the entire surface so as to fill the via hole 424. This copper plating layer is formed by first forming a thin film of about 0.5 μm on the entire surface by electroless copper plating and then by electrolytic plating to a thickness of about 20 μm so as not to be disconnected at the step of the via hole 424. In most cases, palladium is used as the electroless plating catalyst.To attach the electroless plating catalyst to a flexible insulating substrate, palladium is contained in an aqueous solution in the form of a complex, and the To form a nucleus to start plating on the flexible insulating substrate surface by immersing the insulating substrate and attaching the palladium complex to the surface and reducing it to metallic palladium using the reducing agent as it is Can be. Usually, in order to perform such an operation, the object to be plated is washed with an alcohol or an acid to remove oil attached to the surface.

その後、フォトレジストをマスクとして銅めっき層をエッチングし、銅からなる配線４０７を形成する（図５（ｂ））。このとき、ビア４０３も形成される。配線４０７は、たとえば、レジストから露出した箇所に、化学エッチング液をスプレー噴霧して不要な銅箔をエッチング除去することにより形成することができる。エッチングレジストは、通常のプリント配線板に用いることのできるエッチングレジスト材料を用いることができ、レジストインクをシルクスクリーン印刷して形成したり、エッチングレジスト用感光性ドライフィルムを銅箔の上にラミネートして、その上に配線導体の形状に光を透過するフォトマスクを重ね、紫外線を露光し、露光しなかった箇所を現像液で除去して形成することができる。化学エッチング液には、塩化第二銅と塩酸の溶液、塩化第二鉄溶液、硫酸と過酸化水素の溶液、過硫酸アンモニウム溶液など、通常のプリント配線板に用いる化学エッチング液を用いることができる。   Thereafter, the copper plating layer is etched using the photoresist as a mask to form a wiring 407 made of copper (FIG. 5B). At this time, a via 403 is also formed. The wiring 407 can be formed by, for example, spraying and spraying a chemical etching solution on a portion exposed from the resist to remove unnecessary copper foil. For the etching resist, an etching resist material that can be used for a normal printed wiring board can be used.The resist ink is formed by silk-screen printing, or a photosensitive dry film for an etching resist is laminated on a copper foil. Then, a photomask that transmits light in the shape of the wiring conductor is superimposed thereon, exposed to ultraviolet light, and portions that are not exposed can be removed with a developer to form the wiring conductor. As the chemical etching solution, a chemical etching solution used for ordinary printed wiring boards, such as a solution of cupric chloride and hydrochloric acid, a solution of ferric chloride, a solution of sulfuric acid and hydrogen peroxide, and an ammonium persulfate solution can be used.

その後、配線４０７を覆うようにしてさらに層間絶縁膜４０５を形成した後、同様の手順を繰り返すことにより、ビアホール４２４、ビア４０３、配線４０７、および被切断配線４０８の積層構造を形成する（図５（ｃ））。   After that, an interlayer insulating film 405 is further formed so as to cover the wiring 407, and the same procedure is repeated to form a laminated structure of the via hole 424, the via 403, the wiring 407, and the wiring to be cut 408 (FIG. 5). (C)).

図２（ａ）に戻り、多層配線構造４５５の最上層には、絶縁膜４０９を形成する。絶縁膜４０９を構成する材料としては、たとえばエポキシ樹脂、アクリル樹脂、ウレタン樹脂、ポリイミド樹脂等の樹脂、および、これらの混合物、さらに、これらの樹脂にカーボンブラック、アルミナ、窒化アルミニウム、窒化ホウ素、酸化スズ、酸化鉄、酸化銅、タルク、雲母、カオリナイト、炭酸カルシウム、シリカ、酸化チタン等の無機フィラーを混合したもの等が例示される。   Returning to FIG. 2A, an insulating film 409 is formed on the uppermost layer of the multilayer wiring structure 455. As a material for forming the insulating film 409, for example, resins such as epoxy resin, acrylic resin, urethane resin, and polyimide resin, and mixtures thereof, and further, carbon black, alumina, aluminum nitride, boron nitride, oxide Examples thereof include those in which inorganic fillers such as tin, iron oxide, copper oxide, talc, mica, kaolinite, calcium carbonate, silica, and titanium oxide are mixed.

その後、絶縁膜４０９の表面に第一の回路素子４１０ａおよび第二の回路素子４１０ｂを搭載し、第一の回路素子４１０ａおよび第二の回路素子４１０ｂをワイヤ４１２を介して配線４０７および被切断配線４０８と接続する。第一の回路素子４１０ａおよび第二の回路素子４１０ｂは、たとえば半田等のロウ材や接着剤等により絶縁膜４０９上に固着される。   After that, the first circuit element 410a and the second circuit element 410b are mounted on the surface of the insulating film 409, and the first circuit element 410a and the second circuit element 410b are connected via the wire 412 to the wiring 407 and the wiring to be cut. 408. The first circuit element 410a and the second circuit element 410b are fixed on the insulating film 409 by, for example, a brazing material such as solder or an adhesive.

次いで、これらの第一の回路素子４１０ａおよび第二の回路素子４１０ｂを封止膜４１５でモールドする。第一の回路素子４１０ａおよび第二の回路素子４１０ｂのモールドは、金型を用いて同時に行う。ここでは二つの回路素子しか示していないが、より多くの回路素子に対して同時にモールドをすることができる。封止膜４１５の形成は、トランスファーモールド、インジェクションモールド、ポッティングまたはディッピングにより実現できる。樹脂材料としては、エポキシ樹脂等の熱硬化性樹脂がトランスファーモールドまたはポッティングで実現でき、ポリイミド樹脂、ポリフェニレンサルファイド等の熱可塑性樹脂はインジェクションモールドで実現できる。   Next, the first circuit element 410a and the second circuit element 410b are molded with the sealing film 415. Molding of the first circuit element 410a and the second circuit element 410b is performed simultaneously using a mold. Although only two circuit elements are shown here, more circuit elements can be molded simultaneously. The formation of the sealing film 415 can be realized by transfer molding, injection molding, potting, or dipping. As the resin material, a thermosetting resin such as an epoxy resin can be realized by transfer molding or potting, and a thermoplastic resin such as a polyimide resin or polyphenylene sulfide can be realized by injection molding.

また、以上の図２〜図５では、回路素子４１０ａ（および回路素子４１０ｂ）と配線４０７および配線４０８ａ（および配線４０８ｂ）とをワイヤボンディング方式で接続する形態を示したが、図６に示すように回路素子４１０ａをフェイスダウンに配置したフリップ実装とすることもできる。   2 to 5, the circuit element 410a (and the circuit element 410b) and the wiring 407 and the wiring 408a (and the wiring 408b) are connected by a wire bonding method. However, as shown in FIG. Flip mounting in which the circuit element 410a is arranged face down can also be used.

図７は、多層配線構造４５５上に形成された複数の半導体装置４６５がマトリクス状に形成された状態を示す図である。本実施の形態において、複数のモジュール上には封止膜４１５および遮蔽膜４１６が形成されているが、ここでは記載を省略している。複数のモジュール４６５は、ダイシングライン４９０に沿って分割される。本実施の形態において、金属箔を除去した後にダイシングするため、切断面の荒れやブレードの消耗を抑制することができる。また、多層配線構造４５５の表面に位置合わせマーク４７０を設けることにより、ダイシングラインの位置を迅速かつ正確に把握することができる。本実施の形態において、位置合わせマーク４７０は、多層配線構造４５５の表面から裏面にかけてホール状に形成されることが好ましい。これにより、裏面からダイシングを行う際にもダイシングラインの位置を正確に把握することができる。   FIG. 7 is a diagram showing a state in which a plurality of semiconductor devices 465 formed on the multilayer wiring structure 455 are formed in a matrix. In this embodiment mode, a sealing film 415 and a shielding film 416 are formed over a plurality of modules, but the description is omitted here. The plurality of modules 465 are divided along dicing lines 490. In the present embodiment, since dicing is performed after the metal foil is removed, roughness of the cut surface and consumption of the blade can be suppressed. Further, by providing the alignment mark 470 on the surface of the multilayer wiring structure 455, the position of the dicing line can be quickly and accurately grasped. In the present embodiment, it is preferable that alignment mark 470 be formed in a hole shape from the front surface to the back surface of multilayer wiring structure 455. Thereby, even when dicing is performed from the back surface, the position of the dicing line can be accurately grasped.

なお、ＢＧＡ等の従来のＣＳＰにおいては、基板上に形成されたモジュールを金型で打ち抜く方法が採用されている。そのため、本実施の形態で説明したようにダイシング工程との組合せで遮蔽膜４１６を形成するような製造プロセスを従来のＣＳＰに適用するのは困難である。このように、本実施の形態で説明したようなＩＳＢを用いることにより、ダイシングで半導体装置を分割するとともに遮蔽膜４１６をも形成することができ、製造プロセス上、大きなメリットがある。   In a conventional CSP such as a BGA, a method of punching out a module formed on a substrate with a mold is adopted. Therefore, it is difficult to apply a manufacturing process of forming the shielding film 416 in combination with the dicing step to the conventional CSP as described in the present embodiment. As described above, by using the ISB as described in this embodiment, the semiconductor device can be divided by dicing and the shielding film 416 can be formed, which is a great advantage in a manufacturing process.

図８は、半導体装置の他の例を示す図である。
図２および図３においては、一つの半導体装置に一つの回路素子が含まれる構成を示したが、半導体装置は、一つの装置内に複数の回路素子が含まれるモジュールとすることもできる。 FIG. 8 is a diagram illustrating another example of the semiconductor device.
FIGS. 2 and 3 show a configuration in which one semiconductor device includes one circuit element; however, the semiconductor device may be a module in which one device includes a plurality of circuit elements.

図８に示した半導体装置は、複数の受動素子４１０ｃや複数の半導体素子４１０ｄ、４１０ｅ、４１０ｆを含む。ここで、半導体装置は、一つの半導体素子４１０ｅと他の半導体素子４１０ｆとが積層した構成を含む。このような半導体素子４１０ｅと半導体素子４１０ｆとの組み合わせは、たとえばＳＲＡＭとＦｌａｓｈメモリ、ＳＲＡＭとＰＲＡＭとすることができる。この場合、半導体素子４１０ｅと半導体素子４１０ｆとはビア５００により電気的に接続される。   The semiconductor device illustrated in FIG. 8 includes a plurality of passive elements 410c and a plurality of semiconductor elements 410d, 410e, and 410f. Here, the semiconductor device includes a structure in which one semiconductor element 410e and another semiconductor element 410f are stacked. Such a combination of the semiconductor element 410e and the semiconductor element 410f can be, for example, an SRAM and a Flash memory, or an SRAM and a PRAM. In this case, the semiconductor element 410e and the semiconductor element 410f are electrically connected by the via 500.

次に、この半導体装置を製造する工程を説明する。
図８（ａ）は、半導体装置の製造途中における積層体を示す。積層体は、金属箔４０２上に形成された多層配線構造と、その上に形成された複数の受動素子４１０ｃや複数の半導体素子４１０ｄ、４１０ｅ、４１０ｆとを含む。このように構成された積層体に、図中上側から多層配線構造の途中までダイシングして分割溝４１１を形成する（図８（ｂ））。その後、図２を参照して上述したのと同様にして、半導体装置を覆うようにして遮蔽膜を形成する。つづいて、金属箔４０２を除去する。その後、金属箔４０２を除去した面に半田ボール４２０を形成する。次いで、分割溝４１１に沿って、図８（ｂ）で示したのとは反対側の面から再びダイシングして半導体装置を分割する。これにより、図８（ｃ）に示す構成の半導体装置が得られる。 Next, steps for manufacturing the semiconductor device will be described.
FIG. 8A shows a laminate in the process of manufacturing a semiconductor device. The laminate includes a multilayer wiring structure formed on the metal foil 402, and a plurality of passive elements 410c and a plurality of semiconductor elements 410d, 410e, 410f formed thereon. A dicing groove 411 is formed on the laminated body having such a configuration by dicing from the upper side in the figure to the middle of the multilayer wiring structure (FIG. 8B). Thereafter, a shielding film is formed so as to cover the semiconductor device in the same manner as described above with reference to FIG. Subsequently, the metal foil 402 is removed. After that, the solder ball 420 is formed on the surface from which the metal foil 402 has been removed. Next, dicing is performed again along the dividing groove 411 from the surface opposite to the surface shown in FIG. 8B to divide the semiconductor device. Thus, a semiconductor device having the configuration shown in FIG. 8C is obtained.

本例においても、遮蔽膜４１６は、配線４０８ｃを介してハンダボール４２０と電気的に接続される。これにより、ハンダボール４２０を接地することにより、遮蔽膜４１６も接地することができ、半導体装置のノイズを遮断することができる。   Also in this example, the shielding film 416 is electrically connected to the solder ball 420 via the wiring 408c. Thus, by grounding the solder ball 420, the shielding film 416 can also be grounded, and noise of the semiconductor device can be cut off.

ＩＳＢの一例を示す概略構成図である。It is a schematic structure figure showing an example of ISB. 本発明の実施の形態における半導体装置の製造方法を示す工程断面図である。FIG. 4 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device in the embodiment of the present invention. 図２に示した半導体装置の変形例の製造方法を示す工程断面図である。FIG. 13 is a process cross-sectional view illustrating the method of manufacturing the modification example of the semiconductor device illustrated in FIG. 2. 図２に示した多層配線構造部分を詳細に示す半導体装置の断面図である。FIG. 3 is a cross-sectional view of the semiconductor device, showing in detail a multilayer wiring structure shown in FIG. 2; 図２に示した半導体装置の製造途中の積層体の製造方法を示す図である。FIG. 3 is a diagram illustrating a method of manufacturing a stacked body during the manufacture of the semiconductor device illustrated in FIG. 2. 回路素子をフェイスダウンに配置したフリップ実装とした半導体装置の断面図である。FIG. 4 is a cross-sectional view of a flip-mounted semiconductor device in which circuit elements are arranged face-down. 多層配線構造上に複数の半導体装置がマトリクス状に形成された状態を示す図である。FIG. 3 is a diagram showing a state in which a plurality of semiconductor devices are formed in a matrix on a multilayer wiring structure. 半導体装置の他の例を示す図である。FIG. 9 is a diagram illustrating another example of the semiconductor device.

符号の説明Explanation of reference numerals

２０１ ＬＳＩベアチップ、 ２０２ Ｔｒベアチップ、 ２０３ チップＣＲ、 ２０４ 金線ボンディング、 ２０５ 銅パターン、 ２０６ 導電性ペースト、 ２０７ 樹脂パッケージ、 ４０２ 金属箔、 ４０３ ビア、 ４０５ 層間絶縁膜、 ４０７ 配線、 ４０８ 被切断配線、 ４０８ａ 配線、 ４０８ｂ 配線、 ４０９ 絶縁膜、 ４１０ａ 第一の回路素子、 ４１０ｂ 第二の回路素子、 ４１１ 分割溝、 ４１２ ワイヤ、 ４１５ 封止膜、 ４１６ 遮蔽膜、 ４１８ 保護膜、 ４２０ 半田ボール、 ４２２ 導電被膜、 ４２４ ビアホール、 ４５５ 多層配線構造、 ４６５ 半導体装置、 ４７０ マーク、 ４９０ ダイシングライン。
201 LSI bare chip, 202 Tr bare chip, 203 chip CR, 204 gold wire bonding, 205 copper pattern, 206 conductive paste, 207 resin package, 402 metal foil, 403 via, 405 interlayer insulating film, 407 wiring, 408 wiring to be cut, 408a wiring, 408b wiring, 409 insulating film, 410a first circuit element, 410b second circuit element, 411 division groove, 412 wire, 415 sealing film, 416 shielding film, 418 protective film, 420 solder ball, 422 conductive Coating, 424 via hole, 455 multilayer wiring structure, 465 semiconductor device, 470 mark, 490 dicing line.

Claims (6)

絶縁層と、
前記絶縁層内に埋設された配線と、
前記絶縁層上に搭載された回路素子と、
前記回路素子を覆うように形成された封止層と、
前記封止層を覆うように形成された導電性の遮蔽膜と、
を含み、
前記配線と前記遮蔽膜とが電気的に接続していることを特徴とする半導体装置。 An insulating layer,
Wiring buried in the insulating layer;
A circuit element mounted on the insulating layer,
A sealing layer formed so as to cover the circuit element,
A conductive shielding film formed so as to cover the sealing layer,
Including
A semiconductor device, wherein the wiring and the shielding film are electrically connected. 請求項１に記載の半導体装置において、
前記遮蔽膜を覆うように形成され、前記遮蔽膜を構成する材料よりも腐食耐性の高い材料により構成された保護膜をさらに含むことを特徴とする半導体装置。 The semiconductor device according to claim 1,
A semiconductor device further comprising a protective film formed so as to cover the shielding film and made of a material having higher corrosion resistance than a material forming the shielding film. 絶縁層と、前記絶縁層内に埋設された配線と、前記絶縁層表面に搭載された回路素子と、前記回路素子を覆うように形成された封止層と、を含む積層体を分割して前記回路素子を含む半導体装置を製造する方法であって、
前記積層体の表面に分割溝を形成して前記配線の側面を露出させる工程と、
前記積層体の表面側を導電性材料で覆い、前記配線と電気的に接続した遮蔽膜を形成する工程と、
前記積層体を裏面から前記分割溝に沿って切断し、当該積層体の前記回路素子を他の領域から分割する工程と、
を含むことを特徴とする半導体装置の製造方法。 An insulating layer, a wiring buried in the insulating layer, a circuit element mounted on the surface of the insulating layer, and a sealing layer formed so as to cover the circuit element. A method of manufacturing a semiconductor device including the circuit element,
Forming a dividing groove on the surface of the laminate to expose side surfaces of the wiring,
A step of covering the surface side of the laminate with a conductive material and forming a shielding film electrically connected to the wiring;
Cutting the laminated body from the back surface along the dividing groove, and dividing the circuit element of the laminated body from another region;
A method for manufacturing a semiconductor device, comprising: 請求項３に記載の半導体装置の製造方法において、
前記配線を接地させる工程をさらに含むことを特徴とする半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 3,
A method for manufacturing a semiconductor device, further comprising the step of grounding the wiring. 請求項３または４に記載の半導体装置の製造方法において、
前記絶縁層上には複数の回路素子が搭載され、前記配線の側面を露出させる工程の前において、前記配線は前記複数の回路素子に接続して設けられ、
前記配線の側面を露出させる工程において、前記配線を分割し、当該分割された各配線が各前記回路素子にそれぞれ接続されるように前記分割溝を形成することを特徴とする半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 3 or 4,
A plurality of circuit elements are mounted on the insulating layer, and before the step of exposing a side surface of the wiring, the wiring is provided to be connected to the plurality of circuit elements,
A method of manufacturing the semiconductor device, wherein in the step of exposing the side surface of the wiring, the wiring is divided, and the divided grooves are formed such that the divided wirings are respectively connected to the circuit elements. . 請求項３乃至５いずれかに記載の半導体装置の製造方法において、
前記遮蔽膜を、当該遮蔽膜を構成する材料よりも腐食耐性の高い材料により構成された保護膜で覆う工程をさらに含むことを特徴とする半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 3, wherein
A method of manufacturing a semiconductor device, further comprising a step of covering the shielding film with a protective film made of a material having higher corrosion resistance than a material forming the shielding film.
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