JP2004297054A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2004297054A
JP2004297054A JP2004064828A JP2004064828A JP2004297054A JP 2004297054 A JP2004297054 A JP 2004297054A JP 2004064828 A JP2004064828 A JP 2004064828A JP 2004064828 A JP2004064828 A JP 2004064828A JP 2004297054 A JP2004297054 A JP 2004297054A
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semiconductor device
wiring
shielding film
manufacturing
method
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JP4020874B2 (en )
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Ryosuke Usui
良輔 臼井
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Sanyo Electric Co Ltd
三洋電機株式会社
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a countermeasure against noise for a semiconductor device by a simple method. <P>SOLUTION: This semiconductor device comprises an interlayer insulating film 405 and an insulating film 409, interconnect lines 407, 408a and 408b embedded in the insulating film 409, circuit components 410a and 410b mounted on the insulating film 409, a sealing film 415 formed so that circuit components 410a and 410b may be covered, and a conductive shielding film 416 formed so that the sealing film 415 may be covered. The interconnect lines 408a and 408b are configured to be electrically connected to the shielding film 416. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、回路素子を搭載した半導体装置およびその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof mounted circuit elements.

近年、携帯電話、PDA、DVC、DSCといったポータブルエレクトロニクス機器の高機能化が加速している。 In recent years, mobile phone, PDA, DVC, the high performance of portable electronic devices such as DSC is accelerating. これに伴い、これらのエレクトロニクス機器に使用されるLSIに対しても高機能化、高性能化が要求されている。 Accordingly, higher functionality, higher performance has been required even for LSI used in these electronic devices. このため、LSIの動作クロックも高周波となっている。 For this reason, the operation clock of the LSI also has a high frequency. また、このようなエレクトロニクス機器が市場で受け入れられるためには、小型・軽量化が必須となっており、それを実現するために高集積のLSIが求められている。 Further, such electronic equipment is to be accepted in the market, has become smaller and lighter is essential, and highly integrated LSI is required to achieve it.

このように、高周波のLSIを小型に実装するため、半導体チップ間の距離が短くなり高密度となり、ノイズの影響が大きくなるという問題がある。 Thus, to implement a high-frequency LSI to small, the distance between the semiconductor chip becomes becomes dense short, there is a problem that the influence of noise increases. 従来、ノイズ対策として、半導体装置のパッケージを金属の封止材で覆う技術が開示されている(たとえば特許文献1)。 Conventionally, as a noise countermeasure, a technique of covering the package of the semiconductor device with a sealing material of a metal is disclosed (for example, Patent Document 1).

ところで、従来、高周波用LSIを小型でパッケージ化する技術として、CSPが知られている(たとえば特許文献2)。 However, a conventional technique of packaging compact for high frequency LSI, CSP is known (e.g. Patent Document 2). 同公報には、高周波用LSIを搭載するシステム・イン・パッケージが開示されている。 The same publication, system in package mounting a high-frequency LSI is disclosed. このパッケージは、ベース基板上に、多層配線構造が形成され、その上に高周波用LSIをはじめとする回路素子が形成されている。 This package, on a base substrate, the multilayer wiring structure is formed, the circuit elements including a high-frequency LSI is formed thereon. 多層配線構造は、コア基板や樹脂付銅箔などが積層された構造となっている。 Multi-layer wiring structure is a like core substrate or a resin coated copper foil is laminated structure.
特開平5−47962号公報 JP 5-47962 discloses 特開2002−94247号公報 JP 2002-94247 JP 特開2002−110717号公報 JP 2002-110717 JP

しかしながら、これら従来のCSPでは、ポータブルエレクトロニクス機器等において現在望まれているような水準の小型化、薄型化、軽量化を実現することは難しかった。 However, in these conventional CSP, miniaturization of levels, such as currently desired in portable electronic devices such as, thinner, it is difficult to reduce the weight.

また、上述した特許文献1で開示された、半導体装置のパッケージを金属の封止材で覆う技術では、半導体装置とは別部品として、プリント基板に封止材を実装しているため、封止材形成後のパッケージのサイズが大きくなり小型化が図れないと問題があった。 Further, it disclosed in Patent Document 1 described above, in the technique of covering with a sealing material of the metal package of the semiconductor device, as a separate part from the semiconductor device, because it implements the sealing member to the printed circuit board, sealing package size after wood formation had not a problem Hakare becomes large and miniaturization. また、封止材を半導体装置と別部品として形成するため、生産性が低いという問題もあった。 Further, in order to form a sealing material as a semiconductor device and a separate part, there is a problem that productivity is low.

本発明は、上記事情に鑑みなされたものであり、その目的は、簡易な方法で半導体装置のノイズ対策を行う技術を提供することにある。 The present invention has been made in view of the above circumstances, an object thereof is to provide a technique for noise suppression of a semiconductor device in a simple manner.

ところで、本出願人は、ISB(Integrated System in Board;登録商標)とよばれる新規なパッケージを開発した。 By the way, the present applicant, ISB; developed a new package called (Integrated System in Board registered trademark). ISBとは、半導体ベアチップを中心とする電子回路のパッケージングにおいて、銅による配線パターンを持ちながら回路部品を支持するためのコア(基材)を使用しない独自のコアレスシステム・イン・パッケージである。 The ISB, in the packaging of electronic circuits around the semiconductor bare chip, a unique coreless system in package that does not use core (substrate) for supporting the circuit component while having a wiring pattern of copper. 特許文献3には、こうしたシステム・イン・パッケージが記載されている。 Patent Document 3 discloses such a system-in-package.

図1はISBの一例を示す概略構成図である。 Figure 1 is a schematic diagram showing an example of ISB. ここではISBの全体構造をわかりやすくするため、単一の配線層のみ示しているが、実際には、複数の配線層が積層した構造となっている。 Here for clarity of the overall structure of the ISB it shows only a single wiring layer, in fact, a plurality of wiring layers has a structure laminated. このISBでは、LSIベアチップ201、Trベアチップ202およびチップCR203が銅パターン205からなる配線により結線された構造となっている。 This ISB, has a connection structure by wiring LSI bare chip 201, Tr bare chip 202 and chip CR203 is made of copper pattern 205. LSIベアチップ201は、引き出し電極や配線と金線ボンディング204を介して導通されている。 LSI bare chip 201 is conducted through the lead-out electrodes and wirings and gold bonding 204. LSIベアチップ201の直下には、導電性ペースト206が設けられ、これを介してISBがプリント配線基板に実装される。 Immediately below the LSI bare chip 201, the conductive paste 206 is provided, ISB is mounted on the printed circuit board through which. ISB全体はエポキシ樹脂などからなる樹脂パッケージ207により封止された構造となっている。 And it has a sealed structure by the resin package 207 across ISB is made of epoxy resin.

このパッケージによれば、以下の利点が得られる。 According to this package, the following advantages are obtained.
(i)コアレスで実装できるため、トランジスタ、IC、LSIの小型・薄型化を実現できる。 (I) for that can be implemented in coreless, be realized transistors, IC, a smaller and thinner LSI.
(ii)トランジスタからシステムLSI、さらにチップタイプのコンデンサや抵抗を回路形成し、パッケージングすることができるため、高度なSiP(System in Package)を実現できる。 (Ii) System transistors LSI, further circuitry forming a capacitor and resistor chip type, since it is possible to package, it can be realized a high degree of SiP (System in Package).
(iii)現有の半導体チップを組み合わせできるため、システムLSIを短期間に開発できる。 (Iii) because it combines the existing semiconductor chip, you can develop a system LSI in a short period of time.
(iv)半導体ベアチップの下にコア材がないため、良好な放熱性を得ることができる。 (Iv) Since there is no core material under the semiconductor bare chip, it is possible to obtain good heat dissipation.
(v)回路配線が銅材でありコア材がないため、低誘電率の回路配線となり、高速データ転送や高周波回路で優れた特性を発揮する。 (V) circuit wiring since there is no and the core material is copper material becomes a circuit wiring having a low dielectric constant and exhibits excellent properties in high-speed data transfer and high-frequency circuits.
(vi)電極がパッケージの内部に埋め込まれる構造のため、電極材料のパーティクルコンタミの発生を抑制できる。 For the structure (vi) electrodes are embedded inside the package, it is possible to suppress the generation of particles contamination of the electrode material.
(vii)パッケージサイズはフリーであり、1個あたりの廃材を64ピンのSQFPパッケージと比較すると、約1/10の量となるため、環境負荷を低減できる。 (Vii) package size is free, when comparing the waste per piece 64 pin SQFP package, since the amount of about 1/10, can reduce the environmental load.
(viii)部品を載せるプリント回路基板から、機能の入った回路基板へと、新しい概念のシステム構成を実現できる。 (Viii) from the printed circuit board for mounting components, to enter a circuit board with functions, it is possible to realize a system configuration of a new concept.
(ix)ISBのパターン設計は、プリント回路基板のパターン設計と同じように容易であり、セットメーカーのエンジニアが自ら設計できる。 (Ix) ISB pattern design is as easy as the pattern design of the printed circuit board, engineers set makers can be designed themselves.

本発明は、以上のようなISBはもちろん、CSPやSiPに好適な技術である。 The present invention is ISB the above course, is a preferred technology for CSP and SiP.

本発明によれば、絶縁層と、絶縁層内に埋設された配線と、絶縁層上に搭載された回路素子と、回路素子を覆うように形成された封止層と、封止層を覆うように形成された導電性の遮蔽膜と、を含み、配線と遮蔽膜とが電気的に接続していることを特徴とする半導体装置が提供される。 According to the present invention, covered with the insulating layer, a wiring buried in the insulating layer, and a circuit element mounted on an insulating layer, a sealing layer formed so as to cover the circuit elements, the sealing layer anda formed conductive shielding film as the wiring and the shielding film is a semiconductor device which is characterized in that electrically connected is provided. ここで、遮蔽膜は電磁波を遮蔽する機能を有する。 Here, the shielding film has a function of shielding electromagnetic waves. これにより、ノイズの影響を低減することができる。 Thus, it is possible to reduce the influence of noise. 遮蔽膜に電気的に接続された配線は接地することができる。 Wiring electrically connected to the shielding layer may be grounded. これにより、遮蔽膜をも接地することができ、電磁波を遮蔽することができる。 Thus, the shielding film can also be grounded, thereby shielding electromagnetic waves.

遮蔽膜は、配線と同じ材料により構成することができる。 The shielding film can be made of the same material as the wiring. 遮蔽膜は、たとえば銅を主成分として構成することができる。 The shielding film may be formed of, for example copper as a main component. また、配線は、回路素子にも電気的に接続して構成することができる。 The wiring can be configured also electrically connected to the circuit elements. 半導体装置をISBで構成した場合、回路素子に電気的に接続された配線のいずれかは接地される。 Case where the semiconductor device in ISB, either electrically connected to the wiring in the circuit element is grounded. 本発明の半導体装置において、遮蔽膜が、このように接地される配線と電気的に接続されるように構成することができる。 In the semiconductor device of the present invention, the shielding film may be configured so that this is connected to wires and electrically be grounded as.

本発明の半導体装置は、遮蔽膜を覆うように形成され、遮蔽膜を構成する材料よりも腐食耐性の高い材料により構成された保護膜をさらに含むことができる。 The semiconductor device of the present invention is formed so as to cover the shielding film may further include a protective layer made of material having a higher corrosion resistance than the material of the shielding film. 保護膜は、たとえばニッケルや金等により構成することができる。 Protective film may be composed of, for example, nickel, gold or the like.

このようにすれば、遮蔽膜により半導体装置を遮蔽することができるとともに、遮蔽膜表面を腐食耐性の高い保護膜により保護することができるので、遮蔽膜の機能を長期間維持することができる。 In this way, it is possible to shield the semiconductor device by the shielding film, since the surface of the shielding film can be protected by high corrosion resistance protective film, it can be maintained for a long period of time the function of the shielding film.

本発明によれば、絶縁層と、絶縁層内に埋設された配線と、絶縁層表面に搭載され、配線に電気的に接続された回路素子と、回路素子を覆うように形成された封止層と、を含む積層体を分割して回路素子を含む半導体装置を製造する方法が提供される。 According to the present invention, an insulating layer, a wiring buried in the insulating layer, is mounted on the surface of the insulating layer, and a circuit element electrically connected to the wiring, which is formed so as to cover the circuit element sealing method of manufacturing a semiconductor device including a circuit element by dividing the laminate including a layer, is provided. この半導体装置の製造方法は、上記積層体の表面に分割溝を形成して配線の側面を露出させる工程と、積層体の表面側を導電性材料で覆い、配線と電気的に接続した遮蔽膜を形成する工程と、積層体を裏面から分割溝に沿って切断し、当該積層体の回路素子を他の領域から分割する工程と、を含む。 Method of manufacturing a semiconductor device includes the steps of exposing the side surfaces of the wiring by forming a split groove in the surface of the laminate, covering the surface side of the laminate with a conductive material, wiring electrically connected to the shielding film forming a cut along the dividing grooves laminate from the back, and a step of dividing the circuit elements of the stack from other region.

このようにすれば、回路素子を他の領域から分割する工程と組み合わせて遮蔽膜を形成することができるので、簡易な方法で半導体装置のノイズ対策を行うことができる。 Thus, it is possible to form the shielding film in combination with the step of dividing the circuit elements from the other regions, it is possible to perform noise reduction of the semiconductor device in a simple manner. これにより、半導体装置の生産性を向上することができる。 Thus, it is possible to improve the productivity of the semiconductor device.

本発明の半導体装置の製造方法において、配線を接地させる工程をさらに含むことができる。 In the method of the present invention may further comprise the step of grounding the wire. 配線は、回路素子にも電気的に接続して構成することができる。 Wiring can be configured also electrically connected to the circuit elements.

本発明の半導体装置の製造方法において、絶縁層上には複数の回路素子が搭載されてよく、配線の側面を露出させる工程の前において、配線は複数の回路素子に接続して設けられてよく、配線の側面を露出させる工程において、配線を分割し、当該分割された各配線が各回路素子にそれぞれ接続されるように分割溝を形成することができる。 In the method of the present invention may a plurality of circuit elements are mounted on the insulating layer, before the step of exposing the side surfaces of the wiring, the wiring may be provided by connecting a plurality of circuit elements , in the step of exposing the side surfaces of the wiring, to divide the wiring, it is possible to form the dividing grooves to the divided respective wires were are connected to each circuit element.

本発明の半導体装置の製造方法において、導電性材料は銅を主成分とすることができる。 In the method of the present invention, the conductive material may be composed mainly of copper.

本発明の半導体装置の製造方法において、めっき法により遮蔽膜を形成することができる。 In the method of the present invention, it is possible to form the shielding film by plating. また、遮蔽膜は、スクリーン印刷法を用いて導電性ペーストを付着させることにより形成することもできる。 Moreover, the shielding film may be formed by depositing a conductive paste by a screen printing method.

本発明の半導体装置の製造方法において、遮蔽膜を、当該遮蔽膜を構成する材料よりも腐食耐性の高い材料により構成された保護膜で覆う工程をさらに含むことができる。 In the method of the present invention, the shielding film can be a material constituting the shielding film further comprises a step of covering with a protective film composed of a highly corrosive-resistant material.

以上説明したように本発明によれば、簡易な方法で半導体装置のノイズ対策を行うことができる。 According to the present invention described above, it is possible to perform noise reduction of the semiconductor device in a simple manner.

図2は、本発明の実施の形態における半導体装置の製造方法を示す工程断面図である。 Figure 2 is a process cross-sectional views showing a manufacturing method of a semiconductor device in the embodiment of the present invention.

図2(a)は、半導体装置の製造途中における積層体を示す。 2 (a) shows a layered structure in the process of producing a semiconductor device. ここで、積層体は、金属箔402と、その上に形成された多層配線構造455と、その上に形成された第一の回路素子410aおよび第二の回路素子410bと、回路素子410aおよび回路素子410bを覆うように形成された封止膜415とを含む。 Here, the laminate, the metal foil 402, a multilayer wiring structure 455 formed thereon, and a first circuit element 410a and the second circuit element 410b formed thereon, the circuit elements 410a and circuitry and a sealing film 415 that is formed to cover the element 410b. 多層配線構造455は、層間絶縁膜405と、層間絶縁膜405に設けられたビア403と、ビア403に電気的に接続された配線407および被切断配線408と、配線407および被切断配線408を覆うように形成された絶縁膜409とを有する。 Multilayer wiring structure 455, an interlayer insulating film 405, a via 403 formed in the interlayer insulating film 405, a wiring electrically connected to 407 and be cut wiring 408 via 403, the wiring 407 and the cutting wire 408 and an insulating film 409 formed to cover. ここでは、多層配線構造455を省略して記載しているが、多層配線構造455は、複数のビア、配線、および絶縁膜が積層した構造を有する。 Here, although described by omitting the multilayer wiring structure 455, the multilayer wiring structure 455 has a plurality of vias, wirings, and a structure in which insulating films are stacked.

第一の回路素子410aおよび第二の回路素子410bは、たとえば、トランジスタ、ダイオード、ICチップ等の半導体素子、チップコンデンサ、チップ抵抗等の受動素子である。 The first circuit element 410a and the second circuit element 410b is, for example, transistors, diodes, semiconductor devices such as an IC chip, chip capacitors, a passive element chip resistor or the like. 第一の回路素子410aおよび第二の回路素子410bは、ワイヤ412により配線407および被切断配線408に適宜電気的に接続される。 The first circuit element 410a and the second circuit element 410b is suitably electrically connected to the wiring 407 and the cutting wire 408 by wire 412. ここで、被切断配線408は、第一の回路素子410aおよび第二の回路素子410bに共通に接続されている。 Here, the cutting wire 408 is connected in common to the first circuit element 410a and the second circuit element 410b. 多層配線構造455の詳細な構造およびこの段階までの積層体の製造方法については後述する。 It will be described later manufacturing method of the detailed structure and laminates up to this stage of the multi-layer wiring structure 455.

以下、このように構成された積層体を分割して半導体装置を製造する工程を説明する。 Hereinafter, a process of manufacturing a semiconductor device by dividing the thus constituted laminate.
まず、積層体を、表面側(図中上側)から層間絶縁膜405の途中までダイシングして分割溝411を形成する(図2(b))。 First, a laminate, the surface side to form a dividing groove 411 by dicing to the middle of the interlayer insulating film 405 from (in the drawing the upper side) (Figure 2 (b)). これにより、被切断配線408は第一の回路素子410aに接続した配線408aと第二の回路素子410bに接続した配線408bとに分割され、配線408aおよび配線408bともに分割溝411の側面に露出する。 Thus, the object to be cut wiring 408 is divided into a wiring 408b connected to the wiring 408a and the second circuit element 410b connected to the first circuit element 410a, is exposed to the side surfaces of the wiring 408a and a wiring 408b both dividing groove 411 .

つづいて、半導体装置の表面を覆うように遮蔽膜416を形成する(図2(c))。 Subsequently, a shielding film 416 so as to cover the surface of the semiconductor device (FIG. 2 (c)). 遮蔽膜416は、配線407および被切断配線408を構成する金属と同じ材料により構成することができる。 The shielding film 416 may be made of the same material as the metal constituting the wiring 407 and the cutting wire 408. 遮蔽膜416は、たとえば銅や銀等の比較的低抵抗な金属により構成される。 The shielding film 416 is, for example, a relatively low resistance metal as copper or silver. また、遮蔽膜416は、半導体装置を構成する他の構成要素、たとえば封止膜415、配線407、層間絶縁膜405、絶縁膜409等と線膨張係数の差が少ない材料により構成されるのが好ましい。 Moreover, the shielding film 416, other components constituting the semiconductor device, for example a sealing film 415, the wiring 407, the interlayer insulating film 405, that the difference between the insulating film 409 or the like and the linear expansion coefficient is constituted by less material preferable. 遮蔽膜416は、たとえばめっき法、スパッタリング法、CVD法等で形成することができる。 The shielding film 416 may be formed, for example plating, sputtering, a CVD method or the like. めっき法で遮蔽膜416を形成する場合、たとえば硫酸銅等の化学銅を用いて無電解めっきを行い半導体装置の表面に銅の薄膜を形成した後、電解めっきする。 When forming the shielding film 416 by a plating method, for example, after forming a thin film of copper on the surface of the semiconductor device subjected to electroless plating using chemical copper such as copper sulfate and electrolytic plating. 電解めっきは、たとえば半導体装置の表面側を液温約25℃の硫酸銅水溶液に浸漬して行うことができる。 Electrolytic plating can be performed, for example, by immersing the surface side of the semiconductor device to an aqueous copper sulfate solution of a liquid temperature of about 25 ° C.. 遮蔽膜416は、配線408aおよび配線408bと電気的に接続するように形成される。 The shielding film 416 is formed so as to connect the wiring 408a and a wiring 408b electrically. 遮蔽膜416は、半導体装置全体を覆うように形成した後、裏面側をパターニングして不要な遮蔽膜416を除去して形成することもでき、また半導体装置の表面側のみをめっき液に浸漬して形成することもできる。 Shielding film 416, after forming so as to cover the entire semiconductor device, patterning the back surface side can be formed by removing unnecessary shielding film 416, also immersed only the surface side of the semiconductor device in the plating solution to form Te can be. また、遮蔽膜416は、スクリーン印刷法を用いて導電性ペーストを付着させることにより形成することもできる。 Moreover, the shielding film 416 may be formed by depositing a conductive paste by a screen printing method.

その後、金属箔402を除去する。 Then, to remove the metal foil 402. 金属箔402の除去は、研磨、研削、エッチング、レーザの金属蒸発等により行うことができる。 Removal of the metal foil 402 can be carried out polishing, grinding, etching, laser metal evaporation or the like. つづいて露出したビア403に半田等の導電材を被着して多層配線構造455の裏面に半田ボール420を形成する(図2(d))。 A conductive material such as solder vias 403 exposed subsequently to form the solder balls 420 on the back surface of the multilayer wiring structure 455 by adhering (Figure 2 (d)). 配線408aおよび配線408bに接続された半田ボール420は接地される。 The solder balls 420 connected to the wiring 408a and the wiring 408b is grounded. これにより、遮蔽膜416をも接地することができ、半導体装置のノイズを遮断する機能を担保することができる。 This can also be grounded shielding film 416, it is possible to secure the function of blocking the noise of the semiconductor device.

つづいて、分割溝411に沿って、半導体装置の裏面側から再びダイシングして半導体装置を分割する(図2(e))。 Then, along the dividing grooves 411 to divide the semiconductor device by dicing again from the back surface side of the semiconductor device (FIG. 2 (e)). ここで、裏面側からのダイシングは、各半導体装置において、遮蔽膜416がそれぞれ配線408aおよび配線408bと接続した状態を保つように行う。 Here, dicing from the back side, in the semiconductor device, it performed to maintain the state in which the shielding film 416 was connected to the respective wires 408a and the wiring 408b. これにより半導体装置が完成する。 Thus, a semiconductor device is completed.

本実施の形態において、図2(d)に示した金属箔402の除去工程を行うまでは、金属箔402が支持基板となる。 In this embodiment, until the step of removing the metal foil 402 shown in FIG. 2 (d), the metal foil 402 is a supporting substrate. 金属箔402は、ビア403、配線407、および被切断配線408形成時や遮蔽膜416形成時の電解めっき工程において電極としても利用される。 Metal foil 402, the via 403, interconnect 407, and also used as an electrode in the electrolytic plating step during the cutting wire 408 formed or when the shielding film 416 formed. また、封止膜415をモールドする際にも、金型への搬送、金型への実装の作業性を良好にすることができる。 Further, even when molding the sealing film 415, the transport to the mold, the workability of mounting of the mold can be improved.

以上のように、本発明によれば、半導体装置の製造途中で、簡易な方法で半導体装置表面に遮蔽膜416を形成することができ、ノイズ対策を行うことができる。 As described above, according to the present invention, in a process of producing a semiconductor device, it is possible to form the shielding film 416 on the semiconductor device surface in a simple manner, it is possible to perform noise reduction. これにより、半導体装置の生産性を向上することもできる。 Accordingly, it is possible to improve the productivity of the semiconductor device. また、本発明によれば、回路素子がモールドされている封止膜415表面に直接遮蔽膜416が形成されるので、半導体装置を小型・軽量化することができる。 Further, according to the present invention, since the circuit elements directly shielding film 416 is formed on the sealing film 415 surface being molded, it is possible to reduce the size and weight of the semiconductor device.

遮蔽膜416は、図3に示すように、保護膜418で覆われた構成とすることもできる。 Shielding film 416, as shown in FIG. 3, it can be a covered by the protective film 418 configuration. 図2(c)を参照して説明したのと同様に遮蔽膜416を形成した後、遮蔽膜416上にたとえばめっき法、スパッタリング法、CVD法により保護膜418を形成する(図3(a))。 Figure 2 (c) after forming the shielding film 416 in the same manner as described with reference to, plating for example on the shielding film 416, a sputtering method, a protective film 418 by a CVD method (see FIG. 3 (a) ). 保護膜418は、遮蔽膜416を構成する金属よりも腐食耐性の高い材料により構成される。 Protective film 418 is composed of a highly corrosive-resistant material than the metal forming the shielding film 416. このような材料として、たとえばニッケルや金等が例示される。 Such materials, for example, nickel, gold and the like. つづいて、金属箔402を除去して半田ボール420を形成する(図3(b))。 Subsequently, a solder ball 420 by removing the metal foil 402 (Figure 3 (b)). その後、半導体装置の裏面側からダイシングして半導体装置を分割する(図3(c))。 Then, to divide the semiconductor device by dicing from the back side of the semiconductor device (Figure 3 (c)).

このようにすれば、遮蔽膜416により半導体装置の第一の回路素子410aおよび第二の回路素子410bを遮蔽することができるとともに、遮蔽膜416表面を腐食耐性の高い保護膜418により保護することができるので、遮蔽膜416の機能を長期間維持することができる。 In this way, it is possible to shield the first circuit element 410a and the second circuit element 410b of the semiconductor device by the shielding film 416, be protected by a high protection film 418 corrosion resistant shielding film 416 surface since it is, it can be maintained for a long period of time the function of the shielding film 416.

図4は、図2に示した多層配線構造455部分を詳細に示す半導体装置の断面図である。 Figure 4 is a cross-sectional view of a semiconductor device showing in detail the multilayer wiring structure 455 portion shown in FIG. 図2では、多層配線構造455を省略して記載したが、多層配線構造455は、層間絶縁膜405および配線407からなる配線層が複数層積層した多層配線構造体より構成されている。 In Figure 2, it has been described by omitting the multilayer wiring structure 455, the multilayer interconnection structure 455 is composed of a multilayer wiring structure in which the wiring layer composed of the interlayer insulating film 405 and the wiring 407 has a plurality of layers stacked.

以下、図5および図2(a)を参照して、図2(a)に示した段階までの積層体の製造方法を説明する。 Referring to FIGS. 5 and 2 (a), illustrating a method for manufacturing a laminate to the stage shown in FIG. 2 (a).
まず、金属箔402表面上の所定の領域に選択的に導電被膜422を形成する(図5(a))。 First, selectively forming conductive coating 422 in a predetermined region on the metal foil 402 surface (Figure 5 (a)). 具体的には、フォトレジスト(不図示)で金属箔402を被覆した後、所定の領域のフォトレジストを除去して金属箔402表面の一部を露出させる、つづいて、電解めっき法により、金属箔402の露出面に導電被膜422を形成する。 Specifically, after coating the metal foil 402 with a photoresist (not shown), the photoresist is removed in a predetermined region to expose a portion of the metallic foil 402 surface, followed by electrolytic plating, metal forming conductive coating 422 on the exposed surface of the foil 402. 導電被膜422の膜厚は、例えば1〜10μm程度とする。 Thickness of the conductive film 422 is, for example, 1~10μm about. この導電被膜422は、最終的に半導体装置の裏面電極となるので、半田等のロウ材との接着性の良い金、または銀を用いて形成することが好ましい。 The conductive coating 422, because the back electrode of the final semiconductor device, it is preferably formed using an adhesive having good gold or silver, the brazing material such as solder. 金属箔402の主材料は、Cu、Al、Fe−Ni等の合金等とすることが好ましい。 The main material of the metal foil 402, Cu, Al, it is preferable that an alloy such as Fe-Ni. ロウ材の付着性やめっき性が良好だからである。 Adhesion and plating of the brazing material is because it is good. 金属箔402の厚さは、特に制限はないが、たとえば10μm〜300μm程度とすることができる。 The thickness of the metal foil 402 is not particularly limited, for example, about 10Myuemu~300myuemu.

導電被膜422の形成に用いたレジストを除去した後、金属箔402上に、第一層目の配線パターンを形成する。 After resist removal of the used to form the conductive film 422, on the metal foil 402 to form a first layer wiring pattern. まず金属箔402を化学研磨して表面のクリーニングと表面粗化を行う。 For cleaning and surface roughening of the surface is first metal foil 402 by chemical polishing. 次に、金属箔402上に熱硬化性樹脂を堆積して導電被膜422全面を覆い、加熱硬化させて平坦な表面を有する層間絶縁膜405を形成する。 Next, cover the conductive film 422 over the entire surface by depositing a thermosetting resin on the metal foil 402, heating is cured to form an interlayer insulating film 405 having a flat surface. 層間絶縁膜405を構成する樹脂材料としては、BTレジン等のメラミン誘導体、液晶ポリマー、エポキシ樹脂、PPE樹脂、ポリイミド樹脂、フッ素樹脂、フェノール樹脂、ポリアミドビスマレイミド等の熱硬化性樹脂が例示される。 Examples of the resin material constituting the interlayer insulating film 405, melamine derivatives such as BT resin, liquid crystal polymer, epoxy resin, PPE resin, polyimide resin, fluorine resin, phenol resin, thermosetting resin polyamide bismaleimide is illustrated . このうち、高周波特性に優れる液晶ポリマー、エポキシ樹脂、BTレジン等のメラミン誘導体が好適に用いられる。 Among these, a liquid crystal polymer excellent in high frequency characteristics, epoxy resins, melamine derivatives such as BT resin is preferably used. これらの樹脂とともに、適宜、フィラーや添加剤を添加してもよい。 With these resins, as appropriate, may be added a filler and additives.

つづいて、層間絶縁膜405中にたとえば炭酸ガスレーザー、機械加工、薬液による化学エッチング加工、プラズマを用いたドライエッチング法等によりビアホール424を形成する。 Subsequently, an interlayer insulating film 405 in the example a carbon dioxide gas laser, machining, chemical etching with a chemical solution to form a via hole 424 by a dry etching method using plasma. その後、エキシマレーザーを照射してエッチング滓を除去し、つづいて、ビアホール424を埋め込むように全面に銅めっき層を形成する。 Then, by irradiating the excimer laser to remove etching dregs Subsequently, a copper plating layer on the entire surface so as to fill the via hole 424. この銅めっき層はビアホール424の段差で断線しないように、まず無電解銅めっきにより全面に0.5μm程度の薄膜を形成した後、電解めっきにより約20μm程度の厚みに形成する。 The copper plating layer so as not to break at the step of the via hole 424, after forming a thin film of about 0.5μm first on the entire surface by electroless copper plating, is formed to have a thickness of about 20μm by electroplating. 無電解めっき用触媒は、通常パラジウムを用いることが多く、可とう性の絶縁基材に無電解用めっき用触媒を付着させるには、パラジウムを錯体の状態で水溶液に含ませ、可とう性の絶縁基材を浸漬して表面にパラジウム錯体を付着させ、そのまま、還元剤を用いて、金属パラジウムに還元することによって可とう性の絶縁基材表面にめっきを開始するための核を形成することができる。 Electroless plating catalyst are often employed normally palladium, to deposit the electroless plating catalyst on the insulating base of the flexible, the palladium is contained in the aqueous solution in the form of complexes, a flexible the palladium complex is deposited on the surface by immersing the insulating substrate, as it is, with a reducing agent to form nuclei for initiating plating the surface of the flexible insulating substrate by reducing the metallic palladium that can. 通常は、このような操作をするために、被めっき物を、アルコールや酸で洗浄し、表面に付着した油分を除去しておく。 Normally, to make such an operation, the object to be plated, and washed with alcohol or acid, keep remove oil adhering to the surface.

その後、フォトレジストをマスクとして銅めっき層をエッチングし、銅からなる配線407を形成する(図5(b))。 Then, a copper plating layer is etched using the photoresist as a mask to form a wiring 407 made of copper (Figure 5 (b)). このとき、ビア403も形成される。 In this case, vias 403 are also formed. 配線407は、たとえば、レジストから露出した箇所に、化学エッチング液をスプレー噴霧して不要な銅箔をエッチング除去することにより形成することができる。 Wire 407, for example, at a position exposed from the resist can be formed by etching away unwanted copper foil by spraying a chemical etchant. エッチングレジストは、通常のプリント配線板に用いることのできるエッチングレジスト材料を用いることができ、レジストインクをシルクスクリーン印刷して形成したり、エッチングレジスト用感光性ドライフィルムを銅箔の上にラミネートして、その上に配線導体の形状に光を透過するフォトマスクを重ね、紫外線を露光し、露光しなかった箇所を現像液で除去して形成することができる。 Etching resist, it can be used an etching resist material can be used for ordinary printed wiring board, the resist ink may be formed by silk screen printing, laminating an etching resist photosensitive dry film on the copper foil Te, overlapping a photomask which transmits light in the shape of the wiring conductors thereon, and exposed to ultraviolet rays, the portions that were not exposed can be formed by removing a developing solution. 化学エッチング液には、塩化第二銅と塩酸の溶液、塩化第二鉄溶液、硫酸と過酸化水素の溶液、過硫酸アンモニウム溶液など、通常のプリント配線板に用いる化学エッチング液を用いることができる。 The chemical etchant, a solution of cupric chloride and hydrochloric acid, ferric chloride solution, a solution of sulfuric acid and hydrogen peroxide, ammonium persulfate solution, it is possible to use chemical etching solution used for ordinary printed wiring board.

その後、配線407を覆うようにしてさらに層間絶縁膜405を形成した後、同様の手順を繰り返すことにより、ビアホール424、ビア403、配線407、および被切断配線408の積層構造を形成する(図5(c))。 Then, after further forming an interlayer insulating film 405 so as to cover the wiring 407, by repeating the same procedure, the via hole 424, a via 403, interconnect 407, and a laminated structure of the cutting wire 408 (FIG. 5 (c)).

図2(a)に戻り、多層配線構造455の最上層には、絶縁膜409を形成する。 Returning to FIG. 2 (a), the uppermost layer of the multilayer wiring structure 455, an insulating film 409. 絶縁膜409を構成する材料としては、たとえばエポキシ樹脂、アクリル樹脂、ウレタン樹脂、ポリイミド樹脂等の樹脂、および、これらの混合物、さらに、これらの樹脂にカーボンブラック、アルミナ、窒化アルミニウム、窒化ホウ素、酸化スズ、酸化鉄、酸化銅、タルク、雲母、カオリナイト、炭酸カルシウム、シリカ、酸化チタン等の無機フィラーを混合したもの等が例示される。 As a material for forming the insulating film 409, for example epoxy resins, acrylic resins, urethane resins, resins such as polyimide resin, and a mixture thereof, further, these resins to the carbon black, alumina, aluminum nitride, boron nitride, oxide tin, iron oxide, copper oxide, talc, mica, kaolinite, calcium carbonate, silica, or the like obtained by mixing an inorganic filler such as titanium oxide are exemplified.

その後、絶縁膜409の表面に第一の回路素子410aおよび第二の回路素子410bを搭載し、第一の回路素子410aおよび第二の回路素子410bをワイヤ412を介して配線407および被切断配線408と接続する。 Thereafter, the first circuit element 410a and the second circuit element 410b mounted on the surface of the insulating film 409, the first circuit element 410a and the second circuit element 410b of the through wire 412 wire 407 and the cutting wire 408 and connect. 第一の回路素子410aおよび第二の回路素子410bは、たとえば半田等のロウ材や接着剤等により絶縁膜409上に固着される。 The first circuit element 410a and the second circuit element 410b is fixed on the insulating film 409 by, for example, brazing material or an adhesive such as solder or the like.

次いで、これらの第一の回路素子410aおよび第二の回路素子410bを封止膜415でモールドする。 Then, molding these first circuit element 410a and the second circuit element 410b in the sealing film 415. 第一の回路素子410aおよび第二の回路素子410bのモールドは、金型を用いて同時に行う。 Mold of the first circuit element 410a and the second circuit element 410b is conducted simultaneously using a mold. ここでは二つの回路素子しか示していないが、より多くの回路素子に対して同時にモールドをすることができる。 Here not only it shows two circuit elements, but can be simultaneously molded to more circuit elements. 封止膜415の形成は、トランスファーモールド、インジェクションモールド、ポッティングまたはディッピングにより実現できる。 Formation of the sealing film 415, transfer molding, injection molding, can be achieved by potting or dipping. 樹脂材料としては、エポキシ樹脂等の熱硬化性樹脂がトランスファーモールドまたはポッティングで実現でき、ポリイミド樹脂、ポリフェニレンサルファイド等の熱可塑性樹脂はインジェクションモールドで実現できる。 As the resin material, thermosetting resin such as epoxy resin can be realized by transfer molding or potting, polyimide resin, thermoplastic resin such as polyphenylene sulfide can be realized by injection molding.

また、以上の図2〜図5では、回路素子410a(および回路素子410b)と配線407および配線408a(および配線408b)とをワイヤボンディング方式で接続する形態を示したが、図6に示すように回路素子410aをフェイスダウンに配置したフリップ実装とすることもできる。 Further, in FIGS. 2 to 5 described above, although the embodiment for connecting the circuit element 410a (and the circuit element 410b) and the wiring 407 and the wiring 408a (and the wiring 408b) by wire bonding method, as shown in FIG. 6 It may be a flip mounting of arranging the circuit elements 410a to face down.

図7は、多層配線構造455上に形成された複数の半導体装置465がマトリクス状に形成された状態を示す図である。 Figure 7 is a diagram showing a state where a plurality of semiconductor devices 465 formed on the multilayer wiring structure 455 are formed in a matrix. 本実施の形態において、複数のモジュール上には封止膜415および遮蔽膜416が形成されているが、ここでは記載を省略している。 In the present embodiment, although on a plurality of modules are formed sealing film 415 and the shielding film 416, are omitted here. 複数のモジュール465は、ダイシングライン490に沿って分割される。 A plurality of modules 465 are divided along dicing lines 490. 本実施の形態において、金属箔を除去した後にダイシングするため、切断面の荒れやブレードの消耗を抑制することができる。 In this embodiment, since the dicing after removing the metal foil, it is possible to suppress the wear of the roughness and the blade of the cut surface. また、多層配線構造455の表面に位置合わせマーク470を設けることにより、ダイシングラインの位置を迅速かつ正確に把握することができる。 Further, by providing the alignment mark 470 on the surface of the multilayer wiring structure 455, it is possible to grasp the position of the dicing line quickly and accurately. 本実施の形態において、位置合わせマーク470は、多層配線構造455の表面から裏面にかけてホール状に形成されることが好ましい。 In this embodiment, the alignment mark 470 is preferably toward the back side from the surface of the multilayer wiring structure 455 is formed on the hole shape. これにより、裏面からダイシングを行う際にもダイシングラインの位置を正確に把握することができる。 Thus, it is possible to accurately grasp the position of the dicing line even when performing dicing from the back.

なお、BGA等の従来のCSPにおいては、基板上に形成されたモジュールを金型で打ち抜く方法が採用されている。 Incidentally, in the conventional CSP of BGA, etc., a method of punching a module formed on a substrate in a mold is employed. そのため、本実施の形態で説明したようにダイシング工程との組合せで遮蔽膜416を形成するような製造プロセスを従来のCSPに適用するのは困難である。 Therefore, it is difficult to apply as described in this embodiment in combination with dicing the manufacturing process so as to form the shielding film 416 in the conventional CSP. このように、本実施の形態で説明したようなISBを用いることにより、ダイシングで半導体装置を分割するとともに遮蔽膜416をも形成することができ、製造プロセス上、大きなメリットがある。 In this way, by using the ISB as described in the present embodiment, it is possible to also form the shielding film 416 as well as dividing a semiconductor device by a dicing, a manufacturing process, there is a great advantage.

図8は、半導体装置の他の例を示す図である。 Figure 8 is a diagram showing another example of the semiconductor device.
図2および図3においては、一つの半導体装置に一つの回路素子が含まれる構成を示したが、半導体装置は、一つの装置内に複数の回路素子が含まれるモジュールとすることもできる。 In FIG. 2 and FIG. 3 shows a configuration that includes one circuit element on a single semiconductor device, the semiconductor device may also be a module that includes a plurality of circuit elements within a single apparatus.

図8に示した半導体装置は、複数の受動素子410cや複数の半導体素子410d、410e、410fを含む。 The semiconductor device shown in FIG. 8 includes a plurality of passive elements 410c and a plurality of semiconductor elements 410 d, 410e, and 410f. ここで、半導体装置は、一つの半導体素子410eと他の半導体素子410fとが積層した構成を含む。 Here, the semiconductor device includes a configuration in which a single semiconductor device 410e and the other semiconductor elements 410f are laminated. このような半導体素子410eと半導体素子410fとの組み合わせは、たとえばSRAMとFlashメモリ、SRAMとPRAMとすることができる。 The combination of such a semiconductor device 410e and the semiconductor element 410f may be, for example, SRAM and Flash memory, an SRAM and PRAM. この場合、半導体素子410eと半導体素子410fとはビア500により電気的に接続される。 In this case, the semiconductor device 410e and the semiconductor element 410f is electrically connected by a via 500.

次に、この半導体装置を製造する工程を説明する。 Next, a process of manufacturing the semiconductor device.
図8(a)は、半導体装置の製造途中における積層体を示す。 8 (a) shows a layered structure in the process of producing a semiconductor device. 積層体は、金属箔402上に形成された多層配線構造と、その上に形成された複数の受動素子410cや複数の半導体素子410d、410e、410fとを含む。 Laminate comprises a multilayer wiring structure formed on the metal foil 402, the plurality of passive elements formed on the 410c and the plurality of semiconductor elements 410 d, 410e, and 410f. このように構成された積層体に、図中上側から多層配線構造の途中までダイシングして分割溝411を形成する(図8(b))。 Thus the constructed laminate, to form a dicing to divide the groove 411 from the upper side in the figure to the middle of the multilayer wiring structure (Figure 8 (b)). その後、図2を参照して上述したのと同様にして、半導体装置を覆うようにして遮蔽膜を形成する。 Thereafter, in the same manner as that described above with reference to FIG. 2, so as to cover the semiconductor device to form a shielding film. つづいて、金属箔402を除去する。 Subsequently, to remove the metal foil 402. その後、金属箔402を除去した面に半田ボール420を形成する。 Thereafter, a solder ball 420 on the surface to remove the metal foil 402. 次いで、分割溝411に沿って、図8(b)で示したのとは反対側の面から再びダイシングして半導体装置を分割する。 Then, along the dividing grooves 411 to divide the semiconductor device again diced from the surface opposite to that shown in FIG. 8 (b). これにより、図8(c)に示す構成の半導体装置が得られる。 Thus, the semiconductor device having the structure shown in FIG. 8 (c) is obtained.

本例においても、遮蔽膜416は、配線408cを介してハンダボール420と電気的に接続される。 In this embodiment, the shielding film 416 is electrically connected to the solder ball 420 via a wire 408 c. これにより、ハンダボール420を接地することにより、遮蔽膜416も接地することができ、半導体装置のノイズを遮断することができる。 Thus, by grounding the solder balls 420, also it can be grounded shielding film 416, it is possible to cut off the noise of the semiconductor device.

ISBの一例を示す概略構成図である。 Is a schematic diagram showing an example of ISB. 本発明の実施の形態における半導体装置の製造方法を示す工程断面図である。 Is a process cross-sectional views showing a manufacturing method of a semiconductor device in an embodiment of the present invention. 図2に示した半導体装置の変形例の製造方法を示す工程断面図である。 It is a process cross-sectional views showing a manufacturing method of a modification of the semiconductor device shown in FIG. 図2に示した多層配線構造部分を詳細に示す半導体装置の断面図である。 It is a cross-sectional view of a semiconductor device showing in detail the multilayer wiring structure portion shown in FIG. 図2に示した半導体装置の製造途中の積層体の製造方法を示す図である。 It is a diagram showing a manufacturing method of manufacturing the middle of the stack of the semiconductor device shown in FIG. 回路素子をフェイスダウンに配置したフリップ実装とした半導体装置の断面図である。 Is a cross-sectional view of a semiconductor device in which a flip mounting of arranging the circuit elements on the face-down. 多層配線構造上に複数の半導体装置がマトリクス状に形成された状態を示す図である。 A plurality of semiconductor devices on the multilayer interconnection structure is a view showing a state of being formed in a matrix. 半導体装置の他の例を示す図である。 It is a diagram showing another example of the semiconductor device.

符号の説明 DESCRIPTION OF SYMBOLS

201 LSIベアチップ、 202 Trベアチップ、 203 チップCR、 204 金線ボンディング、 205 銅パターン、 206 導電性ペースト、 207 樹脂パッケージ、 402 金属箔、 403 ビア、 405 層間絶縁膜、 407 配線、 408 被切断配線、 408a 配線、 408b 配線、 409 絶縁膜、 410a 第一の回路素子、 410b 第二の回路素子、 411 分割溝、 412 ワイヤ、 415 封止膜、 416 遮蔽膜、 418 保護膜、 420 半田ボール、 422 導電被膜、 424 ビアホール、 455 多層配線構造、 465 半導体装置、 470 マーク、 490 ダイシングライン。 201 LSI bare chip, 202 Tr bare chip, 203 chip CR, 204 gold bonding, 205 copper pattern, 206 conductive paste 207 resin package, 402 a metal foil, 403 via, 405 an interlayer insulating film, 407 a wiring, 408 to be cut wire, 408a wiring 408b wiring, 409 insulating film, 410a a first circuit element, 410b second circuit element, 411 split groove, 412 wire, 415 sealing film 416 shielding film, 418 a protective film, 420 a solder ball, 422 conductive film, 424 via holes 455 a multilayer wiring structure, 465 a semiconductor device, 470 mark, 490 dicing line.

Claims (6)

  1. 絶縁層と、 An insulating layer,
    前記絶縁層内に埋設された配線と、 A wiring embedded in the insulating layer,
    前記絶縁層上に搭載された回路素子と、 And a circuit element mounted on the insulating layer,
    前記回路素子を覆うように形成された封止層と、 A sealing layer which is formed so as to cover the circuit elements,
    前記封止層を覆うように形成された導電性の遮蔽膜と、 A shielding film formed conductive so as to cover the sealing layer,
    を含み、 It includes,
    前記配線と前記遮蔽膜とが電気的に接続していることを特徴とする半導体装置。 Wherein a said wiring and said shielding film is electrically connected.
  2. 請求項1に記載の半導体装置において、 The semiconductor device according to claim 1,
    前記遮蔽膜を覆うように形成され、前記遮蔽膜を構成する材料よりも腐食耐性の高い材料により構成された保護膜をさらに含むことを特徴とする半導体装置。 The shielding film is formed to cover the semiconductor device, characterized in that than the material of the shielding film further comprises a protective layer which is composed of highly corrosive-resistant material.
  3. 絶縁層と、前記絶縁層内に埋設された配線と、前記絶縁層表面に搭載された回路素子と、前記回路素子を覆うように形成された封止層と、を含む積層体を分割して前記回路素子を含む半導体装置を製造する方法であって、 An insulating layer, wherein the buried in the insulating layer wiring, wherein a circuit element mounted on an insulating layer surface, by dividing the laminate including, a sealing layer formed to cover said circuit element a method of manufacturing a semiconductor device including the circuit elements,
    前記積層体の表面に分割溝を形成して前記配線の側面を露出させる工程と、 Exposing a side surface of the wiring by forming a split groove in the surface of the laminate,
    前記積層体の表面側を導電性材料で覆い、前記配線と電気的に接続した遮蔽膜を形成する工程と、 A step in which the surface side of the laminate is covered with a conductive material to form a shielding film the wiring electrically connected,
    前記積層体を裏面から前記分割溝に沿って切断し、当該積層体の前記回路素子を他の領域から分割する工程と、 The cut along the stack from the rear surface to the dividing grooves, a step of dividing the circuit elements of the stack from the other regions,
    を含むことを特徴とする半導体装置の製造方法。 The method of manufacturing a semiconductor device, which comprises a.
  4. 請求項3に記載の半導体装置の製造方法において、 The method of manufacturing a semiconductor device according to claim 3,
    前記配線を接地させる工程をさらに含むことを特徴とする半導体装置の製造方法。 The method of manufacturing a semiconductor device characterized by further comprising the step of grounding the wire.
  5. 請求項3または4に記載の半導体装置の製造方法において、 The method of manufacturing a semiconductor device according to claim 3 or 4,
    前記絶縁層上には複数の回路素子が搭載され、前記配線の側面を露出させる工程の前において、前記配線は前記複数の回路素子に接続して設けられ、 Said on the insulating layer is mounted a plurality of circuit elements, before the step of exposing the side surfaces of the wiring, the wiring is arranged in connection to said plurality of circuit elements,
    前記配線の側面を露出させる工程において、前記配線を分割し、当該分割された各配線が各前記回路素子にそれぞれ接続されるように前記分割溝を形成することを特徴とする半導体装置の製造方法。 In the step of exposing the side surfaces of the wiring, the wiring is divided, and a method of manufacturing a semiconductor device characterized by the divided respective wires were to form the dividing grooves so as to be connected to each of said circuit elements .
  6. 請求項3乃至5いずれかに記載の半導体装置の製造方法において、 The method of manufacturing a semiconductor device according to any one claims 3 to 5,
    前記遮蔽膜を、当該遮蔽膜を構成する材料よりも腐食耐性の高い材料により構成された保護膜で覆う工程をさらに含むことを特徴とする半導体装置の製造方法。 The method of manufacturing a semiconductor device characterized by further comprising the shielding layer, than the material constituting the shielding film is covered with a protective film composed of a highly corrosive-resistant material.
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