JP2004291463A - Data transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obviate the need of a memory device for temporarily storing line data adjacent to line data to be processed in a data transfer device that reads bit map image data from a memory device by each line data to transfer it to a compressing circuit for performing compression processing by referencing the line data adjacent to the line to be processed. <P>SOLUTION: This data transfer device comprises a first memory means for storing an address in a memory device of the line data to be processed, a second memory means for storing an address in a memory device of the line data adjacent to the line data to be processed, and a transferring means. The transferring means reads the line data corresponding to the address stored in the second memory means to transfer it to the compressing circuit after or before it reads the line data corresponding to the address stored in the first memory means from the memory device to transfer it to the compressing circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data transfer device, and in particular, reads out bitmap image data from a storage device for each line data, and transfers the read data to a compression circuit that performs compression processing with reference to line data adjacent to the line data to be processed. The present invention relates to a data transfer device.
[0002]
[Prior art]
A page printer such as a laser printer receives print data written in a printer control language output from a host computer, converts the print data into bitmap image data, and prints a print sheet based on the bitmap image data. A printing mechanism for printing on a print medium.
[0003]
Since the printing mechanism of a page printer performs printing for each page, when the printing mechanism starts printing, one page of bitmap image data must be prepared. Therefore, it is necessary for the image processing unit to temporarily store bitmap image data for one page.
[0004]
However, when a page printer handles a high-resolution image or a color image, the amount of bitmap image data for one page is enormous, and the storage capacity of the image processing unit cannot be satisfied.
[0005]
For this reason, the image processing unit of the page printer that handles high-resolution images, color images, and the like compresses the bitmap image data and temporarily stores it.
[0006]
Various methods have been proposed as compression algorithms for bitmap image data. For each pixel of the line data constituting the bitmap image data, the upper and left and right pixels are referred, and the upper and left and right pixels are not matched. A technique of performing compression based on a difference from an adjacent pixel or the like has been put to practical use. This compression processing is performed in hardware, for example, in a memory controller included in the image processing unit.
[0007]
FIG. 3 is a block diagram for explaining a compression process of a conventional image processing unit using such an algorithm.
[0008]
Bitmap image data generated by a CPU (not shown) is stored in the RAM 130 in band units.
[0009]
The DMA processing unit 111 of the memory controller 110 DMA-transfers the bitmap image data stored in the RAM 130 line by line to the compression unit 112. This one line is a unit of the compression processing. For this reason, the DMA processing unit 111 includes an address counter 111a that indicates the head address of the line data to be subjected to the compression processing, and can sequentially read the data from the RAM 130 and perform the compression processing.
[0010]
In the present algorithm, compression is performed with reference to the upper and left pixels of the target pixel, so that the line data immediately before the line data to be processed is also required. For this reason, the memory controller 110 is provided with an SRAM 113 for temporarily storing line data.
[0011]
The DMA processing unit 111 transfers the line data to be processed to the compression unit 112, reads the line data immediately before the line data to be processed from the SRAM 113, and transfers the line data to the compression unit 112. Then, the contents of the SRAM 113 are updated to the line data to be processed. Further, the address counter 111a is incremented.
[0012]
The compression unit 112 performs a compression process using the transferred line data to be processed and the previous line data. The compressed line data is DMA-transferred to the RAM 130 by the DMA processing unit 111 and stored in band units.
[0013]
[Problems to be solved by the invention]
As described above, since the present compression algorithm performs compression with reference to pixels on other line data adjacent to the line data to be subjected to compression processing, it is necessary to temporarily store other line data.
[0014]
Therefore, a storage device for this is required, and the manufacturing cost of a semiconductor device such as a memory controller that performs compression processing increases. In addition, the area of the semiconductor device is increased due to the arrangement of the storage device.
[0015]
The present invention relates to a data transfer apparatus for reading bitmap image data from a storage device for each line data and transferring the read bitmap image data to a compression circuit that performs compression processing with reference to line data adjacent to the line data to be processed. An object of the present invention is to eliminate a storage device for temporarily storing line data adjacent to line data.
[0016]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides:
A data transfer device that reads bitmap image data from a storage device for each line data, and transfers the read bitmap image data to a compression circuit that performs compression processing with reference to line data adjacent to the line data to be processed.
First storage means for storing an address of the line data to be processed on the storage device;
Second storage means for storing an address on the storage device of line data adjacent to the line data to be processed;
After the line data corresponding to the address stored in the first storage means is read from the storage device and transferred to the compression circuit, or before the transfer, the line data is stored in the address stored in the second storage means. Transfer means for reading out the corresponding line data from the storage device and transferring it to the compression circuit.
[0017]
According to the present invention, since the line data adjacent to the line data to be processed is read from the storage device and transferred to the compression circuit, a storage device for temporarily storing the adjacent line data is not required.
[0018]
Here, the first storage means can be constituted by an address counter.
[0019]
At this time, the transfer unit reads line data corresponding to the address stored in the second storage unit from the storage device and transfers the read line data to the compression circuit. The address is updated by the address indicated by the address counter as the first storage means, and the address counter is incremented.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described with reference to the drawings.
[0021]
FIG. 1 is a block diagram showing a configuration of a page printer to which the present invention is applied. The printer receives print data described in a print control language from a host computer, converts the print data into bitmap image data, and prints on a print medium such as printing paper based on the bitmap image data. And a printing mechanism 2.
[0022]
In the image processing unit 1, the print data sent from the host computer is received by the input interface 50, the CPU 20 develops the data into bitmap image data according to the program recorded in the ROM 40, and stores the data into the RAM 30 for each band. The memory controller 10 sequentially reads the stored bitmap image data, reduces the capacity by compression processing, and stores the data in the RAM 30.
[0023]
When the compressed bitmap image data is stored in the RAM 30, the original bitmap image data can be erased from the RAM 30, so that the storage capacity for storing the bitmap image data for one page is not provided. However, it can handle image data such as high-resolution images and color images.
[0024]
The compressed bitmap image data is DMA-transferred to the video interface 60 by the memory controller 10 when one page of data is available. The video interface 60 expands the compressed bitmap image and transfers it to the printing mechanism 2, and the printing mechanism 2 performs printing according to the bitmap image.
[0025]
In the present embodiment, the compression algorithm of the bitmap image data, for each pixel of the line data constituting the bitmap image data, refer to the upper left and right pixels, match and mismatch with the upper and left and right pixels, the right and left pixels The compression method is adopted based on the difference between the two. This compression processing is performed by hardware in the compression unit 12 provided in the memory controller 10. Note that a method of performing compression by referring to the lower left and right pixels may be used.
[0026]
FIG. 2 is a block diagram illustrating a compression process of the image processing unit 1 according to the present embodiment.
[0027]
The bitmap image data generated by the CPU 20 is stored in the RAM 30 in band units.
[0028]
The DMA processing unit 11 of the memory controller 10 includes a previous line address register 11b that stores a head address immediately before a line to be processed, in addition to a conventional address counter 11a that indicates a head address of a line to be processed. ing.
[0029]
When the DMA processing unit 11 DMA-transfers the line data indicated by the address counter 11a from the RAM 30 to the compression unit 12, the DMA processing unit 11 transfers the line data corresponding to the address stored in the previous line address register 11b from the RAM 30 to the compression unit 12. Forward. This line data is the line data immediately before the line to be processed which has been DMA-transferred first. Note that the order of the DMA transfer may be reversed.
[0030]
Then, the previous line address register 11b is updated with the contents of the address counter 11a, and the address counter 11a is incremented. The previous line address register 11b may also be formed of a counter, and may be incremented together with the address counter 11a.
[0031]
The compression unit 12 performs a compression process using the line data to be processed, which has been DMA-transferred by the DMA processing unit 11, and the previous line data. The compressed line data is DMA-transferred to the RAM 30 by the DMA processing unit 11 and stored in band units.
[0032]
In order to process one line of data, two DMA transfers from the RAM 30 to the compression unit 12 are required. If the transfer speed between the RAM 30 and the memory controller 10 is sufficiently fast (for example, the DMA processing unit 11 Compression can be performed in the same processing time as in the past, which is twice or more the transfer speed with the compression unit 12). This can be realized by using a high-speed RAM such as a DDR SDRAM (Double Data Rate Synchronous DRAM) that has been put into practical use in recent years.
[0033]
As described above, according to the present invention, a storage device for temporarily storing adjacent line data can be omitted.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a page printer to which the present invention is applied.
FIG. 2 is a block diagram for explaining a compression process of an image processing unit according to the present invention.
FIG. 3 is a block diagram for explaining compression processing of a conventional image processing unit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Image processing part, 2 ... Printing mechanism, 10 ... Memory controller, 11 ... Memory controller, 11 ... DMA processing part, 11a ... Address counter, 11b ... Previous line address register, 12 ... Compression part, 50 ... Input interface, 60 ... Video interface, 110 ... Memory controller, 111a ... Address counter, 111 ... DMA processing unit, 112 ... Compression unit

Claims (3)

A data transfer device that reads bitmap image data from a storage device for each line data, and transfers the read bitmap image data to a compression circuit that performs compression processing with reference to line data adjacent to the line data to be processed.
First storage means for storing an address of the line data to be processed on the storage device;
Second storage means for storing an address on the storage device of line data adjacent to the line data to be processed;
After the line data corresponding to the address stored in the first storage means is read from the storage device and transferred to the compression circuit, or before the transfer, the line data is stored in the address stored in the second storage means. Transfer means for reading corresponding line data from the storage device and transferring the read line data to the compression circuit. The data transfer device according to claim 1,
The data transfer device according to claim 1, wherein said first storage means comprises an address counter. The data transfer device according to claim 2,
The transfer unit reads line data corresponding to an address stored in the second storage unit from the storage device and transfers the read line data to the compression circuit, and then stores the contents of the second storage unit in the first storage unit. A data transfer device, wherein the data is updated with an address indicated by an address counter as storage means, and the address counter is incremented.

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