JP2004289131A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which allows laser trimming after completion of assembling, and a manufacturing method therefor. <P>SOLUTION: This semiconductor device has a fuse element 7 which is formed on an insulating film 3 on the main surface of a semiconductor substrate 1. A trimming window opening 37 is formed in the semiconductor substrate 1 at a position corresponding to the position of the fuse element 7. After a polyimide film 29 which functions as a final protective film and an external connection terminal 35 are formed to complete the assembling process, the trimming window opening 37 is formed from the rear side 1b of the semiconductor substrate 1. The fuse element 7 is cut when necessary, then a sealing resin 39 is charged into the trimming window opening 37. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a fuse element on a main surface of a semiconductor substrate via an insulating film and a manufacturing method thereof. An example of the semiconductor device to which the present invention is applied is a chip size package. The chip size package is also called CSP, and is a generic name for packages that are equal to or slightly larger than the chip size, and is a package intended for high-density mounting.

Conventionally, in the semiconductor package field, generally referred to as BGA (Ball Grid Array), a structure having a plurality of solder balls arranged in a plane, or as a fine pitch BGA, the ball pitch of the BGA is further narrowed. A structure in which the package outer shape is close to the chip size is known.
Recently, there is a wafer level CSP (see, for example, Patent Document 1). The wafer level CSP is basically a CSP that creates an array of pads before dicing.

  Also, some semiconductor devices including analog ICs such as power supply ICs (integrated circuits) include a fuse element made of a polysilicon film for adjusting the resistance value. Such a fuse element is cut by laser irradiation through a trimming window opening in a laser trimming process (see, for example, Patent Document 2). In general, the trimming window opening is formed in an insulating film on the main surface of a semiconductor substrate.

  FIG. 33 is a cross-sectional view showing a fuse element portion in a conventional wafer level CSP, where (A) shows a state before laser trimming, (B) shows a state after laser trimming, and (C) shows a state after resin sealing. Show. FIG. 34 is a sectional view showing a fuse element and a metal electrode pad portion in a conventional wafer level CSP. FIG. 35 is a flowchart showing a part of a conventional wafer level CSP manufacturing process including a laser trimming process. Hereinafter, a conventional wafer level CSP manufacturing method including a laser trimming process will be described with reference to FIGS.

  A base insulating film 3 is formed on the main surface 1 a of the silicon substrate 1, and a fuse element 7 made of a polysilicon film and a polysilicon film 5 such as a gate electrode and a resistor are formed on the base insulating film 3. An interlayer insulating film 9 made of, for example, a BPSG (borophosphosilicate glass) film is formed on the entire surface of the silicon substrate 1, a connection hole 11 is formed in the interlayer insulating film 9, and then, for example, Al (on the interlayer insulating film 9 and in the connection hole 11 is formed. A metal wiring layer 13 and a metal electrode pad 15 made of aluminum are formed. Thereafter, for example, a passivation film made of a PSG (phosphosilicate glass) film 17 as a lower layer and a SiN (silicon nitride) film 19 as an upper layer is formed, and a polyimide film 21 is further formed thereon. A trimming window opening 85 for performing laser trimming is formed in the insulating film on the fuse element 7, and a pad opening for establishing electrical connection with a metal wiring layer to be formed later in the insulating film on the metal electrode pad 15. Part 23 is formed. As a result, the insulating film 9 on the fuse element 7 remains thin, for example, 0.2 to 0.6 μm (micrometer) (see FIG. 33A and FIG. 35 (step S61)).

  A wafer test is performed through metal electrode pad 15 (see FIG. 35 (step S62)). In order to increase the accuracy of the analog IC, a laser trimming process is performed according to the wafer test result, and the fuse element 7 is cut (see fuse cut, FIG. 33B and FIG. 35 (step S63)). FIG. 34 shows the fuse element 7 after cutting.

  After the laser trimming process, a barrier metal layer (not shown) made of Cr (chromium) and a plating electrode layer made of Cu (copper) are formed on the entire surface of the silicon substrate 1 by sputtering. This barrier metal layer is interposed between the metal wiring layer made of Cu and the metal electrode pad 15 to prevent Cu and Al from entering each other. A photoresist pattern is formed in a predetermined region on the plating electrode layer, and a second metal wiring layer 25 and a second metal electrode pad 27 made of Cu are formed by electrolytic plating. A barrier metal layer 33 is formed on the second metal wiring layer 25 and the second metal electrode pad 27. The second metal wiring layer 25 and the second metal electrode pad 27 are also referred to as a rewiring layer (see FIG. 35 (step S64)).

  After removing the photoresist pattern, unnecessary plating electrode layers and barrier metal layers are removed by wet etching using the second metal wiring layer 25 and the second metal electrode pad 27 as a mask. A polyimide film 29 is formed on the entire surface of the semiconductor substrate 1 (polyimide coating, see FIG. 33C and FIG. 35 (step S65)), and a second pad opening 31 is formed on the second metal electrode pad 27 (see FIG. Ball mount opening, see FIG. 35 (step S66)). An external connection terminal 35 made of, for example, solder is mechanically fixed to the second metal electrode pad 27 using SMT (surface mounting technology) (see ball mount, FIG. 34 and FIG. 35 (step S67)). The external connection terminal 35 may be formed by applying a heat treatment after the cream solder is printed by a screen printing method.

  After the wafer test, the back surface 1b of the silicon substrate 1 is polished (see FIG. 35 (step S68)), and the silicon substrate 1 is divided into chips by a scribe process to complete a wafer level CSP (see FIG. 35 (step S69)). ).

  36, the individualization of a semiconductor wafer (hereinafter also referred to as a silicon wafer) in the conventional method for manufacturing a semiconductor device will be described. Hereinafter, in the drawings, the silicon wafer is given the same reference numeral as the semiconductor substrate. Such a manufacturing method is described in Patent Document 1, for example.

(1) A wiring made of copper is formed by electroplating or the like on a silicon wafer 1 on which a semiconductor element is formed on one surface and a metal wiring layer (not shown) including an electrode pad is formed thereon. To do. The copper wiring is electrically connected to an electrode pad formed on the silicon wafer 1. After a UV curable dicing tape 87 is attached to the surface (back surface) opposite to the copper wiring forming surface of the silicon wafer 1, a groove 89 is formed on the surface of the silicon wafer 1 by a peripheral blade (dicing saw) rotated at high speed. Form. The groove 89 is formed in a portion that becomes a peripheral portion of each chip (semiconductor device). The blade thickness of the dicing saw used for forming the groove 89 is 35 to 150 μm. The width of the groove 89 is 1-5 μm larger than the blade thickness, and the depth is, for example, 10 μm or more. By setting the depth of the groove 89 to 10 μm or more, it is possible to form the groove 89 with a stable width without depending on the shape of the tip of the blade (see (a)).

(2) Fill the surface of the silicon wafer 1 with resin 91. The resin 91 filled at this time also enters the groove 89. The surface of the resin is polished with a polishing blade until a part of the copper wiring covered with the resin 91 is exposed, and then external connection terminals 35 are formed on the exposed copper wiring by solder balls or the like. Thereafter, a groove 93 is formed in the resin 91 formed on the groove 89 by a dicing saw that rotates at high speed (see (b)).

(3) The silicon wafer 1 in a region corresponding to the groove 93 is cut by a dicing saw rotating at high speed to divide the silicon wafer 1 into individual chips 95. The dicing saw used at the time of cutting uses a thinner blade than the dicing saw used to form the groove 93, and the groove 53 is formed with a narrower width than the groove 93 (see (c)).
(4) After the dicing tape 87 is cured by irradiating ultraviolet rays, the chip 95 that has been separated into pieces is pushed up and taken out using the pickup needle 49 (see (d)).
JP 2000-260910 A JP-A-11-135730

  For example, in an analog IC that adjusts the resistance value by cutting the fuse element, if trimming is performed before the assembly process is completed as in the prior art, the resistance value fluctuates after the assembly process is completed due to changes in film stress, etc. There was a problem that the accuracy of the electrical characteristics was lowered.

  Further, in the manufacturing method of the wafer level CSP, when the laser trimming process is performed according to the customer's request, the assembly process is performed after the laser trimming.

  Therefore, an object of the present invention is to provide a semiconductor device capable of performing a laser trimming process after the assembly process is completed, and a manufacturing method thereof.

  The semiconductor device of the present invention is provided with a fuse element on the main surface of a semiconductor substrate through an insulating film, and a trimming window opening is formed in the semiconductor substrate corresponding to the position where the fuse element is formed. It is what has been. Here, the main surface of the semiconductor substrate refers to one surface of a semiconductor substrate on which a semiconductor element such as a MOS transistor is formed.

  In the semiconductor device of the present invention, it is preferable that the insulating film remains between the fuse element before cutting and the trimming window opening.

  Furthermore, in the semiconductor device of the present invention, the trimming window opening is preferably sealed from the back side of the semiconductor substrate.

Furthermore, it is preferable that the semiconductor substrate is formed so that the thickness in the vicinity of the trimming window opening is thinner than in other regions.
An example in which the semiconductor substrate is formed with a thickness near the trimming window opening thinner than other areas due to a recess formed in the area near the trimming window opening by silicon crystal plane anisotropic etching. Can be mentioned.
In that case, it is preferable that boron is introduced into the formation region of the bottom of the recess in the semiconductor substrate.

Further, the semiconductor substrate has an epitaxial growth layer formed on the main surface side of the silicon substrate, and an opening is formed in the silicon substrate in the vicinity of the trimming window opening. An example in which the trimming window opening is formed in the epitaxial growth layer.
In that case, an example can be given in which the opening formed in the silicon substrate is formed by crystal plane anisotropic etching of silicon.
Further, an example in which the trimming window opening formed in the epitaxial growth layer is formed by crystal plane anisotropic etching of silicon can be given.

  Further, in the semiconductor device of the present invention, it is preferable that roundness is formed at corner portions of the formed shape of the semiconductor device.

  Furthermore, in the semiconductor device of the present invention, when the corner portion of the chip formation shape is rounded, one of the plurality of corner portions is rounded with a size different from that of the other corner portions. Preferably it is.

  Furthermore, in the semiconductor device of the present invention, it is preferable that a barcode having an uneven shape is formed on at least one side surface of the semiconductor device.

  Furthermore, in the semiconductor device of the present invention, it is preferable that a marking made of one or a plurality of recesses is formed on the back surface of the semiconductor substrate.

  Furthermore, in the semiconductor device of the present invention, it is preferable that a marking is formed on the back surface of the semiconductor substrate by laser irradiation.

  As an example of a semiconductor device to which the semiconductor device of the present invention is applied, a semiconductor device having a divided resistor circuit capable of obtaining a voltage output by dividing by two or more resistors and adjusting the voltage output by cutting a fuse element can be cited. it can. In the region where the divided resistor circuit is formed, the fuse element and the trimming window opening constituting the semiconductor device of the present invention are provided.

  As another example of the semiconductor device to which the semiconductor device of the present invention is applied, a divided resistor circuit for dividing an input voltage and supplying a divided voltage, a reference voltage generating circuit for supplying a reference voltage, and the division A semiconductor device including a voltage detection circuit having a comparison circuit for comparing the divided voltage from the resistor circuit with the reference voltage from the reference voltage generation circuit can be given. As the divided resistor circuit, a divided resistor circuit constituting the semiconductor device of the present invention is provided.

  As still another example of a semiconductor device to which the semiconductor device of the present invention is applied, an output driver for controlling the output of the input voltage, a divided resistor circuit for dividing the output voltage and supplying the divided voltage, and a reference voltage A reference voltage generation circuit for supplying, and a comparison circuit for comparing the divided voltage from the division resistor circuit and the reference voltage from the reference voltage generation circuit and controlling the operation of the output driver according to the comparison result A semiconductor device provided with a constant voltage generation circuit can be given. As the divided resistor circuit, a divided resistor circuit constituting the semiconductor device of the present invention is provided.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a fuse element on a main surface of a semiconductor substrate with an insulating film interposed therebetween, and the back side of the wafer-like semiconductor substrate after the formation of the fuse element. And a step of forming a trimming window opening corresponding to the formation region of the fuse element.

In the method for manufacturing a semiconductor device of the present invention, for example, anisotropic etching can be given as a method for forming the trimming window opening.
In that case, the insulating film is preferably used as an etching stopper layer.

  Furthermore, in the method for manufacturing a semiconductor device of the present invention, it is preferable that the wafer-like semiconductor substrate is separated into pieces simultaneously with the formation of the trimming window opening by using anisotropic etching.

  Furthermore, in the semiconductor device manufacturing method of the present invention, after the tape material is attached to the surface of the semiconductor wafer on the main surface side of the semiconductor substrate, the back surface of the semiconductor wafer is polished, and the semiconductor wafer is attached to the tape material. In the state, it is preferable to form the trimming window opening.

  In addition, before the trimming window opening is formed, a step of reducing the thickness of the semiconductor substrate in the vicinity of the trimming window opening formation planned region as compared with other regions may be included.

  As a method of reducing the thickness of the region near the region where the trimming window opening is to be formed as compared with other regions, a silicon substrate is used as the semiconductor substrate, and the trimming window opening is formed by crystal plane anisotropic etching of silicon. An example of forming a recess in the silicon substrate in the vicinity of the planned area can be given.

  When forming the recess, it is preferable to include a step of introducing boron from the main surface side into the region corresponding to the bottom of the recess before the recess is formed.

  As another method of reducing the thickness of the region near the trimming window opening formation planned region as compared with other regions, the semiconductor substrate is formed on the main surface side of the silicon substrate at least near the trimming window opening formation planned region. An example in which an epitaxial growth layer is formed through a silicon oxide film and the silicon oxide film is used as an etching stopper layer to form an opening in the silicon substrate in the vicinity of the region where the trimming window opening is to be formed will be described. be able to.

  In that case, it is preferable to form the opening in the silicon substrate by anisotropic crystal plane etching of silicon.

  Further, as the semiconductor substrate in which the silicon oxide film and the epitaxial layer are formed on the main surface side, a silicon substrate having an opening formed in a region corresponding to the trimming window opening forming region of the silicon oxide film is used. An example can be given in which the formation of the opening in the silicon substrate and the formation of the trimming window opening in the epitaxial growth layer are successively performed by the crystal plane anisotropic etching.

  Furthermore, it is preferable to include a step of forming a mark by laser irradiation on the back surface of the semiconductor substrate when the fuse element is irradiated with laser through the trimming window opening.

Furthermore, the method for manufacturing a semiconductor device of the present invention preferably includes a step of sealing the trimming window opening.
An example of means for sealing the trimming window opening is to fill the trimming window opening with a resin material.

In the semiconductor device according to the first aspect of the present invention, the trimming window opening is not formed in the insulating film on the main surface of the semiconductor substrate as in the prior art, but is formed in the semiconductor substrate. .
In the method for manufacturing a semiconductor device according to the present invention, the trimming window opening is formed from the back side of the wafer-like semiconductor substrate after the fuse element is formed.
Therefore, the laser trimming process can be performed after the final protective film formed on the main surface of the semiconductor substrate is formed, that is, after the assembly process is completed. As a result, for example, in an analog IC that adjusts the resistance value by cutting the fuse element, it is possible to eliminate the resistance value variation after the trimming process due to the formation of the final protective film, and to improve the accuracy of the electrical characteristics. Furthermore, when trimming is performed in accordance with the customer's request, the work period from order receipt to shipping can be shortened.

  In the semiconductor device according to claim 2, since the insulating film remains between the fuse element before cutting and the trimming window opening, the periphery of the fuse element forming region due to moisture absorption, oxidation, or the like. Corrosion can be prevented and reliability can be improved.

  In the semiconductor device according to the third aspect, since the trimming window opening is sealed from the back side of the semiconductor substrate, it is possible to prevent a short circuit due to foreign matter contamination in the cut fuse element. Furthermore, corrosion around the fuse element formation region due to moisture absorption or oxidation can be prevented, and reliability can be improved.

  In the semiconductor device according to claim 4, since the thickness of the region near the trimming window opening is formed thinner than the other regions in the semiconductor substrate, the trimming window opening is formed. The misalignment between the trimming window opening and the fuse element due to the thickness of the semiconductor substrate can be prevented, and the fuse element can be reliably cut when the fuse element is cut by laser irradiation. Furthermore, since the thickness of the area near the trimming window opening is formed thinner than other areas, the state where the sealing material filled in the trimming window opening protrudes from the back surface of the semiconductor substrate can be eliminated. It is possible to improve the reliability by preventing the sealing material from being mechanically peeled off.

  6. The semiconductor device according to claim 5, wherein the thickness of the region near the trimming window opening is different from that of the semiconductor substrate due to a recess formed in the region near the trimming window opening by silicon crystal plane anisotropic etching. The thickness of the region near the opening of the trimming window can be made thinner than other regions by silicon crystal plane anisotropic etching. .

  According to a sixth aspect of the present invention, in the semiconductor device according to the fifth aspect, since the semiconductor substrate is configured such that boron is introduced into the formation region of the bottom of the concave portion. When the recess is formed by anisotropic etching, a region into which boron is introduced can be used as an etching stopper region. Therefore, by controlling the thickness of the region into which boron is introduced in the silicon substrate, the controllability of the thickness of the semiconductor substrate in the region where the trimming window opening is formed can be improved. Underetching can be prevented.

  According to a seventh aspect of the present invention, in the semiconductor device according to the fourth aspect, the semiconductor substrate has an epitaxial growth layer formed on the main surface side of the silicon substrate, and is in the vicinity of the trimming window opening. 9. The semiconductor device according to claim 8, wherein an opening is formed in the silicon substrate in a region, and the trimming window opening is formed in the epitaxial growth layer in the region where the opening is formed. Since the opening is formed in the silicon substrate by crystal plane anisotropic etching, the thickness of the area near the opening of the trimming window is made thinner than other areas by crystal plane anisotropic etching of silicon. Can be.

  In the semiconductor device according to claim 9, the trimming window opening formed in the epitaxial growth layer is formed by crystal plane anisotropic etching of silicon. The formation of the opening in the silicon substrate and the formation of the trimming window opening in the epitaxial growth layer can be performed continuously.

  In the semiconductor device according to claim 10, since the corners of the formed shape of the semiconductor device are rounded, chipping and cracks can be prevented from occurring during the transfer of the chip and the like. Defects can be reduced and reliability can be improved.

  In the semiconductor device according to claim 11, when the corner portion of the chip formation shape is rounded, one of the plurality of corner portions is rounded with a size different from the other corner portions. As a result, the specific corner portion can be recognized from the roundness of the corner portion, and the orientation of the chip, for example, the position of one pin can be recognized.

  In the semiconductor device according to claim 12, since the barcode having the uneven shape is formed on at least one side surface of the semiconductor device, the barcode having the uneven shape provided on the side surface, for example, lot information or Information such as product information can be recorded, and chip recognition can be performed using a barcode.

  In the semiconductor device according to claim 13, since the marking made of one or a plurality of recesses is formed on the back surface of the semiconductor substrate, the marking made of the plurality of recesses, for example, lot information, product information, etc. Information can be recorded, and chip recognition can be performed by marking.

  In the semiconductor device according to claim 14, since the marking is formed on the back surface of the semiconductor substrate by laser irradiation, information such as lot information and product information can be recorded on the marking by laser irradiation. It is possible to recognize the chip by marking.

  In the semiconductor device according to claim 15, as an example of a semiconductor device to which the semiconductor device of the present invention is applied, a voltage output can be obtained by dividing by two or more resistors and a voltage output can be adjusted by cutting a fuse element. In the region where the divided resistor circuit of the semiconductor device provided with the divided resistor circuit is provided, the fuse element and the trimming window opening which constitute the semiconductor device of the present invention are provided. According to the semiconductor device of the invention, the fluctuation of the resistance value after the trimming process can be eliminated, so that the accuracy of the output voltage of the divided resistor circuit can be improved. Furthermore, when trimming is performed in accordance with the customer's request, the work period from order receipt to shipping can be shortened.

  According to another aspect of the semiconductor device of the present invention, as another example of a semiconductor device to which the semiconductor device of the present invention is applied, a divided resistor circuit for dividing an input voltage and supplying a divided voltage, and a reference voltage are provided. The divided resistor circuit of the semiconductor device including a reference voltage generating circuit for supplying, and a voltage detection circuit having a comparison circuit for comparing the divided voltage from the divided resistor circuit and the reference voltage from the reference voltage generating circuit As described above, according to the semiconductor device of the present invention, it is possible to eliminate the fluctuation of the resistance value after the trimming process, and the divided resistor circuit. Since the accuracy of the output voltage of the circuit can be improved, the accuracy of the voltage detection capability of the voltage detection circuit can be improved.

  According to another aspect of the present invention, there is provided a semiconductor device to which the semiconductor device of the present invention is applied, an output driver for controlling the output of the input voltage, and the divided voltage by dividing the output voltage. A divided resistor circuit for supplying, a reference voltage generating circuit for supplying a reference voltage, a divided voltage from the divided resistor circuit, and a reference voltage from the reference voltage generating circuit are compared, and the reference voltage is output according to a comparison result. Since the divided resistor circuit constituting the semiconductor device of the present invention is provided as the divided resistor circuit of the semiconductor device having the constant voltage generating circuit having the comparison circuit for controlling the operation of the output driver, the above-described divided resistor circuit is provided. As described above, according to the semiconductor device of the present invention, the fluctuation of the resistance value after the trimming process can be eliminated, and the accuracy of the output voltage of the divided resistor circuit can be improved. It is possible to improve the stability of the output voltage of the live circuit.

  Further, in the method of manufacturing a semiconductor device, in order to perform laser trimming stably and accurately in the region where the trimming window opening is formed, and from the viewpoint of the reliability of the semiconductor device, the bottom of the trimming window opening and the fuse element It is required to leave an insulating film having an appropriate thickness in between. In general, when the degree of integration of a semiconductor circuit increases and a multilayer wiring is formed, it becomes difficult to stably form the film thickness of the insulating film on the polysilicon of the fuse element in the opening of the fuse element. There is a problem that it is difficult to control the remaining film thickness of the film.

  In the method of manufacturing a semiconductor device according to claim 20, since the insulating film is used as an etching stopper layer, the insulating film is provided between the bottom of the trimming window opening formed in the semiconductor substrate and the fuse element. The film thickness can be stabilized and remain. As a result, the trimming process can be carried out with stable accuracy even in the case of multilayer wiring.

  In the conventional method of manufacturing a semiconductor device in which a chip here is cut out from a silicon wafer using a dicing saw, when dicing is performed, as shown in FIG. There has been a problem that the crack) is increased and the bending stress of the chip is lowered. Further, in the wafer level CSP, the chip back surface is engraved on the back surface of the chip, and the back surface of the chip becomes the front surface side when mounted.

In the method of manufacturing a semiconductor device according to claim 21, since the wafer-like semiconductor substrate is separated into pieces simultaneously with the formation of the trimming window opening using anisotropic etching, a cut-out chip (semiconductor Occurrence of chipping and cracking of the apparatus) can be prevented.
Further, in the conventional chip singulation, the shape of the chip was rectangular because it was cut out in the vertical and horizontal directions by dicing technology, but according to the method for manufacturing a semiconductor device of the present invention, chip singulation is performed by etching. Thus, the chip shape can be processed into an arbitrary shape.

  23. The method of manufacturing a semiconductor device according to claim 22, wherein the tape material is attached to the surface of the semiconductor wafer on the main surface side of the semiconductor substrate, the back surface of the semiconductor wafer is polished, and the semiconductor wafer is attached to the tape material. Since the trimming window opening is formed in the attached state, the thinned semiconductor wafer after polishing is supported by the tape material, so that it can be easily transported and the chip thickness can be reduced. Furthermore, when the semiconductor wafer is separated into pieces at the same time as the trimming window opening is formed, the dicing tape used in the prior art becomes unnecessary, and therefore waste in the manufacturing process can be reduced.

  In the method for manufacturing a semiconductor device according to claim 23, before forming the trimming window opening, the thickness of the semiconductor substrate in the vicinity of the trimming window opening formation planned region is made thinner than other regions. Since the process is included, it is possible to prevent the misalignment between the trimming window opening and the fuse element due to the thickness of the semiconductor substrate when the trimming window opening is formed. As a result, the fuse element can be reliably cut when the fuse element is cut by laser irradiation. Furthermore, by forming the thickness in the vicinity of the trimming window opening thinner than other areas, the state where the sealing material filled in the trimming window opening in the subsequent process protrudes from the back surface of the semiconductor substrate is eliminated. It is possible to improve the reliability by preventing the sealing material from mechanically peeling off.

  25. A method of manufacturing a semiconductor device according to claim 24, wherein a silicon substrate is used as the semiconductor substrate, and a recess is formed in the silicon substrate in a region in the vicinity of the region where the trimming window opening is to be formed by silicon crystal plane anisotropic etching. Since the thickness of the region near the trimming window opening formation planned region is made thinner than other regions, the depth of the recess, that is, the thickness of the silicon substrate in the trimming window opening formation planned region is as follows. With good controllability, the area near the trimming window opening can be formed thinner than other areas.

  A method of manufacturing a semiconductor device according to claim 25 is the method of manufacturing a semiconductor device according to claim 20, wherein before the recess is formed, a region corresponding to the bottom of the recess is mainly formed with respect to the silicon substrate. Since the step of introducing boron from the surface side is included, the region into which boron has been introduced can be used as an etching stopper region, and the depth of the recess, that is, the thickness of the silicon substrate in the region where the trimming window opening is to be formed Controllability can be improved.

  27. The method of manufacturing a semiconductor device according to claim 26, wherein in the manufacturing method according to claim 19, silicon oxide is used as the semiconductor substrate on the main surface side of the silicon substrate, at least in the vicinity of a region where a trimming window opening is to be formed. Using an epitaxial growth layer formed through a film, using the silicon oxide film as an etching stopper layer, an opening is formed in the silicon substrate in the vicinity of the region where the trimming window opening is to be formed, and the trimming window Since the thickness of the area near the opening formation planned area is made thinner than other areas, the thickness of the silicon substrate in the trimming window opening formation planned area can be controlled by controlling the thickness of the epitaxial growth layer. Can be improved.

  In a method of manufacturing a semiconductor device according to a twenty-seventh aspect, in the manufacturing method according to the twenty-second aspect, the opening is formed in the silicon substrate by crystal plane anisotropic etching of silicon. Overetching and underetching when the opening is formed in the silicon substrate can be prevented.

  In a method of manufacturing a semiconductor device according to a twenty-eighth aspect, in the manufacturing method according to the twenty-third aspect, an opening is formed in a region corresponding to a trimming window opening forming region of the silicon oxide film as the semiconductor substrate. Since the silicon crystal plane is anisotropically etched, the opening in the silicon substrate and the trimming window opening in the epitaxial growth layer are continuously formed. The manufacturing process can be shortened compared with the case where the formation of the opening in the substrate and the formation of the trimming window opening in the epitaxial growth layer are performed in separate processes.

  30. The method of manufacturing a semiconductor device according to claim 29, comprising the step of forming a marking by laser irradiation on the back surface of the semiconductor substrate when the fuse element is irradiated with laser through the trimming window opening. Therefore, in the cutting process of the fuse element by laser irradiation, for example, a marking recording information such as lot information and product information can be formed, and the manufacturing time can be shortened.

  A method of manufacturing a semiconductor device according to a thirty-third aspect includes a step of sealing the trimming window opening. For example, in the method of manufacturing a semiconductor device according to the thirty-first aspect, the trimming window opening As an example of the means for sealing, the trimming window opening is filled with a resin material, so that it is possible to prevent a short circuit due to foreign matter mixing in the cut fuse element, and further, a fuse due to moisture absorption or oxidation Corrosion around the element formation region can be prevented, and reliability can be improved.

  1A and 1B are diagrams showing an embodiment of a semiconductor device, in which FIG. 1A is a cross-sectional view showing a fuse element and a metal electrode pad portion where a fuse element is not cut, and FIG. Sectional drawing which shows the fuse element and metal electrode pad part of a part is shown.

  A base insulating film 3 made of, for example, a silicon oxide film is formed on a silicon substrate (semiconductor substrate) 1 having a thickness of 50 to 200 μm. The film thickness of the base insulating film 3 is, for example, 0.5 to 0.8 μm. A polysilicon film 5 such as a gate electrode or a resistor and a fuse element 7 made of a polysilicon film are formed on the base insulating film 3. An interlayer insulating film 9 made of, for example, a BPSG film is formed on the entire surface of the silicon substrate 1 including the formation region of the polysilicon film 5 and the fuse element 7. A connection hole 11 is formed in the interlayer insulating film 9 corresponding to the polysilicon film 5, and a connection hole (not shown) is formed corresponding to the fuse element 7.

  A metal wiring layer 13 and a metal electrode pad 15 made of, for example, an Al—Si alloy (Si: 1 w% (mass percent)) are formed on the interlayer insulating film 9 and in the connection hole 11. In FIG. 1B, the fuse element 7 is cut. Although only one fuse element 7 is shown in each of FIGS. 1A and 1B, a plurality of fuse elements 7 are formed in other regions of the silicon substrate 1.

On the interlayer insulating film 9, for example, a passivation film made of a PSG film 17 having a thickness of 0.4 μm in the lower layer and a SiN film 19 having a thickness of 1.2 μm in the upper layer is formed. Further thereon, a polyimide film 21 having a film thickness of, for example, 5.3 μm is formed. Instead of the polyimide film 21, for example, a film made of polybenzoxazole (Sumiresin CRC-8300 (product of Sumitomo Bakelite Co., Ltd.)) may be used.
In the PSG film 17, the SiN film 19, and the polyimide film 21, pad openings 23 are formed corresponding to the metal electrode pads 15.

  A second metal wiring layer 25 and a second metal electrode pad 27 made of, for example, an Al—Si alloy (Si: 1 w%) are formed on the polyimide film 21 and in the pad opening 23. On the second metal wiring layer 25 and the second metal electrode pad 27, for example, a barrier metal layer composed of Ti layer / Ni layer / Ag layer (thickness: 0.1 μm / 0.4 μm / 0.1 μm) in order from the lower layer. 33 is formed.

  A polyimide film 29 having a film thickness of, for example, 25 μm is formed on the polyimide film 21 including the second metal wiring layer 25. The polyimide film 29 constitutes a final protective film. Instead of the polyimide film 29, for example, a film made of polybenzoxazole (Sumiresin CRC-8300 (product of Sumitomo Bakelite Co., Ltd.)) may be used.

  A second pad opening 31 is formed in the polyimide film 29 corresponding to the second metal electrode pad 27. An external connection terminal 35 made of, for example, solder is formed on the second metal electrode pad 27 via a barrier metal layer 33. The external connection terminal 35 is provided with a tip portion protruding from the surface of the polyimide film 29.

A trimming window opening 37 is formed in the silicon substrate 1 so as to penetrate from the back surface 1 b to the main surface 1 a corresponding to the formation region of the fuse element 7.
The base oxide film 3 remains between the bottom of the trimming window opening 37 corresponding to the uncut fuse element 7 and the fuse element 7 (see FIG. 1A). The underlying oxide film 3 at a position corresponding to the cut fuse element 7 is removed at the same time when the fuse element 7 is cut and does not exist (see FIG. 1B).

  A sealing resin 39 is filled in the trimming window opening 37. Examples of the material of the sealing resin 39 include an epoxy resin (CEL-C-3140 (manufactured by Hitachi Chemical Co., Ltd.)).

  FIG. 2 is a flowchart showing an embodiment of a method for manufacturing a semiconductor device. 3 to 5 are sectional views of the steps. Hereinafter, in the drawings, the silicon wafer is given the same reference numeral as the semiconductor substrate.

(1) A base insulating film 3 is formed on the main surface 1 a of the silicon wafer 1. A polysilicon film 5 and a fuse element 7 are formed on the base insulating film 3. A BPSG film as an interlayer insulating layer 9 is formed on the base insulating film 3. A connection hole 11 is formed in the interlayer insulating layer 9, and the interlayer insulating layer 9 and the base insulating film 3 on the isolation region for dividing the chip from the silicon wafer are selectively removed.

  A metal material layer is formed on the entire surface of the silicon wafer 1 by depositing an Al—Si alloy (Si: 1 w%) to a thickness of 3 μm, for example, by sputtering, and the metal material layer is formed by photolithography and etching techniques. The metal wiring layer 13 and the metal electrode pad 15 are formed by patterning.

  For example, a PSG film 17 is formed to a thickness of 0.4 μm on the entire surface of the silicon wafer 1 by CVD (chemical vapor deposition), and a SiN film 19 is further formed to a thickness of 1.2 μm thereon. To form a passivation film. Further thereon, for example, a positive photosensitive polyimide material layer is formed to a thickness of 5.3 μm by spin coating. Openings are formed in the positive photosensitive polyimide material layer corresponding to the metal electrode pad 15 and the separation region by exposure and development processing. Thereafter, a polyimide curing process at 320 ° C. is performed to form the polyimide film 21.

  Using the polyimide film 21 as a mask, the SiN film 19 and the PSG film 17 are etched to form pad openings 23 in the PSG film 17, the SiN film 19 and the polyimide film 21 on the metal electrode pad 15, and the PSG film in the isolation region 17. The SiN film 19 is removed (see FIG. 2 (Step S1) and FIG. 3A).

(2) A second metal wiring layer 25 and a second metal electrode pad 27 are formed on the polyimide film 21 and in the pad opening 23. A barrier metal layer 33 is formed on the upper surface of the second metal wiring layer 25 and the upper surface of the second metal electrode pad 27 (see FIG. 2 (step S2) and FIG. 3B).

  The material of the second metal wiring layer 25 and the second metal electrode pad 27 is, for example, an aluminum alloy layer (Al—Si alloy (Si: 1 w%), Al—Si—Cu alloy (Si: 1 w%, Cu: 0.5 w). %), Al-Cu (Cu: 1 w%), Al-Cu (Cu: 2 w%), etc.) and copper.

  When an Al—Si alloy (Si: 1 w%) is used as the material for the second metal wiring layer 25 and the second metal electrode pad 27, an aluminum alloy layer made of an Al—Si alloy (Si: 1 w%) is formed by sputtering. A barrier metal layer 33 comprising a Ti layer / Ni layer / Ag layer (film thickness: 0.1 μm / 0.4 μm / 0.1 μm) is formed thereon by sputtering or vapor deposition. Film. A resist pattern corresponding to the wiring pattern is formed by resist coating, exposure by photolithography and development. The barrier metal layer 33 is selectively removed by wet etching, and the aluminum alloy layer is selectively removed by dry etching to complete the second metal wiring layer 25 and the second metal electrode pad 27. After the etching, the resist pattern is removed with a plasma asher. The barrier metal layer 33 may be another metal material, and examples thereof include Ti layer / Ni layer / Au layer, Ni layer / Pd layer / Au layer, and the like.

  When copper is used for the material of the second metal wiring layer 25 and the second metal electrode pad 27, chromium is prevented to have a thickness of 0.1 μm and copper is reduced to 0 μm by sputtering to prevent copper migration and improve adhesion. Sequentially formed with a film thickness of 0.5 μm. A resist pattern corresponding to the wiring pattern is formed by resist coating, exposure by photolithography and development. By electrolytic plating, a copper wiring is formed to a film thickness of 5 μm, and further a nickel film of 3 μm, palladium of 0.5 μm and gold of 1 μm are sequentially formed thereon to form a barrier metal layer 33. . After removing the resist pattern with an asher, the portion of chromium and copper where the copper wiring is not formed is removed by wet etching to complete the second metal wiring layer 25 and the second metal electrode pad 27.

(3) For example, a negative photosensitive polyimide material layer is applied and formed with a film thickness of 25 μm by spin coating (see FIG. 2 (step S3)).

(4) A negative photosensitive polyimide material layer excluding the second pad opening formation region and the separation region by performing an exposure process using a reticle having a light shielding portion corresponding to the second pad opening formation region and the separation region. Irradiate light. A development process is performed to form a second pad opening 31 corresponding to the formation region of the second metal electrode pad 27 in the negative photosensitive polyimide material layer, and the negative photosensitive polyimide material layer in the separation region is removed. . Thereafter, a polyimide curing process is performed at 320 ° C. to form a polyimide film 29 (see FIG. 2 (step S4) and FIG. 3C).

(5) After the cream solder is deposited to a thickness of 300 μm corresponding to the position of the second pad opening 31 by the screen printing method, it is heated for 10 seconds at a temperature of 260 ° C. by a heat melting method using an infrared reflow furnace. Thus, the external connection terminal 35 is formed. Thereafter, the flux used in the screen printing method is removed with a dedicated cleaning solution, washed with water and dried (see FIG. 2 (step 5) and FIG. 3 (d)).

  The subsequent steps will be described with reference to FIGS. 4 and 5, the insulating layer and the metal wiring layer formed in the above steps (1) to (5) are not shown, and are shown as an integrated silicon wafer 1. The illustration of the grooves provided in the polyimide film 29 corresponding to the separation regions is omitted.

(6) A wafer test is performed by bringing the test pins 36 into contact with the external connection terminals 35. As a result, the fuse element to be cut for each chip is determined, and data is stored for each chip (see FIG. 2 (step S6) and FIG. 4E).

(7) A surface protection tape (for example, based on PET (polyethylene terephthalate) or polyolefin) 41 is affixed to the surface 1a of the silicon wafer 1 on the side where the external connection terminals 35 are formed. . Here, as the surface protective tape 41, for example, a tape that is cured by irradiation with ultraviolet rays and loses adhesive force is used (see FIG. 4F).
The back surface 1b of the silicon wafer 1 is grind-polished so that the thickness of the silicon wafer 1 is, for example, 50 to 200 μm (see FIG. 2 (step 7) and FIG. 4 (g)).

(8) After polishing the back surface 1b of the silicon wafer 1, a photoresist 43 is applied on the back surface 1b by spin coating in a state where the surface protection tape 41 is left without being peeled off (see FIG. 4H).
Using the IR aligner IR infrared transmission type alignment function or the front and back alignment function by image recognition, alignment with the trimming window opening forming region and the separation region of the silicon wafer 1 is performed, and the photoresist 43 is exposed and developed. Then, as shown in FIG. 6, the opening 45 is formed corresponding to the trimming window opening forming region, and the opening 47 is formed in the photoresist 43 corresponding to the separation region (see FIG. 5 (i)). ). The dimension of the opening 45 is, for example, 5 × 5 μm, and the width dimension of the opening 47 is, for example, 1 to 10 μm. The photoresist 43 has rounded corners corresponding to the shape of the chip formation region when viewed from the upper surface side (see FIG. 6).

With the surface protection tape 41 left, for example, the silicon wafer 1 is silicon with an anodic-coupled parallel plate dry etching apparatus (ICP (Inductive Coupled Plasma) etcher) with the back surface 1b facing the plasma chamber. Etching of the wafer 1 is performed. A reaction gas in which SF ₆ (sulfur hexafluoride) and C ₄ F ₈ (perfluorocyclobutane) are mixed at a rate of 110 cc and 100 cc, respectively, is caused to flow from the inlet, and the reaction chamber is maintained at a pressure of 2.1 Pa. A 600 W high frequency power is applied for 5.5 seconds to cause a physicochemical reaction or the like between the exposed silicon to be processed and radicals or reactive gas ions remaining in the plasma. Silicon is removed from the workpiece. Next, SF ₆ is stopped, 190 cc of C ₄ F ₈ is flowed, the pressure in the reaction chamber is maintained at a pressure of 1.6 Pa, 600 W of high frequency power is applied to the coil for 5 seconds, and the groove or hole from which silicon is removed is removed. A reaction product is adhered to the side wall. Etching proceeds anisotropically while repeating the steps of 5.5 seconds and 5.0 seconds while the reaction product becomes an etching mask on the side wall of the groove or hole.

  In this plasma etching process, the base oxide film 3 functions as an etching stopper layer in the trimming window opening formation region, and the etching is stopped by the surface protection tape 41 in the separation region. As a result, the trimming window opening 37 is formed corresponding to the formation region of the fuse element, and the silicon wafer 1 is divided into individual chips 4 (see FIG. 2 (step S8) and FIG. 5 (j)).

  The photoresist 43 is removed by an asher (see FIG. 5 (k)). FIG. 7 is an enlarged cross-sectional view showing a state in which the trimming window opening 37 is formed and the silicon wafer 1 is divided into individual chips 4.

(9) Based on the wafer test result in the above step (6), a predetermined fuse element is irradiated with laser using an IR aligner to perform a trimming process (see FIG. 2 (step S9)). FIG. 8 is an enlarged cross-sectional view showing a state where the fuse element 7 is cut. At this time, laser marking for chip identification is performed on the back surface 1b. In laser marking, an IR aligner is used, and printing (not shown) is provided on the back surface 1b corresponding to each chip formation region.

(10) The sealing resin 39 is filled into the trimming window opening 37 of the silicon wafer 1 after the laser trimming process (see FIG. 2 (step S10) and FIG. 5 (l)).
1 and 5L, the sealing resin 39 is filled up to the bottom of the trimming window opening 37 (on the main surface 1a side of the silicon wafer 1), but the present invention is not limited to this. It is sufficient that at least the portion on the back surface 1b side of the trimming window opening 37 is sealed.

(11) The main surface 1a side of the silicon wafer 1 is irradiated with ultraviolet rays by an ultraviolet irradiator to eliminate the adhesive force of the surface protection tape 41. The chip 4 is pushed up by the pickup needle 49, and the chip 4 separated is taken out (see FIG. 2 (step S11) and FIG. 5 (m)).

  In this embodiment, the trimming window opening 37 is not formed in the insulating film on the main surface of the semiconductor substrate, but after the polyimide film 29 as the final protective film is formed (see step (4)). That is, after the assembly process is completed, the trimming window opening 37 is formed from the back surface 1b side of the silicon wafer 1 (see process (8)). Since the laser trimming process (see step (9)) is performed through the trimming window opening 37, there is no step of forming a final protective film after the trimming process as in the prior art. For example, the resistance value is adjusted. In the analog IC that performs the cutting by cutting the fuse element, it is possible to eliminate the fluctuation of the resistance value after the trimming process and to improve the accuracy of the electrical characteristics. Furthermore, when trimming is performed in accordance with the customer's request, the work period from order receipt to shipping can be shortened.

  Further, in this embodiment, since the base insulating film 3 is used as an etching stopper layer when forming the trimming window opening 37 in the step (8) (see FIG. 7), the bottom of the trimming window opening 37 is formed. And the fuse element 7 can be left with a stable film thickness of the insulating film. As a result, the trimming process can be carried out with stable accuracy even in the case of multilayer wiring.

  Furthermore, in this embodiment, after the surface protective tape 41 is attached to the front surface 1a of the silicon wafer 1 in the step (7), the back surface 1b of the silicon wafer 1 is polished, and in the step (8), the silicon wafer Since the trimming window opening 37 is formed with 1 attached to the surface protection tape 41, the thinned silicon wafer 1 after polishing is supported by the surface protection tape 41, so that it is easy to transport, The chip 4 can be made thin.

  Furthermore, in this embodiment, since the silicon wafer 1 is separated into pieces at the same time as the formation of the trimming window opening 37 in the step (8), chipping of the cut-out chip 4 and generation of cracks can be prevented. it can. Furthermore, since the dicing tape used in the prior art becomes unnecessary, it is possible to reduce waste in the manufacturing process.

  Further, in the conventional chip singulation, the shape of the chip was rectangular because it was cut out in the vertical and horizontal directions by the dicing technique, but according to this embodiment, the chip 4 can be singulated by etching. The formed shape can be processed into an arbitrary shape.

FIG. 9 is a plan view showing the chip 4 taken out, (A) shows the top surface, and (B) shows the back surface.
As for the formation shape of the silicon substrate 1 and the polyimide film 29 that form the outer shape of the chip 4 taken out, the corner portions 30 are rounded. Thereby, the occurrence of chipping and cracks during the conveyance of the chip can be prevented, and the appearance defect can be reduced and the reliability can be improved.

  On the back surface 1b of the chip 4, a laser marking 51 is formed by laser irradiation at the same time as the laser trimming process in the step (9) (see (B)). In the laser marking 51, for example, information such as lot information and product information is recorded. By printing the laser marking 51 simultaneously with the laser trimming process, the manufacturing time can be shortened.

  Further, in this embodiment, since the trimming window opening 37 is sealed with the sealing resin 39, it is possible to prevent a short circuit due to foreign matter contamination in the cut fuse element 7 (see FIG. 1B). Furthermore, corrosion around the fuse element formation region due to moisture absorption or oxidation can be prevented, and reliability can be improved.

10A and 10B are diagrams showing another embodiment of the semiconductor device, where FIG. 10A is a plan view and FIG. 10B is a side view. The same parts as those in FIGS. 1 and 9 are denoted by the same reference numerals, and description thereof will be omitted.
A plurality of dots 53 made of concave portions are formed on the surface 1 b of the silicon substrate 1, and markings are formed by the dots 53.

  FIG. 11 is a process cross-sectional view showing a part of another embodiment of the semiconductor device manufacturing method. In this embodiment, the chip shown in FIG. 10 is manufactured. Step (1) to step (7) are substantially the same as the embodiment described with reference to FIGS. Hereinafter, this embodiment will be described from step (8).

(8) The silicon wafer 1 having the photoresist 43 formed on the back surface 1b is aligned with the trimming window opening forming region and the separation region of the silicon wafer 1 using the IR aligner, and the photoresist 43 is exposed and developed. Then, an opening (not shown) is formed corresponding to the trimming window opening formation region, an opening 47 is formed in the photoresist 43 corresponding to the separation region, and marking dots 53 (see FIG. 10). The opening 55 is formed corresponding to (see FIG. 11I). The size of each opening 55 is, for example, the size of the resolution limit of photolithography. Further, the photoresist 43 has rounded corners corresponding to the shape of the chip formation region when viewed from the upper surface side.

(9) With the surface protection tape 41 left, the silicon wafer 1 is etched in the same manner as in the step (8) described with reference to FIG. As a result, a trimming window opening (not shown) is formed, the silicon wafer 1 in the separation region corresponding to the opening 47 is selectively removed, and the silicon wafer 1 is divided into individual chips 4 and the openings are opened. Corresponding to the portion 55, a dot 53 made of a recess is formed on the back surface 1 b of the silicon wafer 1. Since the size of the opening 55 is small, the etching rate of the silicon wafer 1 in the area corresponding to the opening 55 corresponding to the trimming window opening and the opening 55 corresponding to the separation area is slower than the area corresponding to the opening 47. Therefore, the dots 53 do not penetrate the silicon wafer 1 (see FIG. 11J).

(10) The photoresist 43 is removed by an asher.
Based on the wafer test result in the step (6) described with reference to FIG. 4E, a predetermined fuse element is irradiated with laser using an IR aligner to perform a trimming process. At this time, laser marking may be performed on a region different from the trimming window opening (not shown) and the recess 53 on the back surface 1b.
A sealing resin (not shown) is filled in the opening portion of the trimming window of the silicon wafer 1 after the laser trimming process. (See FIG. 11 (k)).

(11) The main surface 1a side of the silicon wafer 1 is irradiated with ultraviolet rays by an ultraviolet irradiator to eliminate the adhesive force of the surface protection tape 41. The chip 4 is pushed up by the pick-up needle 49, and the chip 4 separated is taken out (see FIG. 11 (l)).

  In this way, the trimming window opening is formed and the chip 4 is cut out by using the photoresist 43 having the marking forming opening 55 in the formation area of the chip 4 as a mask, thereby forming the trimming window opening. Simultaneously with the cutting of the chip 4, for example, information such as lot information and product information can be recorded on the marking made of the dots 53, and the marking printing process can be eliminated.

  12A and 12B are diagrams showing still another embodiment of the semiconductor device, where FIG. 12A is a plan view and FIG. 12B is a side view. The same parts as those in FIGS. 1 and 9 are denoted by the same reference numerals, and description thereof will be omitted.

  On one side surface of the chip 4, a bar code 57 having an uneven shape is formed. In the barcode 57, for example, information such as lot information and product information is recorded.

  Other embodiments of the semiconductor device manufacturing method for manufacturing this chip are substantially the same as the embodiments described with reference to FIGS. The difference is that, in the step (8) described with reference to FIG. 5 (i), in addition to the openings 45 and 47, an uneven shape corresponding to the barcode 57 is formed in the photoresist 43. . Thereafter, the silicon wafer 1 is selectively removed using the photoresist 43 having a concavo-convex shape corresponding to the barcode 57 as a mask, thereby simultaneously forming the trimming window opening 37 and cutting out the chip 4, A bar code 57 having an uneven shape can be formed on the side surface. Further, in the laser trimming process in step (9) described with reference to step S9 in FIG. 2, laser marking for chip identification on the back surface 1b of the silicon wafer 1 may or may not be performed. .

  13A and 13B are diagrams showing still another embodiment of the semiconductor device, where FIG. 13A is a plan view and FIG. 13B is a side view. The same parts as those in FIGS. 1 and 9 are denoted by the same reference numerals, and description thereof will be omitted.

  The corner portion 30a closest to the position of one pin, which is one of the external connection terminals 35, is formed with a larger roundness than the other three corner portions 30b. Thereby, the position of 1 pin can be recognized from the size of the corner portions 30a and 30b.

  Other embodiments of the semiconductor device manufacturing method for manufacturing this chip are substantially the same as the embodiments described with reference to FIGS. The difference is that when the openings 45 and 47 are formed in the photoresist 43 in the step (8) described with reference to FIG. 5 (i), the corners of the photoresist 43 in the regions corresponding to the corner portions 30a are different. The opening 47 is formed so that the roundness is larger than the corner of the photoresist 43 in the region corresponding to the corner 30b. Thereafter, the silicon wafer 1 is selectively removed using the photoresist 43 having a different corner roundness as a mask, whereby the corner 30a is rounded simultaneously with the formation of the trimming window opening 37 and the cutting of the chip 4. The chip 4 having a size larger than that of the other three corner portions 30b can be formed. Further, in the laser trimming process in step (9) described with reference to step S9 in FIG. 2, laser marking for chip identification on the back surface 1b of the silicon wafer 1 may or may not be performed. .

  In the above embodiment, the semiconductor device of the present invention is applied to the wafer level CSP. However, the present invention is not limited to this, and a fuse element is provided on the main surface of the semiconductor substrate via an insulating film. The present invention can be applied to any semiconductor device as long as it is a semiconductor device.

  In the above embodiment, the trimming window opening 37 is sealed with the sealing resin 39. However, the present invention is not limited to this, and other methods such as the back surface 1b of the silicon substrate 1 are used. The trimming window opening 37 may be sealed by forming an insulating film or the like.

  As an example of a semiconductor device including an analog circuit whose electrical characteristics are adjusted by laser trimming to which the present invention is applied, for example, a semiconductor device including a constant voltage generation circuit and a semiconductor device including a voltage detection circuit can be cited. it can.

FIG. 14 is a circuit diagram showing an embodiment of a semiconductor device provided with a constant voltage generating circuit.
A constant voltage generation circuit 63 is provided to stably supply power from the DC power supply 59 to the load 61. The constant voltage generating circuit 63 includes an input terminal (Vbat) 65 to which a DC power supply 59 is connected, a reference voltage generating circuit (Vref) 67, an operational amplifier 69, and a P-channel MOS transistor (hereinafter abbreviated as PMOS) constituting an output driver. 71), dividing resistors R1 and R2, and an output terminal (Vout) 73.

  In the operational amplifier 69 of the constant voltage generating circuit 63, the output terminal is connected to the gate electrode of the PMOS 71, the reference voltage Vref is applied from the reference voltage generating circuit 67 to the inverting input terminal, and the output voltage Vout is applied to the non-inverting input terminal by the resistor R1. And the voltage divided by R2 are applied, and the divided voltage of the resistors R1 and R2 is controlled to be equal to the reference voltage Vref.

FIG. 15 is a circuit diagram showing an embodiment of a semiconductor device provided with a voltage detection circuit.
Reference numeral 69 denotes an operational amplifier. A reference voltage generating circuit 67 is connected to an inverting input terminal of the operational amplifier 69, and a reference voltage Vref is applied. The voltage of the terminal to be measured input from the input terminal (Vsens) 77 is divided by the dividing resistors R1 and R2 and input to the non-inverting input terminal of the operational amplifier 69. The output of the operational amplifier 69 is output to the outside through an output terminal 79.

  In the voltage detection circuit 75, when the voltage of the terminal to be measured is high and the voltage divided by the dividing resistors R1 and R2 is higher than the reference voltage Vref, the output of the operational amplifier 69 maintains the H level, and the terminal to be measured When the voltage divided by the dividing resistors R1 and R2 falls below the reference voltage Vref, the output of the operational amplifier 69 becomes L level.

  In general, in the constant voltage generation circuit shown in FIG. 14 and the voltage detection circuit shown in FIG. 15, the reference voltage Vref from the reference voltage generation circuit fluctuates due to variations in the manufacturing process. The resistance value of the divided resistor is adjusted using a resistance circuit (referred to as a divided resistor circuit) whose resistance value can be adjusted by cutting the fuse element as the divided resistor.

  FIG. 16 is a circuit diagram showing an example of a divided resistor circuit to which the fuse element and the trimming window opening of the present invention are applied. 17 and 18 are layout diagrams showing a layout example of the divided resistor circuit. FIG. 17 shows a layout example of the fuse element portion, and FIG. 18 shows a layout example of the set resistor element portion.

  As shown in FIG. 16, resistance elements Rbottom, m + 1 (m is a positive integer) setting resistance elements RT0, RT1,..., RTm, and resistance element Rtop are connected in series. .., RTm are connected in parallel with fuse elements RL0, RL1,..., RLm corresponding to the respective setting resistance elements.

  As shown in FIG. 17, the fuse elements RL0, RL1,..., RLm are formed of, for example, a polysilicon film having a sheet resistance of 20Ω to 40Ω. These fuse elements correspond to the fuse element 7 of FIG. Although not shown in FIG. 16, trimming window openings 37 (see FIG. 1) are formed in the semiconductor substrate corresponding to the formation regions of the fuse elements.

The values of the set resistor elements RT0, RT1,..., RTm are set so as to increase in binary numbers in order from the resistor element Rbottom side. That is, the resistance value of the set resistance element RTn is 2 ⁿ times the unit value, where the resistance value of the set resistance element RT0 is a unit value.
For example, as shown in FIG. 18, a plurality of polysilicon patterns 81 formed in the same material, in the same direction and with the same dimensions are used, and the set resistance element RT0 is set to one polysilicon pattern 81 as a unit resistance value. The element RTn is composed of 2 ⁿ polysilicon patterns 81. The polysilicon pattern 81 is formed of a high-resistance polysilicon film having a sheet resistance of 100Ω to 10 kΩ by implanting, for example, P-type impurities or N-type impurities.

  In FIGS. 17 and 18, the metal wiring 83 is provided between the symbols A-A, between the symbols BB, between the symbols CC, between the symbols DD, EE, FF, and GG. Are electrically connected. The metal wiring 83 is formed of, for example, an alloy containing 98.5% aluminum, 1% silicon, and 0.5% copper, and has a sheet resistance of 0.04Ω to 0.1Ω.

As described above, in the divided resistor circuit in which the accuracy of the ratio of the resistance pair is important, in order to increase the accuracy of manufacturing in the manufacturing process, a unit resistor composed of a pair of setting resistor elements and a fuse element is connected in series to form a ladder. Arranged in a shape.
In such a divided resistance circuit, a desired series resistance value can be obtained by cutting arbitrary fuse elements RL0, RL1,..., RLm with a laser beam.

  When the divided resistor circuit shown in FIG. 16 is applied to the divided resistors R1 and R2 of the constant voltage generating circuit shown in FIG. 14, for example, the resistor element Rbottom end is grounded and the resistor element Rtop end is connected to the drain of the PMOS 71. Further, the terminal NodeL between the resistance elements Rbottom and RT0 or the terminal NodeM between the resistance elements Rtop and RTm is connected to the non-inverting input terminal of the operational amplifier 69.

  Further, when the divided resistor circuit shown in FIG. 16 is applied to the divided resistors R1 and R2 of the voltage detection circuit shown in FIG. 15, for example, the resistor element Rbottom end is grounded and the resistor element Rtop end is connected to the input terminal 77. . Further, the terminal NodeL between the resistance elements Rbottom and RT0 or the terminal NodeM between the resistance elements Rtop and RTm is connected to the non-inverting input terminal of the operational amplifier 69.

  In the divided resistor circuit to which the fuse element and the trimming window opening of the present invention are applied, the laser trimming process can be performed after the assembly process is completed, and the assembly process is not performed after the trimming process as in the prior art. The accuracy of the output voltage of the divided resistor circuit can be improved. Furthermore, when trimming is performed in accordance with the customer's request, the work period from order receipt to shipping can be shortened.

  Further, in the constant voltage generation circuit 63 having the divided resistor circuit to which the fuse element and the trimming window opening of the present invention shown in FIG. 14 are applied, the output voltages of the divided resistors R1 and R2 constituting the divided resistor circuit are provided. Therefore, the stability of the output voltage of the constant voltage generation circuit 63 can be improved.

  Further, in the voltage detection circuit 75 including the divided resistor circuit to which the fuse element and the trimming window opening of the present invention shown in FIG. 15 are applied, the output voltage of the divided resistors R1 and R2 constituting the divided resistor circuit is reduced. Since the accuracy can be improved, the accuracy of the voltage detection capability of the voltage detection circuit 75 can be improved.

  However, the semiconductor device to which the divided resistor circuit to which the fuse element and the trimming window opening of the present invention are applied is applied is not limited to a semiconductor device having a constant voltage generation circuit and a semiconductor device having a voltage detection circuit. However, any semiconductor device provided with a divided resistor circuit can be applied.

  Further, the semiconductor device to which the fuse element and the trimming window opening of the present invention are applied is not limited to the semiconductor device provided with the dividing resistor circuit, and any semiconductor device provided with the fuse element and the trimming window opening may be used. The present invention can be applied.

  19A and 19B are diagrams showing still another embodiment of the semiconductor device, in which FIG. 19A is a cross-sectional view showing a fuse element and a metal electrode pad portion where the fuse element is not cut, and FIG. 19B is a diagram showing the fuse element. Sectional drawing which shows the fuse element and metal electrode pad part of the cut | disconnected part is shown. FIG. 20 is a plan view showing the entirety of this embodiment, where (A) shows the top surface and (B) shows the back surface. Parts having the same role as in FIGS. 1 and 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the thickness of the silicon substrate 1 is, for example, 400 μm, and the main surface 1a and the back surface 1b of the silicon substrate 1 are (100) planes.
The difference between this embodiment and the embodiment shown in FIGS. 1 and 9 will be described.
A tapered recess 101 is formed in the region near the trimming window opening 37 on the back surface 1b of the silicon substrate 1, and the thickness in the region near the trimming window opening in the silicon substrate 1 is formed thinner than other regions. Yes. The recess 101 is formed by silicon crystal plane anisotropic etching using an alkaline aqueous solution. As shown in FIG. 20B, the recess 101 is formed in common by the plurality of trimming window openings 37. However, the recess 101 may be provided for each trimming window opening 37.

Boron is introduced into the region of the silicon substrate 1 corresponding to the bottom of the recess 101 at a high concentration, for example, at a surface concentration of 7 × 10 ¹⁹ / cm ³ on the main surface 1a side, and the boron high concentration region 103 (refer to the portion shown by embossing) ) Is formed.
For example, the depth of the recess 101 is 350 μm, and the thickness of the silicon substrate 1 at the bottom of the recess 101, that is, the thickness of the boron high concentration region 103 is 5 to 10 μm.

  The trimming window opening 37 is provided in the bottom of the recess 101, that is, in the boron high concentration region 103 of the silicon substrate 1. The end of the sealing resin 39 filled in the trimming window opening 37 on the recess 101 side is provided in the recess 101 and protrudes from the bottom of the recess 101, but protrudes from the back surface 1 b of the silicon substrate 1. Not.

In this embodiment, the silicon substrate 1 is formed by the recess 101 so that the thickness of the region near the trimming window opening 37 is thinner than other regions. Therefore, when the trimming window opening 37 is formed, Misalignment between the trimming window opening 37 and the fuse element 7 due to the thickness can be prevented, and the fuse element can be reliably cut when the fuse element is cut by laser irradiation.
Further, since the thickness of the silicon substrate 1 in the vicinity of the trimming window opening 37 is thinner than the other areas due to the recess 101, the sealing material 39 filled in the trimming window opening 37 is formed on the silicon substrate 1. The state of protruding from the back surface 1b can be eliminated, the sealing material 39 can be prevented from being mechanically peeled off, and the reliability can be improved.

  FIG. 21 is a flowchart showing still another embodiment of a method for manufacturing a semiconductor device. 22 and 23 are process sectional views showing a part of the manufacturing process. This embodiment is for manufacturing the embodiment of the semiconductor device shown in FIGS. FIG. 22 shows a step of forming a recess in a region corresponding to the trimming window opening forming region of the silicon wafer for a plurality of chip forming regions, and FIG. 23 shows a step of forming the trimming window opening.

(1) For example, the silicon wafer 1 having a film thickness of 400 μm is subjected to a thermal oxidation process to form silicon oxide films 105a and 105b having a film thickness of 0.5 μm on the main surface 1a and the back surface 1b. Photoresist 107a and 107b are formed on silicon oxide films 105a and 105b by photolithography. The photoresist 107a on the main surface 1a side has an opening corresponding to the region corresponding to the bottom of the tapered recess formed on the back surface 1b in a later step. No opening is formed in the photoresist 107b on the back surface 1b side, and the silicon oxide film 105b is completely covered with the photoresist 107b. (See FIG. 22 (a)).

(2) The silicon oxide film 105a on the main surface 1a side is selectively removed by the etching technique using the photoresist 107a as a mask to form a region corresponding to the bottom of the tapered recess formed on the back surface 1b in a later step. Correspondingly, an opening is formed. The photoresists 107a and 107b are removed. Boron is introduced into the silicon wafer 1 through the opening provided in the silicon oxide film 105a. In the boron introduction treatment method, for example, a silicon wafer 1 is fixed in a quartz tube by a quartz holder, and a vapor obtained by bubbling BBr ₃ using nitrogen gas as a carrier is introduced into the quartz tube together with oxygen gas. After heat treatment is performed for a predetermined time at a temperature of 1100 to 1150 ° C., the silicon wafer 1 is light-etched with a hydrofluoric acid-based etchant, and then drive-in is performed in oxygen gas. As a result, boron is introduced into the silicon wafer 1 in the region corresponding to the bottom of the tapered recess formed on the back surface 1 b in a later step, thereby forming the boron high concentration region 103. The boron high concentration region 103 has, for example, a surface concentration on the main surface 1a side of 7 × 10 ¹⁹ / cm ³ and a diffusion depth of 5 to 10 μm (see FIG. 22B).

(3) After the silicon nitride film is formed on the main surface 1a by the CVD method and the opening of the silicon oxide film 105a is filled, the silicon oxide film 105b on the back surface 1b side is tapered by photolithography and etching techniques. An opening is formed corresponding to the recess formation scheduled region (see FIG. 22C). In FIG. 22C, the silicon oxide film 105a and the silicon nitride film are integrated and denoted by reference numeral 105a.

(4) Crystal plane anisotropic etching is performed on the silicon wafer 1 using a KOH (potassium hydroxide) aqueous solution. Etching of the silicon wafer 1 proceeds along the (111) plane crystal orientation from the back surface 1 b in the opening formation region of the silicon oxide film 105 b and stops at the boron high concentration region 103. Thus, a tapered recess 101 is formed on the back surface 1b of the silicon wafer 1. Thereafter, a nitride film removing process for removing the silicon nitride film formed in the above step (3) and an oxide film removing process for removing the silicon oxide films 105a and 105b are performed, and then potassium is removed by RCA cleaning. (See FIG. 21 (step S21) and FIG. 22 (d)).

  As described above, when the recess 101 is formed, silicon crystal plane anisotropic etching is used, and the boron high-concentration region 103 formed in advance to a desired depth is used as an etching stopper region. That is, the controllability of the thickness of the silicon wafer 1 in the region where the trimming window opening is to be formed can be improved.

(5) In the same manner as in step (1) described with reference to FIG. 3A, the base insulating film 3 and polysilicon are formed on the main surface 1a of the silicon wafer 1 in which the recess 101 is formed on the back surface 1b. The film 5, the fuse element 7, the interlayer insulating layer 9, the connection hole 11, the metal wiring layer 13, the metal electrode pad 15, the PSG film 17, the SiN film 19, the polyimide film 21, and the pad opening 23 are formed (FIG. 21 (step (See S22)).

(6) The second metal wiring layer 25, the second metal electrode pad 27, and the barrier metal layer 33 in the same manner as the steps (2) and (3) described with reference to FIGS. 3B and 3C. (Refer to FIG. 21 (Step S23)), and apply and form a negative photosensitive polyimide material layer with a film thickness of 25 μm (refer to FIG. 21 (Step S24)), corresponding to the second pad opening 31 and the separation region. A polyimide film 29 having a groove to be formed is formed (see FIG. 21 (step S25)).

  The subsequent steps will be described with reference to FIG. In FIG. 23, illustration of the insulating layer and the metal wiring layer formed in the above steps (5) and (6) is omitted, and the silicon wafer 1 is shown integrally. Further, the illustration of the grooves provided in the polyimide film 29 corresponding to the separation regions and the boron high concentration region 103 is omitted.

(7) A photoresist 43 is applied on the back surface 1b of the silicon wafer 1 by spin coating. Using the IR aligner IR infrared transmission type alignment function or the front and back alignment function by image recognition, alignment with the trimming window opening formation region of the silicon wafer 1 is performed, and the photoresist 43 is exposed and developed to form a recess. An opening 45 is formed in the 101 forming region and corresponding to the trimming window opening forming region (see FIG. 23E). The dimension of the opening 45 is, for example, 5 × 5 μm.

(8) For example, the silicon wafer 1 is etched using an ICP etcher with the back surface 1b of the silicon wafer 1 facing the plasma chamber. A reaction gas in which SF ₆ and C ₄ F ₈ are mixed at a rate of 110 cc and 100 cc, respectively, is caused to flow from the inlet, the reaction chamber is maintained at a pressure of 2.1 Pa, and 600 W of high frequency power is applied to the coil for 5.5 seconds. The silicon is removed from the processed portion of the silicon wafer 1 by causing a physicochemical reaction or the like between the exposed silicon in the processed portion and the radicals or reactive gas ions remaining in the plasma. Next, SF ₆ is stopped, 190 cc of C ₄ F ₈ is flowed, the pressure in the reaction chamber is maintained at a pressure of 1.6 Pa, 600 W of high frequency power is applied to the coil for 5 seconds, and the groove or hole from which silicon is removed is removed. A reaction product is adhered to the side wall. Etching proceeds anisotropically while repeating the steps of 5.5 seconds and 5.0 seconds while the reaction product becomes an etching mask on the side wall of the groove or hole.

  In this plasma etching process, the base oxide film 3 functions as an etching stopper layer in the trimming window opening formation region, and the etching stops. As a result, the trimming window opening 37 is formed in the silicon wafer 1 (boron high concentration region 103) corresponding to the formation region of the fuse element 7 (see FIG. 21 (step S26) and FIG. 23 (f)). Thereafter, the photoresist 43 is removed by an asher (see FIG. 23G). FIG. 24 is an enlarged cross-sectional view showing a state in which the trimming window opening 37 is formed in the boron high concentration region 103 of the silicon wafer 1.

  In this trimming window opening forming step, the silicon wafer 1 is formed with a recess 101 in the vicinity of the trimming window opening forming area and is made thinner than the other areas, so that the trimming window opening 37 is formed. At this time, the misalignment between the trimming window opening 37 and the fuse element 7 due to the thickness of the silicon wafer 1 can be prevented. As a result, the fuse element 7 can be reliably cut when the fuse element 7 is cut by laser irradiation in a later step.

(9) The external connection terminal 35 is formed in the same manner as the above-described step (4) described with reference to FIG. 3D (see FIG. 21 (step 27)), and with reference to FIG. A wafer test is performed in the same manner as the above-described step (5) (see FIG. 21 (step S28)).

(10) Based on the wafer test result in the step (9), a predetermined fuse element is irradiated with laser using an IR aligner to perform trimming processing (see FIG. 21 (step S29)). FIG. 25 is an enlarged sectional view showing a state where the fuse element 7 is cut. At this time, laser marking for chip identification is performed on the back surface 1b. In laser marking, an IR aligner is used, and printing (not shown) is provided on the back surface 1b corresponding to each chip formation region.

(11) The sealing resin 39 is filled into the trimming window opening 37 of the silicon wafer 1 after the laser trimming process (see FIG. 21 (step S30)).
In FIG. 19, the sealing resin 39 is filled up to the bottom of the trimming window opening 37 (the main surface 1a side of the silicon wafer 1), but the present invention is not limited to this, and at least the trimming window opening What is necessary is just to be the state by which the part by the side of the back surface 1b of 37 is sealed. Further, instead of sealing each trimming window opening 37, for example, the recess 101 may be filled with a sealing material so that the plurality of trimming window openings 37 are collectively sealed.

(12) A dicing tape is attached to the main surface 1a side of the silicon wafer 1, and chips are separated into pieces by a dicing technique (see FIG. 21 (step S31)). Here, chip singulation may be performed using a dry etching technique or a dicing saw. Here, the chips are separated into pieces using a dry etching technique, and the corners of the chips 4 are rounded (see FIG. 20).

  Further, when the chip is separated using the dry etching technique, the back surface 1b is simultaneously formed with the chip individualization at the same time as the chip individualization at the same time as the chip individualization. Marking may be formed with dots made of recesses, or a bar code 57 having a concavo-convex shape may be formed on one side surface of the chip 4 as in the embodiment described with reference to FIG. Similarly to the embodiment described with reference to FIG. 12, the roundness of the corner portion of the chip 4 may be made different so that the position of the pin 1 can be recognized.

(13) After eliminating the adhesive force of the dicing tape of the silicon wafer 1, the chip is pushed up by the pick-up needle and the separated chip is taken out (see FIG. 21 (step S31)).

  In this embodiment, the trimming window opening 37 is not formed in the insulating film on the main surface of the semiconductor substrate, but after the polyimide film 29 as the final protective film is formed (see step (5)). A trimming window opening 37 is formed from the back surface 1b side of the silicon wafer 1 (see step (8)). Since the laser trimming process (see step (10)) is performed through the trimming window opening 37, there is no step of forming a final protective film after the trimming process as in the prior art. For example, the resistance value is adjusted. In the analog IC that performs the cutting by cutting the fuse element, it is possible to eliminate the fluctuation of the resistance value after the trimming process and to improve the accuracy of the electrical characteristics. Furthermore, when trimming is performed in accordance with the customer's request, the work period from order receipt to shipping can be shortened.

  26A and 26B are diagrams showing still another embodiment of the semiconductor device, in which FIG. 26A is a cross-sectional view showing a fuse element and a metal electrode pad portion where the fuse element is not cut, and FIG. Sectional drawing which shows the fuse element and metal electrode pad part of the cut | disconnected part is shown. Portions having the same role as in FIG. 19 are denoted by the same reference numerals, and detailed description thereof is omitted.

The difference between this embodiment and the embodiment shown in FIG. 19 will be described.
In this embodiment, a semiconductor substrate 109 having an epitaxial growth layer 113 formed on the main surface side of a silicon substrate 111 is used instead of the silicon substrate 1 shown in FIG. For example, the thickness of the silicon substrate 111 is 400 μm, and the thickness of the epitaxial growth layer 113 is 5 to 10 μm. The main surface 109a and the back surface 109b of the semiconductor substrate 109 are (100) planes.

  A tapered opening 115 is formed in the region near the trimming window opening 117 of the silicon substrate 111, and the thickness of the region near the trimming window opening of the silicon substrate 109 is formed thinner than other regions. A tapered trimming window opening 117 is formed in a predetermined region of the epitaxial growth layer 113 in the region where the opening 115 is formed. The opening 115 and the trimming window opening 117 are formed by silicon crystal plane anisotropic etching using an alkaline aqueous solution.

  A silicon oxide film 119 remains in the vicinity of the interface between the silicon substrate 111 and the epitaxial growth layer 113 around the opening 115. The film thickness of the silicon oxide film 119 is, for example, 0.5 μm. The silicon oxide film 119 is a silicon oxide film used as a mask for defining an etching stopper layer and a region for forming a trimming window opening when the opening 115 and the trimming window opening 117 are formed by crystal plane anisotropic etching. Part of the film remains.

  As described above, the trimming window opening 117 is provided in the bottom of the opening 115, that is, in the epitaxial growth layer 113. The end of the sealing resin 39 filled in the trimming window opening 117 on the opening 115 side is provided in the opening 115 and protrudes from the bottom of the opening 115, but the back surface 109 b of the semiconductor substrate 109. It does not protrude from.

  In this embodiment, the semiconductor substrate 109 is formed by the opening 115 provided in the silicon substrate 111 so that the thickness in the vicinity of the trimming window opening 117 is thinner than the other regions. When forming, the misalignment between the trimming window opening 117 and the fuse element 7 due to the thickness of the semiconductor substrate 109 can be prevented, and the fuse element can be surely cut when the fuse element is cut by laser irradiation.

  Further, since the thickness of the semiconductor substrate 109 in the vicinity of the trimming window opening 117 is thinner than the other areas by the opening 115, the sealing material 39 filled in the trimming window opening 117 is used as the semiconductor substrate 109. It is possible to eliminate the state of protruding from the back surface 109b of the substrate, and it is possible to prevent the sealing material 39 from being mechanically peeled off, thereby improving the reliability.

  FIG. 27 is a flowchart showing still another embodiment of a method for manufacturing a semiconductor device. FIG. 28 is a process sectional view showing a part of the manufacturing process. This embodiment is for manufacturing the embodiment of the semiconductor device shown in FIG. FIG. 26 shows a process of forming openings and trimming window openings in a semiconductor wafer composed of a silicon substrate and an epitaxial growth layer for a plurality of chip formation regions. In FIG. 28, the same reference numerals as those of the semiconductor substrate 109 are given to the semiconductor wafer.

(1) For example, a silicon oxide film is formed to a thickness of 0.5 μm on the surface of the silicon substrate 111 having a thickness of 400 μm and a front surface and a back surface of (100), and the silicon oxide film is formed by photolithography and etching techniques. Patterning is performed to form a silicon oxide film 119 that covers a region near the region where the trimming window opening is to be formed and has an opening corresponding to the region where the trimming window opening is to be formed. Silicon is epitaxially grown on the surface of the silicon substrate 111 on which the silicon oxide film 119 is formed by the CVD method to form the epitaxial growth layer 113 with a thickness of 5 to 10 μm. Thereby, a semiconductor wafer 109 composed of the silicon substrate 111 and the epitaxial growth layer 113 is formed. Regarding the semiconductor wafer 109, the surface on the epitaxial layer 113 side is a main surface 109a, and the surface on the silicon substrate 111 side is a back surface 109b. The main surface 109a and the back surface 109b are (100) planes of silicon (see FIG. 28A).

(2) After forming the base insulating film 3 on the epitaxial growth layer 113, polysilicon films 121 a and 121 b are formed on the base insulating film 3 and the back surface 109 b of the semiconductor wafer 109. The polysilicon film 121a is for forming a fuse element and a polysilicon wiring in a later process. Silicon oxide films 123a and 123b for masking are formed on the surfaces of the polysilicon films 121a and 121b by CVD. An opening is formed in the silicon oxide film 123b on the back surface 109b side corresponding to the planned formation region of the opening formed in the vicinity of the trimming window formation region by photolithography and etching techniques (see FIG. 28B). ).

(3) Crystal plane anisotropic etching is performed on the semiconductor wafer 109 using a KOH aqueous solution. Etching of the semiconductor wafer 109 proceeds along the (111) plane crystal orientation from the back surface 109b in the opening forming region of the silicon oxide film 123b, and a tapered opening 115 is formed in the silicon substrate 111. Further, in the opening forming region of the silicon oxide film 119, the crystal plane anisotropic etching of the epitaxial growth layer 113 proceeds along the (111) plane crystal orientation, and the trimming window opening 117 is formed. Etching stops at the silicon oxide film 119 in the formation region of the opening 115 and stops at the silicon oxide film 119 in the formation region of the trimming window opening 117. In this way, the opening 115 and the trimming window opening 117 are continuously formed (see FIG. 27 (step S41) and FIG. 28 (c)).
Thus, the manufacturing process can be shortened by continuously forming the opening 115 and the trimming window opening 117.

(4) The silicon oxide film 123a on the polysilicon film 121a is selectively removed by the photolithography technique and the etching technique so as to remain in the region where the resistor made of the polysilicon film is to be formed. At this time, the silicon oxide film 123a in the region where the fuse element 7 is to be formed is removed. Using the remaining silicon oxide film 123a as a mask, phosphorus is deposited at a high concentration in a predetermined region of the polysilicon film 121a by a phosphorus deposition and thermal diffusion process, and the resistance of the polysilicon film 121a is reduced. (See FIG. 28D).

(5) The silicon oxide films 123a and 123b are removed. At this time, the silicon substrate 111 around the opening 115 and the silicon oxide film 119 at the interface of the epitaxial growth layer 113 remain (see FIG. 28E).

(6) The main surface 109a of the semiconductor wafer 109 in which the opening 115 is formed in the back surface 109b in the same manner as the above steps (1) to (4) described with reference to FIGS. 3 (a) to 3 (d). On the underlying insulating film 3, polysilicon film 5, fuse element 7, interlayer insulating layer 9, connection hole 11, metal wiring layer 13, metal electrode pad 15, PSG film 17, SiN film 19, polyimide film 21, pad opening 23, a second metal wiring layer 25, a second metal electrode pad 27, a polyimide film 29, a second pad opening 31, a barrier metal layer 33, and an external connection terminal 35 are formed (see FIG. 27 (step S42)).

(7) A wafer test is performed in the same manner as in step (5) described with reference to FIG. 4E (see FIG. 27 (step S43)). Based on the wafer test result, a predetermined fuse element is obtained. Then, laser irradiation is performed using an IR aligner to perform trimming processing (see FIG. 27 (step S44)). At this time, laser marking for chip identification is performed on the back surface 109b. In laser marking, an IR aligner is used, and printing (not shown) is provided on the back surface 109b corresponding to each chip formation region.

(8) The sealing resin 39 is filled into the trimming window opening 117 of the semiconductor wafer 109 after the laser trimming process (see FIG. 27 (step S45)).
In FIG. 26, the sealing resin 39 is filled up to the bottom of the trimming window opening 117 (on the main surface 109a side of the semiconductor wafer 109). However, the present invention is not limited to this, and at least the trimming window opening. It suffices that the portion on the back surface 109b side of 117 is sealed. Further, instead of sealing every trimming window opening 117, for example, the opening 115 may be filled with a sealing material so as to be collectively sealed by the plurality of trimming window openings 117.

(9) A dicing tape is affixed to the main surface 109a side of the semiconductor wafer 109, and chips are separated by a dicing technique (see FIG. 27 (step S46)). Here, chip singulation may be performed using a dry etching technique or a dicing saw. Here, the chip is separated into pieces using a dry etching technique, and the corners of the chip are rounded. Further, when the chip is separated using the dry etching technique, the back surface 109b is simultaneously formed with the chip individualization simultaneously with the chip individualization as in the embodiment described with reference to FIGS. Marking may be formed with dots made of recesses, or a bar code 57 having a concavo-convex shape may be formed on one side surface of the chip 4 as in the embodiment described with reference to FIG. Similarly to the embodiment described with reference to FIG. 12, the roundness of the corner portion of the chip 4 may be made different so that the position of the pin 1 can be recognized.

(10) After eliminating the adhesive force of the dicing tape of the semiconductor wafer 109, the chip is pushed up by the pickup needle, and the separated chip is taken out (see FIG. 27 (step S47)).

  In this embodiment, the trimming window opening 117 is not formed in the insulating film on the main surface of the semiconductor substrate, but is formed from the back surface 109b side of the semiconductor wafer 109 (step (3) )reference). Since the laser trimming process (see step (10)) is performed through the trimming window opening 117, there is no step of forming a final protective film after the trimming process as in the prior art. For example, the resistance value is adjusted. In the analog IC that performs the cutting by cutting the fuse element, it is possible to eliminate the fluctuation of the resistance value after the trimming process and to improve the accuracy of the electrical characteristics. Furthermore, when trimming is performed in accordance with the customer's request, the work period from order receipt to shipping can be shortened.

  In this embodiment, the semiconductor wafer 109 having the main surface 109a and the back surface 109b of (100) is used, but the present invention is not limited to this. For example, a silicon oxide film that covers the vicinity of the trimming window opening formation planned area and has an opening corresponding to the trimming window opening formation planned area on the surface of the silicon substrate whose front and back surfaces are (110) planes. A semiconductor wafer formed and formed with an epitaxial growth layer on the surface of the silicon substrate on which the silicon oxide film is formed may be used. In this semiconductor wafer, the main surface (epitaxial growth layer side) and the back surface (silicon substrate side) are silicon (110) planes.

  If a semiconductor device is manufactured using such a semiconductor wafer by the same process as the embodiment of the manufacturing method described with reference to FIGS. 27 and 28, a trimming window opening formed in the silicon substrate About the opening part of the vicinity area | region and the trimming window opening part formed in an epitaxial growth layer, the side surface of these opening parts can be formed in the direction perpendicular | vertical with respect to the back surface of a semiconductor wafer. An embodiment of a semiconductor device manufactured using such a semiconductor wafer is shown in FIG.

  29A and 29B are diagrams showing still another embodiment of the semiconductor device, in which FIG. 29A is a cross-sectional view showing a fuse element and a metal electrode pad portion of a portion where the fuse element is not cut, and FIG. 29B is a cut view of the fuse element. Sectional drawing which shows the fuse element and metal electrode pad part of the part which carried out is shown. Portions having the same role as in FIG. 26 are denoted by the same reference numerals, and detailed description thereof is omitted.

The difference between this embodiment and the embodiment shown in FIG. 26 will be described.
In this embodiment, a semiconductor substrate 125 in which an epitaxial growth layer 129 is formed on the main surface side of a silicon substrate 127 is used instead of the semiconductor substrate 109 shown in FIG. For example, the thickness of the silicon substrate 127 is 400 μm, and the thickness of the epitaxial growth layer 129 is 5 to 10 μm. The main surface 125a and the back surface 125b of the semiconductor substrate 125 are (110) planes.

  An opening 131 is formed in a region near the trimming window opening 133 of the silicon substrate 127, and a thickness of the region near the trimming window opening of the silicon substrate 127 is formed thinner than other regions. A trimming window opening 133 is formed in a predetermined region of the epitaxial growth layer 129 in the region where the opening 131 is formed. The opening 131 and the trimming window opening 133 are formed by silicon crystal plane anisotropic etching using an alkaline aqueous solution, and are perpendicular to the back surface 125b ((110) plane) of the semiconductor substrate 125. Is formed. Although only one trimming window opening 133 is shown in the figure, a plurality of trimming window openings 133 are formed as in the other embodiments described above.

  In this embodiment, since the opening 131 and the trimming window opening 133 are formed in a direction perpendicular to the back surface 125b of the semiconductor substrate 125, the interval between the adjacent trimming window openings 113 can be reduced. The chip area can be reduced.

  Further, the end of the sealing resin 39 filled in the trimming window opening 133 on the opening 131 side is provided in the opening 131 and protrudes from the bottom of the opening 131, but the silicon substrate 125 has Since it does not protrude from the back surface 125b, the sealing material 39 can be prevented from being mechanically peeled off, and the reliability can be improved.

  Furthermore, since the semiconductor substrate 125 is formed with the opening 131 provided in the silicon substrate 127 so that the thickness in the vicinity of the trimming window opening 133 is smaller than that in other regions, the trimming window opening 133 is formed. In addition, the misalignment between the trimming window opening 133 and the fuse element 7 due to the thickness of the semiconductor substrate 125 can be prevented, and the fuse element can be reliably cut when the fuse element is cut by laser irradiation.

  The embodiment of the manufacturing method for manufacturing the semiconductor device shown in FIG. 29 can be realized by the same process as the embodiment of the manufacturing method described with reference to FIGS.

In the embodiment described with reference to FIGS. 27 and 28, the silicon oxide film is disposed in the vicinity of the trimming window opening formation planned area and has an opening corresponding to the trimming window opening formation planned area. Although the semiconductor wafer 109 provided with 119 between the silicon substrate 111 and the epitaxial growth layer 113 is used, the present invention is not limited to this.
For example, an SOI (Silicon On Insulator) substrate in which a silicon oxide film is formed on the entire surface of the silicon substrate 111 and an epitaxial growth layer is further formed thereon may be used. FIG. 30 shows an example of a semiconductor device manufactured using an SOI substrate.

  30A and 30B are diagrams showing still another embodiment of the semiconductor device, in which FIG. 30A is a cross-sectional view showing a fuse element and a metal electrode pad portion where the fuse element is not cut, and FIG. Sectional drawing which shows the fuse element and metal electrode pad part of the part which carried out is shown. Portions having the same role as in FIG. 26 are denoted by the same reference numerals, and detailed description thereof is omitted.

The difference between this embodiment and the embodiment shown in FIG. 26 will be described.
In this embodiment, instead of the semiconductor substrate 109 shown in FIG. 26, an SOI substrate 135 in which an epitaxial growth layer 113 is formed on the main surface side of the silicon substrate 111 via a silicon oxide film 137 is used. For example, the thickness of the silicon substrate 111 is 400 μm, the thickness of the silicon oxide film 137 is 0.5 μm, and the thickness of the epitaxial growth layer 113 is 5 to 10 μm. The main surface 135a and the back surface 135b of the semiconductor substrate 135 are (100) planes, for example.

  An opening 115 formed by crystal plane anisotropic etching of silicon using an alkaline aqueous solution is formed in the silicon substrate 111. The silicon oxide film 137 at the bottom of the opening 115 is removed, and a trimming window opening 139 is formed in a predetermined region of the epitaxial growth layer 113 in the region where the opening 115 is formed. The trimming window opening 139 is formed by, for example, a dry etching technique. Although only one trimming window opening 139 is shown in the drawing, a plurality of trimming window openings 139 are formed as in the other embodiments described above.

  In this embodiment, the semiconductor substrate 135 is formed by the opening 115 provided in the silicon substrate 111 so that the area in the vicinity of the trimming window opening 139 is thinner than the other areas. When forming, the misalignment between the trimming window opening 139 and the fuse element 7 due to the thickness of the semiconductor substrate 135 can be prevented, and the fuse element can be reliably cut when the fuse element is cut by laser irradiation.

  Further, the end portion on the opening 115 side of the sealing resin 39 filled in the trimming window opening 139 is provided in the opening 115 and protrudes from the bottom of the opening 115. Since it does not protrude from the back surface 135b, it is possible to prevent the sealing material 39 from being mechanically peeled off and improve reliability.

  The embodiment of the manufacturing method for manufacturing the semiconductor device shown in FIG. 30 can be realized by the same process as the embodiment of the manufacturing method described with reference to FIGS. In that embodiment, when the opening 115 is formed in the silicon substrate 111, the silicon oxide film 137 functions as an etching stopper layer.

In the embodiment of the manufacturing method described above, a KOH aqueous solution is used as the silicon crystal plane anisotropic etching solution. However, the present invention is not limited to this. For example, tetramethylammonium hydroxide (TMAH) Alternatively, the silicon crystal plane anisotropic etching may be performed using another alkaline aqueous solution such as ethylenediamine pyrocatechol liquid (EDP).
Further, in the embodiment of the manufacturing method described with reference to FIGS. 21 to 23, the concave portion 101 is formed in a direction perpendicular to the back surface of the silicon wafer using a silicon wafer having a main surface and a back surface of (110). You may make it do.
Needless to say, the semiconductor device described with reference to FIGS. 19 to 30 can be applied to the embodiments shown in FIGS.

  As for the trimming opening, if the wafer thickness is thick, the aspect ratio capability of the etching apparatus is insufficient, and the plane dimension of the trimming window opening and the interval between the trimming window openings must be increased. It is conceivable that the size of the laser spot area is large and the density of the trimming opening cannot be made dense. In such a case, it is preferable to devise the layout of the fuse element and the trimming window opening.

  31A and 31B are diagrams showing still another embodiment of the semiconductor device, in which FIG. 31A is a plan view showing the upper surface, and FIG. 31B is a layout diagram showing a layout example of fuse elements and trimming window openings. Portions having the same role as in FIG. 20 are denoted by the same reference numerals, and detailed description thereof is omitted.

This embodiment is different from the embodiment shown in FIG. 20 in that the fuse element 7 is arranged at a position corresponding to the center of the regular hexagon and the trimming window opening 37 is also arranged at the vertex of the regular hexagon according to the arrangement of the fuse element 7. It is arranged at a position corresponding to the center. Thereby, the area of the arrangement region of the trimming window opening 37 can be minimized.
Such an arrangement of the fuse element and the trimming window opening can be applied to all the embodiments described above.

  In the present invention, since the laser is irradiated from the back side of the wafer when the fuse element is cut, a metal wiring pattern or a metal electrode pad can be arranged on the upper layer of the fuse element. Using this feature, one or more layers of metal wiring patterns or metal electrode pads may be arranged on the fuse element or an interlayer insulating film near the fuse element. Thereby, the freedom of a layout of a metal wiring pattern or a metal electrode pad can be improved. In addition, since the area where the metal wiring pattern and the metal electrode pad can be arranged can be increased, it is possible to contribute to the reduction of the chip area.

  When a metal wiring pattern or metal electrode pad is placed in the upper layer of the fuse element, laser reflection is applied to the upper layer of the fuse element to prevent the metal wiring pattern or metal electrode pad from being damaged during laser irradiation of the fuse element. It is preferable to arrange a metal pattern for use.

FIG. 32 is a sectional view showing still another embodiment of the semiconductor device. Portions having the same role as in FIG. 30 are denoted by the same reference numerals, and detailed description thereof is omitted.
This embodiment is different from the embodiment shown in FIG. 30 in that a metal pattern 141 for laser reflection made of a dummy pattern is formed on the fuse element 7. The laser reflecting metal pattern 141 is formed on the interlayer insulating film 9 by the same metal material as the metal wiring layer 13 and the metal electrode pad 15, and is electrically insulated from the metal wiring layer 13 and the metal electrode pad 15. .

  In this embodiment, even if laser irradiation is performed on the fuse element 7 from the back surface 109b side of the SOI substrate 135 in order to cut the fuse element 7, the irradiated laser light is reflected by the metal pattern 141 for laser reflection and is used for laser reflection. It is not irradiated to the upper layer side than the metal pattern 141. Thereby, although not shown in FIG. 32, the metal wiring pattern and the metal electrode pad can be arranged on the upper layer side than the laser reflecting metal pattern 141.

  In the embodiment shown in FIG. 32, the laser reflecting metal pattern 141 is electrically insulated from the metal wiring layer 13 and the metal electrode pad 15, but the laser reflecting metal pattern 141 is a metal wiring pattern for signal wiring. The metal wiring layer 13 and the metal electrode pad 15 may be electrically connected.

Further, in order to prevent the laser reflecting metal pattern 141 from being overheated when the fuse element 7 is irradiated with the laser, a heat radiating connection hole and a metal pattern are provided on the laser reflecting metal pattern 141, and the uppermost layer is formed. An opening may be provided in the insulating film on the metal pattern for heat dissipation, and a structure that can dissipate heat generated in the metal pattern 141 for laser reflection through the connection hole for heat dissipation and the metal pattern may be provided. The heat radiating connection holes and metal patterns may be signal wiring connection holes and metal patterns, or may be dummy patterns not used for signal wiring. For example, in the embodiment shown in FIG. 32, if the metal pattern for laser reflection 141 and the metal wiring layer 13 are continuously formed, the heat generated in the metal pattern for laser reflection 141 is generated. The heat can be radiated out of the chip through the metal electrode pad 15, the pad opening 23, the second metal wiring layer 25, the second metal electrode pad 27, the barrier metal layer 33, and the external connection terminal 35.
The configuration in which the metal pattern for laser reflection is arranged on the upper layer of the fuse element can be applied to all the embodiments described above.

  The embodiment of the present invention has been described above, but the present invention is not limited to this, and the dimensions, shape, material, arrangement, etc. are only examples, and are within the scope of the present invention described in the claims. Various changes can be made.

1A and 1B are diagrams showing an embodiment of a semiconductor device, in which FIG. 1A is a cross-sectional view showing a fuse element and a metal electrode pad portion where a fuse element is not cut, and FIG. 1B is a fuse element where a fuse element is cut; Sectional drawing which shows a metal electrode pad part is shown. 3 is a flowchart showing an embodiment of a method for manufacturing a semiconductor device. It is process sectional drawing which shows the beginning of the Example. It is process sectional drawing which shows the continuation of the Example. It is process sectional drawing which shows the last of the Example. It is a top view which shows the photoresist used for formation of the trimming window opening part and division | segmentation of a silicon wafer in the Example. In the same Example, it is sectional drawing which expands and shows the state by which the trimming window opening part was formed and the silicon wafer was divided | segmented into each chip | tip. In the same Example, it is sectional drawing which shows the state by which the fuse element was cut | disconnected. It is a top view which shows the taken-out chip | tip, (A) shows an upper surface, (B) shows a back surface. It is a figure which shows the other Example of a semiconductor device, (A) is a top view, (B) is a side view. It is process sectional drawing which shows a part of other Example of the manufacturing method of a semiconductor device. It is a figure which shows other Example of a semiconductor device, (A) is a top view, (B) is a side view It is a figure which shows further another Example of a semiconductor device, (A) is a top view, (B) is a side view. It is a circuit diagram which shows one Example of the semiconductor device provided with the constant voltage generation circuit. It is a circuit diagram which shows one Example of the semiconductor device provided with the voltage detection circuit. It is a circuit diagram which shows an example of the division resistance circuit to which the fuse element and trimming window opening part of this invention are applied. It is a layout figure which shows the example of a layout of the fuse element part of a division resistance circuit. It is a layout figure which shows the example of a layout of the setting resistive element part of a division resistance circuit. It is a figure which shows further another Example of a semiconductor device, (A) is sectional drawing which shows the fuse element and metal electrode pad part of the part which has not cut | disconnected a fuse element, (B) is the part of the part which cut | disconnected the fuse element Sectional drawing which shows a fuse element and a metal electrode pad part is shown. It is a top view which shows the whole Example, (A) shows an upper surface, (B) shows a back surface. It is a flowchart which shows the further another Example of the manufacturing method of a semiconductor device. It is process sectional drawing which shows a part of manufacturing process of the Example, and shows the process of forming a recessed part in the area | region corresponding to the trimming window opening part formation area of a silicon wafer about several chip formation area. It is process sectional drawing which shows a part of manufacturing process of the Example, and has shown the process of forming the trimming window opening part about several chip | tip formation area. In the same Example, sectional drawing which expands and shows the state in which the trimming window opening part was formed is shown. In the same Example, sectional drawing of the state by which the fuse element 7 was cut | disconnected is expanded and shown. It is a figure which shows further another Example of a semiconductor device, (A) is sectional drawing which shows the fuse element and metal electrode pad part of the part which has not cut | disconnected a fuse element, (B) is the part of the part which cut | disconnected the fuse element Sectional drawing which shows a fuse element and a metal electrode pad part is shown. It is a flowchart which shows the further another Example of the manufacturing method of a conductor apparatus. It is process sectional drawing which shows a part of manufacturing process of the Example. It is a figure which shows further another Example of a semiconductor device, (A) is sectional drawing which shows the fuse element and metal electrode pad part of the part which has not cut | disconnected a fuse element, (B) is the part of the part which cut | disconnected the fuse element Sectional drawing which shows a fuse element and a metal electrode pad part is shown. It is a figure which shows further another Example of a semiconductor device, (A) is sectional drawing which shows the fuse element and metal electrode pad part of the part which has not cut | disconnected a fuse element, (B) is the part of the part which cut | disconnected the fuse element Sectional drawing which shows a fuse element and a metal electrode pad part is shown. It is a figure which shows the further another Example of a semiconductor device, (A) is a top view which shows an upper surface, (B) is a layout figure which shows the layout example of a fuse element and a trimming window opening part. It is sectional drawing which shows other Example of a semiconductor device. It is sectional drawing which shows the fuse element part in the conventional wafer level CSP, (A) shows the state before laser trimming, (B) shows the state after laser trimming, (C) shows the state after resin sealing. It is sectional drawing which shows the fuse element and metal electrode pad part in the conventional wafer level CSP. It is a flowchart which shows a part of manufacturing process of the conventional wafer level CSP including a laser trimming process. It is process sectional drawing which shows the manufacturing method of the semiconductor device of a prior art. It is a figure which shows the malfunction in the manufacturing method of the semiconductor device of a prior art, (A) is a top view, (B) is sectional drawing in the AA position of (A).

Explanation of symbols

1 Silicon substrate (silicon wafer)
DESCRIPTION OF SYMBOLS 1a Main surface of silicon substrate (silicon wafer) 1b Back surface of silicon substrate (silicon wafer) 3 Base insulating film 5 Polysilicon film 7 Fuse element 9 Interlayer insulating film 11 Connection hole 13 Metal wiring layer 15 Metal electrode pad 17 PSG film 19 SiN Film 21, 29 Polyimide film 23 Pad opening 25 Second metal wiring layer 27 Second metal electrode pad 31 Pad opening 33 Barrier metal layer 35 External connection terminal 37 Trimming window opening 39 Sealing resin 101 Recess 103 Boron high concentration region 105a, 105b Silicon oxide films 107a, 107b Photoresist 109 Semiconductor substrate (semiconductor wafer)
109a Main surface 109b of semiconductor substrate (semiconductor wafer) Back surface 111 of semiconductor substrate (semiconductor wafer) Silicon substrate 113 Epitaxial growth layer 115 Opening 117 Trimming window opening 119 Silicon oxide film 121a, 121b Polysilicon film 123a, 123b Silicon oxide film 125 Semiconductor substrate (semiconductor wafer)
125a Main surface 125b of semiconductor substrate (semiconductor wafer) Back surface 127 of semiconductor substrate (semiconductor wafer) Silicon substrate 129 Epitaxial growth layer 131 Opening 133 Trimming window opening 135 SOI substrate 137 Silicon oxide film 139 Trimming window opening 141 Laser reflecting metal pattern

Claims (31)

In a semiconductor device provided with a fuse element via an insulating film on the main surface of a semiconductor substrate,
A trimming window opening is formed in the semiconductor substrate corresponding to a position where the fuse element is formed.   The semiconductor device according to claim 1, wherein the insulating film remains between the fuse element before cutting and the trimming window opening.   The semiconductor device according to claim 1, wherein the trimming window opening is sealed from the back side of the semiconductor substrate.   4. The semiconductor device according to claim 1, wherein the semiconductor substrate is formed so that a thickness of a region near the opening of the trimming window is thinner than that of other regions.   The semiconductor substrate is formed such that a thickness of the region near the trimming window opening is thinner than other regions due to a recess formed in the region near the trimming window opening by crystal plane anisotropic etching of silicon. Item 5. The semiconductor device according to Item 4.   The semiconductor device according to claim 5, wherein boron is introduced into a formation region of the bottom of the recess in the semiconductor substrate.   In the semiconductor substrate, an epitaxial growth layer is formed on the main surface side of the silicon substrate, an opening is formed in the silicon substrate in the vicinity of the trimming window opening, and the opening forming region is formed in the region where the opening is formed. The semiconductor device according to claim 4, wherein the trimming window opening is formed in the epitaxial growth layer.   The semiconductor device according to claim 7, wherein the opening formed in the silicon substrate is formed by crystal plane anisotropic etching of silicon.   9. The semiconductor device according to claim 8, wherein the trimming window opening formed in the epitaxial growth layer is formed by silicon crystal plane anisotropic etching.   The semiconductor device according to claim 1, wherein roundness is formed at corner portions of the formed shape of the semiconductor device.   The semiconductor device according to claim 10, wherein one of the plurality of corner portions is rounded with a size different from that of the other corner portions.   The semiconductor device according to claim 1, wherein a bar code having an uneven shape is formed on at least one side surface of the semiconductor device.   The semiconductor device according to claim 1, wherein a marking made of one or a plurality of concave portions is formed on a back surface of the semiconductor substrate.   The semiconductor device according to claim 1, wherein a marking by laser irradiation is formed on a back surface of the semiconductor substrate. In a semiconductor device having a divided resistor circuit capable of obtaining a voltage output by dividing by two or more resistors and adjusting the voltage output by cutting a fuse element,
15. A semiconductor device comprising the fuse element according to claim 1 and the trimming window opening in a region where the divided resistor circuit is formed. A divided resistor circuit for dividing the input voltage to supply a divided voltage, a reference voltage generating circuit for supplying a reference voltage, a divided voltage from the divided resistor circuit, and a reference voltage from the reference voltage generating circuit In a semiconductor device including a voltage detection circuit having a comparison circuit for comparison,
A semiconductor device comprising the divided resistor circuit according to claim 15 as the divided resistor circuit. An output driver for controlling the output of the input voltage, a divided resistor circuit for dividing the output voltage and supplying a divided voltage, a reference voltage generating circuit for supplying a reference voltage, and a divided voltage from the divided resistor circuit In a semiconductor device including a constant voltage generation circuit having a comparison circuit for comparing the reference voltage from the reference voltage generation circuit and controlling the operation of the output driver according to the comparison result,
A semiconductor device comprising the divided resistor circuit according to claim 15 as the divided resistor circuit. In a manufacturing method of a semiconductor device provided with a fuse element via an insulating film on a main surface of a semiconductor substrate,
A method of manufacturing a semiconductor device, comprising a step of forming a trimming window opening corresponding to a region where the fuse element is formed from the back side of the wafer-like semiconductor substrate after the fuse element is formed.   The method of manufacturing a semiconductor device according to claim 18, wherein the trimming window opening is formed by anisotropic etching.   The method for manufacturing a semiconductor device according to claim 19, wherein the insulating film is used as an etching stopper layer.   21. The method of manufacturing a semiconductor device according to claim 19, wherein a wafer-like semiconductor substrate is singulated simultaneously with the formation of the trimming window opening.   The trimming window opening is formed in a state where the tape material is affixed to the surface of the semiconductor wafer on the main surface side of the semiconductor substrate, the back surface of the semiconductor wafer is polished, and the semiconductor wafer is affixed to the tape material. Item 22. A method for manufacturing a semiconductor device according to any one of Items 19 to 21.   19. The method of manufacturing a semiconductor device according to claim 18, further comprising a step of reducing a thickness of the semiconductor substrate in a region near a trimming window opening formation scheduled region before forming the trimming window opening, as compared with other regions. .   A silicon substrate is used as the semiconductor substrate, and a recess is formed in the silicon substrate in the vicinity of the trimming window opening formation planned area by silicon crystal plane anisotropic etching, in the vicinity of the trimming window opening formation planned area. 24. The method of manufacturing a semiconductor device according to claim 23, wherein the thickness of the region is made thinner than other regions.   25. The method of manufacturing a semiconductor device according to claim 24, further comprising a step of introducing boron from a main surface side into a region corresponding to a bottom portion of the concave portion with respect to the silicon substrate before forming the concave portion.   As the semiconductor substrate, an epitaxial growth layer is formed on the main surface side of the silicon substrate at least in the vicinity of a region where the trimming window opening is to be formed via a silicon oxide film, and the silicon oxide film is used as an etching stopper layer. An opening is formed in the silicon substrate in a region in the vicinity of the trimming window opening formation planned region, and the thickness of the semiconductor substrate in the region in the vicinity of the trimming window opening formation planned region is made thinner than other regions. 24. A method of manufacturing a semiconductor device according to 23.   27. The method of manufacturing a semiconductor device according to claim 26, wherein the opening is formed in the silicon substrate by crystal plane anisotropic etching of silicon.   As the semiconductor substrate having a silicon oxide film and an epitaxial layer formed on the main surface side, a silicon crystal having an opening formed in a region corresponding to a trimming window opening forming region of the silicon oxide film is used. 28. The method of manufacturing a semiconductor device according to claim 27, wherein the formation of the opening in the silicon substrate and the formation of the trimming window opening in the epitaxial growth layer are successively performed by plane anisotropic etching.   29. The method of manufacturing a semiconductor device according to claim 18, further comprising a step of forming a marking by laser irradiation on a back surface of the semiconductor substrate when the fuse element is irradiated with laser through the trimming window opening. Method.   30. The method of manufacturing a semiconductor device according to claim 18, further comprising a step of sealing the trimming window opening.   31. The method of manufacturing a semiconductor device according to claim 30, wherein the trimming window opening is sealed by filling the trimming window opening with a resin material.

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