JP2004282171A

JP2004282171A - Broadband dc component eliminating circuit and assembling method therefor

Info

Publication number: JP2004282171A
Application number: JP2003067192A
Authority: JP
Inventors: Takatoshi Yagisawa; 孝俊八木澤; Naoki Kuwata; 直樹桑田; Akira Ikeuchi; 公池内
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 2003-03-12
Filing date: 2003-03-12
Publication date: 2004-10-07

Abstract

<P>PROBLEM TO BE SOLVED: To provide a broadband DC component eliminating circuit wherein a high frequency capacitor and a low frequency capacitor are connected in parallel between board patterns opposed to each other with an interval on a dielectric board and a structure realizing ease of mount is realized by decreasing a connection length of metallic conductors such as a gold ribbon and a gold wire incurring deterioration in the high frequency characteristic and to provide an assembling method therefor. <P>SOLUTION: The high frequency capacitor 3 is embedded to a groove 5 provided in a board 1 between the board patterns 2a, 2b, electrodes 3a, 3b of the high frequency capacitor 3 are connected to the board patterns 2a, 2b by metallic conductors 6a, 6b, the low frequency capacitor 4 is placed above the capacitor 3 and the board patterns 2a, 2b and electrodes 4a, 4b of the low frequency capacitor 4 are respectively electrically connected. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、広帯域直流成分除去回路に関し、特に高速の光通信装置、および計測器におけるマイクロ波、ミリ波帯の高周波用コンデンサを低周波用コンデンサと並列に接続して広帯域での直流成分を除去（ＤＣカット）する回路に関するものである。
【０００２】
【従来の技術】
光通信装置における電子回路内での直流成分を除去するためには、誘電体基板上で向き合った２つのパターン間にコンデンサを接続する構造が採られ、図１４の従来例（１）に示す如く、低周波を効率良く伝送するための並行平板型コンデンサ４の電極４ａ，４ｂをそれぞれパターン２ａ，２ｂ間に接続する方法や、図１５の従来例（２）に示す如く高周波用の並行平板コンデンサ３の一方の電極３ｂを一方のパターン２ａ上に載置して接続し、他方のパターン２ｂとコンデンサ３の他方の電極３ａを金リボン、または金ワイヤー９で接続していた。
【０００３】
さらに、通信速度の高速化に伴い広帯域特性（数ＫＨｚ〜数１０ＧＨｚ）が要求されるに至り、図１６の従来例（３）に示すように、図１４の従来例（１）と図１５の従来例（２）とを組み合わせたり、或いは、図１７の従来例（４）（例えば、特許文献１参照。）に示すように、図１５の従来例（２）の状態でパターン２ａと高周波用コンデンサ３の電極３ａにそれぞれ低周波用コンデンサ４の電極４ａ，４ｂを電気的に接続することにより、高周波用のコンデンサ３と低周波用のコンデンサ４を並列に接続する方法が用いられていた。
【０００４】
さらには、複数の結合コンデンサが搭載される範囲で高周波基板又は裏面の高周波アースの一部分を削除することにより伝達特性を改善したものもある（例えば、特許文献２参照。）。
さらには、高周波特性に優れたチップコンデンサを得るために、凹部を有する基板の上面から凹部にかけて第１の電極を設け、基板の凹部内に誘電体を有し、この誘電体と第２の電極を電気的に接続したものもある（例えば、特許文献３参照。）。
【０００５】
さらには、ベースバンド信号を処理する基底帯域部と高周波信号を処理する高周波部とを１つのモジュールとして形成するために、基板と、基板上に形成される第１電気遮蔽線と、受動素子を有し第１電気遮蔽線の上に形成される受動素子層と、受動素子層の上に形成される第２電気遮蔽線と、受動素子と電気的に連結される連結導線を有し第２電気遮蔽線の上に形成される相互連結層と、相互連結層の上に形成される第３電気遮蔽線と、連結導線と電気的に連結され第３電気遮蔽線の外部に形成される多数のバンパーと、バンパーの上に形成される多数の集積回路または電気素子とを含む多層マルチチップモジュールも提案されている（例えば、特許文献４参照。）。
【０００６】
【特許文献１】
特開平５−２３５６０２号公報（第３頁左欄、図１）
【０００７】
【特許文献２】
特開平６−８５５１１号公報（第２−３頁、図２）
【０００８】
【特許文献３】
特開２０００−２６９０６５号公報（要約、図１）
【０００９】
【特許文献４】
特開２００１−２４４４０２号公報（要約、図１）
【００１０】
【発明が解決しようとする課題】
従来の広帯域直流成分除去回路の構造では、高周波用のコンデンサと誘電体基板上のパターン間を接続する金（Ａｕ）リボン、または金ワイヤーの長さが、並行平板型のコンデンサの高さ以上必要になり、その長さに比例して増加するＬ成分と、接続部分のインピーダンスマッチングがとれなくなってしまい、高周波帯域での損失を大きくしてしまうという問題が生じていた。
【００１１】
また、高周波特性の要求が高くなるにつれて寄生容量の低減が必要となり、素子の小型化、高密度実装化が進んだことにより、並行平板型の高周波用コンデンサの電極の一方に金リボンを接続すると共にこれにさらに、低周波用コンデンサを積層させる必要が出てくるなど、誘電体基板上への実装が困難になるという問題があった。
【００１２】
従って本発明は、誘電体基板上で間隔を置いて向き合った基板パターン間に、高周波用コンデンサと低周波用コンデンサを並列に接続した広帯域直流成分除去回路及びその組立方法において、高周波特性の劣化を招く金リボンや金ワイヤーなどの金属導体の接続長を従来例と同程度か又は以下に短縮して、実装が容易な構造を実現することを目的とする。
【００１３】
【課題を解決するための手段】
図１７に示すような低周波用のコンデンサ４と高周波用のコンデンサ３を並列に接続し、コンデンサ３とパターン２ｂ間の接続に金リボン９を用いた場合、この金リボン９の長さは０．３ｍｍ程度になる。
【００１４】
このような構造の等価回路を、図１８に示すような２つのコンデンサＣ１，Ｃ２の並列回路とインダクタンスＬ１とで構成されたＬＣ回路に置き換え、概算で金リボン１ｍｍに対しＬ１＝１ｎＨとして、Ｌ１の値を１００〜４００ｐＨに変化させることにより伝送特性のシミュレーションを行ったところ、図１９の周波数特性（Ｓ２１）に示すように、金リボンなどの接続長を短くすることにより、伝送特性が平坦に近づき向上させることが可能となることが分かった。
【００１５】
そこで、本発明者は以下の通り種々の手段を実現した。
［１］図１は、本発明の概略図（１）を示し、誘電体基板１上に設けたパターン２ａ，２ｂ間に並行平板型の高周波用コンデンサ３が挿入できる程度の溝５を基板１中に設け、その溝５の中に、両電極３ａ，３ｂに金属導体６ａ，６ｂを設けた高周波用コンデンサ３を埋め込む。
【００１６】
その後、金属導体６ａ，６ｂとパターン２ａ，２ｂをそれぞれ電気的に接続すると共にその上に並行平板型の低周波用コンデンサ（図示せず）を載置して各パターン２ａ，２ｂと該低周波用コンデンサの電極をそれぞれ電気的に接続することにより高周波用コンデンサと低周波用コンデンサを並列接続した広帯域直流成分除去回路を実現する。
【００１７】
これにより、高周波用コンデンサ３とパターン２ａ，２ｂ間を接続する金属導体６ａ，６ｂが短くなり、高周波特性を向上させることができる。
［２］図１において、低周波用コンデンサにセラミックコンデンサ、高周波用コンデンサにマイクロチップコンデンサを用い、金属導体６ａ，６ｂとしての金リボンをリボンボンディング等により電極３ａ，３ｂに接続したマイクロチップコンデンサを溝５内に縦方向に挿入するように埋め込み、金リボン６ａ，６ｂの端を両側に開くようにしてパターン２ａ，２ｂに、やはりリボンボンディングにより接続することができる。
【００１８】
［３］図２は、本発明の概略図（２）を示し、パターン２ａ，２ｂ間に高周波用コンデンサ３の電極間間隔に相当する高さの溝５を基板１中に設け、一方のパターン２ｂを溝５内に設けたパターン８と接続し、その溝５内のパターン８上に高周波用コンデンサ３の一方の電極３ｂが接触するようにコンデンサ３を埋め込み、他方のパターン２ａと高周波用コンデンサ３のもう一方の電極３ａを金属導体９である金リボン、または金ワイヤーで接続すると共にさらにその上に低周波用コンデンサ（図示せず）を載置して各パターン２ａ，２ｂと該低周波用コンデンサの各電極をそれぞれ電気的に接続することにより高周波用コンデンサと低周波用コンデンサを並列接続した広帯域直流成分除去回路を実現する。
【００１９】
これにより、高周波用コンデンサに接続される金属導体である金リボン、または金ワイヤーを短くし、高周波特性を向上させることができる。
［４］図３は、本発明の概略図（３）を示し、上記［３］と同様の構造において、溝５内のパターン８を基板１内に延長させ、この延長方向の一方のパターン２ｂとパターン８の延長部分とを基板１内に設けたビア７により接続するもので、上記［３］と同様の作用として、高周波用コンデンサに接続される金属導体９である金リボン、または金ワイヤーの長さを短くし、高周波特性を向上させることができる。
【００２０】
［５］図４は、本発明の概略図（４）を示し、この場合の基板１は誘電体多層基板になっている。すなわち、向き合ったパターン２ａ，２ｂの一方２ｂを、第１層の誘電体基板１０に設けたビア７で第２の層の誘電体基板１１上のパターン８に接続し、このパターン８ともう一方の基板パターン２ａとの間に誘電体基板１０を挟み込むことにより高周波用コンデンサを形成する。
【００２１】
そして、その上方のパターン２ａ，２ｂ間に低周波用のコンデンサ（図示せず）を載置することにより、金属導体である金リボン、または金ワイヤーによる接続を無くし、高周波特性の劣化を防ぐとともに、低周波用コンデンサの実装も容易になる。
【００２２】
［６］図５は、本発明の概略図（５）を示し、高周波用の並行平板コンデンサ３の片面の電極を複数に分割して電極３ｂ１，３ｂ２を設け、これらをそれぞれパターン２ａ，２ｂに接続する。そして、さらにこのコンデンサ３を跨ぐようにパターン２ａ，２ｂ上に設けた金属導体を介して低周波用コンデンサ（図示せず）の各電極をパターン２ａ，２ｂにそれぞれ接続する。
【００２３】
これにより、金属導体としての金リボン、または金ワイヤーによる高周波用コンデンサへの接続を無くし、高周波特性の劣化を防ぐことが可能となる。
［７］図６は、本発明の概略図（６）を示し、向き合ったパターン２ａ，２ｂの一方２ａに高周波用コンデンサ３の一方の電極３ｂが接触するようにコンデンサ３をパターン２ａ上に載置し、他方の電極３ａを、金属導体である金リボン９、またはワイヤーで他方のパターン２ｂと電気的に接続し、その上にさらに低周波用のコンデンサ４を金属導体１２ａ，１２ｂを介して積層する。
【００２４】
すなわち、高周波用コンデンサ３と金リボン９を跨ぐように金属導体１２ａ，１２ｂをそれぞれパターン２ａ，２ｂ上に設け、さらに金属導体１２ａ，１２ｂにそれぞれ電極４ａ，４ｂが電気的に接続されるように低周波用コンデンサ４を載置する。
これにより、高周波用コンデンサ３及び金リボン９に対して低周波用コンデンサ４を立体的に配置できるので、組立を容易に行うことが可能となる。
【００２５】
［８］図１において、誘電体基板１上の２つの向き合ったパターン２ａ，２ｂ間の容量結合の際に、並行平板型のコンデンサ３の両電極に金属導体をボンディングにより片側の端を接続し、反対側の端を広げて向い合った２つのパターン２ａ，２ｂに接続すると共にその上に低周波用コンデンサを載置して各パターン２ａ，２ｂと該低周波用コンデンサの各電極をそれぞれ電気的に接続することにより、高周波用コンデンサと低周波用コンデンサを並列接続した広帯域直流成分除去回路の組立方法を用いることにより、金属導体の接続長を短くすることが可能となる。
【００２６】
同様にして上記［１］〜［７］の概念により、それぞれ本発明による広帯域直流成分除去回路の組立方法を実現することができる。
【００２７】
【発明の実施の形態】
実施例（１）
図７は、図１に示した概略図（１）に対応する本発明の実施例（１）を示し、並行平板型の低周波用のコンデンサ４にセラミックコンデンサ、並行平板型の高周波用のコンデンサ３にマイクロチップコンデンサを用いている。
【００２８】
そして、マイクロチップコンデンサ３の両面、すなわち電極３ａ，３ｂに、金リボン６ａ，６ｂをボンディングし、パターン２ａ，２ｂ間にコンデンサ３の縦長部分に相当する高さで基板１中に掘った溝５にコンデンサ３を縦方向に差し込む。その際、必要に応じて溝５の底部でマイクロチップコンデンサ３を接着剤で固定する。
【００２９】
その後、金リボン６ａ，６ｂとパターン２ａ，２ｂをそれぞれボンディングし、セラミックコンデンサ４の電極４ａ，４ｂを金錫（ＡｕＳｎ）でパターン２ａ，２ｂとそれぞれ接続する。
このようにして、金リボン６ａ，６ｂの長さを、マイクロチップコンデンサ３の高さ以下にすることができ、高周波特性が向上する。
【００３０】
実施例（２）
図８は、図２に示した概略図（２）に対応する本発明の実施例（２）を示し、基板１上のパターン２ａ，２ｂ間の基板１中に、高周波用コンデンサとしてのマイクロチップコンデンサ３の電極３ａ，３ｂ間間隔に相当する高さ程度の溝５を堀り、一方のパターン２ｂを溝５の底部に設けたパターン８と溝５の壁部分に沿って接続し、その溝内のパターン８上にマイクロチップコンデンサ３の電極３ｂを金錫で接続し、他方のパターン２ａとマイクロチップコンデンサ３ａの上面の電極３ａを金リボン９で電気的に接続する。
【００３１】
そして、反対側のパターン２ｂとマイクロチップコンデンサ３の上面電極３ａにそれぞれセラミックコンデンサ４の電極４ｂ，４ａを金錫により接続する。
このようにして、マイクロチップコンデンサ３の電極３ａ面と、パターン２ａ，２ｂ面の高さを合わせることができ、それらを接続する金リボン９の長さを、図１６及び１７に示した従来例（３）及び（４）に比べ、マイクロチップコンデンサ３の高さ分だけ短くすることができ、高周波特性が向上する。
【００３２】
実施例（３）
図９は、図３に示した概略図（３）に対応する本発明の実施例（３）を示し、図８の実施例（２）と異なる点は、一方のパターン２ｂと溝５の底部のパターン８との接続を、溝５の壁部分に沿うのではなく、パターン８を誘電体基板１内に延長し、且つこの延長部とその延長方向のパターン２ｂとをビア７により接続したことである。
【００３３】
これにより、図８の場合と同様にマイクロチップコンデンサ３の電極３ａ，３ｂ面と、パターン２ａ，２ｂ面の高さ方向を合わせることができ、それらを接続する金リボン９の長さを、従来に比べ、マイクロチップコンデンサ３の高さ程度短くすることができ、高周波特性が向上する。
【００３４】
実施例（４）
図１０は、図４に示した概略図（３）に対応する本発明の実施例（４）を示し、誘電体基板１０上で向き合ったパターン２ａ，２ｂの一方２ｂをビア７で下の層の誘電体基板１１上のパターン８に接続する。その際、パターン８ともう一方の基板パターン２ａとの間に基板１０による高誘電体物質が介在するので、両パターン８−２ａ間で高周波用コンデンサを形成することになる。そして、表面のパターン２ａ，２ｂ間にセラミックコンデンサ４の電極４ａ，４ｂを金錫で接続する。
【００３５】
このようにして、金リボンによる接続が無くなり、高周波特性が向上する。また、高周波用コンデンサを素子として別途用意する必要がなく組立の工程も削減でき、組立が容易になる。
実施例（５）
図１１は、図５に示した概略図（５）に対応する本発明の実施例（５）を示し、マイクロチップコンデンサ３の下側の電極を、例えば２つの電極３ｂ１，３ｂ２に分割しておく。そして、その電極３ｂ１，３ｂ２をそれぞれ基板１上のパターン２ａ，２ｂに金錫で接続してパターン２ａ，２ｂ間に高周波用のコンデンサ３を接続したことになる。
【００３６】
その後、マイクロチップコンデンサ３の両脇に金属導体としての金ブロック１２ａ，１２ｂを載置し、金錫でパターン２ａ，２ｂにそれぞれ接続する。さらに、金ブロック１２ａ，１２ｂの上面間にセラミックコンデンサ４を積層し、その電極４ａ，４ｂを金錫により接続する。
【００３７】
このようにして、金リボン等を用いることなくマイクロチップコンデンサの電極面を直接パターン接続できるので、高周波特性が向上する。
実施例（６）
図１２は、図６に示した概略図（６）に対応する本発明の実施例（６）を示し、この場合には、一方のパターン２ａの端部にマイクロチップコンデンサ３の電極３ｂの全面を金錫により接続し、その上面の電極３ａを金リボン９で他方のパターン２ｂと接続する。
【００３８】
ここまでは、図１７に示した従来例（４）と同様であるが、本実施例ではさらに、コンデンサ３の両脇に金ブロック１２ａ，１２ｂを載置してそれぞれパターン２ａ，２ｂに金錫で接続し、上記の実施例（５）と同様にその金ブロック１２ａ，１２ｂの上面間にそれぞれセラミックコンデンサ４を積層し、その電極４ａ，４ｂを金錫により接続する。
【００３９】
このようにして、マイクロチップコンデンサ３の一方の電極面に、セラミックコンデンサと金リボンの両方を接続する必要がなくなり、組立が容易になる。
実施例（７）
図１３は、図７に示した概略図（７）に対応する本発明の実施例（７）を示し、ここでは、図１２の金ブロック１２ａ，１２ｂの代わりに、その役割を、セラミックコンデンサ４の延長した電極４ａ，４ｂによって果たそうとするものであり、同様の効果を発揮するものである。
（付記１）
誘電体基板上で間隔を置いて向き合った基板パターン間に、共に並行平板型の高周波用コンデンサと低周波用コンデンサを並列に接続した広帯域直流成分除去回路において、
該基板パターン間の該基板中に設けた溝に該高周波用コンデンサを埋め込むと共に、該高周波用コンデンサの各電極と各基板パターンを金属導体で接続し、その上方に該低周波用コンデンサを載置して各基板パターンと該低周波用コンデンサの電極をそれぞれ電気的に接続したことを特徴とする広帯域直流成分除去回路。
（付記２）付記１において、
該低周波用コンデンサにセラミックコンデンサ、該高周波用コンデンサにマイクロチップコンデンサを用い、該マイクロチップコンデンサを、その縦長の深さを有する該溝内に縦方向に埋め込むことを特徴とした広帯域直流成分除去回路。
（付記３）
誘電体基板上で間隔を置いて向き合った基板パターン間に、共に並行平板型の高周波用コンデンサと低周波用コンデンサを並列に接続した広帯域直流成分除去回路において、
該基板パターン間に該高周波用コンデンサの電極間間隔に相当する深さの溝を該基板内に設け、該基板パターンの内の一方を該溝内に設けた溝パターンと接続し、その溝パターンと該高周波用コンデンサの一方の電極が接触するように該高周波用コンデンサを該溝内に埋め込み、該基板パターンの他方と該高周波用コンデンサの他方の電極を金属導体で接続し、さらに該他方の電極と該基板パターンの他方にそれぞれ該低周波用コンデンサの各電極を電気的に接続したことを特徴とする広帯域直流成分除去回路。
（付記４）付記３において、
該溝パターンを該基板中に延長し、該溝パターンの延長部分とその延長方向に存在する該基板パターンの一方との接続を、誘電体基板内に設けたビアにより行うことを特徴とした広帯域直流成分除去回路。
（付記５）
誘電体基板上で間隔を置いて向き合った基板パターン間に、高周波用コンデンサと低周波用コンデンサを並列に接続した広帯域直流成分除去回路において、
該誘電体基板が第１の層を形成し、該基板パターンの一方をビアで第２の層の誘電体基板上の基板パターンに接続し、該第２の層の基板パターンと該第１の層の基板パターンの他方との間に該第１の層の誘電体基板を挟み込むことにより該高周波コンデンサを形成し、さらに該第１の層の各基板パターン間に低周波用コンデンサを載置して各基板パターンにそれぞれ該低周波用コンデンサの各電極を電気的に接続したことを特徴とする広帯域直流成分除去回路。
（付記６）
誘電体基板上で間隔を置いて向き合った基板パターン間に、共に並行平板型の高周波用コンデンサと低周波用コンデンサを並列に接続した広帯域直流成分除去回路において、
該高周波用コンデンサの一方の電極を複数に分割して各基板パターンにそれぞれ接続し、該高周波用コンデンサを跨ぐように各基板パターン上に設けた金属導体を介して各基板パターンに該低周波コンデンサの各電極をそれぞれ電気的に接続したことを特徴とする広帯域直流成分除去回路。
（付記７）
誘電体基板上で間隔を置いて向き合った基板パターン間に、共に並行平板型の高周波用コンデンサと低周波用コンデンサを並列に接続した広帯域直流成分除去回路において、
該基板パターンの一方の上に該高周波用コンデンサを載置してその一方の電極を接続し、他方の電極を金属導体により該基板パターンの他方と接続し、さらに該高周波用コンデンサ及び該金属導体を跨ぐように各基板パターン上に設けた金属導体を介して該基板パターンに該低周波用コンデンサの各電極をそれぞれ電気的に接続したことを特徴とする広帯域直流成分除去回路。
（付記８）付記１から７のいずれか１つにおいて、
該金属導体が、金リボン又は金ワイヤであることを特徴とした広帯域直流成分除去回路。
（付記９）
誘電体基板上で間隔を置いて向き合った基板パターン間に、共に並行平板型の高周波用コンデンサと低周波用コンデンサを並列に接続した広帯域直流成分除去回路の組立方法において、
該基板パターン間の該基板中に設けた溝に該高周波用コンデンサを埋め込むと共に、該高周波用コンデンサの各電極と各基板パターンを金属導体で接続し、その上方に該低周波用コンデンサを載置して各基板パターンと該低周波用コンデンサの電極をそれぞれ電気的に接続したことを特徴とする広帯域直流成分除去回路の組立方法。
（付記１０）付記９において、
該低周波用コンデンサにセラミックコンデンサ、該高周波用コンデンサにマイクロチップコンデンサを用い、該マイクロチップコンデンサを、その縦長の深さを有する該溝内に縦方向に埋め込むことを特徴とした広帯域直流成分除去回路の組立方法。
（付記１１）
誘電体基板上で間隔を置いて向き合った基板パターン間に、共に並行平板型の高周波用コンデンサと低周波用コンデンサを並列に接続した広帯域直流成分除去回路の組立方法において、
該基板パターン間に該高周波用コンデンサの電極間間隔に相当する深さの溝を該基板内に設け、該基板パターンの内の一方を該溝内に設けた溝パターンと接続し、その溝パターンと該高周波用コンデンサの一方の電極が接触するように該高周波用コンデンサを該溝内に埋め込み、該基板パターンの他方と該高周波用コンデンサの他方の電極を金属導体で接続し、さらに該他方の電極と該基板パターンの他方にそれぞれ該低周波用コンデンサの各電極を電気的に接続したことを特徴とする広帯域直流成分除去回路の組立方法。
（付記１２）付記１１において、
該溝パターンを該基板中に延長し、該溝パターンの延長部分とその延長方向に存在する該基板パターンの一方との接続を、誘電体基板内に設けたビアにより行うことを特徴とした広帯域直流成分除去回路の組立方法。
（付記１３）
誘電体基板上で間隔を置いて向き合った基板パターン間に、高周波用コンデンサと低周波用コンデンサを並列に接続した広帯域直流成分除去回路の組立方法において、
該誘電体基板が第１の層を形成し、該基板パターンの一方をビアで第２の層の誘電体基板上の基板パターンに接続し、該第２の層の基板パターンと該第１の層の基板パターンの他方との間に該第１の層の誘電体基板を挟み込むことにより該高周波コンデンサを形成し、さらに該第１の層の各基板パターン間に低周波用コンデンサを載置して各基板パターンにそれぞれ該低周波用コンデンサの各電極を電気的に接続したことを特徴とする広帯域直流成分除去回路の組立方法。
（付記１４）
誘電体基板上で間隔を置いて向き合った基板パターン間に、共に並行平板型の高周波用コンデンサと低周波用コンデンサを並列に接続した広帯域直流成分除去回路の組立方法において、
該高周波用コンデンサの一方の電極を複数に分割して各基板パターンにそれぞれ接続し、該高周波用コンデンサを跨ぐように各基板パターン上に設けた金属導体を介して各基板パターンに該低周波コンデンサの各電極をそれぞれ電気的に接続したことを特徴とする広帯域直流成分除去回路の組立方法。
（付記１５）
誘電体基板上で間隔を置いて向き合った基板パターン間に、共に並行平板型の高周波用コンデンサと低周波用コンデンサを並列に接続した広帯域直流成分除去回路の組立方法において、
該基板パターンの一方の上に該高周波用コンデンサを載置してその一方の電極を接続し、他方の電極を金属導体により該基板パターンの他方と接続し、さらに該高周波用コンデンサ及び該金属導体を跨ぐように各基板パターン上に設けた金属導体を介して該基板パターンに該低周波用コンデンサの各電極をそれぞれ電気的に接続したことを特徴とする広帯域直流成分除去回路の組立方法。
（付記１６）付記９から１５のいずれか１つにおいて、
該金属導体が、金リボン又は金ワイヤであることを特徴とした広帯域直流成分除去回路の組立方法。
【００４０】
【発明の効果】
以上説明したように、本発明によれば、高周波用のコンデンサと低周波用のコンデンサを並列に接続した広帯域直流成分除去回路及びその組立方法において、高周波損失の増加の原因となる金リボンや金ワイヤーなどの金属導体の長さを短くすることができ、高周波特性を向上させることができると共に、回路の組立を容易に行うことが可能となる。
【図面の簡単な説明】
【図１】本発明の概略図（１）を示した断面図である。
【図２】本発明の概略図（２）を示した断面図である。
【図３】本発明の概略図（３）を示した断面図である。
【図４】本発明の概略図（４）を示した断面図である。
【図５】本発明の概略図（５）を示した断面図である。
【図６】本発明の概略図（６）を示した断面図である。
【図７】本発明の実施例（１）を示した斜視外観図である。
【図８】本発明の実施例（２）を示した斜視外観図である。
【図９】本発明の実施例（３）を示した斜視外観図である。
【図１０】本発明の実施例（４）を示した斜視外観図である。
【図１１】本発明の実施例（５）を示した斜視外観図である。
【図１２】本発明の実施例（６）を示した斜視外観図である。
【図１３】本発明の実施例（７）を示した斜視外観図である。
【図１４】積層コンデンサを誘電体基板上のパターン間に接続した従来例（１）を示した斜視外観図である。
【図１５】並行平板コンデンサを一方の基板パターン上に接続し、電極と基板パターンを金リボンにより接続した従来例（２）を示した斜視外観図である。
【図１６】基板パターン間を横方向に並列に配置した積層コンデンサと並行平板コンデンサにより接続した従来例（３）を示した斜視外観図である。
【図１７】並行平板コンデンサを金属導体でパターン間に接続し、並行平板コンデンサと他方のパターンをセラミックコンデンサで接続することにより両コンデンサを並列接続した従来例（４）を示した斜視外観図である。
【図１８】広帯域直流成分除去回路の簡略化した等価回路図である。
【図１９】図１８の等価回路における伝送特性のシミュレーション結果を示したグラフ図である。
【符号の説明】
１誘電体基板
２ａ，２ｂ基板上パターン
３高周波用コンデンサ
３ａ，３ｂ，３ｂ１，３ｂ２電極
４低周波用コンデンサ
４ａ，４ｂ電極
５溝
６，９金属導体（金リボン、金ワイヤー）
７ビア
８溝内パターン
１２ａ，１２ｂ金属導体
１２ａ，１２ｂ金ブロック
１０，１１高誘電体層
図中、同一符号は同一又は相当部分を示す。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a broadband DC component removing circuit, and particularly removes a DC component in a wide band by connecting a high-frequency capacitor in a microwave or millimeter wave band in parallel with a low-frequency capacitor in a high-speed optical communication device and a measuring instrument. (DC cut).
[0002]
[Prior art]
In order to remove a DC component in an electronic circuit in an optical communication device, a structure is adopted in which a capacitor is connected between two patterns facing each other on a dielectric substrate, as shown in a conventional example (1) in FIG. A method for connecting the electrodes 4a and 4b of the parallel plate type capacitor 4 between the patterns 2a and 2b for efficiently transmitting low frequency, and a parallel plate type capacitor for high frequency as shown in the prior art (2) of FIG. One electrode 3b of the capacitor 3 is mounted on and connected to one pattern 2a, and the other pattern 2b is connected to the other electrode 3a of the capacitor 3 by a gold ribbon or a gold wire 9.
[0003]
Further, with the increase in communication speed, wideband characteristics (several KHz to several tens of GHz) have been required. As shown in the conventional example (3) in FIG. 16, the conventional example (1) in FIG. 14 and the conventional example (1) in FIG. As shown in the conventional example (4) of FIG. 17 (for example, see Patent Document 1), the pattern 2a and the high-frequency A method has been used in which the high-frequency capacitor 3 and the low-frequency capacitor 4 are connected in parallel by electrically connecting the electrodes 4a and 4b of the low-frequency capacitor 4 to the electrode 3a of the capacitor 3, respectively.
[0004]
Further, there is a device in which a transfer characteristic is improved by removing a part of a high-frequency ground on a high-frequency substrate or a rear surface in a range where a plurality of coupling capacitors are mounted (for example, see Patent Document 2).
Furthermore, in order to obtain a chip capacitor having excellent high-frequency characteristics, a first electrode is provided from the upper surface of the substrate having the concave portion to the concave portion, and a dielectric is provided in the concave portion of the substrate. Are electrically connected (for example, see Patent Document 3).
[0005]
Furthermore, in order to form a baseband unit for processing a baseband signal and a high-frequency unit for processing a high-frequency signal as one module, a substrate, a first electric shield line formed on the substrate, and a passive element are formed. A passive element layer formed on the first electric shield line, a second electric shield line formed on the passive element layer, and a connection conductor electrically connected to the passive element. An interconnecting layer formed on the electrical shielding wire, a third electrical shielding wire formed on the interconnecting layer, and a plurality of electrical connecting wires formed outside the third electrical shielding wire. And a multilayer multi-chip module including a large number of integrated circuits or electric elements formed on the bumper (see, for example, Patent Document 4).
[0006]
[Patent Document 1]
JP-A-5-235602 (page 3, left column, FIG. 1)
[0007]
[Patent Document 2]
JP-A-6-85511 (page 2-3, FIG. 2)
[0008]
[Patent Document 3]
JP 2000-269065 A (abstract, FIG. 1)
[0009]
[Patent Document 4]
JP 2001-244402 A (Abstract, FIG. 1)
[0010]
[Problems to be solved by the invention]
In the structure of the conventional broadband DC component removing circuit, the length of a gold (Au) ribbon or a gold wire connecting between a high-frequency capacitor and a pattern on a dielectric substrate needs to be longer than the height of a parallel plate type capacitor. Therefore, there is a problem that impedance matching of the L component, which increases in proportion to the length thereof, and the connection portion cannot be obtained, thereby increasing the loss in a high frequency band.
[0011]
In addition, as the demand for high-frequency characteristics increases, the parasitic capacitance needs to be reduced, and the miniaturization of elements and high-density mounting have progressed, so that a gold ribbon is connected to one of the electrodes of a parallel-plate high-frequency capacitor. In addition to this, there is a problem that mounting on a dielectric substrate becomes difficult, such as the necessity of laminating a low-frequency capacitor.
[0012]
Accordingly, the present invention provides a broadband DC component removing circuit in which a high-frequency capacitor and a low-frequency capacitor are connected in parallel between substrate patterns facing each other at an interval on a dielectric substrate, and a method for assembling the same. It is an object of the present invention to realize a structure that is easy to mount by reducing the connection length of a metal conductor such as a gold ribbon or a gold wire to be brought about equal to or less than a conventional example.
[0013]
[Means for Solving the Problems]
When a capacitor 4 for low frequency and a capacitor 3 for high frequency as shown in FIG. 17 are connected in parallel, and a gold ribbon 9 is used for connection between the capacitor 3 and the pattern 2b, the length of the gold ribbon 9 is 0. 0.3 mm.
[0014]
The equivalent circuit having such a structure is replaced with an LC circuit composed of a parallel circuit of two capacitors C1 and C2 and an inductance L1 as shown in FIG. The simulation of the transmission characteristics was performed by changing the value of １００ to 100 to 400 pH. As shown in the frequency characteristics (S21) of FIG. 19, the transmission characteristics were flattened by shortening the connection length of the gold ribbon or the like. It turned out that it becomes possible to approach and improve.
[0015]
The inventor has realized various means as described below.
[1] FIG. 1 shows a schematic diagram (1) of the present invention, in which a groove 5 is inserted between patterns 2a and 2b provided on a dielectric substrate 1 such that a parallel plate type high frequency capacitor 3 can be inserted. The high frequency capacitor 3 in which the metal conductors 6a and 6b are provided on both electrodes 3a and 3b is embedded in the groove 5.
[0016]
Thereafter, the metal conductors 6a and 6b are electrically connected to the patterns 2a and 2b, respectively, and a parallel plate type low frequency capacitor (not shown) is mounted thereon to mount the patterns 2a and 2b and the low frequency capacitors. A high-frequency capacitor and a low-frequency capacitor are connected in parallel to realize a broadband DC component removing circuit by electrically connecting the electrodes of the capacitor for each.
[0017]
Thereby, the metal conductors 6a and 6b connecting the high-frequency capacitor 3 and the patterns 2a and 2b are shortened, and high-frequency characteristics can be improved.
[2] In FIG. 1, a ceramic capacitor is used as a low-frequency capacitor, a microchip capacitor is used as a high-frequency capacitor, and a gold ribbon as metal conductors 6a and 6b is connected to electrodes 3a and 3b by ribbon bonding or the like. The gold ribbons 6a, 6b can be connected to the patterns 2a, 2b by ribbon bonding with the ends of the gold ribbons 6a, 6b open to both sides.
[0018]
[3] FIG. 2 shows a schematic diagram (2) of the present invention, in which a groove 5 having a height corresponding to the interelectrode interval of the high-frequency capacitor 3 is provided in the substrate 1 between the patterns 2a and 2b. 2b is connected to the pattern 8 provided in the groove 5, the capacitor 3 is embedded so that one electrode 3b of the high-frequency capacitor 3 is in contact with the pattern 8 in the groove 5, and the other pattern 2a is connected to the high-frequency capacitor. 3 is connected to the other electrode 3a with a gold ribbon or a gold wire as a metal conductor 9, and a low-frequency capacitor (not shown) is further mounted thereon, and the respective patterns 2a, 2b and the low-frequency By electrically connecting each electrode of the capacitor for high frequency, a high frequency capacitor and a capacitor for low frequency are connected in parallel to realize a broadband DC component removing circuit.
[0019]
Thereby, the gold ribbon or the gold wire, which is the metal conductor connected to the high-frequency capacitor, can be shortened, and the high-frequency characteristics can be improved.
[4] FIG. 3 shows a schematic view (3) of the present invention. In the same structure as in the above [3], the pattern 8 in the groove 5 is extended into the substrate 1, and the one pattern 2b in the extending direction is extended. And an extended portion of the pattern 8 are connected by a via 7 provided in the substrate 1. As a function similar to the above [3], a gold ribbon or a gold wire as a metal conductor 9 connected to a high-frequency capacitor is provided. Can be shortened, and high-frequency characteristics can be improved.
[0020]
[5] FIG. 4 shows a schematic view (4) of the present invention, in which the substrate 1 is a dielectric multilayer substrate. That is, one of the opposed patterns 2a and 2b is connected to the pattern 8 on the second layer dielectric substrate 11 by the via 7 provided on the first layer dielectric substrate 10, and the other of the pattern 8 and the other is The high frequency capacitor is formed by sandwiching the dielectric substrate 10 between the substrate pattern 2a and the substrate pattern 2a.
[0021]
By mounting a low-frequency capacitor (not shown) between the upper patterns 2a and 2b, connection by a gold ribbon or a gold wire as a metal conductor is eliminated, and deterioration of high-frequency characteristics is prevented. Also, the mounting of the low-frequency capacitor becomes easy.
[0022]
[6] FIG. 5 shows a schematic view (5) of the present invention, in which the electrodes on one side of the high-frequency parallel plate capacitor 3 are divided into a plurality of parts to provide electrodes 3b1 and 3b2, and these are formed into patterns 2a and 2b, respectively. Connecting. Then, each electrode of a low-frequency capacitor (not shown) is connected to the pattern 2a, 2b via a metal conductor provided on the pattern 2a, 2b so as to straddle the capacitor 3.
[0023]
As a result, the connection of the gold ribbon or the gold wire as the metal conductor to the high-frequency capacitor can be eliminated, and the deterioration of the high-frequency characteristics can be prevented.
[7] FIG. 6 shows a schematic diagram (6) of the present invention, in which the capacitor 3 is mounted on the pattern 2a such that one electrode 3b of the high-frequency capacitor 3 contacts one of the opposed patterns 2a, 2b. And the other electrode 3a is electrically connected to the other pattern 2b by a gold ribbon 9 or a wire, which is a metal conductor, and a low-frequency capacitor 4 is further placed thereon via the metal conductors 12a and 12b. Laminate.
[0024]
That is, the metal conductors 12a and 12b are provided on the patterns 2a and 2b respectively so as to straddle the high-frequency capacitor 3 and the gold ribbon 9, and the electrodes 4a and 4b are electrically connected to the metal conductors 12a and 12b, respectively. The low-frequency capacitor 4 is placed.
Thus, the low-frequency capacitor 4 can be arranged three-dimensionally with respect to the high-frequency capacitor 3 and the gold ribbon 9, so that assembly can be easily performed.
[0025]
[8] In FIG. 1, at the time of capacitive coupling between two opposed patterns 2a and 2b on the dielectric substrate 1, one end is connected to both electrodes of the parallel plate type capacitor 3 by bonding a metal conductor to both electrodes. The low-frequency capacitors are mounted on the two opposing patterns 2a and 2b with the opposite ends extended, and the patterns 2a and 2b and the electrodes of the low-frequency capacitors are electrically connected to each other. By using a method of assembling a broadband DC component removing circuit in which a high-frequency capacitor and a low-frequency capacitor are connected in parallel, it is possible to shorten the connection length of the metal conductor.
[0026]
Similarly, according to the concepts [1] to [7], the method of assembling the broadband DC component removing circuit according to the present invention can be realized.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Example (1)
FIG. 7 shows an embodiment (1) of the present invention corresponding to the schematic diagram (1) shown in FIG. 1. A parallel plate type low frequency capacitor 4 is a ceramic capacitor, and a parallel plate type high frequency capacitor. 3 uses a microchip capacitor.
[0028]
Then, gold ribbons 6a, 6b are bonded to both surfaces of the microchip capacitor 3, that is, the electrodes 3a, 3b, and the grooves 5 dug in the substrate 1 between the patterns 2a, 2b at a height corresponding to the vertically long portion of the capacitor 3. The capacitor 3 in the vertical direction. At that time, the microchip capacitor 3 is fixed with an adhesive at the bottom of the groove 5 as necessary.
[0029]
Thereafter, the gold ribbons 6a, 6b are bonded to the patterns 2a, 2b, respectively, and the electrodes 4a, 4b of the ceramic capacitor 4 are connected to the patterns 2a, 2b with gold tin (AuSn).
In this manner, the length of the gold ribbons 6a and 6b can be made equal to or less than the height of the microchip capacitor 3, and the high-frequency characteristics are improved.
[0030]
Example (2)
FIG. 8 shows an embodiment (2) of the present invention corresponding to the schematic diagram (2) shown in FIG. 2, in which a microchip as a high-frequency capacitor is provided in the substrate 1 between the patterns 2a and 2b on the substrate 1. A groove 5 having a height corresponding to the distance between the electrodes 3a and 3b of the capacitor 3 is dug, and one pattern 2b is connected to a pattern 8 provided at the bottom of the groove 5 along a wall portion of the groove 5, and the groove is formed. The electrode 3b of the microchip capacitor 3 is connected to the inner pattern 8 with gold tin, and the other pattern 2a is electrically connected to the electrode 3a on the upper surface of the microchip capacitor 3a with a gold ribbon 9.
[0031]
Then, the electrodes 4b and 4a of the ceramic capacitor 4 are connected to the opposite pattern 2b and the upper surface electrode 3a of the microchip capacitor 3 by gold and tin, respectively.
In this manner, the height of the electrode 3a surface of the microchip capacitor 3 and the height of the patterns 2a and 2b can be matched, and the length of the gold ribbon 9 connecting them can be reduced by the conventional example shown in FIGS. Compared with (3) and (4), the height can be shortened by the height of the microchip capacitor 3, and the high-frequency characteristics are improved.
[0032]
Example (3)
FIG. 9 shows an embodiment (3) of the present invention corresponding to the schematic diagram (3) shown in FIG. 3, and is different from the embodiment (2) of FIG. The connection with the pattern 8 is not extended along the wall of the groove 5 but the pattern 8 is extended into the dielectric substrate 1 and the extended portion and the pattern 2b in the extending direction are connected by the via 7. It is.
[0033]
8, the height directions of the electrodes 3a and 3b of the microchip capacitor 3 and the surfaces of the patterns 2a and 2b can be matched, and the length of the gold ribbon 9 connecting them can be reduced. In comparison with the above, the height of the microchip capacitor 3 can be shortened by about the height, and the high frequency characteristics are improved.
[0034]
Example (4)
FIG. 10 shows an embodiment (4) of the present invention corresponding to the schematic diagram (3) shown in FIG. 4, in which one of the patterns 2a and 2b facing each other on the dielectric substrate 10 is layered by a via 7 below. To the pattern 8 on the dielectric substrate 11. At this time, since a high dielectric substance by the substrate 10 is interposed between the pattern 8 and the other substrate pattern 2a, a high-frequency capacitor is formed between the two patterns 8-2a. Then, the electrodes 4a and 4b of the ceramic capacitor 4 are connected between the patterns 2a and 2b on the surface with gold and tin.
[0035]
In this way, the connection by the gold ribbon is eliminated, and the high-frequency characteristics are improved. Also, there is no need to separately prepare a high-frequency capacitor as an element, and the number of assembling steps can be reduced.
Example (5)
FIG. 11 shows an embodiment (5) of the present invention corresponding to the schematic diagram (5) shown in FIG. 5, in which the lower electrode of the microchip capacitor 3 is divided into, for example, two electrodes 3b1 and 3b2. deep. Then, the electrodes 3b1 and 3b2 are connected to the patterns 2a and 2b on the substrate 1 with gold and tin, respectively, and the high frequency capacitor 3 is connected between the patterns 2a and 2b.
[0036]
Thereafter, gold blocks 12a and 12b as metal conductors are placed on both sides of the microchip capacitor 3, and are connected to the patterns 2a and 2b with gold tin, respectively. Further, the ceramic capacitor 4 is laminated between the upper surfaces of the gold blocks 12a and 12b, and the electrodes 4a and 4b are connected by gold tin.
[0037]
In this way, the electrode surface of the microchip capacitor can be directly connected in pattern without using a gold ribbon or the like, so that high-frequency characteristics are improved.
Example (6)
FIG. 12 shows an embodiment (6) of the present invention corresponding to the schematic view (6) shown in FIG. 6. In this case, the entire surface of the electrode 3b of the microchip capacitor 3 is provided at one end of one pattern 2a. Are connected by gold tin, and the electrode 3a on the upper surface is connected to the other pattern 2b by the gold ribbon 9.
[0038]
Up to this point, this is the same as the conventional example (4) shown in FIG. 17, but in this embodiment, gold blocks 12a and 12b are placed on both sides of the capacitor 3 and gold tin and gold tin are added to the patterns 2a and 2b, respectively. The ceramic capacitors 4 are stacked between the upper surfaces of the gold blocks 12a and 12b, respectively, and the electrodes 4a and 4b are connected by gold and tin in the same manner as in the embodiment (5).
[0039]
In this way, it is not necessary to connect both the ceramic capacitor and the gold ribbon to one electrode surface of the microchip capacitor 3, and the assembly is facilitated.
Example (7)
FIG. 13 shows an embodiment (7) of the present invention corresponding to the schematic diagram (7) shown in FIG. 7. Here, instead of the gold blocks 12a and 12b in FIG. Are intended to be fulfilled by the extended electrodes 4a and 4b, and have the same effect.
(Appendix 1)
In a broadband DC component removal circuit in which a parallel plate type high frequency capacitor and a low frequency capacitor are connected in parallel between substrate patterns facing each other at intervals on a dielectric substrate,
The high-frequency capacitor is embedded in a groove provided in the substrate between the substrate patterns, and each electrode of the high-frequency capacitor is connected to each substrate pattern by a metal conductor, and the low-frequency capacitor is mounted above the high-frequency capacitor. A broadband DC component removing circuit, wherein each substrate pattern is electrically connected to an electrode of the low-frequency capacitor.
(Supplementary Note 2) In Supplementary Note 1,
A wideband DC component removing device characterized in that a ceramic capacitor is used as the low-frequency capacitor and a microchip capacitor is used as the high-frequency capacitor, and the microchip capacitor is vertically embedded in the groove having a vertically long depth. circuit.
(Appendix 3)
In a broadband DC component removal circuit in which a parallel plate type high frequency capacitor and a low frequency capacitor are connected in parallel between substrate patterns facing each other at intervals on a dielectric substrate,
A groove having a depth corresponding to the distance between the electrodes of the high-frequency capacitor is provided in the substrate between the substrate patterns, and one of the substrate patterns is connected to the groove pattern provided in the groove, and the groove pattern is formed. The high-frequency capacitor is embedded in the groove so that one electrode of the high-frequency capacitor contacts the other electrode of the high-frequency capacitor, and the other electrode of the high-frequency capacitor is connected to the other electrode of the high-frequency capacitor with a metal conductor. A broadband DC component removing circuit, wherein each electrode of the low-frequency capacitor is electrically connected to the other of the electrode and the substrate pattern.
(Supplementary Note 4) In supplementary note 3,
The groove pattern is extended into the substrate, and connection between an extended portion of the groove pattern and one of the substrate patterns existing in the extension direction is performed by a via provided in a dielectric substrate. DC component removal circuit.
(Appendix 5)
In a broadband DC component removal circuit in which a high-frequency capacitor and a low-frequency capacitor are connected in parallel between substrate patterns facing each other at intervals on a dielectric substrate,
The dielectric substrate forms a first layer, one of the substrate patterns is connected to a substrate pattern on a second layer dielectric substrate by a via, and the second layer substrate pattern is connected to the first layer. The high-frequency capacitor is formed by sandwiching the dielectric substrate of the first layer between the other of the substrate patterns of the layer, and the low-frequency capacitor is mounted between the substrate patterns of the first layer. A broadband DC component removing circuit, wherein each electrode of the low-frequency capacitor is electrically connected to each substrate pattern.
(Appendix 6)
In a broadband DC component removal circuit in which a parallel plate type high frequency capacitor and a low frequency capacitor are connected in parallel between substrate patterns facing each other at intervals on a dielectric substrate,
One electrode of the high-frequency capacitor is divided into a plurality of parts and connected to each substrate pattern, and the low-frequency capacitor is connected to each substrate pattern via a metal conductor provided on each substrate pattern so as to straddle the high-frequency capacitor. Wherein the electrodes are electrically connected to each other.
(Appendix 7)
In a broadband DC component removal circuit in which a parallel plate type high frequency capacitor and a low frequency capacitor are connected in parallel between substrate patterns facing each other at intervals on a dielectric substrate,
The high-frequency capacitor is placed on one of the substrate patterns, one of the electrodes is connected, the other electrode is connected to the other of the substrate patterns by a metal conductor, and the high-frequency capacitor and the metal conductor are connected. A broadband DC component removing circuit, wherein each electrode of the low-frequency capacitor is electrically connected to the substrate pattern via a metal conductor provided on each substrate pattern so as to straddle the substrate.
(Supplementary Note 8) In any one of Supplementary Notes 1 to 7,
A wide-band DC component removing circuit, wherein the metal conductor is a gold ribbon or a gold wire.
(Appendix 9)
In a method of assembling a broadband DC component removing circuit in which a parallel plate type high frequency capacitor and a low frequency capacitor are connected in parallel between substrate patterns facing each other at intervals on a dielectric substrate,
The high-frequency capacitor is embedded in a groove provided in the substrate between the substrate patterns, and each electrode of the high-frequency capacitor is connected to each substrate pattern by a metal conductor, and the low-frequency capacitor is mounted above the high-frequency capacitor. A method for assembling a broadband DC component removing circuit, wherein each substrate pattern is electrically connected to an electrode of the low-frequency capacitor.
(Supplementary Note 10) In Supplementary Note 9,
A wideband DC component removing device characterized in that a ceramic capacitor is used as the low-frequency capacitor and a microchip capacitor is used as the high-frequency capacitor, and the microchip capacitor is vertically embedded in the groove having a vertically long depth. How to assemble the circuit.
(Appendix 11)
In a method of assembling a broadband DC component removing circuit in which a parallel plate type high frequency capacitor and a low frequency capacitor are connected in parallel between substrate patterns facing each other at intervals on a dielectric substrate,
A groove having a depth corresponding to the distance between the electrodes of the high-frequency capacitor is provided in the substrate between the substrate patterns, and one of the substrate patterns is connected to the groove pattern provided in the groove, and the groove pattern is formed. The high-frequency capacitor is embedded in the groove so that one electrode of the high-frequency capacitor contacts the other electrode of the high-frequency capacitor, and the other electrode of the high-frequency capacitor is connected to the other electrode of the high-frequency capacitor with a metal conductor. A method for assembling a broadband DC component removing circuit, wherein each electrode of the low-frequency capacitor is electrically connected to the other of the electrode and the substrate pattern.
(Supplementary Note 12) In Supplementary Note 11,
The groove pattern is extended into the substrate, and connection between an extended portion of the groove pattern and one of the substrate patterns existing in the extension direction is performed by a via provided in a dielectric substrate. How to assemble a DC component removal circuit.
(Appendix 13)
In a method of assembling a broadband DC component removing circuit in which a high-frequency capacitor and a low-frequency capacitor are connected in parallel between substrate patterns facing each other at intervals on a dielectric substrate,
The dielectric substrate forms a first layer, one of the substrate patterns is connected to a substrate pattern on a second layer dielectric substrate by a via, and the second layer substrate pattern is connected to the first layer. The high-frequency capacitor is formed by sandwiching the dielectric substrate of the first layer between the other of the substrate patterns of the layer, and the low-frequency capacitor is mounted between the substrate patterns of the first layer. A method for assembling a broadband DC component removing circuit, wherein each electrode of the low-frequency capacitor is electrically connected to each substrate pattern.
(Appendix 14)
In a method of assembling a broadband DC component removing circuit in which a parallel plate type high frequency capacitor and a low frequency capacitor are connected in parallel between substrate patterns facing each other at intervals on a dielectric substrate,
One electrode of the high-frequency capacitor is divided into a plurality of parts and connected to each substrate pattern, and the low-frequency capacitor is connected to each substrate pattern via a metal conductor provided on each substrate pattern so as to straddle the high-frequency capacitor. A method for assembling a broadband DC component removing circuit, wherein the electrodes are electrically connected to each other.
(Appendix 15)
In a method of assembling a broadband DC component removing circuit in which a parallel plate type high frequency capacitor and a low frequency capacitor are connected in parallel between substrate patterns facing each other at intervals on a dielectric substrate,
The high-frequency capacitor is placed on one of the substrate patterns, one of the electrodes is connected, the other electrode is connected to the other of the substrate patterns by a metal conductor, and the high-frequency capacitor and the metal conductor are connected. A method of assembling a broadband DC component removing circuit, wherein each electrode of the low-frequency capacitor is electrically connected to the substrate pattern via a metal conductor provided on each substrate pattern so as to straddle the substrate.
(Supplementary Note 16) In any one of Supplementary Notes 9 to 15,
The method for assembling a broadband DC component removing circuit, wherein the metal conductor is a gold ribbon or a gold wire.
[0040]
【The invention's effect】
As described above, according to the present invention, in a broadband DC component removing circuit in which a high-frequency capacitor and a low-frequency capacitor are connected in parallel and a method of assembling the same, a gold ribbon or a gold that causes an increase in high-frequency loss is provided. The length of a metal conductor such as a wire can be reduced, the high-frequency characteristics can be improved, and the circuit can be easily assembled.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a schematic diagram (1) of the present invention.
FIG. 2 is a sectional view showing a schematic view (2) of the present invention.
FIG. 3 is a sectional view showing a schematic view (3) of the present invention.
FIG. 4 is a sectional view showing a schematic view (4) of the present invention.
FIG. 5 is a sectional view showing a schematic view (5) of the present invention.
FIG. 6 is a sectional view showing a schematic view (6) of the present invention.
FIG. 7 is a perspective external view showing an embodiment (1) of the present invention.
FIG. 8 is a perspective external view showing an embodiment (2) of the present invention.
FIG. 9 is a perspective external view showing an embodiment (3) of the present invention.
FIG. 10 is a perspective external view showing an embodiment (4) of the present invention.
FIG. 11 is a perspective external view showing an embodiment (5) of the present invention.
FIG. 12 is a perspective external view showing an embodiment (6) of the present invention.
FIG. 13 is a perspective external view showing an embodiment (7) of the present invention.
FIG. 14 is a perspective external view showing a conventional example (1) in which a multilayer capacitor is connected between patterns on a dielectric substrate.
FIG. 15 is a perspective external view showing a conventional example (2) in which a parallel plate capacitor is connected on one substrate pattern and an electrode and the substrate pattern are connected by a gold ribbon.
FIG. 16 is a perspective external view showing a conventional example (3) in which a multilayer capacitor in which substrate patterns are arranged in parallel in a horizontal direction and a parallel plate capacitor are connected.
FIG. 17 is a perspective external view showing a conventional example (4) in which a parallel plate capacitor is connected between patterns by a metal conductor and both capacitors are connected in parallel by connecting the parallel plate capacitor and the other pattern by a ceramic capacitor. is there.
FIG. 18 is a simplified equivalent circuit diagram of a broadband DC component removing circuit.
FIG. 19 is a graph showing a simulation result of transmission characteristics in the equivalent circuit of FIG. 18;
[Explanation of symbols]
Reference Signs List 1 Dielectric substrate 2a, 2b Pattern on substrate 3 High frequency capacitor 3a, 3b, 3b1, 3b2 Electrode 4 Low frequency capacitor 4a, 4b Electrode 5 Groove 6, 9 Metal conductor (gold ribbon, gold wire)
7 Via 8 In-groove patterns 12a, 12b Metal conductors 12a, 12b Gold blocks 10, 11 In the high dielectric layer diagrams, the same reference numerals indicate the same or corresponding parts.

Claims

In a broadband DC component removal circuit in which a parallel plate type high frequency capacitor and a low frequency capacitor are connected in parallel between substrate patterns facing each other at intervals on a dielectric substrate,
The high-frequency capacitor is embedded in a groove provided in the substrate between the substrate patterns, and each electrode of the high-frequency capacitor is connected to each substrate pattern by a metal conductor, and the low-frequency capacitor is mounted above the high-frequency capacitor. A broadband DC component removing circuit, wherein each substrate pattern is electrically connected to an electrode of the low-frequency capacitor.

In a broadband DC component removal circuit in which a parallel plate type high frequency capacitor and a low frequency capacitor are connected in parallel between substrate patterns facing each other at intervals on a dielectric substrate,
A groove having a depth corresponding to the distance between the electrodes of the high-frequency capacitor is provided in the substrate between the substrate patterns, and one of the substrate patterns is connected to the groove pattern provided in the groove, and the groove pattern is formed. The high-frequency capacitor is embedded in the groove so that one electrode of the high-frequency capacitor contacts the other electrode of the high-frequency capacitor, and the other electrode of the high-frequency capacitor is connected to the other electrode of the high-frequency capacitor with a metal conductor. A broadband DC component removing circuit, wherein each electrode of the low-frequency capacitor is electrically connected to the other of the electrode and the substrate pattern.

In a broadband DC component removal circuit in which a high-frequency capacitor and a low-frequency capacitor are connected in parallel between substrate patterns facing each other at intervals on a dielectric substrate,
The dielectric substrate forms a first layer, one of the substrate patterns is connected to a substrate pattern on a second layer dielectric substrate by a via, and the second layer substrate pattern is connected to the first layer. The high-frequency capacitor is formed by sandwiching the dielectric substrate of the first layer between the other of the substrate patterns of the layer, and the low-frequency capacitor is mounted between the substrate patterns of the first layer. A broadband DC component removing circuit, wherein each electrode of the low-frequency capacitor is electrically connected to each substrate pattern.

In a broadband DC component removal circuit in which a parallel plate type high frequency capacitor and a low frequency capacitor are connected in parallel between substrate patterns facing each other at intervals on a dielectric substrate,
One electrode of the high-frequency capacitor is divided into a plurality of parts and connected to each substrate pattern, and the low-frequency capacitor is connected to each substrate pattern via a metal conductor provided on each substrate pattern so as to straddle the high-frequency capacitor. Wherein the electrodes are electrically connected to each other.

In a method of assembling a broadband DC component removing circuit in which a parallel plate type high frequency capacitor and a low frequency capacitor are connected in parallel between substrate patterns facing each other at intervals on a dielectric substrate,
The high-frequency capacitor is embedded in a groove provided in the substrate between the substrate patterns, and each electrode of the high-frequency capacitor is connected to each substrate pattern by a metal conductor, and the low-frequency capacitor is mounted above the high-frequency capacitor. A method for assembling a broadband DC component removing circuit, wherein each substrate pattern is electrically connected to an electrode of the low-frequency capacitor.