JP2004282088A - Silicon wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitrogen doped annealed wafer which exhibits low defect density even in inspection under severe conditions and also has less variations by the manufacturing conditions. <P>SOLUTION: A silicon wafer is constituted without forming an epitaxial layer on its surface, and LSTDs existing on a front layer of the wafer whose size is 50 nm or more is 0.24 pieces/cm<SP>2</SP>or less. The silicon wafer is manufactured by pulling-up a nitrogen-doped silicon single crystal by CZ method changing V/G and/or PT, by making the wafer from the single crystal, by judging acceptability based on a prescribed characteristic property after heat treatment, by calculating a correlation between the acceptability judgement and the V/G and PT, and by deciding the manufacturing conditions based on the correlation. The silicon wafer is manufactured by pulling-up a silicon single crystal whose V/G is lower than the V/G and whose PT is shorter than the PT of the single crystal primarily decided by setting nitrogen concentration and oxygen concentration in the silicon single crystal and the heat treatment conditions applied to the silicon wafer to prescribed values, and by setting the defect density of the wafer to a prescribed value. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a conventional epitaxial wafer, an annealed wafer, a silicon wafer having a lower grown-in defect density than a whole N region wafer, a method for determining its manufacturing conditions, and a manufacturing method thereof. The present invention relates to a method for determining the conditions for producing a silicon single crystal for stably producing a silicon wafer having a low grown-in defect density, which is produced by subjecting a silicon wafer produced from a heat treatment to heat treatment, and a method for producing the same.

  In recent years, along with the miniaturization of circuit elements accompanying the high integration of semiconductor circuits, quality requirements for silicon single crystals, which are substrates formed by the CZ method, are increasing. In particular, single-crystal defects, such as FPD (Flow Pattern Defect), LSTD (Laser Scattering Tomography Defect), and COP (Crystal Originated Particle), are referred to as “Grown-in defects”, which degrade the oxide film breakdown voltage characteristics and the characteristics of device growth, which degrade the oxide film breakdown voltage characteristics and device characteristics. And its reduction is regarded as important.

  Therefore, an epitaxial wafer in which a new silicon layer is epitaxially grown on a normal silicon wafer, an annealed wafer subjected to a heat treatment at a high temperature in a hydrogen and argon atmosphere, and a growth condition of a CZ-Si single crystal are improved. Some crystals with few Grown-in defects, such as the entire wafer N region (the region outside the OSF ring and without dislocation clusters), have been developed.

  In addition, there is a demand for additional gettering capability in order to remove contamination due to impurities during the device process. For this purpose, additional heat treatment or doping of impurities such as nitrogen and carbon in the bulk is required. A wafer that promotes oxygen precipitation and has an IG (Intrinsic Gettering) effect has also been developed.

  Among these, a wafer obtained by annealing a nitrogen-doped wafer (hereinafter referred to as a nitrogen-doped annealed wafer) is a wafer in which the grown-in defects on the surface layer of the wafer are reduced and the BMD (Bulk Micro Defect) density in the bulk is high. As very informative. This is a wafer that has been developed using the effect of suppressing the agglomeration of grown-in defects by nitrogen doping and the effect of accelerating the precipitation of oxygen. Since the size of defects is smaller than that of a normal crystal, the elimination efficiency of surface defects by annealing is good. The wafer has a high BMD density in the bulk and an effective gettering ability.

  However, when a high-precision defect evaluation device such as MO-601 (manufactured by Mitsui Mining & Smelting Co., Ltd.) is used for these low-defect silicon wafers, it can be seen that defects exist even though the density is low. Here, the MO-601 is a high-precision defect evaluation apparatus having a function capable of measuring an extremely fine defect having a size of about 50 nm and further capable of evaluating a defect up to 5 μm in a depth direction.

When such a defect evaluation apparatus evaluates a defect (LSTD) having a size of 50 nm or more up to, for example, a depth of 5 μm, about 40/6 ″ wafers are obtained for a normal epitaxial wafer and a wafer epitaxially grown on a nitrogen-doped wafer. (0.23 pieces / cm ²⁾ approximately, the annealed wafer about 3000/6 "wafer (17 pieces / cm ²⁾ approximately, the entire surface N region wafer was entirely N regions wafer and nitrogen-doped to about 70/6 "Wafer (0.40 / cm ² ) defects exist. Since these defects are extremely fine in size, they are often not a problem in current ordinary level device processes. Or it will always be a problem for future devices.

Among these low-defect wafers, the nitrogen-doped annealed wafer has the advantages of the above-described effect of suppressing the aggregation of the grown-in defects and the effect of accelerating the oxygen precipitation, and an annealing process for erasing defects that are not present in epi-wafers or improved CZ wafers. It is considered that the presence of the process has the potential to significantly reduce the grown-in defects. However, in the case of the current nitrogen-doped annealed wafer, there is a large variation in the defect density for each production lot, and according to the measurement using the MO-601, even at the smallest case, about 140 wafers / 6 "wafer (0.79 wafers) / Cm ² ) In order to further reduce these defects and to stably produce a wafer having a low defect density, development in which crystal growth conditions and annealing conditions are balanced is necessary. become.

  By the way, research on nitrogen-doped CZ crystal, which is a raw material of nitrogen-doped annealed wafers, has been actively conducted recently, and research on the effect of suppressing the aggregation of grown-in defects and the effect of accelerating oxygen precipitation have been advanced. Hardly any data were obtained as to whether the thermal history had the same effect on the formation of the grown-in defect in the nitrogen-doped crystal as in the case of the non-doped nitrogen crystal, or was slightly different. . Therefore, even if the annealing conditions are fixed, if the pulling conditions such as the thermal history at the time of pulling the nitrogen-doped crystal fluctuate, it is expected that a large variation will occur in the defect annihilation effect after annealing.

In order to reduce such variations, it is one idea to eliminate more defects by annealing to make them extremely low defects, but it is necessary to use high-cost annealing (high-temperature long-time annealing). It is not desirable to do so. Therefore, the defects should be controlled by the crystal pulling conditions, but as described above, the crystal growth conditions have not been sufficiently studied. Until now, the wafers were pulled up under appropriate growth conditions, the wafer was annealed, and then Has been developed on an ad hoc basis, for example, to check whether a necessary area of a grown-in defect (mainly, a void defect) can be ensured, resulting in high development costs and unstable quality. .
In addition, the annealing conditions may be changed because the thermal history varies depending on the diameter of the crystal. In this case, it is necessary to optimize the crystal for the annealing conditions, but this has also been sufficiently studied. I didn't.

Therefore, the present invention has been made in view of such a problem. By controlling the grown-in defect of a nitrogen-doped crystal serving as a raw material of a nitrogen-doped annealed wafer, the defect density is small and the variation due to manufacturing conditions is small. An object is to produce a nitrogen-doped annealed wafer.
It is a further object of the present invention to provide a silicon wafer having very few surface defects despite the fact that an expensive epitaxial layer is not formed.

  The present invention for solving the above-mentioned problems is directed to a silicon wafer having no epitaxial layer formed on the surface, wherein an LSTD having a size of 50 nm or more in a surface layer portion of the silicon wafer is formed of an epitaxial layer of the silicon epitaxial wafer. The silicon wafer is characterized in that the number is smaller than that existing in the surface layer.

  As described above, although the silicon wafer of the present invention has no epitaxial layer formed on the surface, the LSTD present on the surface layer of the wafer is lower than that on the surface layer of the epitaxial layer of the epitaxial wafer. There is an advantage that a silicon wafer having a defect can be used, and there is no need for a long-time epitaxial growth heat treatment.

In this case, the surface layer may be an area at least 5 μm deep from the wafer surface.
As described above, if the surface portion of the ultra-low defect is at least 5 μm deep from the wafer surface, it is sufficient for forming a device on the wafer surface.

The present invention is also a silicon wafer having no epitaxial layer formed on the surface, wherein the LSTD having a size of 50 nm or more in the surface layer portion of the silicon wafer is 0.23 / cm ² or less. Silicon wafer.

  As described above, the silicon wafer of the present invention can be a low-defect wafer equal to or higher than the epitaxial wafer, even though the epitaxial layer is not formed on the surface. Therefore, the epitaxial growth step becomes unnecessary, and the productivity and cost of the highly integrated device are improved.

In this case, the surface layer may be a region at least from the wafer surface to a depth of at least 5 μm, and the LSTD having the size of 50 nm or more may be 0.06 / cm ² or less.
As described above, although the silicon wafer of the present invention has no epitaxial layer formed thereon, it has significantly lower defect silicon than the epitaxial wafer which is conventionally regarded as the silicon wafer having the lowest defect. It can be a wafer. Therefore, it can sufficiently withstand the use of the present or future highly integrated device.

In this case, BMD of 1.0 × 10 ⁸ / cm ³ or more can be present in the bulk portion of the silicon wafer.
As described above, if a sufficient amount of BMD exists in the bulk portion of the silicon wafer, the wafer can have a sufficient gettering effect in addition to having a low defect in the surface layer portion.

Alternatively, by performing a heat treatment, the BMD of the bulk portion of the silicon wafer can be 1.0 × 10 ⁸ / cm ³ or more.
As described above, if a sufficient amount of BMD is deposited in the bulk portion of the silicon wafer by applying the heat treatment, impurities such as heavy metals in the surface layer portion of the wafer can be removed by the heat treatment. However, if the BMD is too large, the wafer strength may be reduced. Therefore, it is preferable to set the BMD to 1 × 10 ¹² / cm ³ or less.

In this case, the heat treatment can be a heat treatment in a device manufacturing process.
As described above, the gettering heat treatment is performed not by the separate gettering heat treatment but by the device heat treatment, so that the operation can be simplified and the gettering effect can be more easily obtained.

  The present invention also relates to a method for determining the conditions for producing a silicon single crystal, comprising the steps of: pulling one or more silicon single crystals doped with nitrogen by the Czochralski method with a pulling speed V and a temperature gradient G at a solid-liquid interface. The ratio V / G and / or the passing time PT in the temperature zone where the grown-in defects are aggregated are changed and pulled up to produce a silicon wafer from the silicon single crystal, and the silicon wafer is subjected to a predetermined heat treatment. Measuring the characteristic value of the wafer, making a pass / fail judgment based on a predetermined characteristic value, obtaining a correlation between the pass / fail judgment and the V / G, PT, and determining a manufacturing condition based on the correlation. This is a method for determining the manufacturing conditions of the characteristic silicon single crystal.

As described above, a nitrogen-doped silicon single crystal is pulled up by changing the V / G and / or PT by the Czochralski method, a wafer is produced, and the pass / fail judgment based on the characteristic value of the wafer after the heat treatment and V / G The production conditions of the single crystal are determined on the basis of the correlation between the silicon single crystal and the PT. Therefore, even if inspection is performed under severe conditions, a silicon single crystal that is a nitrogen-doped annealed wafer with a low defect density and little variation due to the production conditions can be reliably obtained. Can be manufactured.
Furthermore, by obtaining various V / G and PT samples by using an appropriate HZ (hot zone: the structure inside the furnace in the CZ pulling machine), the subsequent HZ can be manufactured only once, as in the conventional method. Furthermore, even if HZ is not re-created many times, a single crystal having extremely few grown-in defects can be surely obtained, and there is an advantage that the development cost can be reduced.

In this case, the characteristic value of the silicon wafer may be a grown-in defect density or an electric characteristic on the surface of the silicon wafer.
As described above, the grown-in defect density or the electrical characteristics of the silicon wafer surface is measured as the characteristic value of the silicon wafer, and as a pass / fail criterion, a silicon single crystal is manufactured under the manufacturing conditions determined based on the criterion. Thus, a silicon single crystal having a desired grown-in defect density or electric characteristics can be stably manufactured.

In this case, the measurement of the characteristic value of the silicon wafer may be performed after polishing the surface of the silicon wafer after the heat treatment by a predetermined amount.
As described above, by measuring the characteristic value of the silicon wafer after polishing the silicon wafer surface after the heat treatment by a predetermined amount, for example, an apparatus that can measure and evaluate only a grown-in defect on the wafer surface is used. Even when the characteristic value is measured by using the method, the characteristic value at a predetermined depth from the wafer surface can be easily evaluated.

In this case, it is preferable to preset the nitrogen concentration and the oxygen concentration in the silicon single crystal when pulling up the nitrogen-doped silicon single crystal by the Czochralski method.
This is because the nitrogen concentration and the oxygen concentration are parameters closely related to the BMD density, the generation amount of the NO donor, and the like. In order to obtain desired numerical values for them, the nitrogen concentration and the oxygen concentration are set in advance. This is because it is preferable to keep it.

In this case, the nitrogen concentration and the oxygen concentration can be set from a desired BMD density.
The nitrogen concentration and the oxygen concentration are parameters directly related to the BMD density. The higher the oxygen concentration, the higher the BMD density can be. However, if the concentration is too high, there are disadvantages such as an increase in the size of the grown-in defect. This is because it is preferable to set such a value.

In this case, the nitrogen concentration can be set from a desired amount of NO donor generated.
This is because the nitrogen concentration is a value closely related to the amount of generated NO donors, and if too many NO donors are generated, a silicon single crystal having a desired resistivity may not be obtained. .

In this case, when pulling the nitrogen-doped silicon single crystal by the Czochralski method, it is preferable to pull the silicon single crystal under the condition that at least the center of the crystal is a V-rich region.
This is because if the I-rich region and the V-rich region coexist in the plane of a wafer formed from the pulled crystal, it becomes difficult to eliminate defects such as dislocation clusters existing in the I-rich region by heat treatment. That's why.

In this case, when pulling the nitrogen-doped silicon single crystal by the Czochralski method, it is preferable to pull the silicon single crystal under conditions that dislocation clusters do not occur on the entire radial surface of the pulled crystal.
In order to eliminate defects such as dislocation clusters existing in the I-rich region which are difficult to be eliminated by heat treatment, pulling conditions such as V / G are controlled so that dislocation clusters are formed over the entire surface of the pulled crystal in the radial direction. This is because it is preferable to raise under conditions that do not occur.

Further, in the pulling condition determining method of the present invention, the change of the PT can be performed by changing the pulling speed V during the pulling of the silicon single crystal.
According to such a method, it is possible to produce portions manufactured with various PTs in one silicon single crystal ingot, and at least one type of HZ may be used. Need not be designed and manufactured in various ways.

In this case, it is preferable to perform the heat treatment at 1150 ° C. or more for 1 hour or more as the predetermined heat treatment.
As described above, by subjecting the silicon single crystal manufactured under the manufacturing conditions of the present invention to heat treatment at least at 1150 ° C. or more for one hour or more, it is possible to obtain a silicon wafer with extremely low defect which has not existed conventionally. Because you can.

Further, the present invention is characterized in that a silicon single crystal is manufactured using the manufacturing conditions determined by the method for determining a silicon single crystal manufacturing condition of the present invention, and a silicon wafer is manufactured from the silicon single crystal. This is a method for manufacturing a silicon wafer.
As described above, if a silicon wafer is manufactured using a silicon single crystal manufactured under the manufacturing conditions determined by the present invention, a silicon wafer with extremely low defect, which was not obtained conventionally, can be stably manufactured without variation in quality. Can be obtained.

In this case, it is preferable to perform a heat treatment on the manufactured silicon wafer, and it is more preferable that the heat treatment is performed at 1150 ° C. or more for 1 hour or more.
As described above, the heat treatment is performed on the silicon wafer manufactured using the silicon single crystal manufactured under the manufacturing conditions determined by the present invention, and it is particularly preferable that the heat treatment is performed at 1150 ° C. or higher for 1 hour or longer. Thus, a silicon wafer having a predetermined characteristic value can be reliably obtained.
Note that these heat treatment conditions are preferably 1300 ° C. or less and 10 hours or less in consideration of durability of the heat treatment furnace, influence on wafer quality, and cost.

Further, the present invention provides a method for producing a silicon wafer, wherein a silicon wafer is produced from a silicon single crystal pulled up by doping with nitrogen by the Czochralski method, and the silicon wafer is subjected to a heat treatment.
The nitrogen concentration and the oxygen concentration in the silicon single crystal and the heat treatment conditions applied to the silicon wafer are set to predetermined values, and the grown-in defect density of the silicon wafer obtained after the heat treatment is set to a predetermined value. The ratio V / G is lower than the ratio V / G between the pulling speed V of the silicon single crystal and the temperature gradient G at the solid-liquid interface uniquely determined by the above, and the transit time PT in the temperature zone in which the grown-in defects aggregate. This is a method for manufacturing a silicon wafer, wherein a silicon single crystal is pulled up within a short PT range.

  As described above, the nitrogen concentration and oxygen concentration in the silicon single crystal, the heat treatment conditions applied to the silicon wafer, and the defect density of the silicon wafer obtained after the heat treatment are set in advance to predetermined values, and V uniquely determined therefrom. By pulling a silicon single crystal within a range where V / G and PT are lower than / G and PT, it is possible to obtain a silicon wafer having fewer defects than any existing low defect wafer depending on the manufacturing conditions. And quality variation is small.

In this case, the nitrogen concentration and the oxygen concentration are set to 1 × 10 ¹³ to 2 × 10 ¹⁴ / cm ³ and 12 to 18 ppma (JEIDA: Japan Electronic Industry Development Association standard), respectively, and the heat treatment condition is set at 1200 ° C. for 1 hour or more. Alternatively, the temperature is preferably set to 1150 ° C. for 2 hours or more.
As described above, by setting the nitrogen concentration and the oxygen concentration of the silicon single crystal within the above ranges, adverse effects due to an increase in the size of a grown-in defect, generation of an NO donor, and the like can be prevented. By subjecting the silicon wafer to a heat treatment at 1200 ° C. for 1 hour or more or 1150 ° C. for 2 hours or more, an extremely low defect silicon wafer which has not existed conventionally can be manufactured.

  Since the wafer of the present invention has extremely low defects, it can be used even in a state-of-the-art device or a future device in which the defect is severely restricted, without deteriorating device characteristics or reducing the yield. Further, since the heat treatment conditions for reducing defects are equal to or lower than those of a conventional annealing wafer, a costly process such as argon annealing + oxidizing treatment is not required. Further, if an SOI wafer is manufactured using the surface layer portion of the wafer of the present invention, which has extremely low defects, as an SOI (Silicon On Insulator) layer, a device having higher performance and higher functionality can be manufactured. Furthermore, by using the method of the present invention, by obtaining samples of various V / G and transit time in an appropriate HZ, the subsequent HZ can be made only once and the desired grown-in defect can be extremely reduced. Small single crystals and silicon wafers can be obtained.

Hereinafter, embodiments of the present invention will be described in detail, but the present invention is not limited thereto.
The present inventors have conducted intensive studies focusing on the manufacturing conditions of the nitrogen-doped crystal used as the raw material of the nitrogen-doped annealed wafer, particularly on the relationship between the crystal heat history and the grown-in defect. Similarly, the grown-in defect is strongly affected by the heat history of the crystal. However, for the first time, it was found that the temperature range in which the influence is different from that of the grown-in defect. The present inventors have found that a nitrogen-doped annealed wafer having a low defect density and little variation due to manufacturing conditions can be manufactured even when inspection is performed under severe conditions by controlling the grown-in defects of the above, and the present invention has been completed.

Prior to the description of the present invention, each term, particularly the main one of the grown-in defect, will be described in advance.
(1) FPD (Flow Pattern Defect) means that a wafer is cut out from a silicon single crystal rod after growth, and a strained layer on the surface is removed by etching with a mixed solution of hydrofluoric acid and nitric acid, and then K ₂ Cr ₂ O ₇ When the surface is etched (Secco etching) with a mixed solution of water, hydrofluoric acid and water, pits and flow patterns are generated. This flow pattern is called FPD, and the higher the FPD density in the wafer surface, the more the failure of the oxide film breakdown voltage increases (see Japanese Patent Application Laid-Open No. 4-192345).

(2) LSTD (Laser Scattering Tomography Defect) means, for example, that a wafer is cut out from a silicon single crystal rod after growth, and a strained layer on the surface is removed by etching with a mixed solution of hydrofluoric acid and nitric acid, and then the wafer is cleaved. . By irradiating infrared light from this cleavage plane and detecting light emitted from the wafer surface, scattered light due to defects existing in the wafer can be detected. The scatterers observed here have already been reported at academic conferences and the like, and are regarded as oxygen precipitates (see JJAP Vol. 32, P3679, 1993). Recent studies have also reported that it is an octahedral void.

(3) COP (Crystal Originated Particle) is a defect that causes the oxide film breakdown voltage at the center of the wafer to be degraded. The defect that becomes FPD in Secco etching is SC-1 cleaning (NH ₄ OH: H ₂ O). _{2: H 2 O = 1:} 1: the washing with 10 mixture of) by selective etching, manifested as a pit. The diameter of the pit is 1 μm or less and can be examined by a light scattering method.

  First, in the nitrogen-doped annealed wafer, the grown-in defect size and density of the base CZ crystal are very important, and the annealing conditions are important. Among these, the size and density of the grown-in defect of the CZ crystal serving as a base, the conventional nitrogen-doped annealed wafer relies only on the effect of nitrogen, and optimization of other conditions is still insufficient. I noticed that. In other words, nitrogen was merely doped under the standard conditions (or a level at which the pulling rate was increased). However, even in this case, the defect disappeared better than the sufficiently non-doped annealed wafer.

  Here, besides the nitrogen concentration, a thermal history and oxygen concentration during crystal pulling can be considered as parameters affecting the grown-in defect. In this case, there are two crystal heat histories, one of which is V / G which is the ratio of the crystal pulling speed V to the solid-liquid interface temperature gradient G during crystal pulling, which is at least a normal nitrogen non-doped crystal. Is said to be a parameter for determining the concentration of point defects before aggregation. The second is a passage time PT of a temperature zone in which point defects are aggregated to become a grown-in defect, and this is a parameter for determining aggregation. It should be noted that in the case of nitrogen doping, the temperature range in which the coagulation is performed is different from ordinary nitrogen non-doped crystals (see Japanese Patent Application No. 11-243961).

Then, the present inventors first investigated the thermal history during pulling of a nitrogen-doped crystal and the influence on the size and density distribution of the grown-in defect. In order to investigate the effect, the nitrogen concentration was 3.9 × 10 ¹³ / cm ³ ( V / G during crystal growth is 0.27, 0.325 [mm ² / mm] according to the calculated value at the shoulder position of the crystal) and the oxygen concentration at about 13 to 15 ppma (JEIDA: Japan Electronics Industry Promotion Association standard). Kmin], and the coagulation temperature zone is 1050 ° C. to 1000 ° C. when the nitrogen concentration is in the thirteenth power range, so that the passing time is 6, 13, 20, 30, 40, 60 [min]. A total of 12 types of samples were prepared, and the relationship between the grown-in defect and the thermal history was investigated. As a result, it was found that the smaller the V / G and the shorter the transit time in the aggregation temperature zone, the smaller both the defect size and density. In other words, it can be said that, even in the nitrogen-doped sample, the grown-in defect is strongly affected by the thermal history similarly to the non-doped sample.

Next, these samples were annealed at 1200 ° C./1 h and 1150 ° C./2 h under an atmosphere of 100% argon, and MO-601 was used to evaluate a grown-in defect (LSTD) at a depth of 5 μm from the surface. went. As a result, in the case of a sample having a small V / G and a short transit time, a density of 6 pieces / wafer (0.03 pieces / cm ² ) was obtained by the heat treatment at 1200 ° C. As a result, a wafer having an extremely low defect of 6 ″ (0.06 / cm ² ), which was not obtained conventionally, was obtained.

Therefore, based on this result, based on a sample subjected to annealing at 1150 ° C./2h, which has a relatively large number of defects, a LSTD of 10 pieces / 6 "wafer (0.06 pieces / cm ² ) or less is used as a criterion for pass / fail judgment. A correlation diagram between the V / G and the passing time PT was prepared as shown in Fig. 1. In Fig. 1, the ○ plots indicate those which passed the standard of 10/6 "wafer or less, and the X plots indicate The ones that did not meet the criteria of 個 wafers or less are shown. That is, if a nitrogen-doped silicon single crystal is manufactured using the pulling conditions of the shaded region in FIG. By performing annealing at least at 1200 ° C. for at least 1 hour or at 1150 ° C. for at least 2 hours, such a silicon wafer having an extremely low defect which has not existed in the past can be obtained. You can do it.

  The above-mentioned pass / fail judgment criterion was performed for a defect existing at a depth of 5 μm from the wafer surface. However, a defect-free region normally required is about 3 μm from the wafer surface. Therefore, the C-mode non-defective ratio (dielectric breakdown field of 8 MV / cm or more) of the TZDB (Time Zero Dielectric Breakdown) characteristic, which is the oxide film breakdown voltage characteristic, of the surface polished by 3 μm from the surface after the heat treatment at 1200 ° C. for 1 hour is 95%. If the above is selected as the pass / fail judgment criterion, the pass / fail judgment criterion becomes gradual, so that the boundary line moves upward, and becomes the area indicated by the broken line in FIG.

  FIG. 3 shows a comparison of the grown-in defect density between the extremely low defect wafer of the present invention and other conventional low defect crystals. As is clear from these results, it is clear that the wafer of the optimum nitrogen-doped CZ + argon annealing, which has a lower defect than any existing low defect wafer, can be obtained depending on the manufacturing conditions.

  In order to optimize the manufacturing conditions of the nitrogen-doped CZ-Si single crystal with respect to the annealing conditions and to manufacture a wafer having extremely low defects, first, parameters for determining the size and density of the grown-in defects were examined. The parameters for determining the size and density of the grown-in defect include nitrogen concentration, oxygen concentration, the ratio V / G of the pulling speed V and the temperature gradient G of the crystal solid-liquid interface as the heat history during crystal pulling, and the defect. There is a transit time PT of the temperature zone for aggregation.

  Among these, first, the oxygen concentration is usually fixed according to the specification of the user in many cases, and is also a parameter directly related to the BMD density. The higher the oxygen, the higher the BMD density after the heat treatment. Since the size of the -in defect increases, it is preferable to fix the defect in an appropriate range (for example, 12 to 18 ppma, particularly 13 to 15 ppma).

The higher the nitrogen concentration, the better the above-mentioned effect of suppressing coagulation and promoting oxygen precipitation. This is desirable. However, the OSF ring region is enlarged, and secondary defects such as dislocation loops are generated thereon. Also, it cannot be made very high because NO bonds are generated by bonding with oxygen to change the resistivity. Therefore, it is desirable that this is also fixed within a certain range (for example, about 1 to 20 × 10 ¹³ [pieces / cm ³ ]) and is not used for controlling the grown-in defect. The amount of NO donor generated is determined by subjecting a nitrogen-doped wafer to a heat treatment at about 500 to 800 ° C. as a heat treatment for forming an NO donor, measuring the resistivity of the wafer before and after the heat treatment, and measuring the resistivity. Can be estimated from the change in

Further, it is preferable that the nitrogen concentration and the oxygen concentration in the silicon single crystal are set to such an extent that a desired value of the BMD density is obtained within a range in which the above-mentioned adverse effects do not occur. For example, when a BMD of 1.0 × 10 ⁸ [pieces / cm ³ ] or more is required, the oxygen concentration is 12 to 18 ppma, and the nitrogen concentration is 1 × 10 ¹³ to 2 × 10 ¹⁴ [pieces / cm 3]. ³ ].

  Since the oxygen concentration and the nitrogen concentration are set in advance in this way, parameters that can be used for controlling the grown-in defect as actual crystal growth conditions are V / G and the aggregation temperature zone passage time PT. Here, V / G is a parameter that affects the concentration of point defects before a grown-in defect aggregates in a normal crystal.

  Therefore, in order to determine these parameters, first, a silicon wafer is prepared from each of silicon single crystals prepared under different V / G or PT conditions or under different V / G and PT conditions. These silicon single crystals having different conditions may be pulled up by setting the conditions of V / G and PT for each pulling batch of the silicon ingot. However, the change in the conditions of PT is caused when pulling up one ingot. It can also be manufactured by a method in which the lifting speed is changed during the lifting. According to this method, V / G is determined by the initial pulling speed, and PT is determined by the latter pulling speed. Further, in this method, at least one kind of HZ may be used, and it is not necessary to design and manufacture various kinds of HZ for confirmation.

At this time, the G and PT required to calculate V / G are usually calculated using the results of thermal analysis (simulation) in many cases. In this case, however, the unsteady state taking into account the specific heat of the crystal is used. It is preferable to use the analysis results. When PT is calculated from the steady-state analysis without considering the specific heat, a deviation may occur when the diameter of the crystal is different.Therefore, when using the results of the steady-state analysis, consider the effect of the specific heat and perform an experiment for each diameter. It is preferable to make corrections based on the results.
Further, it is preferable to calculate G necessary for calculating V / G by using a G value as close to the solid-liquid interface as possible. In the present invention, an average value between the melting point of silicon and 1400 ° C. is used. FEMAG (a comprehensive heat transfer analysis software: F. Dupret, P. Nicodeme, Y. Ryckmans, P. Wouters, and MJ Crochet, Int. J. Heat Mass Transfer, 33, 1849 (1990)) Simulation is performed for the case of pulling a silicon single crystal in the steady mode, and G is calculated.

  Incidentally, in order to control V / G and PT, the required heat treatment (eg, grown-in defect density, depth of the defect-free layer, Alternatively, it is necessary to determine the critical size of the grown-in defect / density in order to obtain electrical characteristics (such as oxide film breakdown voltage characteristics) of the wafer surface. Therefore, annealing is performed on a silicon wafer manufactured from a silicon single crystal in which V / G and PT are changed. The annealing conditions are appropriately set as necessary, such as, for example, annealing at 1200 ° C. for 1 hour which is typically performed with a hydrogen annealing wafer or the like, or annealing at 1150 ° C. for 2 hours in consideration of a future low temperature. Just set it. The annealing atmosphere can be arbitrarily set from hydrogen, argon, a mixed gas atmosphere thereof, or the like.

  Then, the characteristic value of the wafer after annealing is measured, and a pass / fail judgment is made based on a predetermined characteristic value, and a correlation between the pass / fail judgment and the V / G and PT is obtained. Here, when evaluating the grown-in defect density as the characteristic value of the wafer, an evaluation device capable of evaluating the defect in the depth direction, for example, MO-601 (manufactured by Mitsui Mining & Smelting Co., Ltd.) is used. Can be evaluated in the depth direction up to 5 μm, so if a defect-free layer of about 5 μm is desired, it can be evaluated by this evaluation apparatus. Further, even when an apparatus that can evaluate only the grown-in defect on the wafer surface is used, the measurement may be performed after the annealed wafer is polished to the required depth of the defect-free layer. As a characteristic value of the wafer, a non-defective rate of oxide film breakdown voltage such as TZDB, TDDB (Time Dependent Dielectric Breakdown) can be used as an index. In any case, the pass / fail judgment of the characteristic value of the wafer can be made based on an arbitrary value, and the correlation between the pass / fail judgment and V / G and PT can be obtained based on this.

  FIG. 1 shows the correlation between V / G and PT and the grown-in defect density, and the criteria for the pass / fail judgment is that the grown-in defect density (LSTD density) is 10 pieces / 6 "wafer or less. In this correlation diagram, V / G and PT are arbitrarily selected from the shaded region, a nitrogen-doped silicon single crystal is pulled under these conditions, a silicon wafer is produced from this single crystal, and a predetermined heat treatment is performed. In addition, a wafer having a desired extremely low defect having an LSTD density of 10 wafers / 6 "wafer or less can be obtained.

  When pulling a silicon single crystal doped with nitrogen by V / G selected from the shaded region, it is preferable that at least the center of the crystal be the V-rich region. This is because it is difficult to eliminate defects such as dislocation clusters existing in the I-rich region by heat treatment when I-rich regions are present in the plane of a wafer formed from the pulled crystal.

Thus, from the above-mentioned correlation, by first ascertaining the manufacturable range, it is then only necessary to design the HZ and the growth conditions as necessary, and the HZ is once produced. Therefore, development costs can be reduced. In designing the HZ, first, an arbitrary pulling speed is appropriately determined, then the HZ is analyzed, and the design is performed so that the passage time of the V / G and the coagulation temperature zone is within a predetermined range. Good. For example, if the pulling speed is 1.0 [mm / min] and G is 3.5 [K / mm], V / G becomes 0.286 [mm ² / Kmin]. Such a design condition can be satisfied by setting the region at 1050 to 1000 [deg.] C. to 3 cm or less so that the time is at least 30 minutes or less (actually, it is considered to be possible even about 35 minutes).

Actually, such an HZ (referred to as HZ-A) is manufactured, the pulling speed is 1.0 [mm / min], the oxygen concentration is about 14 [ppma], and the nitrogen concentration is 5 × 10 ¹³ [pcs / cm]. ³ ], a crystal was grown, a silicon wafer was fabricated, and argon annealing was performed at 1200 ° C. for 1 hour. A COP having a size of 0.09 μm or more at a depth of 3 μm from the wafer surface was obtained. A crystal having no defects was obtained.

  By the way, there are cases where it is desired to change the oxygen concentration and the nitrogen concentration. However, if the change is in the direction of low oxygen (for example, BMD may be small) or high nitrogen (for example, the N-O donor is not bothersome), it is not so much. No need to worry. This is because the boundary of whether the defect can be erased in the correlation diagram between V / G and the transit time obtained earlier moves in an advantageous direction (upward in FIG. 1), and thus the HZ and the operating conditions that have already been manufactured are different. Because it can be manufactured. However, a change in the direction of high oxygen (such as wanting more BMD) or low nitrogen (such as anxiety about defects peculiar to nitrogen) requires attention, and the boundary line moves in a disadvantageous direction. Therefore, in this case, it is desirable to produce a silicon single crystal in a direction more disadvantageous than the boundary line by changing V / G and PT, and to determine the boundary by a similar experiment. In this case, since there is already basic data, the number of types of samples can be reduced.

Hereinafter, the present invention will be described specifically with reference to Examples and Comparative Examples, but the present invention is not limited thereto.
(Example 1)
First, a silicon single crystal having a diameter of 6 inches, a p-type, a resistivity of 10 Ω · cm, and a crystal orientation of <100> with a varied V / G and a passing time PT in an aggregation temperature zone is pulled up, and processed into a mirror-polished wafer by a known method. did. V / G was 0.27 and 0.325 [mm ² / Kmin] (G of V / G was calculated by performing a simulation in the above-mentioned quasi-stationary mode of FEMAG), and was in the agglomeration temperature range (1500 to 1000 ° C.). ) Were set to six levels of 5, 13, 20, 30, 40, and 60 [min]. These silicon single crystals are manufactured by changing the PT by changing the pulling speed V during the pulling, and the nitrogen concentration is 3.9 × 10 ¹³ [pieces / cm ³ ] (at the shoulder position of the crystal). The calculated oxygen concentration was controlled to 13 to 15 ppma (JEIDA).

  Specifically, first, the crystal is pulled up from the shoulder of the crystal to a position where the straight body length becomes 50 cm at a pulling speed V1 (1.0 or 1.2 mm / min), and the diameter changes as much as possible between 50 cm and 51 cm. The pulling speed was suddenly changed from V1 to V2 (a pulling speed selected from 1.8 to 0.3 mm / min) while preventing the pulling, and after 51 cm, the pulling speed was raised at V2.

  Since G during crystal pulling is considered to be substantially constant except for about 10 cm from the head of the crystal, V / G is determined by V1 and PT is determined by V2 when the straight body length of the pulled crystal is 37 to 50 cm. Will be. Therefore, if a plurality of crystals are pulled up under the condition of swinging V2, crystals having the same V / G but different PTs can be obtained. Here, the position of the straight body length of 37 cm means a position where the temperature of the crystal is 1050 ° C. (upper limit of the aggregation temperature zone) when the crystal is pulled up to 50 cm. Since the OSF ring is generated up to about 48 cm to 50 cm due to a sudden change in the pulling speed, it is necessary to use a portion up to about 37 cm to 45 cm in order to remove the influence.

  In this manner, a plurality of crystals are pulled up under the condition of swinging V2 by a method of rapidly changing the pulling speed, and a wafer is cut out from a position where each straight body length is 37 to 45 cm, and V / G is the same (this embodiment). (2 levels), mirror-polished wafers having different PTs were produced.

  As a result of measuring the COP of the obtained wafer in the as-grown state (measuring device: SP1, manufactured by KLA Tencor, measuring COP size: 0.09 μm or more), the COP has a clear correlation with the thermal history, and V The higher the / G value and the longer the coagulation temperature zone passage time PT, the larger the size and the density (FIGS. 4 and 5).

  After performing two conditions of argon annealing (1200 ° C./1 hour and 1150 ° C./2 hours) on these wafers, the required COP-free region was set at 3 μm from the surface, and the surface was polished at 3 μm. Then, a COP having a size of 0.09 μm or more existing on the polished surface (that is, a depth of 3 μm from the original wafer surface) was measured, and is also shown in FIGS. 4 and 5.

  After that, in order to make COP having a size of less than 0.09 μm which cannot be detected by this COP measuring device, the measurement was performed again after repeated washing with the SC-1 washing solution. The COP after repeated cleaning of the wafer before the heat treatment with the SC-1 cleaning solution was also measured using another wafer, and is shown in FIGS. 6 and 7.

From the results of FIGS. 6 and 7, in the case of 1200 ° C./1 h annealing, when the V / G is 0.27 [mm ² / Kmin], the passing time PT is 40 minutes or less, and when the V / G is 0. In the case of 325, the sample whose transit time PT was 30 minutes or less had the COP disappeared very well. On the other hand, in the case of 1150 ° C./2h, the V / G is 0.27 [mm ² / Kmin] and the passage time PT is 20 minutes or less. When the V / G is 0.325, the passage time PT is 13 minutes. The following samples showed significant reductions.

  Therefore, a graph indicating the correlation between V / G and PT was created using the 70 / Wafer COP after re-measurement as a criterion for pass / fail judgment. FIG. 1 (solid line) shows a silicon wafer subjected to a heat treatment at 1150 ° C./2 h, and FIG. 2 shows a silicon wafer subjected to a heat treatment at 1200 ° C./1 h. Thus, when the silicon single crystal is pulled up under the conditions below the boundary line in FIGS. 1 and 2 and a silicon wafer is manufactured, each of the heat treatments is performed to substantially eliminate voids in a region from the wafer surface to a depth of 3 μm. It can be seen that the above wafer was obtained.

(Example 2)
An oxide film was formed on the surface of a silicon wafer (wafer subjected to heat treatment and 3 μm polishing) manufactured under the same conditions as in Example 1, and the oxide film breakdown voltage (TZDB, TDDB) was measured under the following conditions. The rate at which both the rate (dielectric breakdown electric field is 8 MV / cm or more) and the GDDB non-defective rate (electric charge at the time of dielectric breakdown is 25 C / cm ² or more) is 95%. And a graph showing the correlation between PT and PT.
The measurement conditions for TZDB and TDDB are shown below.
(TZDB measurement conditions)
Oxide film thickness (25.5 [nm]), gate area (8 [mm ² ]),
Determination current value (1 [mA]), number of measurements (100 [dot / wafer]).
(TDDB measurement conditions)
Oxide film thickness (25.5 [nm]), gate area (4 [mm ² ]),
Stress current value (0.01 [A / cm ² ]),
Number of measurements (100 [dot / wafer]), measurement temperature (100 ° C.).

As a result, the correlations between the oxide film breakdown voltage characteristics and V / G and PT were almost the same as those shown in FIGS. This indicates that the withstand voltage can be predicted from the measurement result of COP. In addition, the smaller the COP size (the smaller the V / G and the shorter the PT), the higher the yield rate of non-defective products after annealing tends to be.
From this result, for example, when the annealing condition is set to 1200 ° C. for 1 hour, if a wafer having a depth of 3 μm and a yield rate of 95% or more is desired, a nitrogen-doped crystal is formed below the boundary line in FIG. Should be manufactured. If the manufacturing conditions are determined in this way, a nitrogen-doped annealed wafer of stable quality can be obtained.

(Example 3)
As a pulling condition below the boundary line (solid line) in FIG. 1, V / G is 0.27 [mm ² / Kmin] (G of V / G is calculated by performing a simulation in the above-described quasi-stationary mode of FEMAG. ), The passing time PT in the agglomeration temperature zone (1050 to 1000 ° C) is set to 13 [min], a silicon single crystal having a p-type, a resistivity of 10 Ω · cm and a crystal orientation of <100> is pulled up, and the mirror-polished wafer is formed. processed. The nitrogen concentration was controlled at 3.9 × 10 ¹³ [pieces / cm ³ ] (calculated value at the shoulder position of the crystal), and the oxygen concentration was controlled at 13 to 15 ppma (JEIDA). Next, these wafers were annealed at 1200 ° C./1 h and 1150 ° C./2 h under an atmosphere of 100% argon, and the MO-601 showed a grown-in defect having a size of 50 nm or more existing up to a depth of 5 μm. LSTD) was measured. As a result, a 6/6 "wafer (about 0.03 / cm ² ) in the heat treatment at 1200 ° C. and an extremely low defect of 10/6" wafer (about 0.06 / cm ² ) in the heat treatment at 1150 ° C. Was obtained.

(Comparative example)
As a comparison with Example 3, for conventional four types of low defect wafers (6 inches, p-type, resistivity of 10 to 20 Ω · cm), grown-in defects (LSTDs) having a size of 50 nm or more and existing up to a depth of 5 μm. ) Was measured. The measurement results are shown in FIG. The manufacturing conditions for these four types of low defect wafers are as follows.

(Annealed wafer)
Wafer obtained by performing hydrogen annealing at 1200 ° C. for 1 hour on a normal CZ wafer with a pulling rate of about 1 mm / min (nitrogen doped annealing wafer)
V / G was 0.51 [mm ² / Kmin] (G of V / G was calculated by performing a simulation in the above-mentioned quasi-stationary mode of FEMAG), and nitrogen doping was raised at a PT of 14 [min]. A wafer obtained by performing argon annealing at 1200 ° C. for 1 hour on a wafer (nitrogen concentration: 4 × 10 ¹³ [pieces / cm ³ ], oxygen concentration: 15 ppma).
(Nitrogen-doped wafer in the entire N region)
A CZ wafer having a nitrogen concentration of 4 × 10 ¹³ [pieces / cm ³ ] and pulled up under the condition that the entire surface becomes an N region.

(Epitaxial wafer)
An epitaxial wafer formed by forming a 7 μm epitaxial layer at 1125 ° C. on a normal CZ wafer at a pulling rate of about 1 mm / min using trichlorosilane as a source gas.

  From FIG. 3, it can be seen that all of the conventional low defect silicon wafers have more defects on the wafer surface than the silicon wafer of the present invention. Further, as described above, the conventional nitrogen-doped wafer has a drawback that the defect density varies greatly among manufacturing lots, and the epi-wafer has a drawback that a process of forming an epitaxial layer is required.

  Note that the present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and has substantially the same configuration as the technical idea described in the claims of the present invention, and any device having the same operation and effect can be realized by the present invention. It is included in the technical scope of the invention.

For example, in the above embodiment, the case of growing a silicon single crystal having a diameter of 6 inches has been described by way of example. However, the present invention is not limited to this, and a silicon silicon single crystal having a diameter of 8 to 16 inches or more is provided. It can also be applied to crystals.
In addition, it goes without saying that the present invention can be applied to a so-called MCZ method in which a horizontal magnetic field, a vertical magnetic field, a cusp magnetic field, or the like is applied to a silicon melt.

FIG. 4 is a correlation diagram showing the relationship between V / G and PT during crystal pulling and the yield rate of a silicon wafer in a silicon wafer annealed at 1150 ° C. for 2 hours. FIG. 9 is a correlation diagram showing the relationship between V / G and PT during crystal pulling and the yield rate of silicon wafer in a silicon wafer annealed at 1200 ° C. for 1 hour. FIG. 3 is a comparison diagram comparing the grown-in defect density of a silicon wafer of the present invention and a conventional low defect silicon wafer. FIG. 4 is a diagram showing a relationship between V / G, PT, annealing heat treatment, and COP before SC-1 cleaning. FIG. 4 is a diagram showing a relationship between V / G, PT, annealing heat treatment, and COP before SC-1 cleaning. FIG. 5 is a diagram showing the relationship between V / G, PT, annealing heat treatment and COP after SC-1 cleaning. FIG. 5 is a diagram showing the relationship between V / G, PT, annealing heat treatment and COP after SC-1 cleaning.

Claims (7)

A nitrogen-doped silicon wafer having no epitaxial layer formed on the surface, wherein 0.23 LSTDs having a size of 50 nm or more and present in a surface layer portion having a depth of at least 5 μm from the surface of the silicon wafer have a density of 0.23 / cm 2. A silicon wafer having a size of ² or less. ^2. The silicon wafer according to claim 1, wherein the LSTD having a size of 50 nm or more in the surface layer portion is 0.06 / cm ² or less. 3. ^3. The silicon wafer according to claim 1, wherein a BMD of 1.0 × 10 ⁸ pieces / cm ³ or more exists in a bulk portion of the silicon wafer. 4. 3. The silicon wafer according to claim 1, wherein a BMD is 1.0 × 10 ⁸ / cm ³ or more in a bulk portion of the silicon wafer by performing a heat treatment. 4. Silicon wafer. The silicon wafer, wherein the heat treatment is performed on a silicon wafer having a nitrogen concentration of 1 × 10 ¹³ to 2 × 10 ¹⁴ / cm ³ and an oxygen concentration of 12 to 18 ppma. The silicon wafer according to claim 4.   6. The silicon wafer according to claim 4, wherein the heat treatment is performed at 1200 ° C. for 1 hour or more or 1150 ° C. for 2 hours or more. 7.   The silicon wafer according to claim 4, wherein the heat treatment is a heat treatment in a device manufacturing process.

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