JP4951927B2 - Method for selecting silicon wafer and method for manufacturing annealed wafer - Google Patents

Description

  The present invention mainly relates to a method of selecting a silicon wafer as a raw material when an annealed wafer is manufactured by annealing (heat treatment) of a silicon wafer.

Silicon wafers are widely used as substrates for semiconductor devices. Silicon wafers are grown by, for example, Czochralski method (CZ method) or CZ method (so-called MCZ method) applying a magnetic field, and after slicing the grown single crystal, chamfering, lapping, polishing, etc. Manufactured with processing.
When a silicon single crystal is grown by the CZ method, the polycrystalline silicon contained in the quartz crucible is heated and melted, and the seed crystal is brought into contact with the raw material melt. Then, while rotating the crucible and pulling up while rotating the seed crystal, a silicon single crystal is grown.

  In the grown silicon single crystal, there are point defects, that is, vacancies lacking silicon atoms and extra atoms between lattices, usually due to aggregates of point defects and oxygen introduced from quartz crucibles. Oxygen related defects exist. Defects resulting from such growth are called grow-in defects, and their occurrence depends on crystal growth conditions. For example, when a single crystal is grown by increasing the crystal growth rate, vacancies become dominant, and void agglomerates (voids) are formed during crystal growth. In general, from the viewpoint of productivity, a silicon single crystal having a large crystal growth rate, that is, a vacancy-dominated silicon single crystal is widely used.

When a void is exposed on the surface of a silicon wafer obtained by processing a single crystal having a void, it is called COP (Crystal Originated Particle) and can be easily detected by a particle counter or the like. In particular, COP and voids in the vicinity of the surface deteriorate the breakdown voltage characteristics of the semiconductor device, so that a silicon wafer having a low void density or a void-free has recently been strongly demanded.
Therefore, when growing a silicon single crystal by the CZ method, nitrogen is doped to suppress aggregation of grow-in defects, and a method for growing a silicon single crystal in which oxygen precipitation is promoted, a furnace structure, a pulling speed, etc. In order to improve the growth conditions, a method for growing a silicon single crystal in a so-called N region in which no agglomerates of point defects are present has been developed.

On the other hand, if the silicon wafer is subjected to high-temperature heat treatment (annealing) under an inert atmosphere such as argon gas, the COP and voids in the surface layer portion can be eliminated or reduced, so that the silicon wafer subjected to such high-temperature heat treatment, Demand for so-called annealed wafers has increased rapidly recently.
Therefore, a method in which a nitrogen-doped silicon single crystal is grown and processed into a wafer and then annealed at a high temperature of 1000 ° C. or higher (see Patent Document 1), nitrogen doping and pulling speed (V) and temperature at the solid-liquid interface There has been proposed a method of growing a silicon single crystal while controlling the ratio (V / G) to the gradient (G), processing it into a wafer, and annealing it (see Patent Document 2).

  When annealing is performed on a nitrogen-doped silicon wafer as described above, the effect of suppressing the growth of grown-in defects and the effect of oxygen precipitation by nitrogen doping is obtained, and the size of the defect is smaller than that of a normal crystal. While defects (surface layer defects) are efficiently reduced or eliminated, the BMD (Bulk Micro Defect) density in the bulk is high, and an annealed wafer having gettering ability can be obtained.

  However, regardless of the presence or absence of nitrogen doping, for example, even if a silicon wafer processed from the same silicon single crystal is annealed under the same conditions, the density of void defects remaining in the surface layer portion varies, and the desired defect density There is a problem that it is not possible to stably supply the annealed wafer having the above.

JP-A-10-98047 JP 2002-356395 A

  The main object of the present invention is to provide a method for stably supplying an annealed wafer having a desired defect density in the surface layer portion.

According to the present invention, a method of selecting a silicon wafer as a raw material when annealing an silicon wafer to produce an annealed wafer, the step of measuring defects in the surface layer portion of the silicon wafer before and after the annealing, From the data obtained by the measurement, obtaining a correlation for defects in the surface layer portion before and after annealing, and based on the correlation, using as a raw material a silicon wafer that can be an annealed wafer having a desired defect density in the surface layer portion after the annealing And a selecting step . A method for selecting a silicon wafer is provided .

  That is, if a correlation between defects in the surface layer portion of the silicon wafer before and after annealing is obtained in advance and a silicon wafer that becomes an annealed wafer having a desired defect density is selected based on the correlation, a desired defect can be obtained. It becomes possible to stably supply an annealed wafer having a density.

A nitrogen-doped silicon wafer can be used as the silicon wafer .
In the case of a nitrogen-doped silicon wafer, the size of the grown-in defect is small and the BMD density in the bulk can be high. Accordingly, if a nitrogen-doped silicon wafer is selected as the raw material for the annealed wafer, it is possible to stably manufacture a high-quality annealed wafer having a small defect density and size in the surface layer portion and high gettering ability.

As a defect in the surface layer portion, a void defect can be measured .
Wafers used for semiconductor devices are strongly required to reduce void defects in the surface layer portion, and the void defects in the surface layer portion show a relatively good correlation before and after annealing. Accordingly, if a correlation is obtained for void defects before and after annealing and a silicon wafer as a raw material is selected based on the correlation, an annealed wafer having a desired void defect density can be stably manufactured.

Moreover, it is preferable to measure the size and / or density of defects in the surface layer portion .
By measuring the defect size and defect density in the surface layer portion, the correlation before and after annealing can be easily obtained, and the silicon wafer as a raw material can be selected more appropriately.

More specifically, the defect size in the surface layer portion of the silicon wafer before annealing and the defect density in the surface layer portion before and after the annealing are measured, and the defect size in the surface layer portion before the annealing and the defect in the surface layer portion after the annealing are measured. The relationship between the density and the defect size in the surface layer portion before annealing and the defect residual rate in the surface layer portion before and after annealing is obtained, and based on these relationships, annealing is performed from a desired defect density in the surface layer portion after annealing. Calculate the defect size in the surface layer part before annealing, calculate the defect density in the surface layer part before annealing from the calculated defect size in the surface layer part before annealing, and calculate the defect size in the surface layer part before annealing and A silicon wafer having a defect density can be selected as a raw material .

  From the relationship between the defect size in the surface layer portion before annealing and the defect density in the surface layer portion after annealing, and the relationship between the defect size in the surface layer portion before the annealing and the defect residual rate in the surface layer portion before and after annealing, the surface layer portion before annealing The defect size and / or defect density can be calculated, and the silicon wafer as the raw material can be selected more appropriately and reliably.

According to the present invention, there is also provided a method for manufacturing an annealed wafer by annealing a silicon wafer, wherein a silicon wafer is selected as a raw material by the above-described method, and the selected silicon wafer is annealed to manufacture an annealed wafer. An annealed wafer manufacturing method is provided .

  In other words, if a silicon wafer as a raw material is selected based on the correlation of defects in the surface layer portion before and after annealing, and the selected silicon wafer is annealed, an annealed wafer having a desired defect density in the surface layer portion is stably manufactured. can do.

  In the present invention, a correlation is obtained for defects in the surface layer portion of the silicon wafer before and after annealing, and based on the correlation, a silicon wafer that can become an annealed wafer having a desired defect density in the surface layer portion after annealing is selected as a raw material. If a silicon wafer is selected and annealed by such a method, an annealed wafer having a desired defect density in the surface layer portion can be stably manufactured.

Hereinafter, the present invention will be described in detail.
The inventor examined and investigated defects in the surface layer portion of the wafer before and after annealing. The size of defects (mainly voids) in the surface layer portion of the silicon wafer before annealing affects the defect density in the surface layer portion after annealing, and it is estimated that the density of surface layer defects after annealing decreases as the defect size decreases. Therefore, by growing a silicon single crystal that can reduce void defects by nitrogen doping and annealing the silicon wafer obtained by processing this, the defect (void) density in the surface layer is extremely small or void-free. It is considered that an annealed wafer can be obtained.
However, the defect density in the surface layer portion of the annealed wafer is not necessarily controlled to a desired amount, and even when annealing is performed under the same conditions, a large amount of COP or void may remain in the surface layer portion.

  The present inventor considered that there is a problem mainly in the selection of a silicon wafer as a raw material as a cause that the defect density in the surface layer portion after annealing is not controlled to a desired amount. Therefore, as a result of further earnest examination and research, if the correlation of defects in the surface layer part of the silicon wafer before and after annealing is obtained, and the silicon wafer as the raw material is selected based on the correlation, the desired defect in the surface layer part is obtained. The inventors have found that an annealed wafer having a density can be stably supplied, and have completed the present invention.

The present invention will be described more specifically with reference to the accompanying drawings.
FIG. 1 shows an example of a flow for selecting a silicon wafer as a raw material when manufacturing an annealed wafer according to the present invention.
First, a silicon wafer for obtaining the correlation between surface layer defects before and after annealing is prepared, and the defects in the surface layer portion of the silicon wafer before annealing are measured (FIG. 1A).

The silicon wafer used for the measurement is not particularly limited. However, when it is desired to produce a void-free annealed wafer having a low density of void defects in the surface layer portion, a silicon wafer doped with nitrogen may be used. preferable. Nitrogen doping provides an effect of suppressing defect aggregation (defect reduction effect) to obtain a surface layer with a small defect size, and an annealed wafer having a low density of surface layer defects after annealing.
Further, the greater the number of silicon wafers used for measurement, the higher the reliability of the correlation of surface layer defects before and after annealing. However, considering the cost and the like, it is preferably about 10 to several tens.

  The surface layer portion defect to be measured is not particularly limited as long as it shows a correlation before and after annealing. For example, void defects (COP) in the surface layer portion can be given. For wafers used in semiconductor devices, control of void defects in the surface layer is important. Further, the size and density of void defects show a relatively good correlation before and after annealing. Therefore, it is preferable to measure the size and density of void defects in the surface layer portion of the silicon wafer before annealing.

  In addition, what is necessary is just to select suitably the apparatus used for the measurement of the surface layer defect of a wafer according to the kind, size, depth, etc. of the defect to be measured. For example, if a defect evaluation apparatus MO-601 (manufactured by Mitsui Mining & Mining Co., Ltd.) is used, it is possible to measure extremely fine defects having a size of about 50 nm, and further evaluate the defects at a depth of 5 μm from the wafer surface. Can do.

Next, the silicon wafer subjected to the above measurement is annealed under certain conditions (FIG. 1B).
The annealing here may be performed under the same conditions as those for manufacturing an annealed wafer as a product. For example, when a batch furnace is used, heat treatment can be performed in an argon atmosphere at 1000 to 1250 ° C. for 30 minutes to 4 hours. Moreover, when using a rapid heating apparatus, it can be set as the heat processing of 1000-1250 degreeC and 1 to 60 second in argon atmosphere.

After the annealing, the defect in the surface layer portion of the silicon wafer is measured again (FIG. 1C).
In the measurement after annealing, the size and density of void defects in the surface layer portion of the wafer may be similarly measured using the same conditions as the measurement before annealing, that is, the same measurement equipment as that before the annealing.

From the data obtained by the measurement before and after the annealing as described above, the correlation is obtained for the defects in the surface layer portion before and after the annealing (FIG. 1D).
For example, in the case of measuring the size and density of void defects before and after annealing as described above, the relationship between the defect size in the surface layer part before annealing and the defect density (residual void density) in the surface layer part after annealing, In addition, it is possible to grasp the relationship between the defect size in the surface layer part before annealing and the defect residual rate in the surface layer part before and after annealing (defect density after annealing process / defect density before annealing process).

Based on the above two relationships, a silicon wafer that can be an annealed wafer having a desired defect density in the surface layer portion after annealing is selected as a raw material (FIG. 1E).
For example, based on the relationship between the defect size in the surface layer portion before annealing and the defect density (residual void density) in the surface layer portion after annealing, in the surface layer portion before annealing so as to obtain a desired defect density in the surface layer portion after annealing. The defect size can be calculated. Furthermore, based on the relationship between the defect size in the surface layer portion before annealing and the defect residual ratio in the surface layer portion before and after annealing, the defect in the surface layer portion before annealing that becomes the calculated defect size in the surface layer portion before annealing is calculated. Density can be calculated. A silicon wafer having the defect size, defect density, and the like in the surface layer portion before annealing calculated in this manner can be selected as a raw material for the annealed wafer to be a product.

  That is, after the annealing process, initial defect size and density threshold values are obtained so that an annealed wafer having a desired surface layer defect density is obtained, and a silicon wafer as an initial material is selected. Then, by annealing the selected silicon wafer, it is possible to stably manufacture an annealed wafer having a desired surface layer defect density after the annealing step.

Examples of the present invention will be described below.
(Example)
A silicon wafer having a diameter of 200 mm was measured for defects on the surface layer of the wafer using “MO-601” (Mitsui Metal Mining Co., Ltd.) as a defect evaluation apparatus, and the average density of defects (mainly voids) in the surface layer and Average size was obtained. In the measurement by MO-601, a surface layer defect in a depth region of about 5 μm from the wafer surface is detected. In addition, about the size of the defect of a surface layer part, the average value of scattering intensity was made into the average size from the relationship that the scattering intensity obtained by the measurement by MO-601 is proportional to the square of a defect volume.

  The wafer measured above was annealed at 1200 ° C./1 hour in an argon atmosphere using a vertical heat treatment furnace “DD-853V” (manufactured by Hitachi Kokusai Electric). With respect to the wafer after Ar annealing, the same measurement as before the annealing was performed again using MO-601, and the average density and average size of the defects remaining on the surface layer of the wafer were obtained.

FIG. 2 shows the relationship between the defect size (scattering intensity) in the surface layer part before the annealing process and the defect density after the annealing process. FIG. 2 shows that the defect size before the annealing process increases and the defect density after the annealing process increases.
On the other hand, FIG. 3 shows the relationship between the defect size (scattering intensity) before the annealing process and the defect residual ratio before and after the annealing process (defect density after annealing / defect density before annealing). Similar to FIG. 2, the defect residual rate also depends on the defect size before the annealing step, and the larger the size, the higher the residual rate.

The relationship between the defect size in the surface layer portion before annealing shown in FIG. 2 and the defect density in the surface layer portion after annealing (Relation A), and the defect size in the surface layer portion before annealing and the surface layer before and after annealing shown in FIG. Based on the relationship with the defect residual rate (relation B) in the part, a silicon wafer as a raw material was selected as follows.
As described above, since the defect in the depth region from the wafer surface to the inside of about 5 μm is detected in the measurement by MO-601, when the defect density after the annealing process in this surface layer portion is controlled to 5 cm ⁻² or less, From relation A, the average size of defects in the initial material is 270a. u. It was determined that (see FIG. 2): Thus, since the average defect size of the raw material in which the defect density after the annealing step in the surface layer portion is 5 cm ⁻² or less has been found, a wafer having such a defect size can be selected as the raw material. However, since the relationship A shown in FIG. 2 varies somewhat, selection is made based on the relationship B in order to further ensure the relationship. That is, the average size of the surface layer defects of the initial material is 270a. u. In the case of the following, from the relationship B, the defect remaining rate is 2.3% or less (see FIG. 3). Here, assuming that the defect density before annealing is Di and the defect density after annealing is Da, Da / Di = 2.3 (%), and the defect density after the annealing process is 5 cm ⁻² or less. Considering this, Di ≦ 5 cm ⁻² /0.023=217 cm ⁻² is calculated. That is, the density of surface layer defects in the initial material before the annealing step can be determined to be 217 cm ⁻² or less.

Note that the wafer as the raw material can be selected by calculating the defect size or defect density in the surface layer part before annealing from either of the relations A and B, but as described above, the relation between both A and B It is preferable to select the raw material from That is, the average size of void defects in the surface layer portion is 270a. u. If a silicon wafer having a defect density of 217 cm ⁻² or less is selected and annealed, the defect density in the measurement region (region from the surface to a depth of about 5 μm) by MO-601 is more reliably set to 5 cm. ^-2 or less can be controlled.

  The present invention is not limited to the above embodiment. The above embodiment is merely an example, and the present invention has the same configuration as that of the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

  For example, in the embodiment and the example, the case where measurement is performed using MO-601 has been described. However, the measurement apparatus is not limited to this, and a desired depth can be obtained by using an apparatus having a different observable depth region. The defect density remaining in the film can be controlled to a desired amount. For example, if measurement of surface layer defects before and after annealing is performed in the same manner as described above using “M-350” (Laserect) having a shallower measurement depth region, a shallower region (from the surface to several hundred nm) It is also possible to control the defect density in the region) to a desired amount.

It is a flowchart which shows an example of the method of selecting the silicon wafer used as a raw material when manufacturing the annealed wafer which concerns on this invention. It is a graph which shows the relationship between the defect size before an annealing process and the defect density in the surface layer part after an annealing process in an Example. It is a graph which shows the relationship between the defect size before an annealing process, and the defect residual rate before and behind an annealing process in an Example.

Claims (3)

A method of selecting a silicon wafer as a raw material when annealing a silicon wafer to produce an annealed wafer,
Measuring the size and density of void defects in the surface layer portion of the silicon wafer before annealing, and the density of void defects in the surface layer portion of the silicon wafer after annealing ;
In correlation, and the surface layer portion of the defect size and before and after annealing in the surface layer before the annealing between the defect density in the surface layer portion after the from the obtained data with the defect size in the surface layer portion of the front the annealing annealed by measuring A step of obtaining a correlation with the defect residual rate;
Based on the two correlation, to calculate the defect size in the surface layer portion of the front the annealing from the desired defect density in the surface layer after the annealing, the annealing before the defect size in the surface layer before annealing issued the calculated And a step of selecting a silicon wafer having a defect size and / or a defect density in the surface layer portion before annealing as a raw material. .   2. The method for selecting a silicon wafer according to claim 1, wherein a silicon wafer doped with nitrogen is used as the silicon wafer. A method for manufacturing an annealed wafer by annealing a silicon wafer, wherein a silicon wafer is selected as a raw material by the method according to claim 1 or 2, and the selected silicon wafer is annealed to produce an annealed wafer. A method of manufacturing an annealed wafer characterized by manufacturing.

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