JP2004281819A - Semiconductor device, electronic device, electronic apparatus, method for manufacturing semiconductor device, and method for manufacturing electronic device - Google Patents

Semiconductor device, electronic device, electronic apparatus, method for manufacturing semiconductor device, and method for manufacturing electronic device Download PDF

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JP2004281819A
JP2004281819A JP2003072564A JP2003072564A JP2004281819A JP 2004281819 A JP2004281819 A JP 2004281819A JP 2003072564 A JP2003072564 A JP 2003072564A JP 2003072564 A JP2003072564 A JP 2003072564A JP 2004281819 A JP2004281819 A JP 2004281819A
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semiconductor chip
conductive layer
semiconductor
wiring layer
side wall
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Toshihiro Sawamoto
俊宏 澤本
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Seiko Epson Corp
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Seiko Epson Corp
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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Abstract

<P>PROBLEM TO BE SOLVED: To make the three-dimensional packaging structure of a semiconductor chip thin without being restricted by the size the semiconductor chip. <P>SOLUTION: Grooves 8a-8c are formed on side walls of semiconductor chips 1a-1c, respectively, and conductive films 7a-7c connected with electrode pads 2a-2c are formed in the grooves 8a-8c, respectively, through insulating films 6a-6c. The grooves 8a-8c of the semiconductor chips 1a-1c are wire bonded and lands 12 of an interposer substrate 11 are connected with the conductive films 7a-7c through wires 13a-13c. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法に関し、特に、半導体チップの積層構造における層間接続方法に適用して好適なものである。
【０００２】
【従来の技術】
従来の半導体装置では、半導体チップの３次元実装構造を実現するため、積層された半導体チップをワイヤボンド接続する方法があった。
図６は、従来の半導体装置の構成を示す断面図である。
図６において、半導体チップ４１ａ〜４１ｃが接着層４２ｂ、４２ｃをそれぞれ介して積層され、半導体チップ４１ｂ、４１ｃが積層された半導体チップ４１ａは、接着層４２ａを介してインターポーザ基板４４上に実装されている。そして、半導体チップ４１ａ〜４１ｃは、ワイヤ４３ａ〜４３ｃをそれぞれ介してインターポーザ基板４４上に設けられたランド４５に接続されている。
【０００３】
ここで、半導体チップ４１ａ〜４１ｃは、上層ほどサイズが小さくなっている。そして、半導体チップ４１ａのワイヤ４３ａの接続領域を避けるように、半導体チップ４１ｂが半導体チップ４１ａ上に積層され、半導体チップ４１ｂのワイヤ４３ｂの接続領域を避けるように、半導体チップ４１ｃが半導体チップ４１ｂ上に積層されている。
【０００４】
図７は、従来の半導体装置の構成を示す断面図である。
図７において、半導体チップ５１ａ〜５１ｃの間には、ミラーチップ５３ａ、５３ｂがそれぞれ設けられ、ミラーチップ５３ａ、５３ｂの両面には、接着層５２ｂ、５２ｃ、５２ｄ、５２ｅがそれぞれ設けられている。そして、半導体チップ５１ａ〜５１ｃは、接着層５２ｂ、５２ｃ、５２ｄ、５２ｅがそれぞれ設けられたミラーチップ５３ａ、５３ｂそれぞれ介して積層され、半導体チップ５１ｂ、５１ｃが積層された半導体チップ５１ａは、接着層５２ａを介してインターポーザ基板５５上に実装されている。そして、半導体チップ５１ａ〜５１ｃは、ワイヤ５４ａ〜５４ｃをそれぞれ介してインターポーザ基板５５上に設けられたランド５６に接続されている。
【０００５】
ここで、ミラーチップ５３ａ、５３ｂを半導体チップ５１ａ〜５１ｃの間に設けることにより、半導体チップ５１ａ〜５１ｃ間の間隔を増加させることができる。このため、半導体チップ５１ａ〜５１ｃのサイズが等しい場合においても、下層の半導体チップ５１ａ〜５１ｃに接続されるワイヤ５４ａ〜５４ｃが上層の半導体チップ５１ａ〜５１ｃに接触することを防止することができ、半導体チップ５１ａ〜５１ｃのサイズを上層ほど小さくする必要がなくなる。
【０００６】
【発明が解決しようとする課題】
しかしながら、図６の半導体装置では、半導体チップ４１ａ〜４１ｃをワイヤボンド接続するために、上層ほどサイズを小さくする必要があり、半導体チップ４１ａ〜４１ｃのサイズに制約がかかるとともに、ワイヤ４３ａ〜４３ｃが半導体チップ４１ａ〜４１ｃの上方に張り出すため、半導体チップの３次元実装構造の高さが大きくなるという問題があった。
【０００７】
また、図７の半導体装置では、半導体チップ５１ａ〜５１ｃのサイズを上層ほど小さくする必要がなくなるものの、半導体チップ５１ａ〜５１ｃの間にミラーチップ５３ａ、５３ｂを挿入する必要があり、半導体チップの３次元実装構造の高さが大きくなるという問題があった。
そこで、本発明の目的は、半導体チップのサイズに制約されることなく、半導体チップの３次元実装構造の薄型化を実現することが可能な半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法を提供することである。
【０００８】
【課題を解決するための手段】
上述した課題を解決するために、本発明の一態様に係る半導体装置によれば、半導体チップ上に形成された配線層と、前記配線層に接続され、前記半導体チップの側壁に形成された導電層と、前記導電層に接続されたワイヤとを備えることを特徴とする。
【０００９】
これにより、半導体チップの側方からワイヤを引き出すことが可能となり、ワイヤが上方に張り出すことを防止することが可能となることから、高さの増大を抑制しつつ、半導体チップを実装することが可能となる。
また、本発明の一態様に係る半導体装置によれば、半導体チップ上に形成された配線層と、前記半導体チップを厚み方向に横切るようにして、前記半導体チップの切断面に形成された溝と、前記溝に形成された導電層と、前記導電層に接続されたワイヤとを備えることを特徴とする。
【００１０】
これにより、半導体チップの側壁に導電層を安定して形成することが可能となり、半導体チップの側方からワイヤを容易に引き出すことが可能となる。このため、ワイヤが上方に張り出すことを防止することが可能となり、高さの増大を抑制しつつ、半導体チップを実装することが可能となる。
また、本発明の一態様に係る半導体装置によれば、第１半導体チップ上に形成された第１配線層と、前記第１配線層に接続され、前記第１半導体チップの側壁に形成された第１導電層と、前記第１半導体チップ上に積層された第２半導体チップと、前記第２半導体チップ上に形成された第２配線層と、前記第２配線層に接続され、前記第２半導体チップの側壁に形成された第２導電層と、前記第１導電層と前記第２導電層とを接続する第１ワイヤとを備えることを特徴とする。
【００１１】
これにより、半導体チップの側方からワイヤを引き出すことが可能となり、ワイヤが上方に張り出すことを防止することが可能となるとともに、ワイヤを接合させる領域を半導体チップの表面に確保する必要がなくなる。このため、上層ほど半導体チップのサイズを小さくする必要がなくなり、積層される半導体チップのサイズの制約をなくすことが可能となるとともに、半導体チップの上下の間隔を減少させることを可能として、半導体チップの３次元実装構造の薄型化を実現することが可能となる。
【００１２】
また、本発明の一態様に係る半導体装置によれば、第１半導体チップ上に形成された第１配線層と、前記第１半導体チップを厚み方向に横切るようにして、前記第１半導体チップの切断面に形成された第１溝と、前記第１溝に形成された第１導電層と、前記第１半導体チップ上に積層された第２半導体チップと、前記第２半導体チップ上に形成された第２配線層と、前記第２半導体チップを厚み方向に横切るようにして、前記第２半導体チップの切断面に形成された第２溝と、前記第２溝に形成された第２導電層と、前記第１導電層と前記第２導電層とを接続する第１ワイヤとを備えることを特徴とする。
【００１３】
これにより、半導体チップの側壁に導電層を安定して形成することが可能となり、半導体チップの側方からワイヤを容易に引き出すことが可能となる。このため、ワイヤが上方に張り出すことを防止することが可能となるとともに、ワイヤを接合させる領域を半導体チップの表面に確保する必要がなくなり、半導体チップのサイズに制約されることなく、半導体チップの３次元実装構造の薄型化を実現することが可能となる。
【００１４】
また、本発明の一態様に係る半導体装置によれば、前記第２半導体チップが積層された前記第１半導体チップを搭載するインターポーザ基板と、前記インターポーザ基板に設けられたランドと、前記ランドと前記第１導電層とを接続する第２ワイヤとを備えることを特徴とする。
これにより、ワイヤボンドを連続して行うことで、積層された半導体チップ同士を接続することが可能となるとともに、積層された半導体チップをインターポーザ基板に接続することが可能となり、実装工程の煩雑化を抑制しつつ、半導体チップを３次元実装することが可能となる。
【００１５】
また、本発明の一態様に係る半導体装置によれば、前記第１半導体チップと前記第２半導体チップとは、サイズ、厚みまたは種類の少なくともいずれか１つが異なっていることを特徴とする。
これにより、半導体チップのワイヤボンド接続を行うことで、様々な機能を持たせることを可能としつつ、半導体チップの３次元実装構造の薄型化を図ることが可能となる。
【００１６】
また、本発明の一態様に係る電子デバイスによれば、第１電子部品上に形成された第１配線層と、前記第１配線層に接続され、前記第１電子部品の側壁に形成された第１導電層と、前記第１電子部品上に積層された第２電子部品と、前記第２電子部品上に形成された第２配線層と、前記第２配線層に接続され、前記第２電子部品の側壁に形成された第２導電層と、前記第１導電層と前記第２導電層とを接続するワイヤとを備えることを特徴とする。
【００１７】
これにより、電子部品の側方からワイヤを引き出すことが可能となり、ワイヤが上方に張り出すことを防止することが可能となるとともに、ワイヤを接合させる領域を電子部品の表面に確保する必要がなくなる。このため、上層ほど電子部品のサイズを小さくする必要がなくなり、積層される電子部品のサイズの制約をなくすことが可能となるとともに、電子部品の上下の間隔を減少させることを可能として、電子部品の３次元実装構造の薄型化を実現することが可能となる。
【００１８】
また、本発明の一態様に係る電子機器によれば、第１半導体チップ上に形成された第１配線層と、前記第１配線層に接続され、前記第１半導体チップの側壁に形成された第１導電層と、前記第１半導体チップ上に積層された第２半導体チップと、前記第２半導体チップ上に形成された第２配線層と、前記第２配線層に接続され、前記第２半導体チップの側壁に形成された第２導電層と、前記第１導電層と前記第２導電層とを接続する第１ワイヤと、前記第２半導体チップが積層された前記第１半導体チップを搭載するインターポーザ基板と、前記インターポーザ基板に設けられたランドと、前記ランドと前記第１導電層とを接続する第２ワイヤとを備えることを特徴とする。
【００１９】
これにより、半導体チップの側方からワイヤを引き出すことが可能となり、ワイヤが上方に張り出すことを防止することが可能となるとともに、ワイヤを接合させる領域を半導体チップの表面に確保する必要がなくなることから、半導体チップのサイズに制約されることなく、半導体チップの３次元実装構造の薄型化を実現することが可能となる。
【００２０】
また、本発明の一態様に係る半導体装置の製造方法によれば、第１半導体チップ上に形成された第１配線層に接続された第１導電層を前記第１半導体チップの側壁に形成する工程と、第２半導体チップ上に形成された第２配線層に接続された第２導電層を前記第２半導体チップの側壁に形成する工程と、前記第１半導体チップ上に前記第２半導体チップを積層する工程と、前記側壁に形成された前記第１導電層と前記第２導電層とをワイヤボンド接続する工程とを備えることを特徴とする。
【００２１】
これにより、半導体チップの側方からワイヤを引き出すことが可能となり、半導体チップのワイヤボンド接続を行うことで、半導体チップのサイズに制約されることなく、半導体チップの３次元実装構造の薄型化を実現することが可能となる。
また、本発明の一態様に係る半導体装置の製造方法によれば、電極パッドが形成された半導体ウェハの切断線上に貫通孔を形成する工程と、前記電極パッドの表面が露出されるようにして、前記貫通孔の表面に絶縁膜を形成する工程と、前記電極パッドに接続された導電膜を前記貫通孔内に形成する工程と、前記切断線に沿って前記半導体ウェハをチップ状に切断する工程と、前記チップ状に切断された半導体チップを積層する工程と、前記切断線に沿って分割された貫通孔内の導電層にワイヤボンドを行うことにより、前記積層された半導体チップを接続する工程とを備えることを特徴とする。
【００２２】
これにより、フォトリソグラフィー技術およびエッチング技術を用いることで、複数の半導体チップの側壁に導電膜を一括形成することが可能となるとともに、半導体チップの側方からワイヤを引き出すことが可能となる。このため、半導体チップのサイズに制約されることなく、半導体チップのワイヤボンド接続を行うことが可能となり、製造工程の煩雑化を抑制しつつ、半導体チップの３次元実装構造の薄型化を実現することが可能となる。
【００２３】
また、本発明の一態様に係る電子デバイスの製造方法によれば、第１電子部品上に形成された第１配線層に接続された第１導電層を前記第１電子部品の側壁に形成する工程と、第２電子部品上に形成された第２配線層に接続された第２導電層を前記第２電子部品プの側壁に形成する工程と、前記第１電子部品上に前記第２電子部品を積層する工程と、前記側壁に形成された前記第１導電層と前記第２導電層とをワイヤボンド接続する工程とを備えることを特徴とする。
【００２４】
これにより、電子部品の側方からワイヤを引き出すことが可能となり、電子部品のサイズに制約されることなく、電子部品の３次元実装構造の薄型化を実現することが可能となる。
【００２５】
【発明の実施の形態】
以下、本発明の実施形態に係る半導体装置およびその製造方法について図面を参照しながら説明する。
図１、３は、本発明の第１実施形態に係る半導体装置の製造方法を示す断面図、図２、４は、本発明の第１実施形態に係る半導体装置の製造方法を示す斜視図である。
【００２６】
図１（ａ）および図２（ａ）において、半導体ウェハＷはスクライブラインＳＬで区画され、各区画領域には素子形成領域９が設けられている。そして、図１（ａ）に示すように、半導体ウェハＷには電極パッド２が形成されるとともに、電極パッド２上には絶縁膜３が形成され、絶縁膜３には電極パッド２の表面を露出させる開口部４が形成されている。
【００２７】
次に、図１（ｂ）に示すように、例えば、フォトリソグラフィー技術およびエッチング技術を用いることにより、スクライブラインＳＬ上に配置された貫通孔５を半導体ウェハＷに形成する。なお、貫通孔５を形成する場合、例えば、レーザ加工などを用いるようにしてもよい。
次に、図１（ｃ）に示すように、例えば、ＣＶＤなどの方法により、貫通孔５内を含む半導体ウェハＷの全面に絶縁膜６を形成する。そして、フォトリソグラフィー技術およびエッチング技術を用いて絶縁膜６をパターニングすることにより、電極パッド２の表面を露出させる。なお、絶縁膜６としては、例えば、シリコン酸化膜またはシリコン窒化膜などを用いることができる。
【００２８】
次に、図１（ｄ）および図２（ａ）に示すように、例えば、スパッタ、蒸着あるいはＣＶＤなどの方法により、貫通孔５内を含む半導体ウェハＷの全面に導電膜７を形成する。そして、フォトリソグラフィー技術およびエッチング技術を用いて導電膜７をパターニングすることにより、電極パッド２と貫通孔５とが各区画領域ごとに１対１に接続されるようにする。なお、導電膜７としては、例えば、Ａｌ、Ｃｕ、Ａｕ、Ｗなどを用いることができる。
【００２９】
次に、図１（ｅ）および図２（ｂ）に示すように、スクライブラインＳＬに沿って半導体ウェハＷをチップ状に切断することにより、半導体ウェハＷから半導体チップ１を切り出すとともに、貫通孔５を縦方向に２分割し、半導体チップ１の側壁に溝８を形成する。
次に、図２（ａ）および図４（ａ）に示すように、同様の方法で形成された半導体チップ１ａ〜１ｃを、接着層１０ｂ、１０ｃをそれぞれ介して積層するとともに、半導体チップ１ｂ、１ｃが積層された半導体チップ１ａを、接着層１０ａを介してインターポーザ基板１１に実装する。なお、各半導体チップ１ａ〜１ｃには、電極パッド２ａ〜２ｃがそれぞれ形成されるとともに、電極パッド２ａ〜２ｃの表面が露出されるようにパターニングされた絶縁膜３ａ〜３ｃがそれぞれ形成されている。そして、各半導体チップ１ａ〜１ｃの側壁には溝８ａ〜８ｃがそれぞれ形成され、各溝８ａ〜８ｃには、絶縁膜６ａ〜６ｃをそれぞれ介し、電極パッド２ａ〜２ｃに接続された導電膜７ａ〜７ｃがそれぞれ形成されている。
【００３０】
次に、図２（ｂ）および図４（ｂ）に示すように、各半導体チップ１ａ〜１ｃの溝８ａ〜８ｃにワイヤボンドを行うことにより、インターポーザ基板１１のランド１２および各導電膜７ａ〜７ｃをワイヤ１３ａ〜１３ｃでそれぞれ接続する。
これにより、半導体チップ１ａ〜１ｃの側方からワイヤ１３ａ〜１３ｃをそれぞれ引き出すことが可能となり、ワイヤ１３ａ〜１３ｃが上方に張り出すことを防止することが可能となるとともに、ワイヤ１３ａ〜１３ｃを接合させる領域を半導体チップ１ａ〜１ｃの表面に確保する必要がなくなる。このため、上層ほど半導体チップ１ａ〜１ｃのサイズを小さくする必要がなくなり、積層される半導体チップ１ａ〜１ｃのサイズの制約をなくすことが可能となるとともに、半導体チップ１ａ〜１ｃの上下の間隔を減少させることを可能として、半導体チップ１ａ〜１ｃの３次元実装構造の薄型化を実現することが可能となる。
【００３１】
なお、上述した実施形態では、３層分の半導体チップ１ａ〜１ｃを積層する方法について説明したが、半導体チップは３層分に限られることなく、１層または２層でもよいし、４層以上でもよい。
図５は、本発明の第２実施形態に係る半導体装置の構成を示す断面図である。図５において、各半導体チップ２１ａ〜２１ｃには、電極パッド２２ａ〜２２ｃがそれぞれ形成されるとともに、電極パッド２２ａ〜２２ｃ上には絶縁膜２３ａ〜２３ｃが形成され、絶縁膜２３ａ〜２３ｃには電極パッド２２ａ〜２２ｃの表面を露出させる開口部２４ａ〜２４ｃが形成されている。そして、各半導体チップ２１ａ〜２１ｃの側壁には溝２８ａ〜２８ｃがそれぞれ形成され、各溝２８ａ〜２８ｃには、絶縁膜２６ａ〜２６ｃをそれぞれ介し、電極パッド２２ａ〜２２ｃに接続された導電膜２７ａ〜２７ｃがそれぞれ形成されている。そして、半導体チップ２１ａ〜２１ｃが、接着層３０ｂ、３０ｃをそれぞれ介して積層されるとともに、半導体チップ３１ｂ、３１ｃが積層された半導体チップ３１ａは、接着層３０ａを介してインターポーザ基板３１に実装されている。なお、半導体チップ２１ａ〜２１ｃのサイズは必ずしも一致している必要はなく、例えば、上層ほどサイズを小さくすることができる。ここで、サイズの異なる半導体チップ２１ａ〜２１ｃを積層する場合、電極パッド２２ａ〜２２ｃの配置領域を避けるように、半導体チップ２１ａ〜２１ｃを必ずしも配置する必要はなく、電極パッド２２ａ〜２２ｃ上に半導体チップ２１ａ〜２１ｃが配置されていてもよい。
【００３２】
そして、各半導体チップ２１ａ〜２１ｃの溝２８ａ〜２８ｃにワイヤボンドを行うことにより、インターポーザ基板３１のランド３２および各導電膜２７ａ〜２７ｃをワイヤ３３ａ〜３３ｃでそれぞれ接続する。
これにより、半導体チップ２１ａ〜２１ｃのサイズが異なる場合においても、ワイヤ３３ａ〜３３ｃが上方に張り出すことを防止しつつ、半導体チップ２１ａ〜２１ｃをワイヤボンド接続することが可能となり、様々な機能を持たせることを可能としつつ、半導体チップ２１ａ〜２１ｃの３次元実装構造の薄型化を図ることが可能となる。
【００３３】
なお、上述した半導体装置および電子デバイスは、例えば、液晶表示装置、携帯電話、携帯情報端末、ビデオカメラ、デジタルカメラ、ＭＤ（Ｍｉｎｉ Ｄｉｓｃ）プレーヤなどの電子機器に適用することができ、電子機器の小型・軽量化を図ることが可能となる。
また、上述した実施形態では、半導体チップを積層する方法を例にとって説明したが、本発明は、必ずしも半導体チップを積層する方法に限定されることなく、例えば、弾性表面波（ＳＡＷ）素子などのセラミック素子、光変調器や光スイッチなどの光学素子、磁気センサやバイオセンサなどの各種センサ類などを積層するようにしてもよい。
【図面の簡単な説明】
【図１】第１実施形態に係る半導体装置の製造方法を示す断面図。
【図２】第１実施形態に係る半導体装置の製造方法を示す斜視図。
【図３】第１実施形態に係る半導体装置の製造方法を示す断面図。
【図４】第１実施形態に係る半導体装置の製造方法を示す斜視図。
【図５】第２実施形態に係る半導体装置の構成を示す断面図。
【図６】従来の半導体装置の構成を示す断面図。
【図７】従来の半導体装置の構成を示す断面図。
【符号の説明】
Ｗ 半導体ウェハ １、２１ａ〜２１ｃ 半導体チップ、２、２２ａ〜２２ｃ電極パッド、３、６、２３ａ〜２３ｃ、２６ａ〜２６ｃ 絶縁膜、４、２４ａ〜２４ｃ 開口部、５ 貫通孔、７、２７ａ〜２７ｃ 再配置配線 ８、２８ａ〜２８ｃ 溝、９ 素子形成領域 １０ａ〜１０ｃ、３０ａ〜３０ｃ 接着層、１１、３１ インターポーザ基板、１２、３２ ランド、１３ａ〜１３ｃ、３３ａ〜３３ｃ ワイヤ、ＳＬ スクライブライン[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, an electronic device, an electronic apparatus, a method for manufacturing a semiconductor device, and a method for manufacturing an electronic device, and is particularly suitable for application to an interlayer connection method in a stacked structure of semiconductor chips.
[0002]
[Prior art]
2. Description of the Related Art In a conventional semiconductor device, there has been a method in which stacked semiconductor chips are connected by wire bonding in order to realize a three-dimensional mounting structure of the semiconductor chips.
FIG. 6 is a cross-sectional view showing a configuration of a conventional semiconductor device.
In FIG. 6, semiconductor chips 41a to 41c are stacked via adhesive layers 42b and 42c, respectively. The semiconductor chip 41a on which the semiconductor chips 41b and 41c are stacked is mounted on an interposer substrate 44 via the adhesive layer 42a. I have. The semiconductor chips 41a to 41c are connected to lands 45 provided on the interposer substrate 44 via wires 43a to 43c, respectively.
[0003]
Here, the size of the semiconductor chips 41a to 41c is smaller in the upper layer. The semiconductor chip 41b is stacked on the semiconductor chip 41a so as to avoid the connection area of the wire 43a of the semiconductor chip 41a, and the semiconductor chip 41c is mounted on the semiconductor chip 41b so as to avoid the connection area of the wire 43b of the semiconductor chip 41b. Are laminated.
[0004]
FIG. 7 is a cross-sectional view showing a configuration of a conventional semiconductor device.
In FIG. 7, mirror chips 53a and 53b are provided between semiconductor chips 51a to 51c, respectively, and adhesive layers 52b, 52c, 52d and 52e are provided on both surfaces of the mirror chips 53a and 53b, respectively. The semiconductor chips 51a to 51c are stacked via mirror chips 53a and 53b provided with adhesive layers 52b, 52c, 52d and 52e, respectively. The semiconductor chip 51a on which the semiconductor chips 51b and 51c are stacked is an adhesive layer. It is mounted on the interposer board 55 via 52a. The semiconductor chips 51a to 51c are connected to lands 56 provided on the interposer substrate 55 via wires 54a to 54c, respectively.
[0005]
Here, by providing the mirror chips 53a and 53b between the semiconductor chips 51a to 51c, the interval between the semiconductor chips 51a to 51c can be increased. Therefore, even when the sizes of the semiconductor chips 51a to 51c are equal, it is possible to prevent the wires 54a to 54c connected to the lower semiconductor chips 51a to 51c from coming into contact with the upper semiconductor chips 51a to 51c. It is not necessary to reduce the size of the semiconductor chips 51a to 51c toward the upper layer.
[0006]
[Problems to be solved by the invention]
However, in the semiconductor device of FIG. 6, in order to wire-bond the semiconductor chips 41a to 41c, it is necessary to reduce the size in the upper layer, and the size of the semiconductor chips 41a to 41c is restricted, and the wires 43a to 43c are There is a problem that the height of the three-dimensional mounting structure of the semiconductor chip becomes large because the semiconductor chip 41a-41c projects above the semiconductor chip 41a-41c.
[0007]
Further, in the semiconductor device of FIG. 7, although it is not necessary to reduce the size of the semiconductor chips 51a to 51c toward the upper layer, mirror chips 53a and 53b need to be inserted between the semiconductor chips 51a to 51c. There is a problem that the height of the three-dimensional mounting structure is increased.
Therefore, an object of the present invention is to provide a semiconductor device, an electronic device, an electronic apparatus, and a method of manufacturing a semiconductor device that can realize a thin three-dimensional mounting structure of a semiconductor chip without being limited by the size of the semiconductor chip. And a method of manufacturing an electronic device.
[0008]
[Means for Solving the Problems]
According to one embodiment of the present invention, there is provided a semiconductor device including a wiring layer formed over a semiconductor chip, a conductive layer connected to the wiring layer, and formed on a sidewall of the semiconductor chip. And a wire connected to the conductive layer.
[0009]
As a result, the wires can be pulled out from the sides of the semiconductor chip, and the wires can be prevented from protruding upward, so that the semiconductor chip can be mounted while suppressing an increase in height. Becomes possible.
Further, according to the semiconductor device of one embodiment of the present invention, the wiring layer formed on the semiconductor chip, and the groove formed on the cut surface of the semiconductor chip so as to cross the semiconductor chip in the thickness direction. , A conductive layer formed in the groove, and a wire connected to the conductive layer.
[0010]
This makes it possible to stably form the conductive layer on the side wall of the semiconductor chip, and to easily pull out the wire from the side of the semiconductor chip. Therefore, it is possible to prevent the wires from projecting upward, and it is possible to mount the semiconductor chip while suppressing an increase in height.
Further, according to the semiconductor device of one embodiment of the present invention, the first wiring layer formed on the first semiconductor chip and the first wiring layer are connected to the first wiring layer and formed on the side wall of the first semiconductor chip. A first conductive layer, a second semiconductor chip stacked on the first semiconductor chip, a second wiring layer formed on the second semiconductor chip, and a second wiring layer connected to the second wiring layer; The semiconductor device includes a second conductive layer formed on a side wall of the semiconductor chip, and a first wire connecting the first conductive layer and the second conductive layer.
[0011]
As a result, the wires can be pulled out from the sides of the semiconductor chip, and it is possible to prevent the wires from extending upward, and it is not necessary to secure a region where the wires are joined on the surface of the semiconductor chip. . Therefore, it is not necessary to reduce the size of the semiconductor chip in the upper layer, and it is possible to eliminate the restriction on the size of the semiconductor chip to be stacked and to reduce the vertical distance between the semiconductor chips. It is possible to reduce the thickness of the three-dimensional mounting structure.
[0012]
Further, according to the semiconductor device of one embodiment of the present invention, the first wiring layer formed on the first semiconductor chip and the first semiconductor chip are formed so as to cross the first semiconductor chip in a thickness direction. A first groove formed in the cut surface, a first conductive layer formed in the first groove, a second semiconductor chip stacked on the first semiconductor chip, and formed on the second semiconductor chip. A second wiring layer, a second groove formed in a cut surface of the second semiconductor chip so as to cross the second semiconductor chip in a thickness direction, and a second conductive layer formed in the second groove. And a first wire connecting the first conductive layer and the second conductive layer.
[0013]
This makes it possible to stably form the conductive layer on the side wall of the semiconductor chip, and to easily pull out the wire from the side of the semiconductor chip. For this reason, it is possible to prevent the wires from projecting upward, and it is not necessary to secure a region for bonding the wires on the surface of the semiconductor chip, and the semiconductor chip is not restricted by the size of the semiconductor chip. It is possible to reduce the thickness of the three-dimensional mounting structure.
[0014]
Further, according to the semiconductor device of one embodiment of the present invention, an interposer substrate on which the first semiconductor chip on which the second semiconductor chip is stacked is mounted, a land provided on the interposer substrate, And a second wire connecting the first conductive layer.
This makes it possible to connect the stacked semiconductor chips to each other by performing the wire bonding continuously, and to connect the stacked semiconductor chips to the interposer substrate, which makes the mounting process complicated. It is possible to three-dimensionally mount the semiconductor chip while suppressing the above.
[0015]
Further, according to the semiconductor device of one embodiment of the present invention, the first semiconductor chip and the second semiconductor chip are different in at least one of size, thickness, and type.
Accordingly, by performing wire bond connection of the semiconductor chip, various functions can be provided, and the three-dimensional mounting structure of the semiconductor chip can be reduced in thickness.
[0016]
Further, according to the electronic device of one embodiment of the present invention, the first wiring layer is formed on the first electronic component, and the first wiring layer is connected to the first wiring layer and formed on the side wall of the first electronic component. A first conductive layer, a second electronic component laminated on the first electronic component, a second wiring layer formed on the second electronic component, and a second wiring layer connected to the second wiring layer; A second conductive layer formed on a side wall of the electronic component; and a wire connecting the first conductive layer and the second conductive layer.
[0017]
Thereby, the wire can be pulled out from the side of the electronic component, and it is possible to prevent the wire from projecting upward, and it is not necessary to secure a region for joining the wire on the surface of the electronic component. . For this reason, it is not necessary to reduce the size of the electronic component in the upper layer, and it is possible to eliminate the restriction on the size of the electronic component to be stacked, and it is possible to reduce the vertical interval of the electronic component. It is possible to reduce the thickness of the three-dimensional mounting structure.
[0018]
Further, according to the electronic device of one embodiment of the present invention, the first wiring layer formed on the first semiconductor chip and the first wiring layer are connected to the first wiring layer and formed on the side wall of the first semiconductor chip. A first conductive layer, a second semiconductor chip stacked on the first semiconductor chip, a second wiring layer formed on the second semiconductor chip, and a second wiring layer connected to the second wiring layer; A second conductive layer formed on a side wall of the semiconductor chip, a first wire connecting the first conductive layer and the second conductive layer, and the first semiconductor chip on which the second semiconductor chip is stacked are mounted. An interposer substrate, a land provided on the interposer substrate, and a second wire connecting the land to the first conductive layer.
[0019]
As a result, the wires can be pulled out from the sides of the semiconductor chip, and it is possible to prevent the wires from extending upward, and it is not necessary to secure a region where the wires are joined on the surface of the semiconductor chip. Therefore, it is possible to reduce the thickness of the three-dimensional mounting structure of the semiconductor chip without being limited by the size of the semiconductor chip.
[0020]
According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the first conductive layer connected to the first wiring layer formed on the first semiconductor chip is formed on the side wall of the first semiconductor chip. Forming a second conductive layer connected to a second wiring layer formed on a second semiconductor chip on a side wall of the second semiconductor chip; and forming the second semiconductor chip on the first semiconductor chip And a step of wire-bonding the first conductive layer and the second conductive layer formed on the side wall.
[0021]
As a result, wires can be drawn out from the sides of the semiconductor chip, and by performing wire bond connection of the semiconductor chip, the thickness of the three-dimensional mounting structure of the semiconductor chip can be reduced without being limited by the size of the semiconductor chip. It can be realized.
According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming a through-hole on a cutting line of a semiconductor wafer on which an electrode pad is formed, and the step of exposing a surface of the electrode pad Forming an insulating film on the surface of the through hole, forming a conductive film connected to the electrode pad in the through hole, and cutting the semiconductor wafer into chips along the cutting line. Connecting the stacked semiconductor chips by performing wire bonding to the conductive layer in the through-hole divided along the cutting line, and the step of stacking the semiconductor chips cut into the chip shape; and And a step.
[0022]
Thus, by using the photolithography technology and the etching technology, it is possible to collectively form the conductive film on the side walls of the plurality of semiconductor chips, and it is possible to draw out the wires from the sides of the semiconductor chip. For this reason, the semiconductor chip can be connected by wire bonding without being restricted by the size of the semiconductor chip, and the thickness of the three-dimensional mounting structure of the semiconductor chip can be reduced while suppressing the complexity of the manufacturing process. It becomes possible.
[0023]
Further, according to the method for manufacturing an electronic device according to one aspect of the present invention, the first conductive layer connected to the first wiring layer formed on the first electronic component is formed on the side wall of the first electronic component. Forming a second conductive layer connected to a second wiring layer formed on the second electronic component on a side wall of the second electronic component, and forming the second electronic layer on the first electronic component. The method further comprises a step of stacking components and a step of wire bonding connecting the first conductive layer and the second conductive layer formed on the side wall.
[0024]
As a result, the wires can be pulled out from the sides of the electronic component, and the three-dimensional mounting structure of the electronic component can be made thinner without being restricted by the size of the electronic component.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention will be described with reference to the drawings.
1 and 3 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention, and FIGS. 2 and 4 are perspective views illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention. is there.
[0026]
1A and 2A, a semiconductor wafer W is partitioned by scribe lines SL, and an element forming region 9 is provided in each partitioned region. Then, as shown in FIG. 1A, an electrode pad 2 is formed on the semiconductor wafer W, an insulating film 3 is formed on the electrode pad 2, and the surface of the electrode pad 2 is formed on the insulating film 3. An opening 4 to be exposed is formed.
[0027]
Next, as shown in FIG. 1B, through holes 5 arranged on the scribe lines SL are formed in the semiconductor wafer W by using, for example, photolithography technology and etching technology. When the through holes 5 are formed, for example, laser processing or the like may be used.
Next, as shown in FIG. 1C, an insulating film 6 is formed on the entire surface of the semiconductor wafer W including the inside of the through hole 5 by a method such as CVD. Then, the surface of the electrode pad 2 is exposed by patterning the insulating film 6 using a photolithography technique and an etching technique. As the insulating film 6, for example, a silicon oxide film or a silicon nitride film can be used.
[0028]
Next, as shown in FIG. 1D and FIG. 2A, a conductive film 7 is formed on the entire surface of the semiconductor wafer W including the inside of the through hole 5 by a method such as sputtering, vapor deposition, or CVD. Then, by patterning the conductive film 7 using a photolithography technique and an etching technique, the electrode pad 2 and the through-hole 5 are connected one-to-one for each of the divided regions. As the conductive film 7, for example, Al, Cu, Au, W, or the like can be used.
[0029]
Next, as shown in FIGS. 1E and 2B, the semiconductor chip 1 is cut out from the semiconductor wafer W by cutting the semiconductor wafer W into chips along the scribe lines SL, and the through holes are formed. 5 is divided into two in the vertical direction, and a groove 8 is formed in the side wall of the semiconductor chip 1.
Next, as shown in FIG. 2A and FIG. 4A, the semiconductor chips 1a to 1c formed by the same method are stacked via adhesive layers 10b and 10c, respectively, and the semiconductor chips 1b and The semiconductor chip 1a on which the layers 1c are stacked is mounted on the interposer substrate 11 via the adhesive layer 10a. In addition, on each of the semiconductor chips 1a to 1c, electrode pads 2a to 2c are formed, respectively, and insulating films 3a to 3c patterned so that the surfaces of the electrode pads 2a to 2c are exposed are formed, respectively. . Grooves 8a to 8c are formed on the side walls of the semiconductor chips 1a to 1c, respectively, and the conductive films 7a connected to the electrode pads 2a to 2c via the insulating films 6a to 6c in the grooves 8a to 8c, respectively. To 7c are respectively formed.
[0030]
Next, as shown in FIGS. 2B and 4B, the lands 12 of the interposer substrate 11 and the conductive films 7a to 7c are formed by wire bonding to the grooves 8a to 8c of the semiconductor chips 1a to 1c. 7c are connected by wires 13a to 13c, respectively.
This makes it possible to pull out the wires 13a to 13c from the sides of the semiconductor chips 1a to 1c, respectively, to prevent the wires 13a to 13c from projecting upward, and to join the wires 13a to 13c. It is not necessary to secure a region to be formed on the surfaces of the semiconductor chips 1a to 1c. For this reason, it is not necessary to reduce the size of the semiconductor chips 1a to 1c in the upper layer, and it is possible to eliminate the restriction on the size of the semiconductor chips 1a to 1c to be stacked and to reduce the distance between the upper and lower semiconductor chips 1a to 1c. By making it possible to reduce the thickness, it is possible to realize a thin three-dimensional mounting structure of the semiconductor chips 1a to 1c.
[0031]
In the above-described embodiment, a method of stacking three layers of semiconductor chips 1a to 1c has been described. However, the number of semiconductor chips is not limited to three, and may be one or two, or four or more. May be.
FIG. 5 is a cross-sectional view illustrating a configuration of a semiconductor device according to a second embodiment of the present invention. In FIG. 5, electrode pads 22a to 22c are respectively formed on the semiconductor chips 21a to 21c, insulating films 23a to 23c are formed on the electrode pads 22a to 22c, and electrodes are formed on the insulating films 23a to 23c. Openings 24a to 24c that expose the surfaces of the pads 22a to 22c are formed. Grooves 28a to 28c are formed on the side walls of the semiconductor chips 21a to 21c, respectively. The conductive films 27a connected to the electrode pads 22a to 22c are formed in the grooves 28a to 28c via the insulating films 26a to 26c, respectively. To 27c are respectively formed. The semiconductor chips 21a to 21c are stacked via the adhesive layers 30b and 30c, respectively, and the semiconductor chip 31a on which the semiconductor chips 31b and 31c are stacked is mounted on the interposer substrate 31 via the adhesive layer 30a. I have. Note that the sizes of the semiconductor chips 21a to 21c do not necessarily have to be the same, and, for example, the size can be reduced in the upper layer. Here, when the semiconductor chips 21a to 21c having different sizes are stacked, the semiconductor chips 21a to 21c do not necessarily need to be arranged so as to avoid the area where the electrode pads 22a to 22c are arranged, and the semiconductor chips 21a to 21c are formed on the electrode pads 22a to 22c. The chips 21a to 21c may be arranged.
[0032]
Then, by bonding the wires to the grooves 28a to 28c of the semiconductor chips 21a to 21c, the lands 32 of the interposer substrate 31 and the conductive films 27a to 27c are connected by wires 33a to 33c, respectively.
Accordingly, even when the sizes of the semiconductor chips 21a to 21c are different, the semiconductor chips 21a to 21c can be wire-bonded while preventing the wires 33a to 33c from projecting upward. It is possible to reduce the thickness of the three-dimensional mounting structure of the semiconductor chips 21a to 21c while allowing the semiconductor chips 21a to 21c to be provided.
[0033]
Note that the above-described semiconductor device and electronic device can be applied to electronic devices such as a liquid crystal display device, a mobile phone, a personal digital assistant, a video camera, a digital camera, and an MD (Mini Disc) player. It is possible to reduce the size and weight.
Further, in the above-described embodiment, a method of stacking semiconductor chips has been described as an example. However, the present invention is not necessarily limited to a method of stacking semiconductor chips, and for example, a surface acoustic wave (SAW) element or the like may be used. Ceramic elements, optical elements such as optical modulators and optical switches, and various sensors such as magnetic sensors and biosensors may be stacked.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to a first embodiment.
FIG. 2 is a perspective view showing the method for manufacturing the semiconductor device according to the first embodiment.
FIG. 3 is a sectional view showing the method of manufacturing the semiconductor device according to the first embodiment.
FIG. 4 is a perspective view showing the method for manufacturing the semiconductor device according to the first embodiment.
FIG. 5 is a sectional view showing a configuration of a semiconductor device according to a second embodiment.
FIG. 6 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.
FIG. 7 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.
[Explanation of symbols]
W semiconductor wafer 1, 21a to 21c semiconductor chip, 2, 22a to 22c electrode pad, 3, 6, 23a to 23c, 26a to 26c insulating film, 4, 24a to 24c opening, 5 through hole, 7, 27a to 27c Relocation wiring 8, 28a-28c groove, 9 element formation region 10a-10c, 30a-30c adhesive layer, 11, 31 interposer substrate, 12, 32 land, 13a-13c, 33a-33c wire, SL scribe line

Claims (11)

半導体チップ上に形成された配線層と、
前記配線層に接続され、前記半導体チップの側壁に形成された導電層と、
前記導電層に接続されたワイヤとを備えることを特徴とする半導体装置。A wiring layer formed on the semiconductor chip,
A conductive layer connected to the wiring layer and formed on a side wall of the semiconductor chip;
And a wire connected to the conductive layer. 半導体チップ上に形成された配線層と、
前記半導体チップを厚み方向に横切るようにして、前記半導体チップの切断面に形成された溝と、
前記溝に形成された導電層と、
前記導電層に接続されたワイヤとを備えることを特徴とする半導体装置。A wiring layer formed on the semiconductor chip,
A groove formed on a cut surface of the semiconductor chip so as to cross the semiconductor chip in a thickness direction,
A conductive layer formed in the groove,
And a wire connected to the conductive layer. 第１半導体チップ上に形成された第１配線層と、
前記第１配線層に接続され、前記第１半導体チップの側壁に形成された第１導電層と、
前記第１半導体チップ上に積層された第２半導体チップと、
前記第２半導体チップ上に形成された第２配線層と、
前記第２配線層に接続され、前記第２半導体チップの側壁に形成された第２導電層と、
前記第１導電層と前記第２導電層とを接続する第１ワイヤとを備えることを特徴とする半導体装置。A first wiring layer formed on the first semiconductor chip;
A first conductive layer connected to the first wiring layer and formed on a side wall of the first semiconductor chip;
A second semiconductor chip stacked on the first semiconductor chip;
A second wiring layer formed on the second semiconductor chip;
A second conductive layer connected to the second wiring layer and formed on a side wall of the second semiconductor chip;
A semiconductor device comprising: a first wire that connects the first conductive layer and the second conductive layer. 第１半導体チップ上に形成された第１配線層と、
前記第１半導体チップを厚み方向に横切るようにして、前記第１半導体チップの切断面に形成された第１溝と、
前記第１溝に形成された第１導電層と、
前記第１半導体チップ上に積層された第２半導体チップと、
前記第２半導体チップ上に形成された第２配線層と、
前記第２半導体チップを厚み方向に横切るようにして、前記第２半導体チップの切断面に形成された第２溝と、
前記第２溝に形成された第２導電層と、
前記第１導電層と前記第２導電層とを接続する第１ワイヤとを備えることを特徴とする半導体装置。A first wiring layer formed on the first semiconductor chip;
A first groove formed in a cut surface of the first semiconductor chip so as to cross the first semiconductor chip in a thickness direction;
A first conductive layer formed in the first groove;
A second semiconductor chip stacked on the first semiconductor chip;
A second wiring layer formed on the second semiconductor chip;
A second groove formed in a cut surface of the second semiconductor chip so as to cross the second semiconductor chip in a thickness direction;
A second conductive layer formed in the second groove;
A semiconductor device comprising: a first wire that connects the first conductive layer and the second conductive layer. 前記第２半導体チップが積層された前記第１半導体チップを搭載するインターポーザ基板と、
前記インターポーザ基板に設けられたランドと、
前記ランドと前記第１導電層とを接続する第２ワイヤとを備えることを特徴とする請求項３または４記載の半導体装置。An interposer substrate on which the first semiconductor chip on which the second semiconductor chip is stacked is mounted;
A land provided on the interposer substrate;
The semiconductor device according to claim 3, further comprising a second wire connecting the land and the first conductive layer. 前記第１半導体チップと前記第２半導体チップとは、サイズ、厚みまたは種類の少なくともいずれか１つが異なっていることを特徴とする請求項３〜５のいずれか１項記載の半導体装置。The semiconductor device according to claim 3, wherein the first semiconductor chip and the second semiconductor chip are different in at least one of size, thickness, and type. 第１電子部品上に形成された第１配線層と、
前記第１配線層に接続され、前記第１電子部品の側壁に形成された第１導電層と、
前記第１電子部品上に積層された第２電子部品と、
前記第２電子部品上に形成された第２配線層と、
前記第２配線層に接続され、前記第２電子部品の側壁に形成された第２導電層と、
前記第１導電層と前記第２導電層とを接続するワイヤとを備えることを特徴とする電子デバイス。A first wiring layer formed on the first electronic component;
A first conductive layer connected to the first wiring layer and formed on a side wall of the first electronic component;
A second electronic component laminated on the first electronic component;
A second wiring layer formed on the second electronic component;
A second conductive layer connected to the second wiring layer and formed on a side wall of the second electronic component;
An electronic device, comprising: a wire connecting the first conductive layer and the second conductive layer. 第１半導体チップ上に形成された第１配線層と、
前記第１配線層に接続され、前記第１半導体チップの側壁に形成された第１導電層と、
前記第１半導体チップ上に積層された第２半導体チップと、
前記第２半導体チップ上に形成された第２配線層と、
前記第２配線層に接続され、前記第２半導体チップの側壁に形成された第２導電層と、
前記第１導電層と前記第２導電層とを接続する第１ワイヤと、
前記第２半導体チップが積層された前記第１半導体チップを搭載するインターポーザ基板と、
前記インターポーザ基板に設けられたランドと、
前記ランドと前記第１導電層とを接続する第２ワイヤとを備えることを特徴とする電子機器。A first wiring layer formed on the first semiconductor chip;
A first conductive layer connected to the first wiring layer and formed on a side wall of the first semiconductor chip;
A second semiconductor chip stacked on the first semiconductor chip;
A second wiring layer formed on the second semiconductor chip;
A second conductive layer connected to the second wiring layer and formed on a side wall of the second semiconductor chip;
A first wire connecting the first conductive layer and the second conductive layer,
An interposer substrate on which the first semiconductor chip on which the second semiconductor chip is stacked is mounted;
A land provided on the interposer substrate;
An electronic device, comprising: a second wire connecting the land and the first conductive layer. 第１半導体チップ上に形成された第１配線層に接続された第１導電層を前記第１半導体チップの側壁に形成する工程と、
第２半導体チップ上に形成された第２配線層に接続された第２導電層を前記第２半導体チップの側壁に形成する工程と、
前記第１半導体チップ上に前記第２半導体チップを積層する工程と、
前記側壁に形成された前記第１導電層と前記第２導電層とをワイヤボンド接続する工程とを備えることを特徴とする半導体装置の製造方法。Forming a first conductive layer connected to a first wiring layer formed on the first semiconductor chip on a side wall of the first semiconductor chip;
Forming a second conductive layer connected to a second wiring layer formed on the second semiconductor chip on a side wall of the second semiconductor chip;
Laminating the second semiconductor chip on the first semiconductor chip;
And a step of wire bonding connecting the first conductive layer and the second conductive layer formed on the side wall. 電極パッドが形成された半導体ウェハの切断線上に貫通孔を形成する工程と、
前記電極パッドの表面が露出されるようにして、前記貫通孔の表面に絶縁膜を形成する工程と、
前記電極パッドに接続された導電膜を前記貫通孔内に形成する工程と、
前記切断線に沿って前記半導体ウェハをチップ状に切断する工程と、
前記チップ状に切断された半導体チップを積層する工程と、
前記切断線に沿って分割された貫通孔内の導電層にワイヤボンドを行うことにより、前記積層された半導体チップを接続する工程とを備えることを特徴とする半導体装置の製造方法。Forming a through hole on a cutting line of the semiconductor wafer on which the electrode pad is formed,
Forming an insulating film on the surface of the through hole so that the surface of the electrode pad is exposed;
Forming a conductive film connected to the electrode pad in the through hole;
Cutting the semiconductor wafer into chips along the cutting line;
Laminating the semiconductor chips cut into chips,
Connecting the stacked semiconductor chips by performing wire bonding on the conductive layer in the through hole divided along the cutting line, thereby manufacturing the semiconductor device. 第１電子部品上に形成された第１配線層に接続された第１導電層を前記第１電子部品の側壁に形成する工程と、
第２電子部品上に形成された第２配線層に接続された第２導電層を前記第２電子部品プの側壁に形成する工程と、
前記第１電子部品上に前記第２電子部品を積層する工程と、
前記側壁に形成された前記第１導電層と前記第２導電層とをワイヤボンド接続する工程とを備えることを特徴とする電子デバイスの製造方法。Forming a first conductive layer connected to a first wiring layer formed on the first electronic component on a side wall of the first electronic component;
Forming a second conductive layer connected to a second wiring layer formed on the second electronic component on a side wall of the second electronic component;
Laminating the second electronic component on the first electronic component;
And a step of wire-bonding the first conductive layer and the second conductive layer formed on the side wall.
JP2003072564A 2003-03-17 2003-03-17 Semiconductor device, electronic device, electronic apparatus, method for manufacturing semiconductor device, and method for manufacturing electronic device Pending JP2004281819A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11469184B2 (en) 2020-03-23 2022-10-11 Kioxia Corporation Semiconductor device and manufacturing method of the same

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