JP2004279855A - Video image capture circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To minimize deterioration of display quality of a moving image while attaining commonality and simplification of circuit arrangements in a video image capture circuit capable of fetching one scene as a still picture while displaying a moving image 12 on a display 11 by converting an analog video signal Sa inputted from video equipment 10 into a digital video signal Sd and also storing it in a video memory 14. <P>SOLUTION: Storage areas for a moving image and a still image are arranged separately in the video memory 14 in which the picture data Dg are stored, and when storing the picture data Dg inputted from the video equipment 10 in the video memory 14, the moving picture data are normally written to the moving picture data storage area, and the still image data for one frame are stored in the still image data storage area at the time of capture. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video image capture circuit capable of reproducing a moving image by writing an analog video signal from a video device to a video memory while digitizing the analog video signal, and capturing one scene in the moving image.
[0002]
[Prior art]
Conventionally, in this type of video image capture circuit, generally, digitized image data is generally stored in a memory for displaying moving images and a memory for storing captured images in parallel (for example, Patent Document 1).
[0003]
[Patent Document 1]
JP 2001-169244 A
[Problems to be solved by the invention]
However, since the capture circuit and the moving image display circuit include many common parts, it is wasteful to provide them in parallel. The present inventor has considered this inconvenience, and as a result, by changing the write address of the image data written in the video memory correspondingly during the writing of one frame, an additional function as a capture circuit is obtained. It has been found that deterioration of the display quality of a moving image can be prevented while minimizing the configuration.
[0005]
The present invention has been made based on such knowledge, and provides a storage area for still image data in a video memory in which moving image data is stored, and writes data for one frame in the area, thereby achieving a circuit configuration. It is an object of the present invention to provide a video image capture circuit capable of minimizing the deterioration of the display quality of a moving image while simplifying the above.
[0006]
[Means for Solving the Problems]
The video image capture circuit according to the present invention has a signal conversion means such as an A / D conversion unit 15 for converting an input analog video signal Sa into a digital video signal Sd, as shown in FIG. Image data generating means 16 for extracting image data Dg from the converted digital video signal Sd; data storage means such as a DRAM controller 28 for storing the extracted image data Dg in the video memory 14; And an instructing means 47 for restricting the acquisition time of still image data.
[0007]
As shown in FIG. 7, the video memory 14 is provided with a storage area 41 for moving image data and a storage area 48 for still image data, and one frame of image data is always stored by the data storage means. While repeatedly writing in the storage area 41, image data for one frame is written in the still image data storage area 48 in response to an instruction from the instruction means 47.
[0008]
The image processing apparatus further includes an image transformation unit 17 for performing a transformation process on the image data extracted from the signal conversion unit, and a masking unit 18 for performing a masking process on the transformed image data and specifying image data to be used. be able to.
[0009]
Here, the image deforming means 17 enables at least one of enlargement or reduction of the image displayed by the image data Dg, and the masking means 18 controls the position within a predetermined coordinate range surrounded by the display frame 27. The image data Dg ′ corresponding to the image can be extracted. It is preferable that the image deforming means 17 and the masking means 18 can set different data processing conditions during writing of moving image data and during writing of still image data.
[0010]
The deformation operation in the image deformation means 17 and the mask operation in the masking means 18 are performed by sequentially specifying data to be written to the video memory 14 in the image data Dg. Further, the analog video signal Sa is of an interlace type, and the digital video signal Sd is a signal in which image data Dg corresponding to the scanning positions of the odd field and the even field are alternately sent.
[0011]
The masking means 18 includes a horizontal direction determining unit 21 for determining whether a pixel corresponding to a horizontal scanning position is valid, and a vertical direction determining unit 25 for determining whether each scanning line is valid. The vertical direction determination unit 25 determines the scanning line position to be determined while shifting the scanning line position by one line between the even field and the odd field.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described with reference to FIG. 1, wherein an analog video signal Sa output from an analog video device 10 such as a video recorder or a video camera is digitally converted to display a moving image 12 on a display 11. This will be described in detail based on an example implemented in the video image capture circuit 13 that enables one scene to be stored as a still image.
[0013]
Here, the analog video signal Sa output from the video device 10 is of the NTSC system. As shown in FIG. 2, the total number of scanning lines is 525, but the odd line groups L ₁ , L _3. The horizontal scanning by the groups L ₂ , L _4, ... Is repeated each time, thereby forming one frame with odd and even fields, and displaying the frame for 30 frames per second. .
[0014]
Further, the analog video signal Sa is input to an A / D converter 15 such as a video decoder, and is converted into a digital video signal Sd. The digital video signal Sd, as shown in FIG. 3 (c), by providing a vertical sync signal S ₂ indicating a break of one field, and a field position signals S ₁ indicating whether odd field or even field, 1 The boundaries of data for frames are shown.
[0015]
Further, between the _two vertical synchronizing signals S ₂ and S ₂ , a horizontal synchronizing signal S ₃ is output in accordance with the start and end timings of one horizontal scan, and two horizontal synchronizing signals S ₂ and S ₂ as shown in FIG. in between the synchronization signals _{S 3} · _S 3, YUV data Dy of one line is output.
[0016]
Here, the YUV data Dy is composed of a luminance signal Y and two types of color difference signals CR and CB. One of the color difference signals is omitted for each pixel as shown in FIG. Two formats are used. Therefore, in order to reproduce an image from data in this format, predetermined data processing is required in the next image data generating means 16 to complement the color difference signal CB or CR thinned out for each pixel. .
[0017]
In this embodiment, the image data creating means 16 creates a series of image data Dg corresponding to the above-described scanning positions. The image data Dg has the highest quality image data assumed in advance, that is, the maximum amount of image data. Data. On the other hand, the entirety of the image data Dg output from the image data creating means 16 is not directly stored in the video memory 14 and the image data Dg is not directly subjected to data processing. Alternatively, the data to be stored in the video memory 14 is realized while the masking means 18 sequentially specifies the thinned-out positions of data unnecessary for display, thereby realizing a unified data writing procedure and simplifying the circuit configuration. The amount is being reduced.
[0018]
Here, as illustrated in FIG. 4, the image deforming unit 17 individually includes a horizontal deforming unit 21 and a vertical deforming unit 25 in the original image 19. For example, in the case where the maximum magnification in the horizontal direction is set to 2 times, by repeating the data of each pixel output from the image data generating means 16 two by two, the standard in which the horizontal direction is enlarged twice. Image data Dg corresponding to the image 19a is created.
[0019]
Further, when the control unit 22 receives an instruction to enlarge the original image 19 twice in the horizontal direction from the control unit 22 to the horizontal direction deformation unit 21, all the data of the image data Dg in each horizontal line is deleted. This is dealt with by outputting an effective pixel signal Sp for instructing to be effective. Similarly, when the original image 19 is not enlarged in the horizontal direction, every other data in the image data Dg is designated as an effective pixel, and when the original image 19 is reduced by half, every four effective pixels are designated. This is handled by outputting the designated effective pixel signal Sp. At other magnifications, a method for determining which pixel in the image data Dg is valid is performed using a conventional algorithm, and therefore a detailed description is omitted here.
[0020]
The horizontal deformation means 21, as illustrated in FIG. 4, for counting a horizontal synchronizing signal S ₃ indicating the start position of each scan line, the clock signal S ₄ that is output in synchronization with each pixel of the image data Dg The first horizontal direction determination unit 23 performs the above-described thinning operation using the pixel number of the scanning position determined as described above and the numerical value Hn indicating the enlargement or reduction ratio input from the control unit 22, thereby expanding the image. Regardless of the reduction, the horizontal enlargement / reduction operation is performed using the same circuit configuration and algorithm.
[0021]
As described above, the case of enlarging in the horizontal direction can be dealt with only by allowing the image data creating means 16 to store data of one pixel. Requires a memory for storing one line of data in the image data creating means 16.
[0022]
Therefore, in the present embodiment, it is necessary to perform only a reduction process as necessary and store it in the video memory 14 without performing an advance enlargement process in the vertical direction, and then it is necessary to enlarge and display the original image 19 in the vertical direction. In such a case, the data is read out from the video memory 14 by using the vertical direction enlarging means 24 separately prepared to perform overlapping display of each line. However, it is a matter of course that the image deformation means 17 may enlarge the image in the vertical direction.
[0023]
On the other hand, with respect to the vertical direction of the reduced display, a vertical sync signal S ₂ indicating a start position in one of the fields shown in FIG. 3, the horizontal sync signal S ₃ indicating the start position of each horizontal line, odd field or even field a field position signals S ₁ indicative of, for a numerical value Vn indicating the vertical reduction ratio between the input data with respect to the vertical direction deformation means 25.
[0024]
Meanwhile, the analog video signal Sa is interlace image data Dg that is output from the image data creating means 16 is also an odd field consisting of a horizontal line group L ₁ · L ₃ ··· of odd rows, the horizontal even rows One frame is formed by combining the image data with an even field composed of the line groups L ₂ , L ₄ ,.
[0025]
Therefore, when the original image 19 is reduced in the vertical direction, the first vertical direction determination unit 20 not only ensures that the valid lines are not biased in one field but also combines them as one frame. Even in such a case, it is preferable to adopt a configuration in which it is determined that the thinned lines are uniformly distributed over the entire frame. It should be noted that which line in the image data Dg is actually made effective corresponding to the difference in the reduction ratio can be determined using a conventional algorithm.
[0026]
Next, the masking means 18 does not display the entire deformed image 19b enlarged or reduced by the image deforming means 17 on the display 11, but enables display of only a part thereof. In the present embodiment, based on the deformed image 19b output from the image deforming means 17, the start line position Lsn and the number of display lines Lwn, the start pixel position Psn and the number of display pixels Pwn in the deformed image 19b are displayed. The display frame 27 is defined by individually designating the display frame 27 as shown in FIG. 2 and the write request signal Sw is sent to the DRAM controller 28 only for the image data Dg contained in the display frame 27 so that the display frame 27 is within the rectangular range. The image data Dg ′ for the image is limitedly written to the video memory 14 and can be displayed as the moving image 12 on the display 11.
[0027]
More specifically, as illustrated in FIGS. 5 and 6, the start pixel position Ps is stored in the first register 30 and the number of display pixels Pw is stored in the second register 31 in the second horizontal direction determination unit 29. in conjunction with the input of the signal _{S 3} is inputted by the CPU 32. Here, the first register 30 is a down counter, which counts down by one each time one valid pixel signal Sp is input, and enters the display frame 27 when the count value becomes zero. And the first flip-flop 33 is set. Then, the output Q of the first flip-flop 33 becomes “1”, and is input to the AND circuit 34 together with the valid pixel signal Sp. As a result, the valid pixel signal Sp is input to the second register 31.
[0028]
Here, the second register 31 is also a down counter, and thereafter, the second register 31 starts counting operation instead of the first register 30. Then, when the value Pw set in the second register 31 becomes zero, it is determined that the value goes out of the display frame 27 and the first flip-flop 33 is reset. As a result, the input of the AND circuit 26 becomes “0”, The write request signal Sw to the DRAM controller 28 provided as image data writing means is forcibly stopped.
[0029]
The same applies to the masking process in the vertical direction. The start line position Ls is stored in the third register 36 of the second vertical direction determination unit 35 in FIG. is inputted by the CPU32 in conjunction with the input of the vertical sync signal _{S 2.} Here, the third register 36 is a down counter, which counts down by one each time one valid line signal S1 is input, and enters the display frame 27 when the count value becomes zero. Is set, and the second flip-flop 33a is set. Then, the output of the second flip-flop 33 a becomes “1”, and is input to the AND circuit 38 together with the valid line signal Sl. As a result, the valid line signal Sl is input to the fourth register 37.
[0030]
Further, the fourth register 37 is also a down counter, and thereafter, the fourth register 37 starts counting operation instead of the third register 36. When the value Lw set in the fourth register 37 becomes "0", it is determined that the value goes out of the frame and the second flip-flop 33a is reset. As a result, the input of the AND circuit 26 becomes "0", and the DRAM controller Thus, the write request signal Sw for the G.28 is forcibly stopped.
[0031]
The start line position Lsn and the number of display lines Lwn shown in FIG. 2 are values converted into one frame, that is, the number of lines on the display 11, whereas the image data Dg written to the video memory 14 is an odd number. those corresponding to the interlace method and the line group L ₁ · L ₃ ··· and the even line group L ₂ · L ₄ ··· are alternately output.
[0032]
Therefore, in the present embodiment, as shown in FIG. 6, the start line position Lsn and the number of display lines Lwn are both halved by the first calculation unit 51 and the second calculation unit 52, respectively, and In that case, the difference between the frame and the field is absorbed by setting the value further shifted down by one line as Ls · Lw.
[0033]
The image data Dg for which the write request signal Sw has been issued as described above is written into the video memory 14 under the control of the DRAM controller 28 as shown in FIG. Here, the write start address A ₁₁ of the image data to be written on the video memory 14, by changing the value stored from the CPU32 to the first register 39 of the address data generator 50 shown in FIG. 4, set arbitrarily Is done.
[0034]
Further, the image data Dg ′ to be written in the video memory 14 is for one frame, but the image data Dg to be sent is in units of fields. So address data Da for writing sent to DRAM controller 28 also causes increased from the start address A ₁₁ at address operation unit 40 of the address data generator 50 by two lines minutes, in the even field start address itself increasing one line and a _12, by storing the value in the second register 53, the moving image data storage area 41 of one frame on the video memory 14 is constituted.
[0035]
The image data Dg ′ for one frame written in the moving image data storage area 41 on the video memory 14 is read out at a predetermined timing, and if necessary, is enlarged in the vertical direction and displayed on the display 11. The original image 19 sent from the video device 10 is enlarged or reduced, and the moving image 12 in which unnecessary portions are masked by the display frame 27 is displayed.
[0036]
In the present invention, in addition to the above configuration, one frame of the still image is stored in the video memory 14 in conjunction with a manual operation by the instruction means 47 shown in FIG. 1 or a control signal at an arbitrary timing sent from another circuit. Can be imported to In this case, as described above, data corresponding to the moving image 12 being displayed on the display 11 can be directly captured as a still image for one frame.
[0037]
However, in the present embodiment, the moving image 12 and the still image that are being displayed can have different enlargement ratios or images in the display frame can be captured. Therefore, as shown in FIGS. The values Hn, Vn, Hc, Vc that determine the ratio, the values Psn, Pwn, Lsn, Lwn, and Psc, Pwc, Lsc, Lwc that determine the display frame 27, and the start addresses in the image data storage areas 41, 48 on the video memory 14. provided by distinguishing registers for storing a ₁₁ and a ₂₁ in the moving image and a still image, simultaneously the switch group 43, 43, ... by the switching signal Ss output from the capture timing control unit 42 Switching, the two register groups are selectively switched in response to a frame break.
[0038]
As shown in FIG. 4, the capture timing control unit 42 is composed of two flip-flops 44 and 45 and one AND circuit 46. Both flip-flops 44 and 45 are always reset by the frame end signal Sf. The switching signal Ss of “0” is sent to 43, 43..., And the register group can be used for moving images.
[0039]
In this state, when a capture signal Sc corresponding to an instruction to the instruction unit 47 and instructing to capture a still image is applied to the set terminal of the flip-flop 44 in the middle of the frame, the flip-flop 44 is immediately set and ANDed. The “1” signal is input to one input terminal of the circuit 46. Further, at the end of the frame, the "1" signal is applied to the other end of the AND circuit 46 by the frame end signal Sf. As a result, the flip-flop 45 is also set, and the switch groups 43, 43,. Switch.
[0040]
At this time, as a result of the write address of the video memory 14 Da is changed to the head address A ₂₁ of the still image data storage area 48, the image data in the still image data storage area 48 in place of the moving image data storage area 41 as shown in FIG. 7 Dg 'is stored. Since the switching state of the switch 43 is reset at the break of the next frame, only the image data Dg 'for one frame is captured as still image data.
[0041]
The still image data captured in this manner is extracted at an appropriate time such as when the display of the moving image 12 is stopped, written into another memory such as a hard disk, and then compressed and transmitted as necessary. Data printing such as printing or printing is performed.
[0042]
In the above embodiment, one still image data is stored in response to one capture instruction. However, the present invention is not limited to this, and a plurality of still images may be simultaneously captured at predetermined time intervals. Is also possible. In this case, the storage area 48 for the still image data can be secured for a plurality of frames and stored individually, or writing and reading can be alternately repeated with the storage area 48 being one frame.
[0043]
Further, the timing of capturing the still image is not limited to the timing corresponding to the instruction operation of the operator to the instruction means 47, and is automatically performed every time a predetermined event occurs, such as a predetermined detection operation or the elapse of a set time by a timer. There is no limitation, such as performing a capture operation.
[0044]
The setting of the enlargement ratio of the moving image 12 and the display frame 27 to be displayed on the display 11 can be changed while visually confirming the change state on the screen of the display 11, or the menu 11 is provided with a menu-type indicating means 47. It can be carried out with appropriate changes such as setting specific numerical values. Further, as shown in FIG. 4, a drawing means 49 is further provided, so that a still image can be displayed in a state of overlapping with the reference image 19a.
[0045]
In the above embodiment, the masking means 18 restrictively captures an image within the predetermined coordinate range of the original image 19 using the display frame 27. However, the content to be masked is not limited to the coordinate range, but may be specified in the color moving image. The contents to be masked, such as masking a color or masking depth information in a three-dimensional moving image, can be changed and implemented as appropriate.
[0046]
Although the original image was subjected to the scaling process before the masking process, it is also possible to omit part or all of such processing or to add another data processing operation.
[0047]
【The invention's effect】
As described above, the present invention provides a storage area 48 for still image data in the video memory 14 for storing moving image data, and writes one frame of data in the area 48 in response to a capture instruction. While maximizing the simplicity and commonality of the configuration, it is possible to minimize the deterioration of the display quality of moving images.
[0048]
Furthermore, instead of storing all of the input image data Dg in the video memory 14, the display frame 27 is set in advance and only data within a limited range is selectively stored in the video memory 14 for writing. The amount of data to be suppressed is suppressed to a necessary minimum, and even when frequent access is required, such as when the moving image 12 is displayed, a decrease in display quality can be prevented.
[0049]
When data processing is performed on the image data Dg prior to the video memory 14, the circuit configuration and data are not processed by the image data itself, but by processing the data position to be written in the image data Dg. Since the processing algorithm is the same for the case of a moving image and the case of a still image, the processing algorithm can be simplified and easily configured.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing an example in which the present invention is applied to a video image capture circuit, and compares a block diagram schematically showing a circuit configuration with an image changing process.
FIG. 2 is an explanatory diagram showing a relationship between image data and a display frame.
FIG. 3 is a waveform diagram showing details of a digital video signal.
FIG. 4 is a block diagram illustrating an example of an image transformation unit.
FIG. 5 is a block diagram showing an example of a masking means.
FIG. 6 is a block diagram showing a state of passing parameters for masking.
FIG. 7 is an explanatory diagram showing a storage state of image data in a video memory.
[Explanation of symbols]
REFERENCE SIGNS LIST 10 video equipment 11 display 12 moving image 13 video image capture circuit 14 video memory 15 A / D converter 16 image data creating means 17 image deforming means 18 masking means 19 original image 19 a reference image 19 b deformed image 20 first vertical direction determination Unit 21 horizontal direction deformation unit 22 control unit 23 first horizontal direction determination unit 24 vertical direction expansion unit 25 vertical direction deformation unit 27 display frame 28 DRAM controller 29 second horizontal direction determination unit 32 CPU
35 second vertical direction determination section 40 address calculation section 41 moving image data storage area 42 capture timing control section 43 switch 47 instructing means 48 still image data storage area 49 drawing means 50 address data generation section 51 first calculation section 52 second Arithmetic unit

Claims (5)

Signal conversion means for converting the input analog video signal into a digital video signal,
Image data creating means for extracting image data from the converted digital video signal,
Data storage means for storing the extracted image data in a video memory;
Instruction means for regulating the acquisition time of still image data from the image data, and a video image capture circuit comprising:
The video memory includes a storage area for moving image data and a storage area for still image data,
While the storage unit constantly writes image data for one frame repeatedly in the moving image data storage area,
A video image capture circuit, wherein one frame of image data is written to the still image data storage area in response to an instruction from the instruction means. Signal conversion means for converting the input analog video signal into a digital video signal,
Data extracting means for extracting image data from the converted digital video signal,
Image deformation means for performing a deformation process on the extracted image data;
Masking means for performing a masking process on the transformed image data and specifying image data to be used;
Data storage means for storing the specified image data in a video memory;
A video capture circuit comprising an instruction unit that regulates the acquisition time of still image data from the image data,
The video memory includes a storage area for moving image data and a storage area for still image data,
While the storage unit constantly writes image data for one frame repeatedly in the moving image data storage area,
A video image capture circuit for writing one frame of image data into the still image data storage area in response to an instruction from the instruction means. The image deforming means enables at least one of enlargement or reduction of an image displayed by the image data,
The masking means is capable of extracting image data corresponding to an image within a predetermined coordinate range,
3. The video image capture circuit according to claim 2, wherein the image deforming means and the masking means can set different data processing conditions during the writing of the moving image data and during the writing of the still image data. 4. The video image capture circuit according to claim 2, wherein the deformation operation in the image deformation unit and the mask operation in the masking unit are performed by sequentially specifying data to be written to a video memory in the image data. The analog video signal is of an interlace type, and the digital video signal is one in which image data corresponding to scanning positions of an odd field and an even field are alternately sent,
The masking means includes:
A horizontal direction determining unit that determines whether a pixel corresponding to a horizontal scanning position is valid,
A vertical direction determination unit that determines whether each scan line is valid,
5. The video image capture circuit according to claim 4, wherein the vertical direction determination unit determines the scan line position to be determined while shifting the scan line position by one line between the even field and the odd field.

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