JP2004260557A - Digital/analog conversion circuit and display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital/analog conversion circuit and a display capable of high speed operation while reducing power consumption. <P>SOLUTION: The digital/analog conversion circuit comprises a circuit 8 outputting a plurality of reference voltages, a circuit 9 for selecting a desired reference voltage, and a D/A converter 10 performing D/A conversion of digital pixel data based on the selected reference voltage. The reference voltage output circuit 8 comprises a resistor array 21 consisting of a plurality of resistive elements, a capacitor C1 having one end set at a voltage of 3.75V, a capacitor C2 having one end set at a voltage of 1.25V, an analog switch SW1 connected between one end of the capacitor C1 and the joint of resistive elements R1 and R2, an analog switch SW2 connected between one end of the capacitor C2 and the joint of the resistive elements R1 and R2, an analog switch SW3 connected between one end of the capacitor C1 and the joint of resistive elements R3 and R4, and an analog switch SW4 connected between one end of the capacitor C2 and the joint of the resistive elements R3 and R4. Output impedance of the reference voltage output circuit can be reduced without decreasing the resistance of each resistive element constituting the resistor array and thereby power consumption can be reduced. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a digital-to-analog conversion circuit that selects a reference voltage according to a digital signal from a plurality of reference voltages generated by resistance voltage division, and a display device incorporating this type of digital-to-analog conversion circuit.
[0002]
[Prior art]
The liquid crystal display device includes a pixel array unit in which signal lines and scanning lines are arranged in rows, and a driving circuit that drives the signal lines and scanning lines. Conventionally, since the pixel array section and the drive circuit are formed on separate substrates, the cost of the entire liquid crystal display device cannot be reduced.
[0003]
Recently, a manufacturing technique for forming a TFT (Thin Film Transistor) using polysilicon as a material on a glass substrate has been advanced, and it is also possible to use this technique to form a pixel array portion and a driving circuit on the same substrate. Has become fully possible.
[0004]
While it is necessary to supply analog pixel voltages to the signal lines in the pixel array, the drive circuit is composed of digital components such as gate circuits and flip-flops, and performs various signal processing in the state of digital signals. It is carried out. For this reason, it is common to provide a digital-to-analog conversion circuit inside the drive circuit and supply the converted analog signal to the pixel array unit (see Patent Document 1).
[0005]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2000-305535
[Problems to be solved by the invention]
When a digital-to-analog conversion circuit is formed on a glass substrate, as shown in FIG. 5, a resistor array 21 including a plurality of resistor elements connected in series is provided, and a plurality of reference signals output from between stages of the resistor array 21 are provided. A reference voltage corresponding to the digital signal is selected from the voltages.
[0007]
In general, a liquid crystal display device is driven by polarity inversion in order to prevent burn-in of liquid crystal. Therefore, the power supply voltage applied to both ends of the resistor array 21 is periodically switched.
[0008]
A capacitance element (not shown in FIG. 5) is provided inside the digital-to-analog conversion circuit. Each time the polarity is inverted, the capacitance element is charged and discharged. For this reason, it is desirable that the output impedance of the resistor array 21 be as small as possible.
[0009]
In order to reduce the output impedance of the resistance array 21, it is effective to reduce the resistance value of each resistance element constituting the resistance array 21, but in this case, the current flowing through the resistance array 21 increases, There is a problem that power consumption increases.
[0010]
The present invention has been made in view of such a point, and an object of the present invention is to provide a digital-analog conversion circuit and a display device that can operate at high speed and reduce power consumption.
[0011]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention outputs a voltage between a first voltage and a second voltage, the voltage corresponding to a digital signal of n bits (n is an integer of 2 or more). A digital-to-analog conversion circuit having a resistance array including three or more resistance elements connected in series, the first voltage being applied to one end, and the second voltage being applied to the other end; A reference voltage output circuit for outputting a reference voltage from a connection path of each resistance element in the array, a reference voltage selection circuit for selecting a reference voltage according to the digital signal, and one end of the first and second voltages A first capacitance element to which a third voltage is applied between the first and second voltages; a second capacitance element to which a fourth voltage between the first and second voltages is applied to one end; and the resistance array Of the first and second resistance elements connected adjacently A first switching means for controlling whether to connect one end of the first capacitance element or one end of the second capacitance element to a path, and a first switching means which is adjacently connected in the resistance array. A second switching means for controlling whether to connect one end of the second capacitance element or one end of the first capacitance element to a connection path between the third and fourth resistance elements; Have.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a digital-analog conversion circuit and a display device according to the present invention will be specifically described with reference to the drawings.
[0013]
FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the liquid crystal display device according to the present invention. The liquid crystal display device of FIG. 1 includes a pixel array unit 1 in which signal lines and scanning lines are arranged in a row, a signal line driving circuit 2 that drives signal lines, and a scanning line driving circuit 3 that drives scanning lines. I have. These circuits are formed on the same insulating substrate (hereinafter, pixel array substrate). Each circuit on the pixel array substrate is formed by, for example, a polysilicon process, and a pixel TFT (Thin Film Transistor) is formed near each intersection of a signal line and a scanning line in the pixel array unit 1.
[0014]
The signal line driving circuit 2 includes a shift register 4 for generating a shift pulse obtained by sequentially shifting a start pulse, a data bus 5 for transmitting digital pixel data supplied from a host computer (not shown), and a synchronization with the shift pulse. A sampling latch 6 for sequentially latching digital pixel data, a load latch 7 for collectively latching latch outputs of the sampling latch 6 at the same timing, and a reference voltage output circuit 8 for outputting a plurality of reference voltages having different voltage levels. A reference voltage selecting circuit 9 for selecting a desired reference voltage based on the upper bit string of the digital pixel data; and a D / A converter (DAC) for D / A converting the digital pixel data based on the selected reference voltage. ) 10 and an amplifier (AMP) 11 for amplifying the D / A converted analog pixel signal Has a signal line selection circuit 12 for switching whether to supply the output of the amplifier 11 to which the signal lines, and a timing control circuit 13 for timing control of the signal line drive circuit 2 and the scanning line driving circuit 3.
[0015]
FIG. 2 is a circuit diagram showing a detailed configuration of the reference voltage output circuit 8. More specifically, the right side of the dotted line in FIG. 2 shows the configuration of the reference voltage output circuit 8 formed on the pixel array substrate, and the left side of the dotted line is provided on a drive circuit substrate separate from the pixel array substrate. .
[0016]
As shown in the figure, the reference voltage output circuit 8 includes a resistor array 21 including a plurality of resistance elements R1, R2, R3, and R4 connected in series between the first and second power supply terminals REF1 and REF2. A capacitor C1 set to a voltage of 3.75 V, a capacitor C2 whose one end is always set to a voltage of 1.25 V, and a capacitor C1 connected between one end of the capacitor C1 and a connection node N1 between the resistance elements R1 and R2. An analog switch SW1, an analog switch SW2 connected between one end of the capacitor C2 and a connection node N1 between the resistance elements R1 and R2, and an analog switch SW2 connected between one end of the capacitor C1 and a connection node N2 between the resistance elements R3 and R4. And an analog switch SW4 connected between one end of the capacitor C2 and a connection node N2 of the resistance elements R3 and R4. To. A voltage XVPRC of 2.5 V is always applied to a connection node N5 between the resistance elements R2 and R3.
[0017]
One of the first power supply terminal REF1 connected to one end of the resistance array 21 and the second power supply terminal REF2 connected to the other end is 5V, and the other is 0V, and the voltage level is adjusted in accordance with the polarity inversion cycle of the liquid crystal. Switch alternately. For example, when the first power supply terminal REF1 is 0V, the second power supply terminal REF2 is 5V, and when the first power supply terminal REF1 is 5V, the second power supply terminal REF2 is 0V.
[0018]
Of the analog switches SW1 to SW4, the analog switches SW1 and SW4 are simultaneously turned on and off in the same direction, and the analog switches SW2 and SW3 are simultaneously turned on and off in the same direction. When the analog switches SW1 and SW4 are on, the analog switches SW2 and SW3 are off, and when the analog switches SW1 and SW4 are off, the analog switches SW2 and SW3 are on.
[0019]
The on / off control of the analog switches SW1 to SW4 is also performed in synchronization with the polarity inversion drive timing of the liquid crystal.
[0020]
FIG. 3 is a diagram showing the relationship between the voltages of the first and second power supply terminals REF1 and REF2, the states of the analog switches SW1 to SW4, and the voltages of the nodes N1, N2, N3 and N4 in FIG.
[0021]
Hereinafter, the operation of the liquid crystal display device of the present embodiment will be described with reference to FIG. First, from time t1 to t2, the analog switches SW1 and SW4 are turned on, and the analog switches SW2 and SW3 are turned off. Thus, one end N3 of the capacitor C1 has the same voltage as the voltage N1 on the connection path between the resistance elements R1 and R2, and one end N4 of the capacitor C2 has the same voltage as the voltage N2 on the connection path between the resistance elements R3 and R4.
[0022]
Therefore, assuming that the resistance values of the resistance elements R1 to R4 are all equal, one end N3 of the capacitor becomes 3.75V and one end N4 of the capacitor becomes 1.25V.
[0023]
Thereafter, at times t2 to t3, the analog switches SW1 and SW4 are turned off and the analog switches SW2 and SW3 are turned on. However, since the voltage applied to both ends of the resistor array 21 is inverted, one end N3 of the capacitors C1 and C2 is inverted. , N4 do not change.
[0024]
Thereafter, between times t3 and t4, the analog switches SW1 and SW4 are turned on and the analog switches SW2 and SW3 are turned off. In this case as well, none of the voltages at the one ends N3 and N4 of the capacitors C1 and C2 change.
[0025]
Similarly, between times t4 and t5, none of the voltages at the one ends N3 and N4 of the capacitors C1 and C2 change.
[0026]
As described above, even if the on / off states of the analog switches SW1 to SW4 change, the voltages of the one ends N3 and N4 of the capacitors C1 and C2 do not change. Therefore, even if the voltage at both ends of the resistor array 21 is inverted at the time of the polarity inversion driving, the voltages of the connection nodes N1 and N2 in the resistor array 21 can be quickly set to a desired voltage.
[0027]
A capacitance element (not shown) is provided inside the D / A converter 10, and the capacitance element is charged and discharged by the reference voltage output circuit 8. Each time the polarity is inverted, the reference voltage output circuit 8 has to charge and discharge the capacitance element of the D / A converter 10, and the output impedance of the reference voltage output circuit 8 is set so that a sufficient current can flow at the time of the polarity inversion. Is preferably as low as possible.
[0028]
In the reference voltage output circuit 8 of FIG. 2, the connection nodes N1 and N2 of the resistor array 21 in the reference voltage output circuit 8 can be quickly set to a desired voltage by the capacitors C1 and C2. Therefore, the output impedance of the reference voltage output circuit 8 can be set low.
[0029]
Conventionally, in order to reduce the output impedance of the reference voltage output circuit 8, the resistance value of each resistance element of the resistance array 21 has been reduced. However, when the resistance value is reduced, power consumption increases accordingly. On the other hand, in the present embodiment, the output impedance of the reference voltage output circuit 8 can be reduced without reducing the resistance value of the resistance element, and power consumption can be reduced.
[0030]
In FIG. 2, although the resistance array 21 is formed by four resistance elements connected in series, the number of resistance elements forming the resistance array 21 is not particularly limited. For example, when the number of resistance elements is increased as compared with FIG. 2, it is necessary to increase the number of the above-described analog switches and capacitors for reducing output impedance.
[0031]
FIG. 4 is a diagram comparing the underwriting voltage difference between the present embodiment and the conventional example with respect to the underwriting voltage difference between the reference voltage output circuit 8 and the capacitance element inside the D / A converter 10. This shows a conventional example. As shown in the figure, regardless of the reference voltage, the underwriting voltage difference of the present embodiment is smaller than that of the conventional example, and it can be seen that the output impedance is smaller than that of the conventional example.
[0032]
As described above, in the present embodiment, the connection node between the resistance elements of the resistance array 21 constituting the reference voltage output circuit 8 is quickly set to a desired voltage by the capacitor via the analog switch when the polarity is inverted. Therefore, the output impedance of the reference voltage output circuit 8 can be reduced without reducing the resistance value of the resistance array 21, and the power consumption of the reference voltage output circuit 8 can be reduced.
[0033]
In the above-described embodiment, the liquid crystal display device is described as an example of the display device of the present invention. However, the present invention is also applied to a flat display device other than the liquid crystal display device (for example, an EL display device or a plasma display device). It is possible.
[0034]
【The invention's effect】
As described above in detail, according to the present invention, the voltage of the connection path between the first and second resistance elements and the connection path of the third and fourth resistance elements in the resistance array is set to a predetermined voltage. Therefore, the output impedance of the reference voltage output circuit can be reduced without reducing the resistance value of each resistance element constituting the resistance array. Therefore, power consumption can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a liquid crystal display device according to the present invention.
FIG. 2 is a circuit diagram showing a detailed configuration of a reference voltage output circuit.
FIG. 3 is a diagram showing a relationship between voltages at first and second power supply terminals, states of an analog switch, and voltages at respective nodes in FIG. 2;
FIG. 4 is a diagram comparing a difference between the present embodiment and a conventional example in a writing undervoltage difference in a capacitance element inside a D / A converter by a reference voltage output circuit.
FIG. 5 is a diagram showing a schematic configuration of a conventional digital-to-analog conversion circuit formed on a glass substrate.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 pixel array unit 2 signal line drive circuit 3 scan line drive circuit 4 shift register 5 data bus 6 sampling latch 7 load latch 8 reference voltage output circuit 9 reference voltage line home circuit 10 D / A converter 11 amplifier 12 signal line selection circuit 13 Timing control circuit

Claims (7)

In a digital-to-analog conversion circuit that outputs a voltage between a first voltage and a second voltage, the voltage corresponding to a digital signal of n (n is an integer of 2 or more) bits,
A resistor array comprising three or more resistor elements connected in series to one end to which the first voltage is applied and the other end to which the second voltage is applied; A reference voltage output circuit that outputs a reference voltage from each connection path,
A reference voltage selection circuit that selects a reference voltage according to the digital signal;
A first capacitive element to which a third voltage between the first and second voltages is applied at one end;
At one end, a second capacitive element to which a fourth voltage between the first and second voltages is applied;
Switching between connecting one end of the first capacitive element or connecting one end of the second capacitive element to a connection path between the first and second resistive elements that are connected adjacently in the resistance array. First switching means for controlling;
Switching between connecting one end of the second capacitive element or connecting one end of the first capacitive element to the connection path between the third and fourth resistive elements connected adjacently in the resistance array A digital-to-analog conversion circuit, comprising: second switching means for controlling. When connecting one end of the first capacitance element to the connection path of the first and second resistance elements, the first and second switching means may connect the one end of the first capacitance element to the connection path of the third and fourth resistance elements. Connecting one end of the second capacitive element,
The first and second switching means are connected to the connection path of the third and fourth resistance elements when connecting one end of the second capacitance element to the connection path of the first and second resistance elements. 2. The digital-to-analog conversion circuit according to claim 1, wherein one end of the first capacitance element is connected. Applying the first voltage to one end of the resistor array and applying the second voltage to the other end, or applying the second voltage to the one end and applying the first voltage to the other end. A third switching means for switching control whether to apply the voltage of
The digital-to-analog conversion circuit according to claim 1, wherein the first, second, and third switching units perform switching in conjunction with each other. The first switching means,
A first switch connected between one end of the first capacitance element and a connection path between the first and second resistance elements;
A second switch connected between one end of the second capacitance element and a connection path between the first and second resistance elements;
The second switching means,
A third switch connected between one end of the first capacitance element and a connection path between the third and fourth resistance elements;
3. The device according to claim 1, further comprising a fourth switch connected between one end of the second capacitor and a connection path between the third and fourth resistors. Digital-to-analog conversion circuit. Signal lines and scanning lines arranged vertically and horizontally on an insulating substrate,
A display element formed near each intersection of the signal line and the scanning line;
A scanning line driving circuit that drives the scanning line;
A signal line driving circuit for driving the signal line,
The signal line drive circuit,
a latch circuit for latching n (n is an integer of 2 or more) bits of digital pixel data;
A resistor array comprising three or more resistor elements connected in series to one end to which the first voltage is applied and the other end to which the second voltage is applied; A reference voltage output circuit that outputs a reference voltage from each connection path,
A reference voltage selection circuit that selects a reference voltage according to the digital pixel data;
A first capacitive element to which a third voltage between the first and second voltages is applied at one end;
At one end, a second capacitive element to which a fourth voltage between the first and second voltages is applied;
Switching between connecting one end of the first capacitive element or connecting one end of the second capacitive element to a connection path between the first and second resistive elements that are connected adjacently in the resistance array. First switching means for controlling;
Switching between connecting one end of the second capacitive element or connecting one end of the first capacitive element to the connection path between the third and fourth resistive elements connected adjacently in the resistance array A display device comprising: a second switching unit for controlling. When connecting one end of the first capacitance element to the connection path of the first and second resistance elements, the first and second switching means may connect the one end of the first capacitance element to the connection path of the third and fourth resistance elements. Connecting one end of the second capacitive element,
The first and second switching means are connected to the connection path of the third and fourth resistance elements when connecting one end of the second capacitance element to the connection path of the first and second resistance elements. The liquid crystal display device according to claim 5, wherein one end of the first capacitor is connected. Applying the first voltage to one end of the resistor array and applying the second voltage to the other end, or applying the second voltage to the one end and applying the first voltage to the other end. A third switching means for switching control whether to apply the voltage of
7. The display device according to claim 5, wherein the first, second, and third switching units perform switching in synchronization with each other in accordance with timing of polarity inversion driving of the display element. 8.

Images