JP2004260066A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

Info

Publication number
JP2004260066A
JP2004260066A JP2003050977A JP2003050977A JP2004260066A JP 2004260066 A JP2004260066 A JP 2004260066A JP 2003050977 A JP2003050977 A JP 2003050977A JP 2003050977 A JP2003050977 A JP 2003050977A JP 2004260066 A JP2004260066 A JP 2004260066A
Authority
JP
Japan
Prior art keywords
semiconductor device
resin
power element
insulator
semiconductor power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2003050977A
Other languages
Japanese (ja)
Other versions
JP4319426B2 (en
Inventor
Yoshinori Oda
佳典 小田
Noriyasu Terasawa
徳保 寺沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Device Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Device Technology Co Ltd filed Critical Fuji Electric Device Technology Co Ltd
Priority to JP2003050977A priority Critical patent/JP4319426B2/en
Publication of JP2004260066A publication Critical patent/JP2004260066A/en
Application granted granted Critical
Publication of JP4319426B2 publication Critical patent/JP4319426B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of a prior art that in a semiconductor device having a structure permitting various electronic parts to be mounted on a metal frame, and coupled and wired with each other, characteristics thereof can not be measured till a tie bar is cut after the outside thereof is covered with resin and inner leads are fixed, and hence a semiconductor device having accurate electric output characteristics can not be obtained. <P>SOLUTION: In the semiconductor device having the structure permitting semiconductor power elements, electronic parts, and control ICs or the like to be mounted, and coupled and wired with a wire, after a part of the metal frame is fixed using an insulator before the outside thereof is covered with resin, the tie bar is cut to bring about an electrically isolated state thereof. In this state, the electronic parts or the control ICs are subjected to trimming in order to make optimum the electric characteristics of the semiconductor device while measuring the output characteristics of the semiconductor device, and thereafter the outside thereof is covered with resin. Hereby, the semiconductor device having the electric output characteristics with less variations is obtained. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体パワー素子を搭載した半導体装置の電気的出力特性の最適化を可能とした、半導体装置及び半導体装置の製造方法に関するものである。
【０００２】
【従来の技術】
図７は、半導体パワー素子を搭載した半導体装置の従来例を示す図である。図７では、半導体装置が複数連結した状態で組み立てが完了し、樹脂で封止された後、隣接する外部への取り出し端子間を連結するタイバー４０、４１が切断される前の構造を示す。図７に示すように半導体装置１は外側が樹脂１０で封止され、内部の半導体パワー素子３１、３２、制御用ＩＣ３３などを内蔵し、各電極及び外部への取り出し端子へアルミまたは金などのワイヤ５１、５２、５３、５４、５５、５６で配線、結合され、樹脂で封止されたインナーリード２５ａ、２６ａ、２７ａ、２８ａ、２９ａを経由してアウターリード２５ｂ、２６ｂ、２７ｂ、２８ｂ、２９ｂに接続されている。金属フレーム２０は、ダイパット２１、２２、２３、隣接する外部への取り出し端子間を結合するタイバー４０、４１、前記インナーリード、アウターリードから構成されている。金属フレームのダイパット２１、２２、２３には、半導体パワー素子及び制御用ＩＣなどが搭載され、ワイヤで配線されている。
【０００３】
この構造であると、タイバーによって接続され電気的に同電位になっているため、半導体パワー素子、制御用ＩＣなどが搭載され、ワイヤで結合、配線されても、外側が樹脂で封止されインナーリードが固定された後、タイバーを切断するまで電気的出力特性を測定することができず、精度良い電気的出力特性を持った半導体装置が得られなかった。従って半導体パワー素子の電流検出値を制御用ＩＣに入力して、過電流保護を行う際には，半導体パワー素子の電流検出端子から出力される検出値には、個々の半導体パワー素子によってバラツキがあるため、その半導体パワー素子が流し得る最大定格電流に対して、制御用ＩＣにおける最大電流（過電流と判断する設定値）には、マージンを取らざるを得ない。
【０００４】
従来この問題を解決する方法としては、半導体装置を組み立てる前にトリミングを行い、抵抗精度の高い抵抗を使用する方法や（例えば特許文献１）外側を樹脂で封止した後、パッケージの外側のアウターリードに調整可能な抵抗を設け、動作させながらトリミングを行い、半導体パワー素子に対し、最適化する方法がある（例えば特許文献１，２，３）。しかし、より確実に精度を高めた電気的出力特性を得ることや半導体装置の外側に電子部品を実装する必要のない半導体装置が求められている。
【０００５】
【特許文献１】
特開平４−３３４７６５号公報
【特許文献２】
特開平１０−１６３４１２号公報
【特許文献３】
特許第２６１２１０６号公報
【０００６】
【発明が解決しようとする課題】
金属フレームのダイパットには、半導体パワー素子、制御用ＩＣなどが搭載され、ワイヤで結合、配線されているが、金属フレームはタイバーによって接続され電気的に同電位になっているため、外側が樹脂で封止されインナーリードが固定された後、タイバーを切断するまで電気的出力特性の測定が出来ない。
本発明の目的は、外側が樹脂で封止される前に、電気的出力特性の測定を行えるような構造とする加工工程を追加し、半導体パワー素子、制御用ＩＣとの組み合わせにより、電気的出力特性の測定を行いながら制御用ＩＣをトリミングなどによって調整することによって電気的出力特性を最適化した半導体装置を提供することにある。
【０００７】
【課題を解決するための手段】
そこで、上記課題を解決するために、請求項１に係る発明において、半導体パワー素子、該半導体パワー素子の電気的出力特性を最適化すべく調整された制御用ＩＣとを、複数の外部引き出し用端子を有する金属フレーム上に搭載し、外側を樹脂で封止した半導体装置において、前記制御用ＩＣは、金属フレーム上に搭載された状態で、半導体パワー素子の電気的出力特性を最適化すべくトリミングされたものであることを特徴とする。
請求項２に係る発明は、半導体パワー素子、該半導体パワー素子の制御用ＩＣとを、金属フレームのダイパット部分に搭載し、ワイヤボンディングで配線を行い、金属フレームのアウターリード、インナーリードまたはダイパットの一部を絶縁物で固定し、アウターリード部分を連結固定しているタイバーを切断し、電気的に独立した状態にして、半導体装置の出力を測定しながら半導体パワー素子の電気的特性を最適化すべく、制御用ＩＣのトリミングを行い、外側を樹脂で封止することを特徴とする半導体装置の製造方法である。
【０００８】
請求項３に係る発明は、金属フレームのアウターリード、インナーリードまたはダイパット一部をあらかじめ絶縁物で固定した後、半導体パワー素子及び制御用ＩＣとを金属フレームに搭載し、ワイヤボンディングで配線を行い、アウターリード部分を連結固定しているタイバーを切断し、電気的に独立した状態にして、半導体装置の出力を測定しながら半導体パワー素子の電気的特性を最適化すべく、制御用ＩＣのトリミングを行い、外側を樹脂で封止することを特徴とする半導体装置の製造方法である。
請求項４に係る発明は、請求項２、３に係る発明において、金属フレームの少なくともアウターリードの一部を絶縁物で固定したことを特徴とする半導体装置の製造方法である。
【０００９】
請求項５に係る発明は、請求項２、３に係る発明において、金属フレームの少なくともインナーリードの一部またはダイパットの一部を絶縁物で固定したことを特徴とする半導体装置の製造方法である。
請求項６に係る発明は、請求項４に係る発明において、樹脂封止の後、アウターリードを固定した絶縁物は、アウターリードの切断によって除去されることを特徴とする半導体装置製造方法である。
請求項７に係る発明は、請求項５に係る発明において、インナーリードの一部またはダイパットの一部を固定した絶縁物を、外側の封止樹脂で覆うことを特徴とする半導体装置の製造方法である。
【００１０】
【発明の実施の形態】
以下本発明の実施の形態について図面を用いて詳細に説明する。図１、２，３に本発明の第１の実施例を示す。図１は半導体装置全体の構成を示す図である。図１に示すように半導体装置１は外側が樹脂１０で封止され、内部の半導体パワー素子３１、３２、制御用ＩＣ３３、を内蔵している。その他に、他の電子部品を内蔵する場合もある。このうちで制御用ＩＣ３３またはその他電子部品のどちらかまたは両方が電気的出力特性を最適化すべく調整可能な抵抗等を内蔵した電子部品または制御用ＩＣである。この様な調整用の抵抗が制御用ＩＣ３３内部に集積できれば、その他電子部品はなくてもよいため、調整可能な抵抗等を内蔵した制御用ＩＣの場合についての実施例を示す。半導体パワー素子３１、３２、制御用ＩＣ３３の電極及びインナーリード２５ａ、２６ａ、２７ａ、２８ａ、２９ａとの間は、アルミまたは金などのワイヤ５１、５２、５３、５４、５５、５６でボンディングされ接続される。インナーリード部は樹脂で封止され、アウターリード２５ｂ、２６ｂ、２７ｂ、２８ｂ、２９ｂは外部への取り出し端子となる。半導体装置取り付け用穴１１はない場合もある。
【００１１】
図２は半導体装置が樹脂で覆われる前の状態を示す図である。金属フレーム２０は、ダイパット２１、２２、２３、隣接する外部への取り出し端子間を結合するタイバー４０、４１、図１に示すインナーリード、アウターリードから構成されている。金属フレームのダイパット２１、２２、２３には、それぞれ半導体パワー素子３１、３２及び制御用ＩＣ３３などが搭載される。電極及びインナーリードとの間はワイヤボンディングによって配線される。なお金属フレームは半導体装置の種類によってダイパット及びインナーリード、アウターリードの形状及び数量は変化する。
【００１２】
この構造では、金属フレームはタイバーによって接続され電気的に同電位になっているため、例えば接地しておけば半導体パワー素子及び制御用ＩＣなどを搭載し、ワイヤで結合、配線する工程において、静電気等で各素子が破壊されるのを防ぐことができる。
つづいて図２に示すように、絶縁物６０を用いてアウターリードの一部を固定する。その後、図２に示すＸ１−Ｘ１線でタイバー４１を切断し、タイバー４０の連結部をカットすると、図３に示すようなアウターリードが絶縁物６０で連結され、各端子は電気的に独立した状態の構造のものが得られる。この状態で端子２５、２６、２７、２８、２９を用いて、半導体装置の出力特性の測定を行いながら電気的特性を最適化すべく、制御用ＩＣのトリミングを行う。制御用ＩＣのトリミングは、その内部に内蔵する抵抗をレザーでトリミングする方法が一般的に行われている。ここで、半導体パワー素子３１の出力特性の最適化は、例えば半導体パワー素子の補助エミッタからの電流検出値を制御用ＩＣに入力する際の検出値のバラツキの調整ができる。トリミング終了後インナーリード、ダイパットなど所望の領域を樹脂にて封止する。樹脂で封止した後、絶縁物６０にて固定した部分を含めて、図３のＸ２−Ｘ２にて切断をすると、半導体パワー素子３１と、この素子の出力特性を最適化するために調整された制御用ＩＣ３３が同一のパッケージ内に樹脂で封止される。
【００１３】
図４に本発明の第２の実施例を示す。前記と同様に半導体パワー素子３１、半導体パワー素子３２及び制御用ＩＣ３３などが搭載され、ワイヤで結合、配線された後、絶縁物６１を用いてインナーリードの一部を固定する。その後、前記タイバー４０、４１をカットすると図４に示す各端子が電気的に独立した状態の構造の物が得られる。以下前記と同様、半導体装置の出力特性の測定を行いながら、制御用ＩＣのトリミングを行った後、外側を樹脂で封止する。このとき、絶縁物６１を覆うように樹脂封止を行えば、絶縁物６１を全体の封止樹脂内に取り込み、樹脂の硬化後、絶縁物６１の連結部分を切除すると、前記と同様半導体パワー素子３１、３２と、この素子の出力特性を最適化するために調整された制御用ＩＣ３３が同一のパッケージ内に樹脂で封止される。
【００１４】
図５に本発明の第３の実施例を示す。前記と同様に半導体パワー素子及び制御用ＩＣなどが搭載され、ワイヤで結合、配線された後、絶縁物６０、６１を用いてそれぞれアウターリード、インナーリードの一部を固定し、その後、タイバー４０、４１をカットすると図５（ａ）に示す各端子が電気的に独立した状態の物が得られる。以下前記と同様、半導体装置の出力特性の測定を行いながら、制御用ＩＣのトリミングを行った後、樹脂で封止する。金属フレームのインナーリード、アウターリードを絶縁物６０、６１で固定する際に、絶縁物６０は、図示のように連続した形状に、絶縁物６１は各半導体装置毎に区切って固定しておくとよい。このようにすれば絶縁物６１の端部を装置全体の封止樹脂の外部の露出させることなく、完全に封止することができる。この方法では６１の切除が不要となるためより効果的な工程となる。
【００１５】
あるいは、樹脂封止の際に、図５（ａ）に示す絶縁物６０は連続した状態で、絶縁物６１をＹ１−Ｙ１、Ｙ２−Ｙ２、Ｙ３−Ｙ３、Ｙ４−Ｙ４にて切断、連結部を切除し、各半導体装置のインナーリードの一部を固定した絶縁物６１ａに分離した後、樹脂で封止すると図５（ｂ）に示すように、絶縁物６１の端部を装置全体の封止樹脂の外部の露出させることなく、完全に封止することができる。絶縁物の切除はタイバー４０、４１をカットする際に、同時に絶縁物６１の連結部を切除すると効率的な工程となる。また上述のように、インナーリード部の絶縁物６１を覆うように封止した後、絶縁物６０で固定した部分のアウターリードと、絶縁物６１の連結部を切除してもよい。
【００１６】
図６に本発明の第４の実施例を示す。前記と同様半導体パワー素子及び制御用ＩＣなどが搭載され、ワイヤで結合、配線された後、絶縁物６２を用いてダイパットの一部を制御用ＩＣ３３の被トリミング部を露出させて固定する。図６に示す例ではダイパットの裏面の一部を固定している。その後、タイバー４０、４１をカットすると、図６（ａ）に示す各端子が電気的に独立した状態の物が得られる。その後、上述のように、ダイパット部の絶縁物６２を覆うように封止した後、絶縁物６２で固定した部分のダイパット部を切除する。
また、前記と同様、図５（ａ）に示す絶縁物６０でアウターリードを固定し、連続した状態にしておき、半導体装置の出力特性の測定を行いながら、制御用ＩＣのトリミングを行った後、外側を樹脂で覆う。図６（ｂ）にトリミングを行った物を樹脂で覆った構造を示す。金属フレームのアウターリード、ダイパット部を絶縁物６０、６２で固定する際に、絶縁物６０は、図示のように連続した形状に、絶縁物６２は各半導体装置毎に区切って固定しておくとよい。このようにすれば絶縁物６２の端部を装置全体の封止樹脂の外部の露出させることなく、完全に封止することができる。この方法では６２の切除が不要となるためより効果的な工程となる。
【００１７】
あるいは、図６（ａ）に示す絶縁物６２をＹ５−Ｙ５、Ｙ６−Ｙ６、Ｙ７−Ｙ７、Ｙ８−Ｙ８にて切断すると、各半導体装置のダイパットの一部を固定した絶縁物６２ａに分離される。その絶縁物６２ａがついた状態で、外側の樹脂１０にて覆ってしまうと、絶縁物６２の端部を装置全体の封止樹脂の外部の露出させることなく、完全に封止することができる。その後、絶縁物６０で固定した部分のアウターリードを切除する。
以上説明した各実施例において、半導体パワー素子及び制御用ＩＣなどが搭載された後にアウターリード、インナーリードまたはダイパットの固定を行ったが、半導体パワー素子、制御用ＩＣなどが搭載される前にアウターリード、インナーリードまたはダイパットの固定を行ってもよい。
【００１８】
また半導体装置内部に半導体パワー素子、制御用ＩＣなどを個別に内蔵した場合について記載したが、半導体パワー素子、制御用ＩＣ、その他電子部品を一体化したワンチップ形半導体でダイパットが一個で複数のアウターリードを持つ半導体装置の場合でも、半導体装置の出力特性の測定を行いながら、制御用ＩＣのトリミングを行った後、外側を樹脂で覆う場合はいずれの実施例も適用することができる。
さらに金属フレームの一部を絶縁物で固定する場合、アウターリード、インナーリードまたはダイパットそれぞれ一箇所でもよく、２箇所以上の固定してもよい。２箇所以上の固定の場合どの組み合わせでも可能である。
【００１９】
【発明の効果】
本発明では、外側が樹脂で覆われ、半導体パワー素子、制御用ＩＣ等を、複数の外部引き出し用端子を有する金属フレーム上に搭載した半導体装置において、半導体パワー素子とこの半導体パワー素子の特性を最大にすべくセンス特性を調整した制御用ＩＣを同一パッケージ内に封止するので、特性調整のためにパッケージの外側に電子部品を後付けする必要がない。また半導体パワー素子についてそれぞれ制御用ＩＣが調整されるので、半導体パワー素子の特性を余すことなく活用することができる。すなわち過剰な特性の半導体パワー素子を用いる必要がなく、パワー半導体素子の小型化ができ低コスト製品の提供が可能となる。さらに半導体装置の出力特性に対してはより製品のバラツキを小さくできるため、良品率アップが達成できる。
【図面の簡単な説明】
【図１】本発明の第１の実施例を示し、半導体装置全体の図である。
【図２】本発明の第１の実施例を示し、半導体装置が樹脂で覆われる前の状態を示す図である。
【図３】本発明の第１の実施例を示し、アウターリードが絶縁物で連結され、各端子は電気的に独立した状態の図である。
【図４】本発明の第２の実施例を示し、インナーリードが絶縁物で連結され、各端子は電気的に独立した状態の図である。
【図５】本発明の第３の実施例を示す。（ａ）はアウターリード、インナーリードが絶縁物で連結され、各端子は電気的に独立した状態の図である。（ｂ）はインナーリードを連結した部分を切除した後、樹脂で封止した時の半導体装置全体の図である。
【図６】本発明の第４の実施例を示す。（ａ）はダイパットが絶縁物で連結され、各端子は電気的に独立した状態の図である。（ｂ）はダイパットを連結した部分を切除した後、樹脂で封止した時の半導体装置全体の図である。
【図７】半導体パワー素子を搭載した半導体装置の製造工程の従来例を示す図である。
【符号の説明】
１ 半導体装置
１０ 樹脂
１１ 半導体装置取り付け用穴
２０ 金属フレーム
２１、２２、２３ ダイパット
２５ａ、２６ａ、２７ａ、２８ａ、２９ａ インナーリード
２５ｂ、２５ｂ、２５ｂ、２５ｂ、２５ｂ アウターリード
３１、３２ 半導体パワー素子
３３ 制御用ＩＣ
４０、４１ タイバー
５１、５２、５３、５４、５５、５６ ワイヤ
６０、６１、６２ 絶縁物
６１ａ インナーリードの一部を固定した絶縁物
６２ａ ダイパットの一部を固定した絶縁物[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, which enable optimization of electrical output characteristics of a semiconductor device having a semiconductor power element mounted thereon.
[0002]
[Prior art]
FIG. 7 is a diagram showing a conventional example of a semiconductor device on which a semiconductor power element is mounted. FIG. 7 shows a structure in which assembly is completed in a state where a plurality of semiconductor devices are connected, sealed with a resin, and before tie bars 40 and 41 connecting adjacent takeout terminals to the outside are cut. As shown in FIG. 7, the outside of the semiconductor device 1 is sealed with a resin 10 and includes internal semiconductor power elements 31 and 32, a control IC 33, and the like. Outer leads 25b, 26b, 27b, 28b, 29b are wired and connected by wires 51, 52, 53, 54, 55, 56, and are sealed with resin via inner leads 25a, 26a, 27a, 28a, 29a. It is connected to the. The metal frame 20 is composed of die pads 21, 22, and 23, tie bars 40 and 41 for connecting between adjacent take-out terminals to the outside, the inner leads, and the outer leads. Semiconductor power elements, control ICs, and the like are mounted on the die pads 21, 22, and 23 of the metal frame, and are wired with wires.
[0003]
With this structure, since they are connected by tie bars and are electrically at the same potential, semiconductor power elements, control ICs, etc. are mounted, and even if they are connected and wired with wires, the outside is sealed with resin and the inner After the leads were fixed, the electrical output characteristics could not be measured until the tie bars were cut, and a semiconductor device having accurate electrical output characteristics could not be obtained. Therefore, when the current detection value of the semiconductor power element is input to the control IC to perform overcurrent protection, the detection value output from the current detection terminal of the semiconductor power element varies depending on each semiconductor power element. For this reason, a margin must be provided for the maximum current (set value determined as overcurrent) in the control IC with respect to the maximum rated current that the semiconductor power element can flow.
[0004]
Conventionally, as a method for solving this problem, trimming is performed before assembling a semiconductor device, a method using a resistor having high resistance accuracy (for example, Patent Document 1), after sealing the outside with resin, and then using an outer package outside. There is a method of optimizing a semiconductor power element by providing an adjustable resistor on a lead and performing trimming while operating (for example, Patent Documents 1, 2, and 3). However, there is a need for a semiconductor device that more reliably obtains an improved electrical output characteristic and that does not require mounting electronic components outside the semiconductor device.
[0005]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 4-334765 [Patent Document 2]
JP-A-10-163412 [Patent Document 3]
Japanese Patent No. 2612106
[Problems to be solved by the invention]
On the die pad of the metal frame, semiconductor power elements, control ICs, etc. are mounted and connected and wired with wires, but since the metal frame is connected by tie bars and has the same electric potential, the outside is resin. After the inner lead is fixed and sealed, the electrical output characteristics cannot be measured until the tie bar is cut.
An object of the present invention is to add a processing step having a structure capable of measuring an electric output characteristic before the outside is sealed with a resin, and to provide an electric power by combining with a semiconductor power element and a control IC. An object of the present invention is to provide a semiconductor device in which electrical output characteristics are optimized by adjusting a control IC by trimming or the like while measuring output characteristics.
[0007]
[Means for Solving the Problems]
Therefore, in order to solve the above problem, in the invention according to claim 1, a semiconductor power element and a control IC adjusted to optimize the electrical output characteristics of the semiconductor power element are connected to a plurality of external lead terminals. In a semiconductor device mounted on a metal frame having an outer surface and sealed with a resin, the control IC is trimmed to optimize the electrical output characteristics of the semiconductor power element while mounted on the metal frame. It is characterized in that it is.
According to a second aspect of the present invention, a semiconductor power element and a control IC for the semiconductor power element are mounted on a die pad portion of a metal frame, wiring is performed by wire bonding, and an outer lead, an inner lead or a die pad of the metal frame is mounted. A part is fixed with an insulator, and the tie bar that connects and fixes the outer lead part is cut off to make it electrically independent, and the electrical characteristics of the semiconductor power element are optimized while measuring the output of the semiconductor device. Therefore, a method of manufacturing a semiconductor device, characterized by trimming a control IC and sealing the outside with a resin.
[0008]
The invention according to claim 3 is that after fixing the outer lead, the inner lead, or a part of the die pad of the metal frame in advance with an insulator, the semiconductor power element and the control IC are mounted on the metal frame and wiring is performed by wire bonding. Then, trim the control IC to optimize the electrical characteristics of the semiconductor power element while measuring the output of the semiconductor device by cutting the tie bar that connects and secures the outer lead part and making it electrically independent. And sealing the outside with a resin.
The invention according to claim 4 is the method according to claims 2 and 3, wherein at least a part of the outer lead of the metal frame is fixed with an insulator.
[0009]
The invention according to claim 5 is the method according to claims 2 and 3, wherein at least a part of the inner lead or a part of the die pad of the metal frame is fixed with an insulator. .
According to a sixth aspect of the present invention, there is provided the semiconductor device manufacturing method according to the fourth aspect, wherein the insulator to which the outer lead is fixed is removed by cutting the outer lead after resin sealing. .
According to a seventh aspect of the present invention, in the method according to the fifth aspect, a method of manufacturing a semiconductor device, comprising: covering an insulator to which a part of an inner lead or a part of a die pad is fixed with an outer sealing resin. It is.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. 1, 2 and 3 show a first embodiment of the present invention. FIG. 1 is a diagram showing the configuration of the entire semiconductor device. As shown in FIG. 1, the semiconductor device 1 is sealed on the outside with a resin 10 and incorporates internal semiconductor power elements 31 and 32 and a control IC 33. In addition, other electronic components may be incorporated. Either or both of the control IC 33 and the other electronic components are electronic components or control ICs incorporating resistors or the like that can be adjusted to optimize the electrical output characteristics. If such a resistor for adjustment can be integrated inside the control IC 33, other electronic components are not required. Therefore, an embodiment in the case of a control IC having a built-in adjustable resistor and the like will be described. The semiconductor power elements 31, 32, the electrodes of the control IC 33, and the inner leads 25a, 26a, 27a, 28a, 29a are bonded and connected by wires 51, 52, 53, 54, 55, 56 such as aluminum or gold. Is done. The inner lead portion is sealed with resin, and the outer leads 25b, 26b, 27b, 28b, 29b serve as terminals for taking out to the outside. The semiconductor device mounting hole 11 may not be provided.
[0011]
FIG. 2 is a diagram showing a state before the semiconductor device is covered with the resin. The metal frame 20 is composed of die pads 21, 22, and 23, tie bars 40 and 41 for connecting between adjacent take-out terminals to the outside, inner leads and outer leads shown in FIG. Semiconductor power elements 31, 32, a control IC 33, and the like are mounted on the die pads 21, 22, and 23 of the metal frame, respectively. The electrodes and the inner leads are wired by wire bonding. The shape and quantity of the die frame, the inner lead, and the outer lead of the metal frame vary depending on the type of the semiconductor device.
[0012]
In this structure, since the metal frames are connected by tie bars and are at the same electric potential, if they are grounded, for example, a semiconductor power element and a control IC are mounted, and in a process of coupling and wiring with wires, static electricity is generated. For example, each element can be prevented from being destroyed.
Subsequently, as shown in FIG. 2, a part of the outer lead is fixed using an insulator 60. Then, when the tie bar 41 is cut along the line X1-X1 shown in FIG. 2 and the connecting portion of the tie bar 40 is cut, the outer leads as shown in FIG. 3 are connected by the insulator 60, and each terminal is electrically independent. The structure of the state is obtained. In this state, the control IC is trimmed using the terminals 25, 26, 27, 28, and 29 to optimize the electrical characteristics while measuring the output characteristics of the semiconductor device. The trimming of a control IC is generally performed by trimming a resistor built therein with a laser. Here, the output characteristics of the semiconductor power element 31 can be optimized, for example, by adjusting the variation in the detection value when the current detection value from the auxiliary emitter of the semiconductor power element is input to the control IC. After trimming, a desired region such as an inner lead and a die pad is sealed with a resin. After sealing with resin, cutting along the line X2-X2 in FIG. 3 including the portion fixed with the insulator 60 is performed to adjust the semiconductor power element 31 and the output characteristic of the element to optimize the output characteristics. The control IC 33 is sealed with resin in the same package.
[0013]
FIG. 4 shows a second embodiment of the present invention. Similarly to the above, the semiconductor power element 31, the semiconductor power element 32, the control IC 33, etc. are mounted, connected and wired by wires, and a part of the inner lead is fixed using the insulator 61. Thereafter, when the tie bars 40 and 41 are cut, a product having a structure in which each terminal shown in FIG. 4 is electrically independent is obtained. Thereafter, the control IC is trimmed while the output characteristics of the semiconductor device are measured in the same manner as described above, and then the outside is sealed with a resin. At this time, if the resin is sealed so as to cover the insulator 61, the insulator 61 is taken into the entire sealing resin, and after the resin is cured, the connection portion of the insulator 61 is cut off, and the semiconductor power is reduced in the same manner as described above. The elements 31 and 32 and the control IC 33 adjusted to optimize the output characteristics of the elements are sealed with a resin in the same package.
[0014]
FIG. 5 shows a third embodiment of the present invention. As described above, the semiconductor power element and the control IC are mounted and connected and wired by wires. Then, the outer leads and the inner leads are partially fixed using insulators 60 and 61, respectively. , 41 are cut out to obtain a product in which each terminal shown in FIG. 5A is electrically independent. Thereafter, the control IC is trimmed while the output characteristics of the semiconductor device are measured in the same manner as described above, and then the semiconductor device is sealed with a resin. When fixing the inner lead and the outer lead of the metal frame with the insulators 60 and 61, the insulator 60 should be fixed in a continuous shape as shown in the figure, and the insulator 61 should be fixed separately for each semiconductor device. Good. In this way, the end of the insulator 61 can be completely sealed without exposing the end of the sealing resin of the entire device. This method is a more effective process because the excision of 61 is not required.
[0015]
Alternatively, at the time of resin sealing, the insulator 61 shown in FIG. 5A is cut in the Y1-Y1, Y2-Y2, Y3-Y3, and Y4-Y4 while the insulator 60 is continuous, and the connecting portion is formed. Is cut off, a part of the inner lead of each semiconductor device is separated into a fixed insulator 61a, and then sealed with resin. As shown in FIG. 5B, the end of the insulator 61 is sealed with the entire device. It can be completely sealed without exposing the sealing resin outside. The cutting of the insulating material is an efficient process if the connecting portion of the insulating material 61 is cut at the same time when the tie bars 40 and 41 are cut. Further, as described above, after sealing so as to cover the insulator 61 of the inner lead portion, the connection portion between the outer lead and the insulator 61 fixed by the insulator 60 may be cut off.
[0016]
FIG. 6 shows a fourth embodiment of the present invention. As described above, the semiconductor power element, the control IC, and the like are mounted, connected and wired by wires, and then a part of the die pad is fixed using the insulator 62 so that the trimmed portion of the control IC 33 is exposed. In the example shown in FIG. 6, a part of the back surface of the die pad is fixed. Thereafter, when the tie bars 40 and 41 are cut, an object in which each terminal shown in FIG. 6A is electrically independent is obtained. After that, as described above, after sealing to cover the insulator 62 of the die pad portion, the die pad portion of the portion fixed by the insulator 62 is cut off.
Further, similarly to the above, after the outer leads are fixed with the insulator 60 shown in FIG. 5A and kept in a continuous state, and after the output characteristics of the semiconductor device are measured, the control IC is trimmed. Cover the outside with resin. FIG. 6B shows a structure in which the trimmed object is covered with a resin. When fixing the outer lead and the die pad portion of the metal frame with the insulators 60 and 62, the insulator 60 should be fixed in a continuous shape as shown in the figure, and the insulator 62 should be fixed for each semiconductor device. Good. In this way, the end of the insulator 62 can be completely sealed without exposing the end of the sealing resin of the entire device. This method is a more effective process because the excision of 62 is unnecessary.
[0017]
Alternatively, when the insulator 62 shown in FIG. 6A is cut at Y5-Y5, Y6-Y6, Y7-Y7, and Y8-Y8, the insulator 62a is separated into insulators 62a to which a part of a die pad of each semiconductor device is fixed. You. If the insulator 62a is covered and covered with the outer resin 10, the end of the insulator 62 can be completely sealed without exposing the sealing resin of the entire device to the outside. . Thereafter, the outer lead at the portion fixed by the insulator 60 is cut off.
In each of the embodiments described above, the outer lead, the inner lead, or the die pad is fixed after the semiconductor power element and the control IC are mounted. However, the outer power is fixed before the semiconductor power element, the control IC, and the like are mounted. The lead, inner lead or die pad may be fixed.
[0018]
In addition, the case where the semiconductor power element, the control IC, and the like are individually incorporated in the semiconductor device has been described. However, the semiconductor power element, the control IC, and other electronic components are integrated into a one-chip type semiconductor. Even in the case of a semiconductor device having outer leads, any of the embodiments can be applied to the case where the control IC is trimmed while the output characteristics of the semiconductor device are measured, and then the outside is covered with resin.
Further, when a part of the metal frame is fixed with an insulator, the outer lead, the inner lead, and the die pad may be fixed at one place or at two or more places. In the case of fixing at two or more locations, any combination is possible.
[0019]
【The invention's effect】
According to the present invention, in a semiconductor device in which the outside is covered with a resin and a semiconductor power element, a control IC, and the like are mounted on a metal frame having a plurality of external lead terminals, the semiconductor power element and the characteristics of the semiconductor power element are determined. Since the control IC whose sense characteristics have been adjusted to maximize it is sealed in the same package, there is no need to retrofit electronic components outside the package for characteristic adjustment. In addition, since the control IC is adjusted for each semiconductor power element, the characteristics of the semiconductor power element can be fully utilized. That is, it is not necessary to use a semiconductor power element having excessive characteristics, and the power semiconductor element can be reduced in size and a low-cost product can be provided. Furthermore, the variation in products with respect to the output characteristics of the semiconductor device can be reduced, so that the yield rate can be increased.
[Brief description of the drawings]
FIG. 1 shows a first embodiment of the present invention and is a view of an entire semiconductor device.
FIG. 2 is a view showing the first embodiment of the present invention and showing a state before the semiconductor device is covered with a resin.
FIG. 3 is a view showing the first embodiment of the present invention, in which outer leads are connected by an insulator and each terminal is electrically independent.
FIG. 4 is a view showing a second embodiment of the present invention, in which inner leads are connected by an insulator and each terminal is electrically independent.
FIG. 5 shows a third embodiment of the present invention. (A) is a diagram in which an outer lead and an inner lead are connected by an insulator, and each terminal is electrically independent. (B) is a view of the entire semiconductor device when a portion where the inner leads are connected is cut off and then sealed with a resin.
FIG. 6 shows a fourth embodiment of the present invention. (A) is a figure in which a die pad is connected with an insulator and each terminal is electrically independent. (B) is a view of the entire semiconductor device when a portion where the die pads are connected is cut off and then sealed with resin.
FIG. 7 is a diagram showing a conventional example of a manufacturing process of a semiconductor device on which a semiconductor power element is mounted.
[Explanation of symbols]
Reference Signs List 1 semiconductor device 10 resin 11 semiconductor device mounting hole 20 metal frame 21, 22, 23 die pad 25a, 26a, 27a, 28a, 29a inner lead 25b, 25b, 25b, 25b, 25b outer lead 31, 32 semiconductor power element 33 control IC
40, 41 Tie bars 51, 52, 53, 54, 55, 56 Wires 60, 61, 62 Insulator 61a Insulator 62a to which a part of inner lead is fixed Insulator to which a part of die pad is fixed

Claims (7)

半導体パワー素子、該半導体パワー素子の電気的出力特性を最適化すべく調整された制御用ＩＣとを、複数の外部引き出し用端子を有する金属フレーム上に搭載し、外側を樹脂で封止した半導体装置において、前記制御用ＩＣは、前記金属フレーム上に搭載された状態で、前記半導体パワー素子の電気的出力特性を最適化すべく調整されたものであることを特徴とする半導体装置。A semiconductor device in which a semiconductor power element and a control IC adjusted to optimize the electrical output characteristics of the semiconductor power element are mounted on a metal frame having a plurality of external lead terminals, and the outside is sealed with resin. 3. The semiconductor device according to claim 1, wherein the control IC is mounted on the metal frame and adjusted to optimize an electrical output characteristic of the semiconductor power element. 半導体パワー素子、該半導体パワー素子の制御用ＩＣとを、金属フレームのダイパット部分に搭載し、ワイヤボンディングで配線を行い、前記金属フレームのアウターリード、インナーリード、ダイパットの一部を絶縁物で固定し、前記アウターリード部分を連結固定しているタイバーを切断し、電気的に独立した状態にして、前記半導体パワー素子の出力を測定しながら、該半導体パワー素子の電気的特性を最適化すべく、前記制御用ＩＣのトリミングを行い、外側を樹脂で封止することを特徴とする半導体装置の製造方法。A semiconductor power element and a control IC for the semiconductor power element are mounted on a die pad portion of a metal frame, wiring is performed by wire bonding, and outer leads, inner leads, and a part of the die pad of the metal frame are fixed with an insulator. Then, cutting the tie bar connecting and fixing the outer lead portion, in an electrically independent state, while measuring the output of the semiconductor power element, to optimize the electrical characteristics of the semiconductor power element, A method of manufacturing a semiconductor device, comprising trimming the control IC and sealing the outside with a resin. 金属フレームのアウターリード、インナーリード、ダイパットの一部をあらかじめ絶縁物で固定した後、半導体パワー素子及び制御用ＩＣとを前記金属フレームに搭載し、ワイヤボンディングで配線を行い、前記アウターリード部分を連結固定しているタイバーを切断し、電気的に独立した状態にして、前記半導体パワー素子の出力を測定しながら該半導体パワー素子の電気的特性を最適化すべく、前記制御用ＩＣのトリミングを行い、外側を樹脂で封止することを特徴とする半導体装置の製造方法。After fixing a part of the outer lead, the inner lead, and the die pad of the metal frame with an insulator in advance, the semiconductor power element and the control IC are mounted on the metal frame, wiring is performed by wire bonding, and the outer lead part is formed. The control IC is trimmed so as to optimize the electrical characteristics of the semiconductor power element while measuring the output of the semiconductor power element while cutting the tie bar fixed and connected to make it electrically independent. And a method of manufacturing a semiconductor device, wherein the outside is sealed with a resin. 前記金属フレームの少なくとも前記アウターリードの一部を絶縁物で固定したことを特徴とする請求項２、３に記載の半導体装置の製造方法。4. The method according to claim 2, wherein at least a part of the outer lead of the metal frame is fixed with an insulator. 前記金属フレームの少なくとも前記インナーリードの一部またはダイパットの一部を絶縁物で固定したことを特徴とする請求項２、３に記載の半導体装置の製造方法。4. The method according to claim 2, wherein at least a part of the inner lead or a part of the die pad of the metal frame is fixed with an insulator. 樹脂封止の後、前記アウターリードを固定した絶縁物は、前記アウターリードの切断によって除去されることを特徴とする請求項４記載の半導体装置製造方法。The method according to claim 4, wherein after the resin sealing, the insulator to which the outer lead is fixed is removed by cutting the outer lead. 前記インナーリードの一部またはダイパットの一部を固定した絶縁物を、前記外側の封止樹脂で覆うことを特徴とする請求項５記載の半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 5, wherein an insulator to which a part of the inner lead or a part of the die pad is fixed is covered with the outer sealing resin.
JP2003050977A 2003-02-27 2003-02-27 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4319426B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003050977A JP4319426B2 (en) 2003-02-27 2003-02-27 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003050977A JP4319426B2 (en) 2003-02-27 2003-02-27 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2004260066A true JP2004260066A (en) 2004-09-16
JP4319426B2 JP4319426B2 (en) 2009-08-26

Family

ID=33116247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003050977A Expired - Fee Related JP4319426B2 (en) 2003-02-27 2003-02-27 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4319426B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180042106A (en) * 2016-10-16 2018-04-25 알파 앤드 오메가 세미컨덕터 (케이맨) 리미티드 Molded power module having single in-line leads

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180042106A (en) * 2016-10-16 2018-04-25 알파 앤드 오메가 세미컨덕터 (케이맨) 리미티드 Molded power module having single in-line leads
KR102321627B1 (en) * 2016-10-16 2021-11-04 알파 앤드 오메가 세미컨덕터 (케이맨) 리미티드 Molded power module having single in-line leads

Also Published As

Publication number Publication date
JP4319426B2 (en) 2009-08-26

Similar Documents

Publication Publication Date Title
US7847391B2 (en) Manufacturing method for integrating a shunt resistor into a semiconductor package
US5523617A (en) Fuse frames, programmable fuse frames, and methods for programming by fusing
JPH041503B2 (en)
US8324721B2 (en) Integrated shunt resistor with external contact in a semiconductor package
JPH05299576A (en) Multi-chip semiconductor device and manufacture thereof
US8802502B2 (en) TSOP with impedance control
US5841187A (en) Molded electronic component
JPH06216307A (en) Semiconductor device sealed with resin
JP2004260066A (en) Semiconductor device and its manufacturing method
JP3396541B2 (en) Circuit board mounted with hybrid integrated circuit device
JP2873127B2 (en) Positive / negative stabilized power supply
JP2678696B2 (en) Method for manufacturing semiconductor device
JPH0786489A (en) Resin-molded semiconductor device
JP2693688B2 (en) Multi-input / low-loss voltage regulator
JP2713141B2 (en) Semiconductor device
JPH11219969A (en) Semiconductor device
JPH10163412A (en) Resin-sealed hybrid integrated circuit
JPH0648877Y2 (en) Semiconductor device
JPH0864747A (en) Lead frame, manufacture thereof, semiconductor device and manufacture thereof
JPH0294551A (en) Lead frame for semiconductor device
US20140374892A1 (en) Lead frame and semiconductor device using same
JPH0951071A (en) Hybrid integrated circuit device
JPS6351544B2 (en)
JPH09331006A (en) Resin sealed semiconductor device
US20150162269A1 (en) Semiconductor die package with insulated wires for routing power signals

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050816

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060118

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20060703

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20060704

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070403

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070604

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20070710

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20081216

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20090219

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090528

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120605

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4319426

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120605

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120605

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120605

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120605

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130605

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees