JPS6351544B2 - - Google Patents

Info

Publication number
JPS6351544B2
JPS6351544B2 JP6659382A JP6659382A JPS6351544B2 JP S6351544 B2 JPS6351544 B2 JP S6351544B2 JP 6659382 A JP6659382 A JP 6659382A JP 6659382 A JP6659382 A JP 6659382A JP S6351544 B2 JPS6351544 B2 JP S6351544B2
Authority
JP
Japan
Prior art keywords
frame
lead pins
semiconductor element
semiconductor
semiconductor elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6659382A
Other languages
Japanese (ja)
Other versions
JPS58182857A (en
Inventor
Matsuki Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP6659382A priority Critical patent/JPS58182857A/en
Publication of JPS58182857A publication Critical patent/JPS58182857A/en
Publication of JPS6351544B2 publication Critical patent/JPS6351544B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、複数の樹脂モールド等で封止され
た半導体素子をフレームで接続し固定した半導体
装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device in which a plurality of semiconductor elements sealed with resin molds or the like are connected and fixed by a frame.

〔発明の技術的背景〕[Technical background of the invention]

一般に、集積回路等を構成する半導体素子は、
外部環境からの保護等の理由でパツケージングさ
れる。このパツケージングは、従来第1図に示す
ように複数の半導体素子11を金属製のフレーム
12に接続し固定した状態で、各半導体素子11
をそれぞれ樹脂モールド等で封止してなされる。
さらに、半導体素子11とボンデイングワイヤ
(図示せず)で接続されるリードピン13がフレ
ーム12に接続し固定されている。
In general, semiconductor elements that make up integrated circuits, etc.
It is packaged for reasons such as protection from the external environment. This packaging conventionally involves connecting and fixing a plurality of semiconductor elements 11 to a metal frame 12, as shown in FIG.
These are each sealed with a resin mold or the like.
Further, lead pins 13, which are connected to the semiconductor element 11 by bonding wires (not shown), are connected and fixed to the frame 12.

〔背景技術の問題点〕[Problems with background technology]

上記のようにパツケージングされた半導体素子
11をフレーム12から分離して、製品として出
荷する前に、通常各半導体素子11の電気的試験
のために各種測定を行なう。しかしながら、上記
のように半導体素子11がフレーム12に接続し
固定されている状態では、そのまま測定すること
はできない。したがつて、半導体素子11を個々
にフレーム12から分離するか、またはリードピ
ン13の部分のみを各半導体素子11毎に切り離
した状態で測定する必要がある。ところで、半導
体集積回路は、近年ますます小型化が要求されて
いるため、リードピン13の間隔が例えば0.05イ
ンチのように非常に狭くなる傾向にある。このよ
うにリードピン13の間隔が狭いと、各リードピ
ン13を半導体素子11毎に切り離して測定する
場合、リードピン13が機械的強度が弱くなるた
めに折れ曲がるなどの状態が生じる。したがつ
て、リードピン13を介して測定信号を入出力す
ることによつて、半導体素子11の電気的測定を
行なうことが非常に困難であるという欠点があつ
た。
Before the semiconductor elements 11 packaged as described above are separated from the frame 12 and shipped as a product, various measurements are usually performed for electrical testing of each semiconductor element 11. However, in the state where the semiconductor element 11 is connected and fixed to the frame 12 as described above, measurement cannot be performed as is. Therefore, it is necessary to separate the semiconductor elements 11 individually from the frame 12 or to measure only the lead pins 13 after each semiconductor element 11 is separated. Incidentally, as semiconductor integrated circuits are required to be more and more compact in recent years, the spacing between the lead pins 13 tends to become very narrow, for example, 0.05 inch. If the spacing between the lead pins 13 is narrow in this way, when each lead pin 13 is separated into each semiconductor element 11 for measurement, the mechanical strength of the lead pins 13 is weakened, resulting in a situation such as bending. Therefore, there is a drawback that it is very difficult to electrically measure the semiconductor element 11 by inputting and outputting measurement signals via the lead pins 13.

〔発明の目的〕[Purpose of the invention]

この発明は上記の事情を鑑みてなされたもの
で、フレームに接続し固定された複数の半導体素
子に対して、各半導体素子のリードピンの機械的
強度を向上し、リードピンを介して測定信号を入
出力して行なう電気的測定を容易にしかも確実に
行なうことができる半導体装置を提供することを
目的とする。
This invention was made in view of the above circumstances, and it improves the mechanical strength of the lead pins of each semiconductor element for a plurality of semiconductor elements connected and fixed to a frame, and inputs measurement signals through the lead pins. It is an object of the present invention to provide a semiconductor device that can easily and reliably perform electrical measurements by outputting data.

〔発明の概要〕[Summary of the invention]

上記の目的を達成するために、この発明におい
ては、フレームに接続し固定した複数のモールド
加工された半導体素子において、隣接する半導体
素子間の各リードピンの先端部をモールド樹脂等
のモールド絶縁体で接続し固定することにより、
リードピンの機械的強度を向上させるものであ
る。
In order to achieve the above object, in the present invention, in a plurality of molded semiconductor elements connected and fixed to a frame, the tip of each lead pin between adjacent semiconductor elements is covered with a molded insulator such as molded resin. By connecting and fixing,
This improves the mechanical strength of the lead pin.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照してこの発明の一実施例につい
て説明する。第2図は、この発明に係る半導体装
置の構成を示すもので、樹脂モールド等で封止さ
れた半導体素子11が複数個、金属製のフレーム
12に接続し固定されている。各半導体素子11
には、ボンデイングワイヤ(図示せず)等で接続
されるリードピン13が設けられる。そして、隣
接する半導体素子11間の各リードピン13の先
端部を樹脂モールド等のモールド絶縁体21で共
通に接続し固定する。
An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows the configuration of a semiconductor device according to the present invention, in which a plurality of semiconductor elements 11 sealed with a resin mold or the like are connected and fixed to a metal frame 12. Each semiconductor element 11
A lead pin 13 is provided to be connected with a bonding wire (not shown) or the like. Then, the tips of each lead pin 13 between adjacent semiconductor elements 11 are commonly connected and fixed using a mold insulator 21 such as a resin mold.

このように構成される半導体装置を製造するに
は、まずフレーム12にリードピン13およびベ
ツド(図示せず)の両者に対応する部分を形成す
る。上記ベツドに半導体素子をマウントし、この
半導体素子とリードピン13間をボンデイングワ
イヤ(図示せず)で接続する。この場合、各リー
ドピン13は、フレーム12の延長部22等で共
通に接続されている。この延長部22を切り離
し、モールド工程で半導体素子11とともに上記
のようなリードピン13の先端部を樹脂モールド
等でモールド加工する。したがつて、半導体素子
11は封止され、各リードピン13は第2図に示
すように共通に接続されフレーム12に固定され
る。
To manufacture a semiconductor device constructed in this manner, first, portions corresponding to both the lead pins 13 and the bed (not shown) are formed in the frame 12. A semiconductor element is mounted on the bed, and the semiconductor element and lead pins 13 are connected with bonding wires (not shown). In this case, each lead pin 13 is commonly connected by an extension 22 of the frame 12 or the like. The extension portion 22 is cut off, and the tip of the lead pin 13 as described above is molded with a resin mold or the like together with the semiconductor element 11 in a molding process. Therefore, the semiconductor element 11 is sealed, and each lead pin 13 is commonly connected and fixed to the frame 12 as shown in FIG.

このような半導体装置に対して、各半導体素子
11の電気的試験を行なう場合、それぞれのリー
ドピン13を介して測定信号の入出力を行なう。
この場合、各リードピン13は上記のようにモー
ルド絶縁体21で共通に接続されフレーム12に
固定されているため、リードピン13の機械的強
度は大きくなり、折れ曲がるなどの状態は生じな
い。したがつて、リードピン13に対して測定装
置から測定信号を入出力する場合、きわめて容易
にしかも確実に行なうことができる。さらに、
個々の半導体素子11はリードピン13およびモ
ールド絶縁体21を介して接続されているが、電
気的に絶縁されているため、上記のような測定に
対して悪影響を及ぼすことはない。
When electrically testing each semiconductor element 11 of such a semiconductor device, measurement signals are input and output via each lead pin 13.
In this case, since the lead pins 13 are commonly connected by the mold insulator 21 and fixed to the frame 12 as described above, the mechanical strength of the lead pins 13 is increased and no bending or the like occurs. Therefore, when inputting and outputting measurement signals from the measuring device to and from the lead pins 13, this can be done extremely easily and reliably. moreover,
Although the individual semiconductor elements 11 are connected via the lead pins 13 and the mold insulator 21, they are electrically insulated, so that there is no adverse effect on the above measurements.

〔発明の効果〕〔Effect of the invention〕

以上詳述したようにこの発明によれば、複数の
半導体素子をフレームに接続し固定してなる半導
体装置において、各半導体素子のリードピンをモ
ールド絶縁体でフレームに固定して、リードピン
の機械的強度を大幅に向上し、しかも各半導体素
子間は電気的絶縁を保持できる。したがつて、リ
ードピンを介して測定信号を入出力して行なう各
半導体素子の電気的測定を容易にしかも確実に行
なうことができるものである。
As detailed above, according to the present invention, in a semiconductor device in which a plurality of semiconductor elements are connected and fixed to a frame, the lead pins of each semiconductor element are fixed to the frame with a molded insulator, thereby increasing the mechanical strength of the lead pins. In addition, electrical insulation can be maintained between each semiconductor element. Therefore, it is possible to easily and reliably perform electrical measurements on each semiconductor element by inputting and outputting measurement signals via the lead pins.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の半導体装置の構成図、第2図は
この発明の一実施例に係る半導体装置の構成図で
ある。 11……半導体素子、12……フレーム、13
……リードピン、21……モールド絶縁体。
FIG. 1 is a block diagram of a conventional semiconductor device, and FIG. 2 is a block diagram of a semiconductor device according to an embodiment of the present invention. 11...Semiconductor element, 12...Frame, 13
...Lead pin, 21...Mold insulator.

Claims (1)

【特許請求の範囲】[Claims] 1 複数のモールド加工された半導体素子を一列
に接続し固定するフレームと、上記半導体素子の
それぞれに接続されているリードピンと、隣接す
る上記半導体素子間の各リードピンの先端部を共
通に接続して上記フレームに固定するモールド絶
縁体とを具備したことを特徴とする半導体装置。
1 A frame for connecting and fixing a plurality of molded semiconductor elements in a row, lead pins connected to each of the semiconductor elements, and a common connection between the tips of the lead pins between the adjacent semiconductor elements. A semiconductor device comprising a molded insulator fixed to the frame.
JP6659382A 1982-04-21 1982-04-21 Semiconductor device Granted JPS58182857A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6659382A JPS58182857A (en) 1982-04-21 1982-04-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6659382A JPS58182857A (en) 1982-04-21 1982-04-21 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS58182857A JPS58182857A (en) 1983-10-25
JPS6351544B2 true JPS6351544B2 (en) 1988-10-14

Family

ID=13320379

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6659382A Granted JPS58182857A (en) 1982-04-21 1982-04-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58182857A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0493482U (en) * 1991-01-08 1992-08-13

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4852519B2 (en) * 2007-11-30 2012-01-11 株式会社ニフコ Movable body support device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0493482U (en) * 1991-01-08 1992-08-13

Also Published As

Publication number Publication date
JPS58182857A (en) 1983-10-25

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