JPH04158562A - Semiconductor devices, their lead frames and manufacture of semiconductor devices and their inspection method - Google Patents
Semiconductor devices, their lead frames and manufacture of semiconductor devices and their inspection methodInfo
- Publication number
- JPH04158562A JPH04158562A JP28507390A JP28507390A JPH04158562A JP H04158562 A JPH04158562 A JP H04158562A JP 28507390 A JP28507390 A JP 28507390A JP 28507390 A JP28507390 A JP 28507390A JP H04158562 A JPH04158562 A JP H04158562A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- die pad
- frame
- semiconductor device
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000007689 inspection Methods 0.000 title abstract description 13
- 239000011347 resin Substances 0.000 claims abstract description 31
- 229920005989 resin Polymers 0.000 claims abstract description 31
- 238000012360 testing method Methods 0.000 claims description 12
- 238000005520 cutting process Methods 0.000 claims description 8
- 238000007789 sealing Methods 0.000 claims description 7
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract description 10
- 229910000679 solder Inorganic materials 0.000 abstract description 6
- 238000007747 plating Methods 0.000 abstract description 5
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000012856 packing Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は比較的大型の樹脂成形部を備えた半導体装置、
特に大電力用半導体装置、それに用いるリードフレーム
、半導体装置の製造方法および半導体装置の検査方法に
関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device having a relatively large resin molded part;
In particular, the present invention relates to a high-power semiconductor device, a lead frame used therein, a method for manufacturing a semiconductor device, and a method for testing a semiconductor device.
従来の技術
通常、１連のリードフレームに複数個の半導体装置を形
成し、リードフレームの切断により個々の半導体装置を
製造する。2. Description of the Related Art Generally, a plurality of semiconductor devices are formed on a series of lead frames, and individual semiconductor devices are manufactured by cutting the lead frame.
第５図は従来の半導体装置、それに用いるリードフレー
ム、半導体装置の製造方法および半導体装置の検査方法
を示すものである。第５図において、ｌは半導体素子、
２はダイパッド、３は外部導出リード、４はボンディン
グワイヤ、５は接着剤、６はタイバー、７は枠、８はモ
ールド樹脂、９はリード線半田である。FIG. 5 shows a conventional semiconductor device, a lead frame used therein, a method for manufacturing the semiconductor device, and a method for testing the semiconductor device. In FIG. 5, l is a semiconductor element,
2 is a die pad, 3 is an external lead, 4 is a bonding wire, 5 is an adhesive, 6 is a tie bar, 7 is a frame, 8 is a molding resin, and 9 is a lead wire solder.
まず、リードフレームの構成を第５図（ａ）を用いて説
明する。First, the structure of the lead frame will be explained using FIG. 5(a).
リードフレームは半導体素子１を載置するダイパッド２
と、一端がワイヤボンディングされる外部導出リード３
と、ダイパッド２と外部導出り一ド３を中間で支えるタ
イバー６と、タイツ（・ソド２と外部導出リード３の他
端を支える枠７とから構成される。The lead frame has a die pad 2 on which a semiconductor element 1 is placed.
and an external lead 3 whose one end is wire-bonded.
, a tie bar 6 that supports the die pad 2 and the external lead 3 in the middle, and a frame 7 that supports the other end of the tights 2 and the external lead 3.
次に、半導体装置の製造方法を第５図を用いて説明する
。Next, a method for manufacturing a semiconductor device will be explained using FIG. 5.
ダイパッド２に半導体素子１を接着剤５で接着し、半導
体素子ｌの外部接続端子と外部導出り−ド３の一端とを
ボンディングワイヤ４で結線する（第５図（ａ））。次
に、タイツく−６と枠７の部分を残し、他の部分をモー
ルド樹脂８で封止する（第５図（ｂ））。最後に、タイ
バー６および枠７を切断し、個々の半導体装置に分断し
、リード線半田９を付ける（第５図（Ｃ））。The semiconductor element 1 is bonded to the die pad 2 with an adhesive 5, and the external connection terminal of the semiconductor element 1 and one end of the external lead-out lead 3 are connected with a bonding wire 4 (FIG. 5(a)). Next, leaving the tights 6 and the frame 7, the other parts are sealed with mold resin 8 (FIG. 5(b)). Finally, the tie bars 6 and frame 7 are cut to separate the semiconductor devices into individual semiconductor devices, and lead wire solder 9 is attached (FIG. 5(C)).
半導体装置の検査方法は、個々に分断された半導体装置
をマガジンまたはパレットに再配列し、１個または数個
の半導体装置を検査設備へ投入して、検査する（第５図
（Ｃ））。A semiconductor device testing method involves rearranging the individual semiconductor devices in a magazine or pallet, loading one or several semiconductor devices into testing equipment, and testing them (FIG. 5(C)).
第６図に半導体装置の製造、検査工程のライン構成を示
す。FIG. 6 shows a line configuration of semiconductor device manufacturing and inspection processes.
ダイスボンド工程１１、ワイヤボンド工程１２、樹脂封
止工程１３、リードカット工程１４が第１のラインとな
り、マガジン詰め工程１５と半田付けまたはメツキ工程
１６が第２のラインとなり、再度マガジン詰め工程１７
と検査・マーキング工程が第３のラインとなる。Dice bonding process 11, wire bonding process 12, resin sealing process 13, and lead cutting process 14 are the first line, magazine packing process 15 and soldering or plating process 16 are the second line, and again magazine packing process 17.
The inspection and marking process is the third line.
発明が解決しようとする課題
従来の大電力用半導体素子が代表する比較的大型の半導
体装置は、外部導出リード３をタイバー６と枠７で連結
することによって、１０〜２０個の半導体装置を連とな
し、ダイスボンド、ワイヤーボンドあるいは封止成形工
程のインライン化を実現してきた
しかしながら従来の構成では、各々の半導体装置が短絡
したままのため、半導体装置の電気的特性を検査するこ
とができず、検査の工程前でタイバー６および枠７を切
断し、半導体装置をマガジンまたはパレットに再配列し
て、１個または数個の半導体装置を検査設備へ投入し、
検査しなければならない。Problems to be Solved by the Invention Relatively large semiconductor devices represented by conventional high-power semiconductor devices can be connected by connecting 10 to 20 semiconductor devices by connecting external leads 3 with tie bars 6 and frames 7. However, with the conventional configuration, each semiconductor device remains short-circuited, making it impossible to inspect the electrical characteristics of the semiconductor device. , before the inspection process, cut the tie bars 6 and frame 7, rearrange the semiconductor devices in a magazine or pallet, and load one or several semiconductor devices into the inspection equipment;
Must be inspected.
この方法では、いったんラインを切ってマガジンまたは
パレットに配列するか、もしくは、ロボットまたはパー
ツフィーダーを導入し配列するかであるが、動作が複雑
で全体の工数が増えたり、高額な投資が必要になる。そ
のため全ラインをインライン化する上で問題である。In this method, the lines are cut and arranged on magazines or pallets, or a robot or parts feeder is introduced and arranged, but the operations are complicated, the overall man-hours increase, and a large amount of investment is required. Become. Therefore, it is a problem to inline all lines.
本発明は上記従来の問題点を解決するもので、全ライン
をインライン化できる半導体装置、それに用いるリード
フレーム、半導体装置の製造方法および半導体装置の検
査方法を提供することを目的とする。The present invention solves the above conventional problems, and aims to provide a semiconductor device in which all lines can be inlined, a lead frame used therein, a method for manufacturing a semiconductor device, and a method for testing a semiconductor device.
課題を解決するための手段
この目的を達成するために本発明の半導体装置は、ダイ
パッドと、このダイパッド上の半導体素子と、この半導
体素子の外部接続端子とボンディングワイヤで接続され
た外部導出リードと、ダイパッドおよび外部導出リード
と絶縁され、かつ隣合う樹脂成形体間を連結して支える
連結細条の一端を含み封止した樹脂からなり、タイバー
および枠の切断後も各半導体装置の封止樹脂間を接続し
、半導体素子と絶縁された連結細条を僅えたリードフレ
ームを用い、タイバーおよび枠の切断時に連結細条は切
断しないで複数個連結された状態で検査する方法をとり
、検査後封止樹脂の外側の連結細条を切断する工程を備
えた方法で製造される。Means for Solving the Problems To achieve this object, the semiconductor device of the present invention includes a die pad, a semiconductor element on the die pad, and an external lead connected to an external connection terminal of the semiconductor element with a bonding wire. , is insulated from the die pad and external leads, and is made of a sealed resin that includes one end of a connecting strip that connects and supports adjacent resin molded bodies, and the sealing resin of each semiconductor device remains intact even after the tie bars and frame are cut. We use a lead frame with a few connecting strips that are insulated from the semiconductor element, and when the tie bars and frames are cut, the connecting strips are not cut but are inspected in a state in which multiple pieces are connected. It is manufactured by a method that includes the step of cutting the connecting strips on the outside of the sealing resin.
作用
この構成によって、タイバーおよび枠の切断後も連結細
条で複数個の半導体装置が連結され、かつ外部導出リー
ドが分離しているため、個々の半導体装置の検査が可能
である。Effect: With this configuration, a plurality of semiconductor devices are connected by the connecting strips even after the tie bars and frames are cut, and the external leads are separated, so that it is possible to test each semiconductor device individually.
実施例
以下本発明の一実施例について、図面を参照しながら説
明する。EXAMPLE An example of the present invention will be described below with reference to the drawings.
第１図は本発明の第１の実施例における半導体装置、そ
れに用いるリードフレーム、半導体装置の製造方法およ
び半導体装置の検査方法を示すものである。FIG. 1 shows a semiconductor device, a lead frame used therein, a method for manufacturing the semiconductor device, and a method for testing the semiconductor device according to a first embodiment of the present invention.
第１図において、１は半導体素子、２はダイパッド、３
は外部導出リード、４はボンディングワイヤ、５は接着
剤、６はタイバー、７は枠、８はモールド樹脂、９はリ
ード線半田、２１は連結細条で、ダイパッド２とは絶縁
され、かつ、隣合う半導体装置の、モールド樹脂８から
なる成形体間を連結して支えている。In FIG. 1, 1 is a semiconductor element, 2 is a die pad, and 3 is a semiconductor element.
1 is an external lead, 4 is a bonding wire, 5 is an adhesive, 6 is a tie bar, 7 is a frame, 8 is a mold resin, 9 is a lead wire solder, 21 is a connecting strip, which is insulated from the die pad 2, and The molded bodies made of mold resin 8 of adjacent semiconductor devices are connected and supported.
まず、リードフレームの構成について、第１図（ａ）を
用いて説明する。First, the structure of the lead frame will be explained using FIG. 1(a).
リードフレームは半導体素子１を載置するダイパッド２
と、一端がワイヤボンディングされる外部導出リード３
と、ダイパッド２と外部導出り−ド３を中間で支えるタ
イバー６と、ダイパッド２と外部導出リード３の他端を
支える枠７と、タイバー６と枠７とで支えられ、かつ隣
合う半導体装置のモールド樹脂８成形体間を連結して支
え、かつダイパッド２とは絶縁された連結細条２１から
構成される。The lead frame has a die pad 2 on which a semiconductor element 1 is placed.
and an external lead 3 whose one end is wire-bonded.
, a tie bar 6 that supports the die pad 2 and the external lead-out lead 3 in the middle, a frame 7 that supports the other end of the die pad 2 and the external lead-out lead 3, and a semiconductor device that is supported by the tie bar 6 and the frame 7 and is adjacent to each other. The connecting strip 21 connects and supports the molded resin 8 molded bodies and is insulated from the die pad 2.
次に、半導体装置の製造方法について、第１図を用いて
説明する。Next, a method for manufacturing a semiconductor device will be explained using FIG.
ダイパッド２に半導体素子１を接着剤５で接着し、半導
体素子１の外部接続端子と外部導出り−ド３の一端とを
ボンディングワイヤ４で結線する（第１図（ａ））。次
に、タイバー６および枠７部分を残しモールド樹脂８で
封止する（第１図（ｂ）〉。The semiconductor element 1 is bonded to the die pad 2 with an adhesive 5, and the external connection terminal of the semiconductor element 1 and one end of the external lead-out lead 3 are connected with a bonding wire 4 (FIG. 1(a)). Next, the tie bar 6 and the frame 7 are sealed with mold resin 8 (FIG. 1(b)).
次に、タイバー６および枠７を切断し、外部導出リード
３を電気的に分離し、連結細条２１でモールド樹脂８間
を連結した状態にし、その後、外部導出リード３にリー
ド線半田９あるいはメツキを付ける（第１図（Ｃ））。Next, the tie bar 6 and the frame 7 are cut, the external lead-out leads 3 are electrically separated, the molded resin 8 is connected with the connecting strip 21, and then the external lead-out leads 3 are soldered with lead wire solder 9 or Attach plating (Figure 1 (C)).
最後に、連結細条２１のモールド樹脂８の外側部分を切
断し、個々の半導体装置に分断する（第１図ω））。Finally, the outer portion of the molded resin 8 of the connecting strip 21 is cut to separate the semiconductor devices into individual semiconductor devices (see ω in FIG. 1).
半導体装置の検査方法は、連結細条２１でモールド樹脂
８間を連結した状態のままに個々の半導体装置の電気的
特性を検査するものである（第１図（Ｃ））。The method for testing semiconductor devices is to test the electrical characteristics of each semiconductor device while keeping the mold resins 8 connected by connecting strips 21 (FIG. 1(C)).
さらに詳細に説明すると、タイバー６および枠７を切断
した状態で、かつ複数の半導体装置がダイパッド２と外
部導出リード３と絶縁された連結細条２１でモールド樹
脂８間を連結した状態で、これら半導体装置の電気的特
性を独立して検査することができる。つまり、連結細条
２１は複数個の半導体装置がばらばらにならないように
連結する役割をし、それにより複数個の半導体装置を連
結した状態で検査することができる。More specifically, when the tie bars 6 and the frame 7 are cut, and when a plurality of semiconductor devices are connected to the die pad 2 and the external leads 3 by the insulated connecting strips 21, the molded resin 8 is connected. Electrical characteristics of semiconductor devices can be independently tested. In other words, the connecting strips 21 serve to connect a plurality of semiconductor devices so that they do not come apart, so that a plurality of semiconductor devices can be inspected in a connected state.
第２図は本発明の第２の実施例を示すリードフレームで
、第２図（ａ）はその平面図、第２図（ｂ）はその側面
図である。その構成は連結細条２１をダイパッド２と平
面的に重なる位置に配置するものである（第２図（ａ）
）。連結細条２１とダイパッド２が重ならないように途
中で折り曲げて、連結細条２１とダイパッド２を絶縁す
るものである（第２図（ｂ））。FIG. 2 shows a lead frame showing a second embodiment of the present invention, FIG. 2(a) is a plan view thereof, and FIG. 2(b) is a side view thereof. The structure is such that the connecting strips 21 are arranged in a position that overlaps the die pad 2 in a plane (Fig. 2(a)).
). The connecting strip 21 and the die pad 2 are bent in the middle so that they do not overlap, thereby insulating the connecting strip 21 and the die pad 2 (FIG. 2(b)).
第３図は本発明の第３の実施例を示すリードフレームの
平面図で、第１図および第２図に示す連結細条２１を両
方備えた構成のものである。FIG. 3 is a plan view of a lead frame showing a third embodiment of the present invention, which has both the connecting strips 21 shown in FIGS. 1 and 2.
第４図に半導体装置の製造、検査工程のライン構成を示
す。FIG. 4 shows the line configuration of semiconductor device manufacturing and inspection processes.
ダイスボンド工程１１、ワイヤボンド工程１２、樹脂封
圧工程１３、リードカット工程１４、半田付けまたはメ
ツキ工程１６、検査・マーキング工程１８がすべて１ラ
インとなる。これにより、インライン状態のまま製造、
検査が可能となる。A die bonding process 11, a wire bonding process 12, a resin sealing process 13, a lead cutting process 14, a soldering or plating process 16, and an inspection/marking process 18 all form one line. This allows for in-line manufacturing,
Inspection becomes possible.
発明の効果
以上のように本発明は隣合う樹脂成形体間を連結して支
え、かつ前記ダイパッドとは絶縁された連結細条を設け
ることにより、タイバーおよび枠の切断後も複数の半導
体装置が連結細条で連結されており、半導体装置の製造
・検査工程もインラインによって処理でき、複雑な設備
・工程が不要となり、リードタイムの短縮にも大きな効
果をもたらす。Effects of the Invention As described above, the present invention provides connecting strips that connect and support adjacent resin molded bodies and are insulated from the die pad, so that a plurality of semiconductor devices can be connected even after the tie bars and frames are cut. Since they are connected by connecting strips, the manufacturing and inspection processes for semiconductor devices can be performed in-line, eliminating the need for complex equipment and processes, and having a significant effect on shortening lead times.
第１図は本発明の第１の実施例における半導体装置の製
造方法およびそれに用いるリードフレームを示す平面図
、第２図は本発明の第２の実施例におけるリードフレー
ムを示す構成図、第３図は本発明の第３の実施例におけ
るリードフレームを示す平面図、第４図は本発明の一実
施例における半導体装置の製造、検査工程のライン構成
図、第５図は従来の半導体装置の製造方法およびそれに
用いるリードフレームを示す平面図、第６図は従来の半
導体装置の製造、検査工程のライン構成図である。
１・・・・・・半導体素子、２・・・・・・ダイパッド
、３・・・・・・外部導出リード、４・・・・・・ボン
ディングワイヤ、５・・・・・・接着剤、６・・・・・
・タイバー、７・・・・・・枠、８・・・・・・モール
ド樹脂、９・・・・・・リード線半田、１１・・・・・
・ダイスボンド工程、１２・・・・・・ワイヤボンド工
程、１３・・・・・・樹脂封止工程、１４・・・・・・
リードカット工程、１６・・・・・・半田付けまたはメ
ツキ工程、１８・・・・・・検査・マーキング工程、２
１・・・・・・連結細条。
代理人の氏名 弁理士小蝦治明 ほか２名第２図FIG. 1 is a plan view showing a semiconductor device manufacturing method and a lead frame used therein according to a first embodiment of the present invention, FIG. 2 is a configuration diagram showing a lead frame according to a second embodiment of the present invention, and FIG. The figure is a plan view showing a lead frame in a third embodiment of the present invention, FIG. 4 is a line configuration diagram of the manufacturing and inspection process of a semiconductor device in one embodiment of the present invention, and FIG. 5 is a diagram of a conventional semiconductor device. FIG. 6 is a plan view showing a manufacturing method and a lead frame used therein, and is a line configuration diagram of a conventional semiconductor device manufacturing and inspection process. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 2... Die pad, 3... External lead-out lead, 4... Bonding wire, 5... Adhesive, 6...
・Tie bar, 7...Frame, 8...Mold resin, 9...Lead wire solder, 11...
・Dice bonding process, 12...Wire bonding process, 13...Resin sealing process, 14...
Lead cutting process, 16...Soldering or plating process, 18...Inspection/marking process, 2
1... Connection details. Name of agent: Patent attorney Haruaki Koebi and two others Figure 2
Claims (4)
、前記半導体素子の外部接続端子とボンディングワイヤ
で接続された外部導出リードと、前記ダイパッドおよび
前記外部導出リードと絶縁された連結細条と、前記ダイ
パッド、前記半導体素子、前記外部導出リードの一端お
よび前記連結細条の一端を封止した樹脂からなる半導体
装置。(1) a die pad, a semiconductor element on the die pad, an external lead-out lead connected to an external connection terminal of the semiconductor element with a bonding wire, a connecting strip insulated from the die pad and the external lead-out lead; A semiconductor device comprising a die pad, the semiconductor element, one end of the external lead-out lead, and one end of the connecting strip made of resin sealed.
形領域間を連結して支え、かつ前記ダイパッドとは絶縁
された連結細条と、前記ダイパッドと前記外部導出リー
ドと前記連結細条とを中間および端でそれぞれ支えるタ
イバーと枠とが複数連なってなるリードフレーム。(2) A die pad, an external lead-out lead, a connecting strip that connects and supports adjacent resin molded areas and is insulated from the die pad, and a connecting strip that connects the die pad, the external lead-out lead, and the connecting strip. A lead frame is made up of a series of tie bars and frames that are supported at the middle and ends, respectively.
ドとは絶縁された、隣合う樹脂成形体間を連結するため
の連結細条と、前記ダイパッドと前記外部導出リードと
前記連結細条とを中間および端でそれぞれ支えるタイバ
ーと枠とからなるリードフレームの前記ダイパッド上に
半導体素子を接着する工程と、前記半導体素子の外部接
続端子と前記外部導出リードをボンディングワイヤで結
線する工程と、前記連結細条の一端を含み、前記ダイパ
ッド、前記半導体素子、および前記外部導出リードの一
端を樹脂封止する工程と、前記タイバーおよび前記枠を
切断する工程と、封止樹脂の外側にある前記連結細条を
切断する工程とを備えた半導体装置の製造方法。(3) A die pad, an external lead-out lead, a connecting strip for connecting adjacent resin molded bodies that are insulated from the die pad, and an intermediate between the die pad, the external lead-out lead, and the connecting strip. a step of bonding a semiconductor element onto the die pad of a lead frame comprising a tie bar and a frame supported at respective ends; a step of connecting an external connection terminal of the semiconductor element and the external lead-out lead with a bonding wire; a step of sealing the die pad, the semiconductor element, and one end of the external leads including one end of the strip with a resin; a step of cutting the tie bar and the frame; and a step of cutting the tie bar and the frame, and the connecting strip located outside the sealing resin. A method for manufacturing a semiconductor device, comprising the step of cutting.
支えるタイバーと、隣合う複数の半導体素子の樹脂成形
体間を連結して支え、かつ前記ダイパッドと前記外部導
出リードとは絶縁された連結細条とを枠で繋いだリード
フレームを備えた半導体装置の前記タイバーおよび前記
枠を切断し、前記隣合う樹脂成形体間が前記連結細条で
連結された状態で前記複数の半導体素子の電気的特性を
検査する半導体装置の検査方法。(4) A die pad, an external lead, a tie bar that supports the external lead, and a connecting wire that connects and supports the resin molded bodies of a plurality of adjacent semiconductor elements, and that the die pad and the external lead-out lead are insulated. The tie bars and the frame of a semiconductor device equipped with a lead frame in which strips are connected by a frame are cut, and the electrical connection of the plurality of semiconductor elements is performed while the adjacent resin molded bodies are connected by the connecting strips. A semiconductor device testing method for testing characteristics.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28507390A JPH04158562A (en) | 1990-10-22 | 1990-10-22 | Semiconductor devices, their lead frames and manufacture of semiconductor devices and their inspection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28507390A JPH04158562A (en) | 1990-10-22 | 1990-10-22 | Semiconductor devices, their lead frames and manufacture of semiconductor devices and their inspection method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04158562A true JPH04158562A (en) | 1992-06-01 |
Family
ID=17686799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28507390A Pending JPH04158562A (en) | 1990-10-22 | 1990-10-22 | Semiconductor devices, their lead frames and manufacture of semiconductor devices and their inspection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04158562A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006253719A (en) * | 2002-02-01 | 2006-09-21 | Sharp Corp | Manufacturing method for semiconductor laser apparatus |
-
1990
- 1990-10-22 JP JP28507390A patent/JPH04158562A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006253719A (en) * | 2002-02-01 | 2006-09-21 | Sharp Corp | Manufacturing method for semiconductor laser apparatus |
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