JP2004260032A - Semiconductor device, method for testing the same and method for correcting its reference voltage - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To sharply improve test efficiency by recording the correction value of a reference voltage generating circuit in a semiconductor device without using a fuse blowing device. <P>SOLUTION: A semiconductor device 11 is provided with an ID holding means 19 for holding an ID for identification; a reference voltage generating means 15 for changing and outputting a reference voltage 14 by trimming; a non-volatile memory 23 in which ID 20 for confirmation having the same value as the ID for identification and a correction value 21 are stored; and a reference voltage correcting means 17 for changing a reference voltage 14 according to a preliminarily decided retrieval procedure, for reading the ID 20 for confirmation from the non-volatile memory part 23, for comparing the ID 20 for confirmation with the ID for identification, for reading the correction value 21 from the non-volatile memory part 23 when those ID match, and for operating to set the reference voltage 14 as a desired value. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a reference voltage generation circuit capable of correcting a reference voltage to a desired value by trimming, a test method thereof, and a reference voltage correction method. In particular, the present invention is applied to a memory embedded logic IC that requires a highly accurate reference voltage and stores a correction value used for trimming of a reference voltage generation circuit in a semiconductor device in a test process at the time of manufacturing.
[0002]
[Prior art]
2. Description of the Related Art A semiconductor device having a nonvolatile memory cell region such as an EEPROM requires a high-precision reference voltage which is not affected by a power supply voltage or an operating temperature for writing data to a memory cell and reading data from the memory cell. In particular, in recent years, a so-called multi-value cell that stores two-bit data in one memory cell has appeared, and the improvement of the accuracy of the reference voltage has become increasingly important.
[0003]
As one means for achieving such an object, a reference voltage generating circuit capable of changing an output voltage by trimming is provided, and the output voltage is measured in a test process at the time of manufacturing, and a difference from a desired design value is corrected. Is recorded in the semiconductor device.
[0004]
FIG. 13 is a circuit block diagram showing a conventional semiconductor device 301. Here, the reference voltage generation circuit 305 and a portion related to the correction are mainly shown.
[0005]
The conventional semiconductor device 301 includes a Vcc terminal 302 to which an external power is supplied, an internal power supply circuit 303 for generating a power supply voltage required in each circuit block in the semiconductor device 301, and a reference voltage for generating a highly accurate reference voltage 304. A generation circuit 305, a correction fuse 306 for holding trimming data for correcting the reference voltage 304 (hereinafter referred to as a correction value), a reference voltage measurement pad 307 for measuring the reference voltage 304, and arbitrary data. A nonvolatile memory unit 309 having a memory cell region 308 and a logic circuit unit 310 for performing necessary processing based on specifications are provided.
[0006]
The input of the internal power supply circuit 303 is connected to the Vcc terminal 302, and the output is connected to the power supply input of each circuit block including the logic circuit unit 310 in the semiconductor device 301.
[0007]
A correction signal 311 output from the correction fuse 306 is connected to an input of a reference voltage generation circuit 305, and a reference voltage 304 output from the reference voltage generation circuit 305 is input to a nonvolatile memory unit 309 and a reference voltage measurement pad. 307.
[0008]
The measurement probe of the tester 312 placed outside the semiconductor device 301 is connected to the reference voltage measurement pad 307. Further, the fuse element in the correction fuse 306 is cut by the laser light of the fuse blow device 313 placed outside the semiconductor device 301.
[0009]
The internal power supply circuit 303 steps down or boosts the external power supply voltage supplied from the Vcc terminal 302 to generate a plurality of voltages necessary for the operation of each circuit in the semiconductor device 301, and the semiconductor device 301 including the logic circuit unit 310 Is supplied to each circuit block inside. Since the internal power supply circuit 303 must supply a relatively large current, the internal power supply circuit 303 is susceptible to load fluctuations due to the circuit operation, and the internal voltage generated here cannot avoid a certain degree of voltage fluctuations.
[0010]
Further, it is not unusual for process parameters to vary at the time of chip manufacture, and that the respective time average values of the internal voltage deviate from the design values by several percent. For this reason, the high-precision reference voltage 304 required for reading and writing of the nonvolatile memory unit 309 is generated by separately providing a dedicated reference voltage generation circuit 305.
[0011]
Generally, a band gap reference circuit (hereinafter, referred to as BGR) using an operational amplifier is used as the reference voltage generation circuit 305. The reference voltage generation circuit 305 is designed to change the resistance ratio of BGR by trimming, change this resistance ratio based on the correction signal 311 from the correction fuse 306, and correct the value of the reference voltage 304 as an output. I have.
[0012]
The reference voltage 304 corrected in this manner is supplied to the nonvolatile memory unit 309 and, at the same time, is output to the reference voltage measurement pad 307 for measurement by the tester 312. Various measures have been devised to suppress the fluctuation of the reference voltage 304 due to the load fluctuation, but it is fundamentally to design the system so as to minimize the load current fluctuation.
[0013]
The correction fuse 306 has fuse elements made of polysilicon, polycide, or aluminum (Al) for a required number of bits, and information corresponding to the number of bits depends on whether or not each of these fuse elements is cut. Can be stored. The correction value obtained in the test process at the time of manufacturing the semiconductor device 301 is written here by the fuse blow device 313. The correction fuse 306 outputs a correction signal 311 to the reference voltage generation circuit 305 based on the fuse data (correction value).
[0014]
Next, a test method of the above-described semiconductor device 301 will be described. FIG. 14 is a flowchart showing a test method of the conventional semiconductor device 301. Here, a test method mainly related to the correction of the reference voltage 304 and the pass / fail judgment of the semiconductor device 301 based on the corrected reference voltage 304 has been described.
[0015]
The conventional semiconductor device 301 test method includes an initial voltage measuring step 321 for measuring an initial value of the reference voltage 304, a correction value obtaining step 322 for obtaining a difference between the initial value of the reference voltage 304 and a design value as a correction value, A fuse blow step 323 for cutting the fuse element using the device 313, a reference voltage measurement step 324 for measuring the reference voltage 304 corrected by the correction value, and a non-defective or defective product is determined and recorded based on the measured value. The determination step 325 is constituted.
[0016]
In the initial voltage measuring step 321, the reference voltage 304, which is the output of the reference voltage generating circuit 305 in an initial state, is measured by the tester 312. Here, the initial state refers to a state equivalent to a state in which the initialization of the semiconductor device 301 is completed immediately after power-on, and the reference voltage generation circuit 305 does not perform correction by trimming. In this initial state, the resistance ratio of the BGR is set so that the reference voltage 304 outputs a desired design value when various process parameters have ideal values.
[0017]
In the actually manufactured semiconductor device 301, since the process parameters vary from ideal values, the resistance ratio of BGR does not always become the value assumed at the time of design, and the initial value of the reference voltage 304 is Will be different for each. Therefore, a circuit is configured so that the resistance ratio of the BGR can be changed by trimming within a certain range in consideration of the variation in the process parameters at the time of design.
[0018]
In the correction value obtaining step 322, a difference between the initial value obtained in the initial voltage measuring step 321 and a desired design value assumed at the time of design is obtained for each semiconductor device 301, and these are output in a data format that can be output to the outside of the tester 312. And is recorded as a correction value on a magnetic medium or the like.
[0019]
The initial voltage measurement step 321 and the correction value acquisition step 322 are executed with the wafer of the semiconductor device 301 set in the wafer prober device to which the tester 312 is connected.
[0020]
In the fuse blowing step 323, respective correction values are written to the correction fuse 306 by using the fuse blowing device 313 in which the above-described recording medium is set. As a specific writing method, there are cutting of a fuse by a laser beam and blowing of a fuse by an electric current. Recently, a method using a laser beam is used from the viewpoint of easiness of circuit configuration and writing efficiency.
[0021]
This fuse blowing step 323 must be executed by transferring a wafer to be processed from the wafer prober device to the fuse blowing device 313. For this reason, it is necessary to transfer the correction value obtained in the correction value obtaining step 322 from the tester 312 to the fuse blow device 313 via a magnetic medium or a communication medium.
[0022]
In the reference voltage measurement step 324, the wafer to be processed is returned to the wafer prober again, and the corrected reference voltage 304 is measured by the tester 312. Since the correction fuses 306 are written in accordance with the respective semiconductor devices 301 in the above-described fuse blowing step 323, ideally, in this step, the reference voltage 304, which is the output of the reference voltage generation circuit 305, is set at the time of design. The value is corrected to substantially the same value as the assumed desired design value.
[0023]
However, when the variation in the process parameters exceeds the range assumed at the time of design, when the reference voltage generation circuit 305 or the like causes an operation failure due to a trouble during chip manufacture, or when the fuse element is physically For example, when disconnection cannot be performed properly, the reference voltage 304 may not be corrected correctly.
[0024]
The semiconductor device 301 for which the reference voltage 304 has not been correctly corrected is selected in the pass / fail determination step 325. That is, it is determined whether the reference voltage 304 measured in the reference voltage measurement step 324 is within the allowable error range of the desired design value, and the semiconductor device 301 that has not been correctly corrected is recorded as a defective product, and the test process ends. It will be removed in a later assembly step.
[0025]
Thus, the reference voltage 304, which is the output of the reference voltage generation circuit 305, can be set to a desired value with high precision by trimming using the correction fuse 306. However, in the conventional test method for the semiconductor device 301, as described above, the wafer must be moved from the wafer prober device to the fuse blow device 313 each time the correction fuse 306 is written, and the test efficiency is extremely high. It was low.
[0026]
Further, a required number of fuse blow devices 313 must be prepared separately from the tester 312, and capital investment is also required.
[0027]
In order to cope with this problem, a plurality of nonvolatile memory cells are provided in the semiconductor device 301 in place of the correction fuse 306, and a correction value is stored in the nonvolatile memory cell in a test process at the time of manufacturing, and the nonvolatile memory cell is used. A method has been proposed in which the reference voltage generation circuit 305 is trimmed. That is, Patent Document 1 discloses a method of using a PROM cell instead of the correction fuse 306, and Patent Document 2 discloses a method of using a part of a nonvolatile memory cell area 308 for data storage for holding a correction value. Each is listed.
[0028]
However, each of these has an essential disadvantage that, in the initial state immediately after power-on, when the correction value is read from the nonvolatile memory cell, the reference voltage 304 used for reading is not correctly corrected. . In other words, there is a possibility that the correction value cannot be read correctly, and as a result, the reference voltage 304 greatly differs from a desired design value. In particular, due to the recent miniaturization of semiconductor processes and multi-valued nonvolatile memory cells (so-called multi-valued cells), the problem of erroneous reading of correction values in the initial state has become serious. In some cases, it also causes a significant decrease in the yield of the semiconductor device 301.
[0029]
[Patent Document 1]
JP-A-5-265579 (FIG. 2)
[0030]
[Patent Document 2]
JP 2001-357688 A (FIG. 1)
[0031]
[Problems to be solved by the invention]
As described above, in the conventional semiconductor device, its test method, and its reference voltage correction method, the correction value used for trimming the reference voltage generation circuit is recorded in the correction fuse by the fuse blow device, so that the test efficiency is significantly reduced. There was a problem of doing.
[0032]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a semiconductor device capable of recording a correction value of a reference voltage generation circuit in a semiconductor device without using a fuse blow device, thereby greatly improving test efficiency. It is an object to provide an apparatus, a test method thereof, and a reference voltage correction method thereof.
[0033]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention includes: an ID holding unit that holds an identification ID that is a predetermined bit pattern; a reference voltage generation unit that changes and outputs a reference voltage by trimming; A confirmation ID having the same value as the identification ID and a correction value for setting the reference voltage to a desired value are stored in some of the plurality of nonvolatile memory cells, and A nonvolatile memory to which a reference voltage is supplied, and a trimming value for changing the reference voltage output from the reference voltage generating means in accordance with a predetermined search procedure; Each time the reference voltage output from the generating means is changed, the confirmation ID is read from the nonvolatile memory unit. The ID for confirmation is compared with the ID for identification held by the ID holding means, and when they match, the correction value is read from the nonvolatile memory unit, and the reference voltage is read by the read correction value. Generating means for setting the reference voltage to a desired value.
[0034]
According to the present invention, a correction value can be recorded in a semiconductor device without using a fuse blow device, and furthermore, reading and setting of the correction value can be guaranteed to be performed correctly. Instead, it is possible to realize a semiconductor device having highly accurate reference voltage generating means.
[0035]
The test method of a semiconductor device according to the present invention includes: an ID holding unit for holding an identification ID which is a predetermined bit pattern; a reference voltage generating unit for changing and outputting a reference voltage by trimming; A non-volatile memory unit provided with a plurality of non-volatile memory cells to which the reference voltage is supplied from a generation unit, wherein the non-trimmed initial output voltage of the reference voltage generation unit is An initial voltage measurement step of measuring a value, and a correction value obtaining step of calculating a correction value for correcting a difference between the initial output voltage value obtained in the initial voltage measurement step and a desired reference voltage value. Irrespective of the value of the output voltage of the reference voltage generating means, a predetermined reference voltage is forcibly supplied from the outside to the nonvolatile memory unit. An external voltage application step, a confirmation ID having the same value as the identification ID held in the ID holding means, and the correction value obtained in the correction value acquisition step, A writing step of writing to the plurality of nonvolatile memory cells of the nonvolatile memory unit to which a predetermined reference voltage is supplied.
[0036]
According to the present invention, a correction value can be recorded in a semiconductor device without using a fuse blow device, and furthermore, reading and setting of the correction value can be guaranteed to be performed correctly. Instead, it is possible to realize a method of testing a semiconductor device having a highly accurate reference voltage generating means.
[0037]
Further, the reference voltage correcting method for a semiconductor device according to the present invention includes: an ID holding unit that holds an identification ID that is a predetermined bit pattern; a reference voltage generating unit that changes and outputs a reference voltage by trimming; A confirmation ID having the same value as the identification ID and a correction value for setting the reference voltage to a desired value are stored in some of the plurality of nonvolatile memory cells, and the reference value from the reference voltage generation means is stored in the nonvolatile memory cells. A reference voltage correction method for a semiconductor device, comprising: a non-volatile memory unit to which a voltage is supplied; a check ID reading step of reading the check ID from the non-volatile memory unit; An ID judging step of comparing the identified ID and the confirmation ID read in the confirmation ID reading step; When the comparison result in the fixed step is “mismatch”, a trimming value for changing the reference voltage output from the reference voltage generating means according to a predetermined search procedure is generated, and the trimming value is generated. Every time, the search result change step of changing the reference voltage supplied to the nonvolatile memory unit in the confirmation ID read step by the trimming value and the comparison result in the ID determination step are “match”. Reading the correction value from the nonvolatile memory unit, and setting the reference voltage of the reference voltage generation unit to a desired value based on the read correction value. It is characterized by.
[0038]
According to the present invention, a correction value can be recorded in a semiconductor device without using a fuse blow device, and furthermore, reading and setting of the correction value can be guaranteed to be performed correctly. Instead, it is possible to realize a reference voltage correction method for a semiconductor device having a highly accurate reference voltage generating means.
[0039]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention (hereinafter, referred to as embodiments) will be described with reference to the drawings.
[0040]
(1st Embodiment)
FIG. 1 is a circuit block diagram showing a semiconductor device 11 according to the first embodiment of the present invention. Here, the reference voltage generating circuit 15 and the portion related to its correction are mainly shown.
[0041]
The semiconductor device 11 according to the first embodiment of the present invention includes a Vcc terminal 12 to which external power is supplied, an internal power supply circuit 13 for generating a power supply voltage required in each circuit block in the semiconductor device 11, and a high precision. A reference voltage generation circuit 15 for generating the reference voltage 14, a reference voltage correction circuit 17 for generating a trimming signal 16 for changing the reference voltage 14, a test pad 18 for measuring the reference voltage 14, a predetermined bit pattern An ID holding circuit 19 for holding the ID for identification, a confirmation ID 20 having the same value as the ID for identification, and a correction value 21 for correcting the reference voltage 14 to a desired value are stored in the memory cell area 22. It has a nonvolatile memory unit 23 and a logic circuit unit 24 that performs necessary processing based on external specifications.
[0042]
The input of the internal power supply circuit 13 is connected to the Vcc terminal 12, and the output is connected to the power supply input of each circuit block including the logic circuit unit 24 in the semiconductor device 11.
[0043]
The output of the ID holding circuit 19 is connected to one input of the reference voltage correction circuit 17, and the other input of the reference voltage correction circuit 17 is connected to the output of the nonvolatile memory unit 23. Further, a trimming signal 16 which is an output of the reference voltage correction circuit 17 is connected to an input of the reference voltage generation circuit 15, and a read request signal 25 which is an output of the reference voltage correction circuit 17 is connected to one input of the nonvolatile memory unit 23. It is connected.
[0044]
Further, the reference voltage 14, which is the output of the reference voltage generation circuit 15, is connected to the other input of the nonvolatile memory unit 23 and the test pad 18.
[0045]
The input / output probe of a tester 26 placed outside the semiconductor device 11 is connected to the test pad 18.
[0046]
The internal power supply circuit 13 steps down or boosts the external power supply voltage supplied from the Vcc terminal 12 to generate a plurality of voltages necessary for each circuit operation in the semiconductor device 11, and the semiconductor device 11 including the logic circuit unit 24. Is supplied to each circuit block inside. The internal voltage generated here has a voltage variation of several% due to a variation in process parameters at the time of manufacturing a chip, a load variation accompanying a circuit operation, and the like. For this reason, the high-precision reference voltage 14 required for reading and writing of the nonvolatile memory unit 23 is generated by providing a dedicated reference voltage generating circuit 15 separately.
[0047]
The reference voltage generation circuit 15 is based on a band gap reference circuit (hereinafter, referred to as BGR) using an operational amplifier, and is designed so that the resistance ratio of the BGR can be changed by trimming. Then, based on the trimming signal 16 from the reference voltage correction circuit 17, the resistance ratio is changed to operate to change the voltage value of the reference voltage 14, which is the output.
[0048]
The ID holding circuit 19 is a ROM circuit in which an identification ID has been written at the time of manufacturing the chip of the semiconductor device 11, and is designed so that data cannot be changed after the chip is manufactured. At least in the same lot at the time of chip manufacture, all the semiconductor devices 11 hold the same identification ID.
[0049]
The identification ID is a plurality of bit strings of “0” or “1”, and is used as a reference value for determining whether the confirmation ID 20 has been correctly read from the nonvolatile memory unit 23. Therefore, a 16-bit long bit pattern in which “0” and “1” are randomly arranged is used for the identification ID.
[0050]
The ID holding circuit 19 supplies the held ID for identification to the reference voltage correction circuit 17.
[0051]
The non-volatile memory unit 23 includes a memory cell area 22 including a plurality of non-volatile memory cells storing the confirmation ID 20 and the correction value 21, a writing unit that writes arbitrary data to the memory cell area 22, And reading means for reading data from the storage 22. Further, the reference voltage 14 which is an output of the reference voltage generation circuit 15 is supplied to the nonvolatile memory unit 23.
[0052]
The reference voltage 14 is used for writing data to the memory cell region 22 and reading data from the memory cell region 22.
[0053]
Further, the nonvolatile memory unit 23 receives the read request signal 25 from the reference voltage correction circuit 17 and outputs the confirmation ID 20 or the correction value 21 to the reference voltage correction circuit 17 according to the read request signal 25.
[0054]
The reference voltage correction circuit 17 sequentially generates a trimming value according to a predetermined search procedure described later, and sequentially outputs a trimming signal 16 to the reference voltage generation circuit 15 based on the trimming value. Further, every time the trimming signal 16 is output, a read request signal 25 of the confirmation ID 20 is output to the nonvolatile memory unit 23.
[0055]
Then, the confirmation ID 20 read by the read request signal 25 is compared with the identification ID held by the ID holding circuit 19, and until the two match, the change of the trimming signal 16 and the non-volatile memory unit 23 are performed. The reading of the confirmation ID 20 from is repeated.
[0056]
If the confirmation ID 20 and the identification ID match, the reference voltage correction circuit 17 then outputs a read request signal 25 for the correction value 21 to the nonvolatile memory unit 23, and based on the read correction value 21, The trimming signal 16 is output to the reference voltage generation circuit 15.
[0057]
That is, the reference voltage correction circuit 17 uses the confirmation ID 20 and the identification ID to find a reference voltage 14 from which data can be correctly read from the nonvolatile memory unit 23. Then, the correction value 21 is read using the reference voltage 14, and the reference voltage 14 is finally corrected.
[0058]
Thus, it is guaranteed that the correction value 21 has been correctly read from the nonvolatile memory unit 23. In order to reliably achieve this object, the confirmation ID 20 and the correction value 21 are stored in mutually adjacent areas of the memory cell area 22.
[0059]
In this way, it can be expected that the correction value 21 is correctly read even if the process parameters vary during the manufacture of the chip of the semiconductor device 11.
[0060]
The reference voltage 14 finally corrected based on the correction value 21 is supplied to the non-volatile memory unit 23 and, at the same time, is output to the test pad 18 for measurement by the tester 26. The test pad 18 is also used for the purpose of forcibly supplying a desired voltage to the nonvolatile memory unit 23 irrespective of the voltage value of the reference voltage 14 output from the reference voltage generation circuit 15. This is used for writing the confirmation ID 20 and the correction value 21 to the nonvolatile memory unit 23.
[0061]
FIG. 2 is a circuit block diagram illustrating the reference voltage correction circuit 17 of the semiconductor device 11 according to the first embodiment of the present invention.
[0062]
The reference voltage correction circuit 17 of the semiconductor device 11 according to the first embodiment of the present invention receives the identification ID held by the ID holding circuit 19 and temporarily stores the identification ID, and receives the ID from the nonvolatile memory unit 23. A confirmation ID register 32 for temporarily storing the confirmation ID 20 thus obtained, a comparator 33 for comparing the identification ID and the confirmation ID 20 and judging the coincidence or non-coincidence, a trimming signal 16 based on the set value, and a reference voltage generating circuit 15. And a control circuit 36 for controlling the operation of each circuit block in the reference voltage correction circuit 17.
[0063]
The input of the ID register 31 is connected to the output of the ID holding circuit 19, and the output of the ID register 31 is connected to one input of the comparator 33. The other input of the comparator 33 is connected to the output of the confirmation ID register 32, and the output of the determination signal 37 of the comparator 33 is connected to the input of the control circuit 36.
[0064]
The output of the error signal 38 of the control circuit 36 is connected to the input of the error register 35, the output of the read request signal 25 of the control circuit 36 is connected to the input of the nonvolatile memory 23, and the output of the trimming value 39 of the control circuit 36 is 34 is connected to one input.
[0065]
The other input of the trimming circuit 34 and the input of the confirmation ID register 32 are connected to the output of the nonvolatile memory unit 23, and the output of the trimming signal 16 of the trimming circuit 34 is connected to the input of the reference voltage generating circuit 15. Although not shown in FIG. 2, a control signal for instructing each circuit block in the reference voltage correction circuit 17 to perform necessary processing is supplied from the control circuit 36 to each circuit block.
[0066]
Each of the ID register 31 and the confirmation ID register 32 is composed of 16 master-slave type D flip-flop circuits (hereinafter, referred to as D latches) in accordance with the bit length of the identification ID. Are connected to the comparator 33.
[0067]
The comparator 33 includes 16 EXNOR circuits (hereinafter, referred to as EXNOR) and one 16-input AND circuit (hereinafter, referred to as AND). One input of each EXNOR is an output of each D latch of the ID register 31. And the other input is connected to the output of each D latch of the confirmation ID register 32.
[0068]
The output of each EXNOR is connected to the input of AND, and the output of AND is connected as a determination signal 37 to the input of a control circuit 36.
[0069]
If each bit of the identification ID temporarily stored in the ID register 31 and each bit of the confirmation ID 20 temporarily stored in the confirmation ID register all match, the comparator 33 determines that the determination signal 37 is “OK”. The comparator 33 outputs “NG” (“0” in the positive logic) as the determination signal 37 if there is a different bit even in one bit.
[0070]
The error register 35 includes a plurality of D latches, receives an error signal 38 from the control circuit 36 and stores the error information when the correction value 21 cannot be correctly read from the nonvolatile memory unit 23, for example. .
[0071]
The trimming circuit 34 receives the trimming value 39 from the control circuit 36 or the correction value 21 from the nonvolatile memory unit 23, and decodes this into a trimming signal 16 for selecting the resistance ratio of the reference voltage generating circuit 15. Logic circuit.
[0072]
The control circuit 36 is a dedicated logic circuit that generates the read request signal 25, the trimming value 39, and the error signal 38 based on the determination signal 37 output from the comparator 33.
[0073]
Next, the function of the control circuit 36, that is, the method of correcting the reference voltage of the semiconductor device 11 according to the first embodiment of the present invention will be described.
[0074]
FIG. 3 is a flowchart illustrating a reference voltage correction method for the semiconductor device 11 according to the first embodiment of the present invention.
[0075]
As shown in the figure, the reference voltage correction method for the semiconductor device 11 according to the first embodiment of the present invention includes an initial setting step 51 for initializing the trimming circuit 34, the error register 35, and the ID register 31; ID reading step 52 for reading the checking ID 20 from the memory unit 23, ID determining step 53 for determining whether the read checking ID 20 is correct, and changing the search value for changing the reference voltage 14 according to a predetermined procedure. Step 54, a range determination step 55 for determining whether the change of the reference voltage 14 is within a predetermined search range, a correction value setting step 56 for finally correcting the reference voltage 14 based on the correction value 21, and error information And an error setting step 57 for storing
[0076]
In the initial setting step 51, the control circuit 36 adjusts the trimming value 39 so that the reference voltage 14, which is the output of the reference voltage generation circuit 15, becomes a desired design value Vt60 described later with the center value of the process parameter assumed at the time of design. It is generated and output to the trimming circuit 34. Further, it operates to set the identification ID held in the ID holding circuit 19 in the ID register 31 and reset the error register 35.
[0077]
Next, the reference voltage correction circuit 17 reads the confirmation ID 20 from the nonvolatile memory unit 23 while performing the read voltage search 50, compares the read ID 20 with the identification ID temporarily stored in the ID register 31, and compares the read ID 20 with the identification ID. Is read correctly.
[0078]
That is, first, in the confirmation ID reading step 52, the control circuit 36 outputs the read request signal 25 of the confirmation ID 20 to the nonvolatile memory unit 23. Then, an operation is performed such that the confirmation ID 20 read from the memory cell area 22 by the reading means of the nonvolatile memory unit 23 is temporarily stored in the confirmation ID register 32.
[0079]
Next, in the ID determination step 53, the control circuit 36 selects the search value change step 54 according to the determination signal 37 of the comparator 33 if this is “NG”, and if the determination signal 37 is “OK”, The correction value setting step 56 is selected.
[0080]
In the search value changing step 54, the control circuit 36 generates a new trimming value 39 according to a predetermined search procedure described later, and outputs this to the trimming circuit 34.
[0081]
Next, in a range determination step 55, the control circuit 36 determines whether the newly generated trimming value 39 does not exceed a predetermined search range. If the determination result is "OK", the confirmation ID readout is performed. The operation is performed so as to select the step 52 and repeat the read voltage search 50 again. If the result of the determination in the range determination step 55 is “NG”, the control circuit 36 selects the error setting step 57.
[0082]
In this read voltage search 50, the confirmation ID 20 is correctly read, and the determination result is “OK” in the ID determination step 53 and the correction value setting step 56 is selected, or the determination result in the range determination step 55 is “ NG "and the process is repeated until the error setting step 57 is selected.
[0083]
In the correction value setting step 56, the control circuit 36 outputs a read request signal 25 for the correction value 21 to the nonvolatile memory unit 23. Then, the correction value 21 read from the memory cell area 22 by the reading means of the nonvolatile memory unit 23 is set in the trimming circuit 34, and the reference voltage 14 output from the reference voltage generation circuit 15 is finally corrected. Works as follows.
[0084]
If the correction value 21 cannot be read out for some reason, for example, the nonvolatile memory unit 23 is physically destroyed due to a trouble at the time of manufacturing the chip of the semiconductor device 11, or the process is performed more than expected at the time of design. If the parameters vary and the confirmation ID 20 cannot be read correctly within the changeable range of the trimming value 39, the determination result becomes “NG” in the range determination step 55, and the error setting step 57 is selected.
[0085]
In the error setting step 57, the control circuit 36 outputs an error signal 38 to the error register 35, and operates so that the error register 35 temporarily stores the error information.
[0086]
In this way, even if the correction value 21 cannot be read correctly from the non-volatile memory unit 23 in the initial state immediately after the power is turned on due to a variation in the process parameters at the time of manufacturing the chip, the reference voltage of the semiconductor device 11 of the present invention is not changed. The correction circuit 17 can correct the reference voltage 14 output from the reference voltage generation circuit 15 to a desired design value Vt60.
[0087]
Next, a search procedure in the read voltage search 50 will be described.
[0088]
FIG. 4 is an image diagram showing a search procedure in the reference voltage correction method for the semiconductor device 11 according to the first embodiment of the present invention.
[0089]
FIG. 4A is an image diagram showing an output waveform of the reference voltage 14 according to the read voltage search 50, and FIG. 4B is a diagram showing a voltage value of the reference voltage 14 in an initial state immediately after power-on (hereinafter referred to as an initial voltage). 2 is a histogram showing the distribution of the value Vi). This histogram is created by extracting samples from a plurality of lots at the time of manufacturing a chip of the semiconductor device 11.
[0090]
In the initial state immediately after the power is turned on, as described above, the control circuit 36 trims the reference voltage 14 to the desired design value Vt60 shown in FIG. 4B with the center value of the process parameter assumed at the time of design. Generate the value 39. Hereinafter, this value is referred to as an initial trimming value. However, in the reference voltage generation circuit 15 of the actual semiconductor device 11, as shown in FIG. 4B, the reference voltage 14 is a desired value in the initial state immediately after the power is turned on due to the variation in the process parameters during chip manufacture. In many cases, it does not reach the design value Vt60.
[0091]
At the time of design, a certain degree of variation in process parameters is taken into consideration, and a design is made so that data can be normally read from the nonvolatile memory unit 23 even if the reference voltage 14 varies within the readable range ΔVt. In the device 11, there are not a few cases where the initial voltage value Vi of the reference voltage 14 is out of the readable range ΔVt.
[0092]
As shown in FIG. 4A, the search procedure in the reference voltage correction method for the semiconductor device 11 according to the first embodiment of the present invention is such that the reference voltage 14 is sequentially turned up and down from the initial voltage value Vi. This is a method to search by expanding.
[0093]
That is, first, the confirmation ID 20 is read and determined using the initial trimming value. If the result of this determination is "NG", then a trimming value 39 is generated and set so that the reference voltage 14 is higher than the initial voltage value Vi by the search voltage Va, and the confirmation ID 20 is read and determined. If the determination result is “NG”, the trimming value 39 is generated and set so that the reference voltage 14 is lower than the initial voltage value Vi by the search voltage Va, and the confirmation ID 20 is read and determined.
[0094]
If the result of this determination is "NG", then the trimming value 39 is generated and set so that the reference voltage 14 is twice the search voltage Va, ie, 2 Va, higher than the initial voltage value Vi. Is read and determined. If this determination result is “NG”, the trimming value 39 is further generated and set so that the reference voltage 14 is twice the search voltage Va, that is, 2 Va lower than the initial voltage value Vi. Read and judge.
[0095]
If the determination result is "NG", the trimming value 39 is generated and set so that the reference voltage 14 is higher than the initial voltage value Vi by three times the search voltage Va, that is, by 3 Va. Is read and determined. If the determination result is “NG”, the trimming value 39 is further generated and set so that the reference voltage 14 is lower than the initial voltage value Vi by three times the search voltage Va, that is, 3 Va, and the trimming value 39 is set. Read and judge.
[0096]
In this way, the read voltage search 50 is repeated while sequentially increasing the search voltage width until the confirmation ID 20 read from the nonvolatile memory unit 23 matches the identification ID temporarily stored in the ID register 31.
[0097]
In FIG. 4A, at the stage when the search voltage width is set to 3 Va, that is, at the read voltage of Vi + 3 Va, the confirmation ID 20 and the identification ID match, and the judgment is “OK”. The value of the search voltage Va is set to の of the readable range ΔVt in consideration of the search efficiency.
[0098]
Further, in consideration of a case where the nonvolatile memory unit 23 is physically damaged due to a trouble at the time of manufacturing the semiconductor device 11, the maximum value of the search voltage width is set to twice the readable range ΔVt. It is. In other words, when the search voltage width exceeds 2ΔVt, the determination result is “NG” in the range determination step 55 of FIG. 3, the error setting step 57 is selected, and the read voltage search 50 ends.
[0099]
Next, a test method of the semiconductor device 11 having the above-described configuration after manufacturing the chip will be described.
[0100]
FIG. 5 is a flowchart illustrating a test method of the semiconductor device 11 according to the first embodiment of the present invention. Here, the part mainly related to the correction of the reference voltage 14, which is the output of the reference voltage generation circuit 15, and the judgment on the quality of the semiconductor device 11 based on the corrected reference voltage 14 is shown.
[0101]
In the test method for the semiconductor device 11 according to the first embodiment of the present invention, an initial voltage measurement step 71 for measuring an initial voltage value Vi, and a difference between the initial voltage value Vi and a desired design value Vt60 is obtained as a correction value 21. A correction value obtaining step 72, an external voltage applying step 73 for forcibly supplying a predetermined reference voltage 14 from the outside to the nonvolatile memory unit 23, a writing step 74 for writing the correction value 21 and the confirmation ID 20 to the nonvolatile memory unit 23, A reference voltage correction step 75 for correcting the reference voltage 14 by the reference voltage correction circuit 17, an error determination step 76 for determining whether an error has occurred in the course of this correction, and a reference voltage measurement step 77 for measuring the corrected reference voltage 14. And a pass / fail determination step 78 for determining pass / fail of the semiconductor device 11 based on the measured reference voltage 14. It is made.
[0102]
The input / output probe of the tester 26 is connected to the test pad 18, and these series of steps are continuously executed.
[0103]
First, in the initial voltage measurement step 71, the tester 26 measures the reference voltage 14, which is the output of the reference voltage generation circuit 15, via the test pad 18, and stores it as the initial voltage value Vi.
[0104]
Next, in a correction value acquisition step 72, a difference between a desired design value Vt60 of the reference voltage 14 and this initial voltage value Vi is obtained by calculation and stored as a correction value 21.
[0105]
Next, in the external voltage application step 73, the tester 26 forcibly applies the predetermined reference voltage 14 to the nonvolatile memory unit 23 via the test pad 18 so that writing to the nonvolatile memory unit 23 can be performed normally. Supply. This is because the voltage value of the reference voltage 14 supplied from the reference voltage generation circuit 15 to the nonvolatile memory unit 23 is not guaranteed even in the write operation in the initial state immediately after the power is turned on, as in the above-described read operation. is there.
[0106]
The test pad 18 is also connected to the output of the reference voltage generation circuit 15, but does not pose a problem because the current supply capability of the tester 26 is sufficiently large.
[0107]
Next, in a writing step 74, the tester 26 stores the correction value 21 obtained in the correction value obtaining step 72 and the confirmation ID 20 having the same value as the identification ID held in the ID holding circuit 19 in a nonvolatile manner. The writing unit of the memory unit 23 operates to write data into the memory cell area 22.
[0108]
Next, in a reference voltage correction step 75, the tester 26 operates so that the reference voltage correction circuit 17 corrects the reference voltage 14 according to the above-described reference voltage correction method based on the correction value 21 written in the writing step 74. .
[0109]
Next, in an error determination step 76, the tester 26 reads out the error information set in the error register 35 by the control circuit 36 by a predetermined method, and determines whether there is a fatal error. If a fatal error has occurred in the reference voltage correction step 75 (“NG”), the tester 26 records the semiconductor device 11 as a defective product without executing the subsequent test steps, End the test.
[0110]
If there is no fatal error (“OK”), in a reference voltage measurement step 77, the tester 26 measures the reference voltage 14 corrected in the reference voltage correction step 75 via the test pad 18.
[0111]
Finally, in a pass / fail determination step 78, the tester 26 determines whether the reference voltage 14 measured in the reference voltage measurement step 77 falls within a predetermined allowable error range with respect to a desired design value Vt60. If it is within the allowable range (“OK”), the semiconductor device 11 is recorded as a non-defective product, otherwise (“NG”), the semiconductor device 11 is recorded as a defective product, and the test ends. I do.
[0112]
The allowable error range is set to a voltage value corresponding to twice the minimum setting unit of the trimming value 39. This is because trimming is performed discretely in the above-described circuit configuration.
[0113]
According to the first embodiment, the correction value 21 can be recorded in the semiconductor device 11 without using a fuse blow device, and further, it is guaranteed that the correction value 21 is correctly read and set. The semiconductor device 11 having the highly accurate reference voltage generation circuit 15 can be realized without lowering the test efficiency at the time of manufacturing.
[0114]
In the first embodiment, the bit pattern of the identification ID is a random array of “0” and “1” in consideration of the character as a reference value, but the present invention is not limited to this. In principle, anything can be used. Although the bit length of the identification ID is 16 bits, the present invention is not limited to this.
[0115]
In addition, although the confirmation ID 20 and the correction value 21 are stored in areas close to each other, the present invention is not limited to this, and in principle, the nonvolatile memory unit to which the same reference voltage 14 is supplied. If it is stored in 23, there is no problem.
[0116]
Further, the ID register 31 and the confirmation ID register 32 are not essential, and the reference voltage correction circuit 17 is configured so that the comparator 33 directly receives the signals from the ID holding circuit 19 and the nonvolatile memory unit 23 and makes a comparison judgment. You can also.
[0117]
Further, the control circuit 36 is provided as a dedicated circuit in the reference voltage correction circuit 17, but the present invention is not limited to this. The same function as the above-described control circuit 36 is provided by the CPU and its microcode. It is also possible to implement using. In this case, not only the control circuit 36 but also the entire reference voltage correction circuit 17 can be replaced. In particular, in a non-volatile memory embedded IC having a general-purpose CPU, the general-purpose CPU can be used for this purpose, so that the circuit size and the manufacturing cost of the semiconductor device 11 of the present invention can be reduced.
[0118]
Further, the test pad 18 is used for both measurement of the reference voltage 14 and forcible application of an external voltage to the nonvolatile memory unit 23. However, a switching element may be provided as necessary to be electrically switched. .
[0119]
Furthermore, in the read voltage search 50, the search voltage Va is set to 1/2 of the readable range ΔVt, and the maximum value of the search voltage width is set to twice the ΔVt. However, the present invention is not limited to this. The optimum value can be set based on the assumed readable range ΔVt and the expected distribution of the initial voltage value Vi.
[0120]
Also, in the read voltage search 50, when the generated trimming value 39 exceeds the maximum value of the search voltage width, the error setting step 57 is selected in the range determination step 55, but the present invention is not limited to this. The error setting step 57 may be selected when the number of generations of the trimming value 39 exceeds a predetermined value.
[0121]
Further, in the above-described first embodiment, the error determination step 76 is used to improve the test efficiency, but this is not essential in the present invention. When a fatal error occurs, the reference voltage 14, which is the output of the reference voltage generating circuit 15, deviates greatly from the desired design value Vt60 even after the correction. It is.
[0122]
(Second embodiment)
FIG. 6 is a circuit block diagram showing the reference voltage correction circuit 100 of the semiconductor device 11 according to the second embodiment of the present invention.
[0123]
The configuration of the semiconductor device 11 using the reference voltage correction circuit 100 of the present embodiment, and the configuration, function, and operation of each circuit block in the semiconductor device 11 excluding the reference voltage correction circuit 100 of the present embodiment are described below. This is the same as the first embodiment.
[0124]
The reference voltage correction circuit 100 of the semiconductor device 11 according to the second embodiment of the present invention includes an ID register 101 for temporarily storing an identification ID, and a confirmation ID for temporarily storing a confirmation ID 20 received from the nonvolatile memory unit 23. A register 102; a comparator 103 for comparing the identification ID and the confirmation ID 20 to determine whether they match or not match; a trimming circuit 104 for outputting a trimming signal 16 based on a set value; an error register 105 for storing an error; It has an HL determination circuit 107 that outputs an HL signal 106 indicating whether or not 14 is higher or lower than a desired design value Vt60, and a control circuit 108 that controls the operation of each circuit block in the reference voltage correction circuit 100.
[0125]
The input of the ID register 101 is connected to the output of the ID holding circuit 19, and the output of the ID register 101 is connected to one input of the comparator 103. The other input of the comparator 103 is connected to one output of the confirmation ID register 102, and the judgment signal 109, which is the output of the comparator 103, is connected to one input of the control circuit 108.
[0126]
The other input of the control circuit 108 is connected to the HL signal 106 which is the output of the HL determination circuit 107, and the error signal 110 which is the output of the control circuit 108 is connected to the input of the error register 105. The read request signal 25 is connected to the input of the nonvolatile memory unit 23, and the trimming value 111, which is also the output of the control circuit 108, is connected to one input of the trimming circuit 104.
[0127]
The other input of the trimming circuit 104 and the input of the confirmation ID register 102 are connected to the output of the nonvolatile memory unit 23, and the trimming signal 16 which is the output of the trimming circuit 104 is connected to the input of the reference voltage generating circuit 15. .
[0128]
The input of the HL determination circuit 107 is connected to the other output of the confirmation ID register 102, and the HL signal 106, which is the output of the HL determination circuit 107, is connected to the other input of the control circuit 108. Although not shown in FIG. 6, a control signal for instructing each circuit block in the reference voltage correction circuit 100 to perform necessary processing is supplied from the control circuit 108 to each circuit block.
[0129]
The configurations and functions of the ID register 101, the comparator 103, the trimming circuit 104, and the error register 105 are the same as in the first embodiment.
[0130]
The confirmation ID register 102 has 16 D-latches as in the first embodiment, and is configured to function as a shift register. That is, the output of a 2-input selection circuit (hereinafter referred to as a selector) is connected to the input of each D latch, the output of the nonvolatile memory unit 23 is connected to one input of each selector, and the other of the selectors Is connected to the output of the adjacent D latch.
[0131]
In such a configuration, when the selector is set to a state of selecting the output of the adjacent D latch and a clock signal is input to the clock input of the D latch, the 16-bit data in the D latch is converted into a parallel-serial signal. In this way, they can be sequentially output in synchronization with the clock signal.
[0132]
Thus, the confirmation ID register 102 outputs the confirmation ID 20 to the HL determination circuit 107. However, the output to the HL determination circuit 107 is performed after the comparison between the identification ID and the confirmation ID 20 in the comparator 103 ends and the determination signal 109 is output to the control circuit 108.
[0133]
The HL determination circuit 107 includes a 0-counter that counts the number of “0” bits of the confirmation ID 20 sent from the confirmation ID register 102, a 1-counter that also counts the number of “1” bits, And a comparator for comparing the magnitude of the counting result. The inputs of the 0-counter and 1-counter are both connected to the output of the confirmation ID register 102, and their outputs are respectively connected to the input of the comparator, and the output of the comparator is connected to the control circuit 108 as the HL signal 106. ing.
[0134]
When the voltage value of the reference voltage 14 output from the reference voltage generation circuit 15 is high, the HL determination circuit 107 erroneously reads that the “1” bit of the data read from the memory cell area 22 of the nonvolatile memory unit 23 is “0”. On the other hand, the fact that when the voltage value of the reference voltage 14 is low, the probability that the "1" bit is erroneously read as "0" increases.
[0135]
That is, the reference voltage 14 is used as a criterion for determining “0” or “1” in reading data from the memory cell region 22. When the reference voltage 14 is higher than the upper limit of the readable range ΔVt, the reference voltage 14 The data written as "1" is determined to be lower than the reference voltage 14, and there is a possibility of erroneous reading.
[0136]
In the second embodiment, the identification ID and the confirmation ID 20 written in the memory cell area 22 have the same bit pattern in which the same number of “0” and “1” bits are randomly arranged. Therefore, if the number of “0” bits of the read confirmation ID 20 is larger than the number of “1” in the HL determination circuit 107, it is estimated that the reference voltage 14 is higher than the upper limit of the readable range ΔVt. it can. Then, at this time, the HL determination circuit 107 outputs “High” as the HL signal 106 to the control circuit 108.
[0137]
Conversely, if the reference voltage 14 is lower than the lower limit of the readable range ΔVt, data written as “0” in the memory cell region 22 may be determined to be higher than the reference voltage 14. Therefore, if the number of “1” bits of the read confirmation ID 20 is larger than the number of “0” bits in the HL determination circuit 107, it is estimated that the reference voltage 14 is lower than the lower limit of the readable range ΔVt. it can. At this time, the HL determination circuit 107 outputs “Low” as the HL signal 106 to the control circuit 108.
[0138]
If the reference voltage 14 is within the readable range ΔVt, the HL signal 106 is not used by the control circuit 108 because the confirmation ID 20 has been correctly read.
[0139]
As in the first embodiment, the control circuit 108 outputs a read signal 25, a trimming value 111, and an error based on the determination signal 109 output from the comparator 103 and the HL signal 106 output from the HL determination circuit 107. This is a dedicated logic circuit that generates the signal 110.
[0140]
Next, the function of the control circuit 108, that is, the method of correcting the reference voltage of the semiconductor device 11 according to the second embodiment of the present invention will be described.
[0141]
FIG. 7 is a flowchart illustrating a reference voltage correction method for the semiconductor device 11 according to the second embodiment of the present invention.
[0142]
The difference from the first embodiment is that in the read voltage search 120, the search value is changed based on not only the determination signal 109 output from the comparator 103 but also the HL signal 106 output from the HL determination circuit 107. It is that you are.
[0143]
As shown in the figure, the reference voltage correction method for the semiconductor device 11 according to the second embodiment of the present invention includes an initial setting step 121 for initializing the trimming circuit 104, the error register 105, and the ID register 101, Confirmation ID reading step 122 for reading the confirmation ID 20 from the memory unit 23, an ID determination step 123 for determining whether the read confirmation ID 20 is correct, a search value change for changing the reference voltage 14 according to a predetermined procedure. Step 124, range determination step 125 for determining whether the change of reference voltage 14 is within a predetermined search range, correction value setting step 126 for finally correcting reference voltage 14 based on correction value 21, and error information And an error setting step 127 for storing.
[0144]
Steps other than the search value changing step 124 are the same as in the first embodiment.
[0145]
The search value change step 124 is an HL determination step 128 for determining whether the reference voltage 14 output from the reference voltage generation circuit 15 is higher or lower than a predetermined voltage value, and downward correction for lowering the search voltage value to the present value. Step 129 and an upward correction step 130 for making the search voltage value higher than the current value.
[0146]
The HL determination step 128 is selected when the determination result in the ID determination step 123 is “NG”. In the HL determination step 128, the control circuit 108 selects the lower correction step 129 when the HL signal 106 output from the HL determination circuit 107 is “High”, and selects the upper correction step when the HL signal 106 is “Low”. Operate to select 130.
[0147]
In a downward correction step 129, the control circuit 108 generates a trimming value 111 so that the reference voltage 14 is lower than the current value by a predetermined search voltage, and outputs this to the trimming circuit 104.
[0148]
In the upward correction step 130, the control circuit 108 generates a trimming value 111 so that the reference voltage 14 is higher than the current value by a predetermined search voltage, and outputs this to the trimming circuit 104.
[0149]
When the downward correction step 129 or the upward correction step 130 ends, a range determination step 125 is executed.
[0150]
In this way, the read voltage search 120 can be efficiently performed by using the HL signal 106.
[0151]
Next, a search procedure in the read voltage search 120 will be described.
[0152]
FIGS. 8 and 9 are image diagrams showing a search procedure in the reference voltage correction method for the semiconductor device 11 according to the second embodiment of the present invention.
[0153]
FIG. 8A is an image diagram showing a first output waveform of the reference voltage 14 accompanying execution of the read voltage search 120, and FIG. 8B is an image diagram showing a second output waveform of the reference voltage 14 similarly. 9 is an image diagram showing a third output waveform of the reference voltage 14 in the same manner.
[0154]
FIG. 8A shows a search procedure when the initial voltage value Vi immediately after power-on is lower than the lower limit of the readable range ΔVt. That is, first, the confirmation ID 20 is read and determined using the initial trimming value. In the case of FIG. 8A, since the determination result in the ID determination step 123 is "NG" and the determination result in the HL determination step 128 is "Low", the reference voltage 14 is trimmed so as to be higher by the search voltage Va. The value 111 is generated and set, and the confirmation ID reading step 122 is executed again.
[0155]
Since the search voltage Va is set to の of the readable range ΔVt, there is no danger that the reference voltage 14 jumps over the readable range ΔVt by one addition of the search voltage Va. Therefore, in FIG. 8A, the addition of the search voltage Va to the reference voltage 14 is repeated until the result of the determination in the ID determination step 123 becomes “OK”.
[0156]
Similarly, FIG. 8B shows a search procedure when the initial voltage value Vi immediately after power-on is higher than the upper limit of the readable range ΔVt. That is, first, the confirmation ID 20 is read and determined using the initial trimming value. In the case of FIG. 8B, since the determination result in the ID determination step 123 is “NG” and the determination result in the HL determination step 128 is “High”, the reference voltage 14 is trimmed so as to be lower by the search voltage Va. The value 111 is generated and set, and the confirmation ID reading step 122 is executed again.
[0157]
Since the search voltage Va is set to の of the readable range ΔVt, the subtraction of the search voltage Va from the reference voltage 14 is repeated until the determination result in the ID determination step 123 becomes “OK”.
[0158]
FIG. 9 shows a method in which a so-called binary search technique is incorporated in the read voltage search 120. That is, first, the confirmation ID 20 is read and determined using the initial trimming value. In the case of FIG. 9, the determination result in the ID determination step 123 is “NG” and the determination result in the HL determination step 128 is “Low”, so that the reference voltage 14 is increased by the maximum voltage search width, that is, 16 Va. The trimming value 111 is generated and set, and the confirmation ID reading step 122 is executed again.
[0159]
Next, each time the lower correction step 129 or the upper correction step 130 is selected in the search value change step 124 according to the binary search method, the trimming value 111 is generated and set while the voltage search width is reduced by half. repeat.
[0160]
In this way, the number of repetitions in read voltage search 120 can be significantly reduced. In particular, the effect is great when the initial voltage value Vi deviates greatly from the desired design value Vt60 and the readable range ΔVt is narrow.
[0161]
The test method of the semiconductor device 11 according to the second embodiment having the above-described configuration after manufacturing the chip is the same as that of the first embodiment (FIG. 5).
[0162]
According to the second embodiment, in addition to the effects described in the first embodiment, the number of repetitions in the read voltage search 120 can be reduced, so that the time required in the test process at the time of manufacturing the semiconductor device 11 is significantly reduced. Thus, cost reduction can be realized.
[0163]
In the above-described second embodiment, the bit pattern of the identification ID is a random arrangement of “0” and “1”, and the number of bits of “0” and the number of bits of “1” are the same. However, the present invention is not limited to this, and in principle, any ratio between the number of bits “0” and the number of bits “1” can be used. Although the bit length of the identification ID is 16 bits, the present invention is not limited to this.
[0164]
Further, similarly to the first embodiment, the ID register 101 and the confirmation ID register 102 are not essential.
[0165]
Further, similarly to the first embodiment, the control circuit 108 can be implemented using a CPU and its microcode, and the HL determination circuit 107 can be added thereto.
[0166]
Further, the search voltage Va and the maximum value of the search voltage width are also set to optimal values based on the readable range ΔVt assumed at the time of design and the expected distribution of the initial voltage value Vi, as in the first embodiment. Can be set.
[0167]
(Third embodiment)
FIG. 10 is a circuit block diagram showing a semiconductor device 201 according to the third embodiment of the present invention. Here, similarly to the first embodiment, mainly the reference voltage generating circuit and the part related to the correction thereof are shown.
[0168]
The semiconductor device 201 according to the third embodiment of the present invention includes a Vcc terminal 202 to which external power is supplied, an internal power supply circuit 203 for generating a power supply voltage required in each circuit block in the semiconductor device 201, and a high precision. A reference voltage generation circuit A205 for generating a reference voltage A204, a reference voltage generation circuit B207 for generating a highly accurate reference voltage B206, a trimming signal A208 for changing the reference voltage A204, and a trimming signal B209 for changing the reference voltage B206. , A reference voltage measuring pad 211 for measuring the reference voltage A204, an ID holding circuit 212 for holding an identification ID which is a predetermined bit pattern, and the same value as the identification ID. Corrects the confirmation ID 213 and the reference voltage A204 to have desired values. Memory section B216 storing the correction value 214 for the memory cell area B215, a nonvolatile memory section A218 having a memory cell area A217 comprising a plurality of nonvolatile multi-level cells, and a nonvolatile memory section B216 from outside. It has an external voltage application pad 219 for forcibly supplying a predetermined external voltage, and a logic circuit unit 220 for performing necessary processing based on external specifications.
[0169]
The input of the internal power supply circuit 203 is connected to the Vcc terminal 202, and the output is connected to the power supply input of each circuit block including the logic circuit section 220 in the semiconductor device 201. The output of the ID holding circuit 212 is connected to one input of the reference voltage correction circuit 210.
[0170]
The other input of the reference voltage correction circuit 210 is connected to the output of the nonvolatile memory unit B216, and the trimming signal A208, which is the output of the reference voltage correction circuit 210, is connected to the input of the reference voltage generation circuit A205. A trimming signal B209 output from 210 is connected to an input of a reference voltage generation circuit B207. The read request signal 221 output from the reference voltage correction circuit 210 is connected to one input of the nonvolatile memory unit B216.
[0171]
The reference voltage A204, which is the output of the reference voltage generation circuit A205, is connected to the input of the nonvolatile memory unit A218 and the test pad 211.
[0172]
The reference voltage B206, which is the output of the reference voltage generation circuit B207, is connected to the other input of the nonvolatile memory unit B216 and the external voltage application pad 219.
[0173]
The configuration, function, and operation of each circuit block are the same as in the first embodiment.
[0174]
The semiconductor device 201 according to the third embodiment is different from the first embodiment in that a nonvolatile memory unit A218 including a memory cell area A217 composed of multi-valued memory cells used for normal data storage, and a confirmation ID 213. And a non-volatile memory section B216 for initial setting values for storing correction values 214 and the like, and corresponding reference voltage generating circuits A205 and B207.
[0175]
That is, the non-volatile memory unit A218 has a memory cell area A217 composed of a plurality of non-volatile multi-valued memory cells, and means for writing arbitrary data into the memory cell area A217 and reading means for reading data from the memory cell area A217. And The reference voltage A204, which is the output of the reference voltage generation circuit A205, is supplied to the nonvolatile memory unit A218.
[0176]
A trimming signal A208 is supplied from the reference voltage correction circuit 210 to the reference voltage generation circuit A205. The trimming signal A208 is generated based on a correction value 214 read from the nonvolatile memory unit B216 according to a reference voltage correction method described later. The reference voltage A204 output from the reference voltage generation circuit A205 is used for writing data to the memory cell area A217 and reading data from the memory cell area A217.
[0177]
The nonvolatile memory unit B216 includes a memory cell area B215 including a plurality of nonvolatile memory cells storing the confirmation ID 213 and the correction value 214, a writing unit that writes arbitrary data to the memory cell area B215, and a memory cell area. Reading means for reading data from B215. The reference voltage B206, which is the output of the reference voltage generation circuit B207, is supplied to the nonvolatile memory unit B216.
[0178]
The confirmation ID 213 and the correction value 214 are stored in areas close to each other, as in the first embodiment.
[0179]
The reference voltage generation circuit B207 is supplied with a trimming signal B209 by the reference voltage correction circuit 210. The trimming signal B209 is generated by the reference voltage correction circuit 210 according to a reference voltage correction method described later. The reference voltage B206 output from the reference voltage generation circuit B207 is used for writing data to the memory cell region B215 and reading data from the memory cell region B215.
[0180]
Further, the nonvolatile memory unit B 216 outputs the confirmation ID 213 or the correction value 214 to the reference voltage correction circuit 210 according to the read request signal 221 from the reference voltage correction circuit 210.
[0181]
Similar to the first embodiment, the reference voltage correction circuit 210 sequentially generates a trimming value according to a predetermined search procedure, and sequentially outputs a trimming signal B209 to the reference voltage generation circuit B207 based on the trimming value. Then, every time the trimming signal B209 is output, the read request signal 221 of the confirmation ID 213 is output to the nonvolatile memory unit B216.
[0182]
Further, the confirmation ID 213 read by the read request signal 221 is compared with the identification ID held by the ID holding circuit 212, and the above-described change of the trimming signal B209 and the non-volatile memory unit B216 are performed until they match. The reading of the confirmation ID 213 from is repeated.
[0183]
If the confirmation ID 213 and the identification ID match, the reference voltage correction circuit 210 then outputs a read request signal 221 for the correction value 214 to the nonvolatile memory unit B 216, and based on the read correction value 214 The trimming signal A208 is output to the reference voltage generation circuit A205.
[0184]
The reference voltage A204 finally corrected based on the correction value 214 in this manner is supplied to the nonvolatile memory unit A218 and, at the same time, is output to the reference voltage measurement pad 211 for measurement by the tester 222. .
[0185]
The external voltage application pad 219 is used for the purpose of forcibly supplying a predetermined voltage from the outside to the nonvolatile memory unit B216 irrespective of the voltage value of the reference voltage B206 output from the reference voltage generation circuit B207.
[0186]
FIG. 11 is a circuit block diagram showing the reference voltage correction circuit 210 of the semiconductor device 201 according to the third embodiment of the present invention.
[0187]
The reference voltage correction circuit 210 of the semiconductor device 201 according to the third embodiment of the present invention includes an ID register 231 for temporarily storing the identification ID, and a confirmation ID for temporarily storing the confirmation ID 213 received from the nonvolatile memory unit B216. A register 232, a comparator 233 for comparing the identification ID and the confirmation ID 213 to determine whether they match or mismatch, a trimming circuit A234 that outputs a trimming signal A208 based on the set value, and a trimming signal B209 based on the set value. , An error register 236 for storing an error, and a control circuit 237 for controlling the operation of each circuit block in the reference voltage correction circuit 210.
[0188]
The input of the ID register 231 is connected to the output of the ID holding circuit 212, and the output of the ID register 231 is connected to one input of the comparator 233. The other input of the comparator 233 is connected to the output of the confirmation ID register 232, and the judgment signal 238, which is the output of the comparator 233, is connected to the input of the control circuit 237.
[0189]
An error signal 239 output from the control circuit 237 is connected to an input of an error register 236, and a read request signal 221 also output from the control circuit 237 is connected to an input of the nonvolatile memory unit B216.
[0190]
Further, a trimming value A240 output from the control circuit 237 is connected to one input of a trimming circuit A234, and a trimming value B241 output from the control circuit 237 is connected to an input of the trimming circuit B235.
[0191]
The other input of the trimming circuit A234 and the input of the confirmation ID register 232 are connected to the output of the nonvolatile memory unit B216, and the trimming signal A208, which is the output of the trimming circuit A234, is connected to the input of the reference voltage generating circuit A205. The trimming signal B209, which is the output of the circuit B235, is connected to the input of the reference voltage generation circuit B207. Although not shown in FIG. 11, a control signal for instructing each circuit block in the reference voltage correction circuit 210 to perform necessary processing is supplied from the control circuit 237 to each circuit block.
[0192]
The configuration, function, and operation of each circuit block except the control circuit 237 are the same as those of the first embodiment.
[0193]
This embodiment is different from the first embodiment in that the semiconductor device 201 has two reference voltage generation circuits A205 and B207, and the reference voltage correction circuit 210 has two trimming circuits A234 and B235. That is.
[0194]
The trimming circuit A234 receives the correction value 214 from the nonvolatile memory unit B216 or the trimming value A240 from the control circuit 237, and decodes this into a trimming signal A208 for selecting a resistance ratio of the reference voltage generating circuit A205. Circuit. A reference voltage A204 used in the nonvolatile memory unit A218 is set by the trimming signal A208.
[0195]
The trimming circuit B235 is a logic circuit that receives the trimming value B241 from the control circuit 237 and decodes the trimming value B241 into a trimming signal B209 for selecting the resistance ratio of the reference voltage generation circuit B207. The trimming value B241 is sequentially generated by the control circuit 237 according to a predetermined procedure.
[0196]
The function of the control circuit 237, that is, the method of correcting the reference voltage of the semiconductor device 201 according to the third embodiment of the present invention is the same as that of the first embodiment (FIG. 3).
[0197]
The difference from the first embodiment is that the read voltage search 50 is performed on the non-volatile memory unit B216 via the trimming circuit B235 and the reference voltage generation circuit B207, and the final value in the correction value setting step 56. The correction is performed on the nonvolatile memory unit A218 via the trimming circuit A234 and the reference voltage generating circuit A205.
[0198]
The non-volatile memory unit A218 uses a multi-level memory cell, and requires a higher-precision reference voltage A204 for reading and writing. By separating the nonvolatile memory unit B216 having the correction value 214 from the nonvolatile memory unit A218 and using normal nonvolatile memory cells for the nonvolatile memory unit B216, the reference voltage A204 can be increased without increasing the number of searches. It becomes possible to correct with accuracy.
[0199]
The search procedure in the read voltage search 50 of the semiconductor device 201 is the same as in the first embodiment (FIG. 4). The difference from the first embodiment is that the search is performed on the nonvolatile memory unit B216 as described above.
[0200]
The test method of the semiconductor device 201 after manufacturing the chip is the same as that of the first embodiment (FIG. 5). The difference from the first embodiment is that the writing of the confirmation ID 213 and the correction value 214 in the writing step 74 is performed on the non-volatile memory B216, and that the initial voltage measurement step 71 and the reference voltage measurement step 77 The voltage measurement by the tester 222 is performed via the reference voltage measurement pad 211, and the forced supply of the external voltage in the external voltage application step 73 is performed via the external voltage application pad 219. What is done for
[0201]
According to the third embodiment, not only the same effects as in the first embodiment can be obtained, but also the nonvolatile memory unit A218 which requires a higher-precision reference voltage A204 such as a multi-valued memory cell. However, the reference voltage A204 can be corrected efficiently.
[0202]
In the above-described third embodiment, the nonvolatile memory unit A218 is a single circuit block. However, the present invention is not limited to this, and the nonvolatile memory unit A218 may be divided into a plurality of circuit blocks. . Further, it is also possible to provide a reference voltage generating circuit A205 corresponding to each of the plurality of nonvolatile memory units A218, and set the correction value 214 separately.
[0203]
Further, the non-volatile memory unit B216 is used for initial setting values for storing the confirmation ID 213, the correction value 214, and the like. However, the present invention is not limited to this, and normal data is stored in the non-volatile memory unit B216. Can be stored, and the reference voltage generation circuit B207 is also corrected in the correction value setting step 56.
[0204]
(Fourth embodiment)
FIG. 12 is a circuit block diagram illustrating a reference voltage correction circuit 270 of the semiconductor device 201 according to the fourth embodiment of the present invention.
[0205]
The configuration of the semiconductor device 201 using the reference voltage correction circuit 270 of the present embodiment, and the function and operation of each circuit block in the semiconductor device 201 excluding the reference voltage correction circuit 270 of the present embodiment are the same as those of the third embodiment. Same as the form.
[0206]
The reference voltage correction circuit 270 of the semiconductor device 201 of the present invention includes an ID register 271 for temporarily storing an identification ID, a confirmation ID register 272 for temporarily storing a confirmation ID 213 received from the nonvolatile memory unit B216, and an identification ID. A comparator 273 that compares the confirmation IDs 213 to determine whether they match or not, a trimming circuit A274 that outputs a trimming signal A208 based on the set value, a trimming circuit B275 that outputs a trimming signal B209 based on the set value, The error register 276 for storing an error, the HL determination circuit 278 for outputting an HL signal 277 indicating whether the reference voltage B206 is higher or lower than a desired design value Vt60, and the operation of each circuit block in the reference voltage correction circuit 270 are shown. It has a control circuit 279 for controlling.
[0207]
The input of the ID register 271 is connected to the output of the ID holding circuit 212, and the output of the ID register 271 is connected to one input of the comparator 273. The other input of the comparator 273 is connected to one output of the confirmation ID register 272, and the judgment signal 280 which is the output of the comparator 273 is connected to one input of the control circuit 279.
[0208]
The other input of the control circuit 279 is connected to the HL signal 277 which is the output of the HL determination circuit 278, and the error signal 281 which is the output of the control circuit 279 is connected to the input of the error register 276. The read request signal 221 is connected to the input of the nonvolatile memory unit B216.
[0209]
Further, a trimming value A282 which is an output of the control circuit 279 is connected to one input of a trimming circuit A274, and a trimming value B283 which is an output of the control circuit 279 is also connected to an input of the trimming circuit B275.
[0210]
The other input of the trimming circuit A 274 and the input of the confirmation ID register 272 are connected to the output of the nonvolatile memory unit B 216, and the trimming signal A 208, which is the output of the trimming circuit A 274, is connected to the input of the reference voltage generating circuit A 205. The trimming signal B209, which is the output of the circuit B275, is connected to the input of the reference voltage generation circuit B207.
[0211]
The input of the HL determination circuit 278 is connected to the other output of the confirmation ID register 272, and the HL signal 277 output from the HL determination circuit 278 is connected to the other input of the control circuit 279. Although not shown in FIG. 12, a control signal for instructing each circuit block in the reference voltage correction circuit 270 to perform necessary processing is supplied from the control circuit 279 to each circuit block.
[0212]
The configurations and functions of the ID register 271, the comparator 273, the trimming circuit A 274, the trimming circuit B 275, and the error register 276 are the same as those in the third embodiment.
[0213]
The confirmation ID register 273 is also configured to function as a shift register, as in the second embodiment, and outputs the retained confirmation ID 213 to the HL determination circuit 278.
[0214]
Further, similarly to the second embodiment, the HL determination circuit 278 outputs an HL determination signal 277 indicating whether the reference voltage B206 output from the reference voltage generation circuit B207 is higher or lower than a desired design value Vt60, to the control circuit 279. Output to
[0215]
In the present embodiment, similarly to the second embodiment, an HL determination circuit 278 is added to the reference voltage correction circuit 270 of the third embodiment, and the HL determination signal is output in the read voltage search 120 of the nonvolatile memory unit B216. 277 is used.
[0216]
The function of the control circuit 279, that is, the reference voltage correction method for the semiconductor device 201 and the search procedure used in the read voltage search 120 are the same as those in the second embodiment (FIGS. 7-9).
[0219]
The difference from the second embodiment is that the read voltage search 120 is performed on the non-volatile memory unit B216 via the trimming circuit B275 and the reference voltage generation circuit B207, and the final value in the correction value setting step 12 is changed. The correction is performed on the nonvolatile memory unit A218 via the trimming circuit A274 and the reference voltage generating circuit A205.
[0218]
The test method of the semiconductor device 201 according to the fourth embodiment after manufacturing the chip is the same as that of the third embodiment.
[0219]
According to the fourth embodiment, in addition to the effects described in the third embodiment, the number of repetitions in the read voltage search 120 can be greatly reduced. Time and cost can be reduced.
[0220]
【The invention's effect】
As described above, according to the present invention, a correction value of a reference voltage can be recorded in a semiconductor device without using a fuse blow device, and it is guaranteed that reading and setting of the correction value are performed correctly. A semiconductor device having a highly accurate reference voltage generation circuit, a test method thereof, and a reference voltage correction method thereof can be realized without reducing test efficiency at the time.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram showing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a circuit block diagram showing a reference voltage correction circuit of the semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a flowchart illustrating a reference voltage correction method for the semiconductor device according to the first embodiment of the present invention.
FIG. 4 is an image diagram showing a search procedure in the reference voltage correction method for the semiconductor device according to the first embodiment of the present invention.
FIG. 5 is a flowchart illustrating a test method of the semiconductor device according to the first embodiment of the present invention.
FIG. 6 is a circuit block diagram showing a reference voltage correction circuit of a semiconductor device according to a second embodiment of the present invention.
FIG. 7 is a flowchart illustrating a reference voltage correction method for a semiconductor device according to a second embodiment of the present invention.
FIG. 8 is an image diagram showing a search procedure in a reference voltage correction method for a semiconductor device according to a second embodiment of the present invention.
FIG. 9 is an image diagram showing a search procedure in a reference voltage correction method for a semiconductor device according to a second embodiment of the present invention.
FIG. 10 is a circuit block diagram showing a semiconductor device according to a third embodiment of the present invention.
FIG. 11 is a circuit block diagram showing a reference voltage correction circuit of a semiconductor device according to a third embodiment of the present invention.
FIG. 12 is a circuit block diagram showing a reference voltage correction circuit of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 13 is a circuit block diagram showing a conventional semiconductor device.
FIG. 14 is a flowchart illustrating a conventional semiconductor device test method.
[Explanation of symbols]
11, 201 Semiconductor device
12, 202 Vcc terminal
13,203 Internal power supply circuit
14 Reference voltage
15 Reference voltage generation circuit
16 Trimming signal
17, 100, 210, 270 Reference voltage correction circuit
18 Test Pad
19, 212 ID holding circuit
20, 213 Confirmation ID
21, 214 correction value
22 Memory cell area
23 Non-volatile memory section
24, 220 logic circuit section
25, 221 Read request signal
26,222 tester
31, 101, 231, 271 ID register
32, 102, 232, 272 Confirmation ID register
33, 103, 233, 273 Comparators
34,104 trimming circuit
35, 105, 236, 276 error register
36, 108, 237, 279 control circuit
37, 109, 238, 280 Judgment signal
38, 110, 239, 281 Error signal
39, 111 trimming value
50, 120 Read voltage search
51, 121 Initial setting step
52, 122 ID reading step for confirmation
53, 123 ID determination step
54, 124 search value change step
55, 125 Range judgment step
56, 126 Correction value setting step
57, 127 Error setting step
60 Design value Vt
71 Initial voltage measurement step
72 Correction value acquisition step
73 External voltage application step
74 Write Step
75 Reference voltage correction step
76 Error judgment step
77 Reference voltage measurement step
78 Pass / fail judgment step
106, 277 HL signal
107,278 HL judgment circuit
128 HL judgment step
129 Downward correction step
130 Upward Correction Step
204 Reference voltage A
205 Reference voltage generation circuit A
206 Reference voltage B
207 Reference voltage generation circuit B
208 Trimming signal A
209 Trimming signal B
211 Reference voltage measurement pad
215 Memory cell area B
216 Non-volatile memory B
217 Memory cell area A
218 Nonvolatile memory A
219 External voltage application pad
234, 274 trimming circuit A
235, 275 trimming circuit B
240, 282 trimming value A
241, 283 trimming value B

Claims (32)

ID holding means for holding an ID for identification which is a predetermined bit pattern;
Reference voltage generating means for changing and outputting a reference voltage by trimming,
A confirmation ID having the same value as the identification ID and a correction value for setting the reference voltage to a desired value are stored in a part of a plurality of nonvolatile memory cells, A nonvolatile memory unit to which a reference voltage is supplied,
A trimming value for changing the reference voltage output from the reference voltage generating means according to a predetermined search procedure is generated, and the reference voltage output from the reference voltage generating means is changed according to the trimming value. Each time the confirmation ID is read from the nonvolatile memory unit, and the read confirmation ID is compared with the identification ID held by the ID holding unit. Reference voltage correction means for reading the correction value from, and the reference voltage generation means sets the reference voltage to a desired value according to the read correction value;
A semiconductor device comprising: The reference voltage correction unit includes:
An ID register that receives the identification ID from the ID holding unit and temporarily stores the ID;
A confirmation ID register for receiving and temporarily storing the confirmation ID from the nonvolatile memory unit;
A comparator that compares the contents held by the ID register and the confirmation ID register and outputs a determination signal according to the comparison result;
The trimming value or the correction value is set, and a trimming unit that outputs a trimming signal to the reference voltage generating unit based on the set value;
When the determination signal of the comparator is "mismatch", the trimming value is generated such that the reference voltage output from the reference voltage generating means is changed according to a predetermined search procedure, and the trimming value is transmitted to the trimming means. Setting, further, reading the confirmation ID from the nonvolatile memory unit and setting the same in the confirmation ID register; and, when the judgment signal is “match”, the correction value from the nonvolatile memory unit. Control means for reading and setting the trimming means, the reference voltage generating means setting the reference voltage to a desired value,
The semiconductor device according to claim 1, further comprising: The control means,
An initial setting function of setting a predetermined value as the trimming value in the trimming means and operating so that the reference voltage becomes an initial output voltage value;
A first generation function of generating the trimming value such that the reference voltage is higher than the initial output voltage value by a predetermined search voltage value;
A second generation function of generating the trimming value such that the reference voltage is lower than the initial output voltage value by a predetermined search voltage value;
After executing the initial setting function, the first generating function and the second generating function are alternately and repeatedly executed, and each time the execution of the second generating function is completed, the search voltage value is set to a constant value. Search function to increase by
The semiconductor device according to claim 2, further comprising: ID holding means for holding an ID for identification which is a predetermined bit pattern;
First reference voltage generating means for changing and outputting the first reference voltage by trimming;
Second reference voltage generating means for changing and outputting the second reference voltage by trimming;
A confirmation ID having the same value as the identification ID and a correction value for setting the second reference voltage to a desired value by trimming are stored in some of the plurality of nonvolatile memory cells, A non-volatile memory unit to which the first reference voltage is supplied from the reference voltage generation unit;
A trimming value for changing the first reference voltage output from the first reference voltage generating means in accordance with a predetermined search procedure is generated, and an output from the first reference voltage generating means is generated based on the trimming value. Each time the first reference voltage is changed, the confirmation ID is read from the nonvolatile memory unit, and the read confirmation ID is compared with the identification ID held by the ID holding unit. When the values match, the correction value is read from the nonvolatile memory unit, and the second reference voltage generation unit sets the second reference voltage to a desired value based on the read correction value. Reference voltage correction means,
A semiconductor device comprising: The semiconductor device according to claim 1, further comprising a second nonvolatile memory unit to which the second reference voltage, which is an output of the second reference voltage generating means, is supplied, and is configured by a plurality of nonvolatile multilevel memory cells. Item 5. The semiconductor device according to item 4. The reference voltage correction unit includes:
An ID register that receives the identification ID from the ID holding unit and temporarily stores the ID;
A confirmation ID register for receiving and temporarily storing the confirmation ID from the nonvolatile memory unit;
A comparator that compares the contents held by the ID register and the confirmation ID register and outputs a determination signal according to the comparison result;
A first trimming unit that sets the trimming value and outputs a first trimming signal to the first reference voltage generating unit based on the set value;
A second trimming unit that sets the correction value and outputs a second trimming signal to the second reference voltage generating unit based on the set value;
When the determination signal of the comparator is “mismatch”, the trimming value is generated such that the first reference voltage output from the first reference voltage generating means is changed according to a predetermined search procedure. Setting the first trimming means, reading the confirmation ID from the non-volatile memory unit and setting the confirmation ID in the confirmation ID register; and Control means for reading the correction value from the non-volatile memory unit, setting the correction value in the second trimming means, and setting the second reference voltage of the second reference voltage generation means to a desired value;
5. The semiconductor device according to claim 4, comprising: The control means,
An initial setting function of setting a predetermined value as the trimming value in the first trimming means and operating so that the first reference voltage becomes an initial output voltage value;
A first generation function of generating the trimming value such that the first reference voltage is higher than the initial output voltage value by a predetermined search voltage value;
A second generation function for generating the trimming value such that the first reference voltage is lower than the initial output voltage value by a predetermined search voltage value;
After executing the initial setting function, the first generating function and the second generating function are alternately and repeatedly executed, and each time the execution of the second generating function is completed, the search voltage value is set to a constant value. Search function to increase by
The semiconductor device according to claim 6, further comprising: The identification ID is a bit pattern having the same number of "0" bits and "1" bits, or a bit pattern having "0" or "1" one bit more. The semiconductor device according to claim 1, claim 2, claim 4, or claim 6. The reference voltage correction unit includes:
If the number of “0” is larger than the number of “1” based on the result of counting the number of bits “0” and “1” of the confirmation ID temporarily stored in the confirmation ID register, the first signal HL determination means for outputting an HL signal indicating a second signal to the control means when the number of “1” is larger than the number of “0”,
The control means,
If the judgment signal of the comparator does not match and the HL signal is the first signal, the reference voltage generation means supplied to the nonvolatile memory unit when reading the confirmation ID next time The trimming value is generated such that the reference voltage of is lower than a current value,
If the determination signal of the comparator does not match and the HL signal is the second signal, the reference voltage generating means supplied to the nonvolatile memory unit when reading the confirmation ID next time 3. The semiconductor device according to claim 2, further comprising a function of generating the trimming value such that the reference voltage becomes higher than a current value. The reference voltage correction unit includes:
If the number of “0” is larger than the number of “1” based on the result of counting the number of bits “0” and “1” of the confirmation ID temporarily stored in the confirmation ID register, the first signal HL determination means for outputting an HL signal indicating a second signal to the control means when the number of “1” is larger than the number of “0”,
The control means,
If the determination signal of the comparator does not match and the HL signal is the first signal, the first reference voltage supplied to the nonvolatile memory unit when reading the confirmation ID next time Generating the trimming value such that the first reference voltage from the generating means is lower than a current value;
If the determination signal of the comparator does not match and the HL signal is the second signal, the first reference voltage supplied to the nonvolatile memory unit when reading the confirmation ID next time 7. The semiconductor device according to claim 6, further comprising a function of generating the trimming value so that the first reference voltage from the generating unit is higher than a current value. 5. The semiconductor device according to claim 1, wherein the correction value and the confirmation ID are stored in the plurality of non-volatile memory cells in an area adjacent to each other. 6. ID holding means for holding an ID for identification which is a predetermined bit pattern;
Reference voltage generating means for changing and outputting a reference voltage by trimming,
A non-volatile memory unit to which the reference voltage is supplied from the reference voltage generation means, and which includes a plurality of non-volatile memory cells;
A method for testing a semiconductor device having:
An initial voltage measuring step of measuring an untrimmed initial output voltage value of the reference voltage generating means,
A correction value obtaining step of calculating a correction value for correcting a difference between the initial output voltage value obtained in the initial voltage measurement step and a desired reference voltage value,
Irrespective of the value of the output voltage of the reference voltage generating means, an external voltage application step of forcibly supplying a predetermined reference voltage to the nonvolatile memory unit from the outside,
The predetermined reference voltage is supplied in the external voltage applying step by supplying the confirmation ID having the same value as the identification ID held in the ID holding unit and the correction value obtained in the correction value obtaining step. Writing to the plurality of nonvolatile memory cells of the nonvolatile memory unit,
A method for testing a semiconductor device, comprising: A trimming value for changing the reference voltage output from the reference voltage generating means according to a predetermined search procedure is generated, and the reference voltage output from the reference voltage generating means is changed according to the trimming value. Each time the confirmation ID written in the writing step is read from the non-volatile memory unit, and the read confirmation ID is compared with the identification ID held by the ID holding unit, and the read ID matches. In the case, the correction value written in the writing step is read from the nonvolatile memory unit, and the reference voltage from the reference voltage generation unit is set to a desired value by the read correction value. Steps and
The test method for a semiconductor device according to claim 12, further comprising: A reference voltage measuring step of measuring the reference voltage from the reference voltage generating means corrected to a desired value in the reference voltage correcting step;
According to whether the value of the reference voltage obtained in the reference voltage measurement step is within a predetermined allowable range, whether or not the semiconductor device is good or bad,
14. The test method for a semiconductor device according to claim 13, further comprising: ID holding means for holding an ID for identification which is a predetermined bit pattern;
First reference voltage generating means for changing and outputting the first reference voltage by trimming;
Second reference voltage generating means for changing and outputting the second reference voltage by trimming;
A non-volatile memory unit to which the first reference voltage is supplied from the first reference voltage generation means and which includes a plurality of non-volatile memory cells;
A method for testing a semiconductor device having:
An initial voltage measuring step of measuring an untrimmed initial output voltage value of the second reference voltage generating means;
A correction value obtaining step of calculating a correction value for correcting a difference between the initial output voltage value obtained in the initial voltage measurement step and a desired reference voltage value,
Irrespective of the value of the output voltage of the first reference voltage generation means, an external voltage application step of forcibly supplying a predetermined reference voltage to the nonvolatile memory unit from the outside,
The confirmation ID having the same value as the identification ID held in the ID holding means and the correction value obtained in the correction value obtaining step are supplied with the predetermined reference voltage in the external voltage application step. Writing to the plurality of nonvolatile memory cells of the nonvolatile memory unit,
A method for testing a semiconductor device, comprising: A trimming value for changing the first reference voltage output from the first reference voltage generating means according to a predetermined search procedure is generated, and an output from the first reference voltage generating means is generated based on the trimming value. Each time the first reference voltage is changed, the confirmation ID written in the writing step is read from the nonvolatile memory unit, and the read ID is held by the ID holding unit. The correction value written in the writing step is read from the non-volatile memory unit when the ID value matches with the identification ID, and the second reference voltage generating means is used in accordance with the read correction value. A reference voltage correction step of setting the second reference voltage from
The test method for a semiconductor device according to claim 15, further comprising: A reference voltage measuring step of measuring the second reference voltage from the second reference voltage generating means corrected to a desired value in the reference voltage correcting step;
A pass / fail judgment step of judging the semiconductor device as a non-defective or defective product according to whether or not the value of the second reference voltage obtained in the reference voltage measurement step is within a predetermined allowable range;
17. The method for testing a semiconductor device according to claim 16, further comprising: 13. The non-volatile memory cell according to claim 12, wherein the correction value and the confirmation ID written in the non-volatile memory unit in the writing step are stored in the plurality of non-volatile memory cells located in mutually adjacent regions. A method for testing a semiconductor device according to claim 15. ID holding means for holding an ID for identification which is a predetermined bit pattern;
Reference voltage generating means for changing and outputting a reference voltage by trimming,
A confirmation ID having the same value as the identification ID and a correction value for setting the reference voltage to a desired value are stored in a part of a plurality of nonvolatile memory cells, A nonvolatile memory unit to which a reference voltage is supplied,
Reference voltage correction method for a semiconductor device having
A confirmation ID reading step of reading the confirmation ID from the nonvolatile memory unit;
An ID determining step of comparing the identification ID held in the ID holding unit with the confirmation ID read in the confirmation ID reading step;
When the comparison result in the ID determination step is “mismatch”, a trimming value for changing the reference voltage output from the reference voltage generating means in accordance with a predetermined search procedure is generated. A search value changing step of changing the reference voltage supplied to the non-volatile memory unit in the confirmation ID reading step by the trimming value each time
When the comparison result in the ID determination step is “match”, the correction value is read from the nonvolatile memory unit, and the reference voltage of the reference voltage generation unit is desired based on the read correction value. A correction value setting step for setting the value of
A reference voltage correcting method for a semiconductor device, comprising: ID holding means for holding an ID for identification which is a predetermined bit pattern;
First reference voltage generating means for changing and outputting the first reference voltage by trimming;
Second reference voltage generating means for changing and outputting the second reference voltage by trimming;
A confirmation ID having the same value as the identification ID and a correction value for setting the second reference voltage to a desired value by trimming are stored in some of the plurality of nonvolatile memory cells, A non-volatile memory unit to which the first reference voltage is supplied from the reference voltage generation unit;
Reference voltage correction method for a semiconductor device having
A confirmation ID reading step of reading the confirmation ID from the nonvolatile memory unit;
An ID determining step of comparing the identification ID held in the ID holding unit with the confirmation ID read in the confirmation ID reading step;
A trimming value for changing the first reference voltage output from the first reference voltage generating means in accordance with a predetermined search procedure when the comparison result in the ID determination step is “mismatch”; And a search value changing step of changing the first reference voltage supplied to the nonvolatile memory unit in the confirmation ID reading step by the trimming value each time the trimming value is generated,
When the comparison result in the ID determination step is “match”, the correction value is read from the non-volatile memory unit, and the second reference voltage generation unit is configured to read the correction value based on the read correction value. A correction value setting step of setting the reference voltage of No. 2 to a desired value;
A reference voltage correcting method for a semiconductor device, comprising: The search procedure for changing the reference voltage output from the reference voltage generation means,
An initial step in which the reference voltage is in a state of an uncorrected initial output voltage value, and a first step of generating the trimming value so that the reference voltage is higher than the initial output voltage value by a predetermined search voltage value. When,
A second step of generating the trimming value such that the reference voltage is lower than the initial output voltage value by a predetermined search voltage value,
After the initial step, the first step and the second step are alternately repeated, and each time the second step is completed, the search voltage value is increased by a constant value. 20. The method for correcting a reference voltage of a semiconductor device according to claim 19. The search procedure for changing the first reference voltage output from the first reference voltage generation means includes:
An initial step in which the first reference voltage is in an uncorrected initial output voltage value state;
A first step of generating the trimming value such that the first reference voltage is higher than the initial output voltage value by a predetermined search voltage value;
A second step of generating the trimming value such that the first reference voltage is lower than the initial output voltage value by a predetermined search voltage value,
After the initial step, the first step and the second step are alternately repeated, and each time the second step is completed, the search voltage value is increased by a constant value. 21. The reference voltage correction method for a semiconductor device according to 20. If the trimming value generated in the search value changing step is within a predetermined range, select the confirmation ID reading step,
20. The apparatus according to claim 19, further comprising a range determining step of selecting an error setting step of temporarily storing error information indicating that the semiconductor device is defective if the trimming value is not within the predetermined range. A method for correcting a reference voltage of a semiconductor device according to claim 20. An error indicating that the semiconductor device is defective when generation of the trimming value for changing the reference voltage, which is an output of the reference voltage generating means in the search value changing step, exceeds a predetermined number of times. 20. The method according to claim 19, further comprising a search number determining step of selecting an error setting step of temporarily storing information. When the generation of the trimming value for changing the first reference voltage, which is an output of the first reference voltage generating means in the search value changing step, exceeds a predetermined number of times, the semiconductor device becomes defective. 21. The method according to claim 20, further comprising: a search number determining step of selecting an error setting step of temporarily storing error information indicating that the error information indicates that the reference voltage is zero. The confirmation ID is a bit pattern having the same number of “0” bits and “1” bits, or a bit pattern in which “0” or “1” has one more bit number,
The search value changing step includes:
Based on the result of counting the number of bits of “0” and “1” of the confirmation ID, if the number of “0” is larger than the number of “1”, the first signal is set to “1” than the number of “0”. HL output step of outputting a second signal when the number of "is large;
When the HL output step outputs a first signal, the reference voltage from the reference voltage generation means supplied to the nonvolatile memory unit in the confirmation ID reading step is determined in advance from a current value. A downward correction step of generating the trimming value so as to be lower by the searched voltage value,
20. The method according to claim 19, further comprising: The confirmation ID is a bit pattern having the same number of “0” bits and “1” bits, or a bit pattern in which “0” or “1” has one more bit number,
The search value changing step includes:
Based on the result of counting the number of bits of “0” and “1” of the confirmation ID, if the number of “0” is larger than the number of “1”, the first signal is set to “1” than the number of “0”. HL output step of outputting a second signal when the number of "is large;
When the HL output step outputs a second signal, the reference voltage from the reference voltage generation means supplied to the nonvolatile memory unit in the confirmation ID reading step is determined in advance from a current value. Upward correction step of generating the trimming value so as to be higher by the searched voltage value,
20. The method according to claim 19, further comprising: The confirmation ID is a bit pattern having the same number of “0” bits and “1” bits, or a bit pattern in which “0” or “1” has one more bit number,
The search value changing step includes:
Based on the result of counting the number of bits of “0” and “1” of the confirmation ID, if the number of “0” is larger than the number of “1”, the first signal is set to “1” than the number of “0”. HL output step of outputting a second signal when the number of "is large;
When the HL output step outputs a first signal, the first reference voltage from the first reference voltage generation means, which is supplied to the non-volatile memory unit in the confirmation ID reading step, is a current value. A downward correction step of generating the trimming value so as to be lower by a predetermined search voltage value than the value of
21. The method according to claim 20, further comprising: The confirmation ID is a bit pattern having the same number of “0” bits and “1” bits, or a bit pattern in which “0” or “1” has one more bit number,
The search value changing step includes:
Based on the result of counting the number of bits of “0” and “1” of the confirmation ID, if the number of “0” is larger than the number of “1”, the first signal is set to “1” than the number of “0”. HL output step of outputting a second signal when the number of "is large;
When the HL output step outputs a second signal, the first reference voltage from the first reference voltage generation means, which is supplied to the nonvolatile memory unit in the confirmation ID reading step, is equal to a current value. An upper correction step of generating the trimming value so as to be higher by a predetermined search voltage value than the value of
21. The method according to claim 20, further comprising: 29. The method according to claim 25, wherein the predetermined search voltage value is a constant value regardless of a search condition. The confirmation ID is a bit pattern having the same number of “0” bits and “1” bits, or a bit pattern in which “0” or “1” has one more bit number,
The search value changing step includes:
Based on the result of counting the number of bits of “0” and “1” of the confirmation ID, if the number of “0” is larger than the number of “1”, the first signal is set to “1” than the number of “0”. HL output step of outputting a second signal when the number of "is large;
When the HL output step outputs a first signal, the reference voltage from the reference voltage generation means supplied to the nonvolatile memory unit in the confirmation ID reading step is determined in advance from a current value. A downward correction step of generating the trimming value so as to be lower by the searched voltage value,
When the HL output step outputs a second signal, the reference voltage from the reference voltage generation means supplied to the nonvolatile memory unit in the confirmation ID reading step is determined in advance from a current value. Upward correction step of generating the trimming value so as to be higher by the searched voltage value,
Further having
20. The search voltage value in the lower correction step and the search voltage value in the upper correction step are sequentially reduced to half each time the lower correction step or the upper correction step is performed. 3. The method for correcting a reference voltage of a semiconductor device according to claim 1. The confirmation ID is a bit pattern having the same number of “0” bits and “1” bits, or a bit pattern in which “0” or “1” has one more bit number,
The search value changing step includes:
Based on the result of counting the number of bits of “0” and “1” of the confirmation ID, if the number of “0” is larger than the number of “1”, the first signal is set to “1” than the number of “0”. HL output step of outputting a second signal when the number of "is large;
When the HL output step outputs a first signal, the first reference voltage from the first reference voltage generation means, which is supplied to the non-volatile memory unit in the confirmation ID reading step, is a current value. A downward correction step of generating the trimming value so as to be lower by a predetermined search voltage value than the value of
When the HL output step outputs a second signal, the first reference voltage from the first reference voltage generation means, which is supplied to the nonvolatile memory unit in the confirmation ID reading step, is equal to a current value. An upper correction step of generating the trimming value so as to be higher by a predetermined search voltage value than the value of
Further having
21. The search voltage value in the lower correction step and the search voltage value in the upper correction step are sequentially reduced to half the value each time the lower correction step or the upper correction step is performed. 3. The method for correcting a reference voltage of a semiconductor device according to claim 1.

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