JP2004259926A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
JP2004259926A
JP2004259926A JP2003048859A JP2003048859A JP2004259926A JP 2004259926 A JP2004259926 A JP 2004259926A JP 2003048859 A JP2003048859 A JP 2003048859A JP 2003048859 A JP2003048859 A JP 2003048859A JP 2004259926 A JP2004259926 A JP 2004259926A
Authority
JP
Japan
Prior art keywords
hole
resin
wiring board
multilayer wiring
filled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003048859A
Other languages
Japanese (ja)
Inventor
Kenji Tanaka
健司 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP2003048859A priority Critical patent/JP2004259926A/en
Publication of JP2004259926A publication Critical patent/JP2004259926A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which improves adhesion between a sealing resin and a multi-layered wiring substrate at a low cost. <P>SOLUTION: Green sheets with through holes for filling conductive paste, and through holes not filling the conductive paste, are formed and at the same time are laminated and sintered to prepare the multi-layered wiring substrate. A semiconductor element is mounted on a wiring pattern formed on the multi-layered wiring substrate. Resin sealing is effected so that the through holes, in which the conductive paste is not filled, is filled with the resin. The resin filled into the through holes improves the adhesion by an anchor effect. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は配線パターン形成した多層配線基板上に半導体素子を実装し、樹脂封止する半導体装置の製造方法に関する。
【０００２】
【従来の技術】
リードレスチップキャリア（ＬＣＣ）構造の半導体装置では、キャリア基板として信頼性が高く小型化が可能なセラミック多層配線基板が多く用いられている。図３及び図４は一般的なセラミック多層配線基板の製造方法を工程順に示した図である。図に示すように、上層基板及び下層基板それぞれについて、セラミック原料粉末を有機樹脂で結合したグリーンシートを用意し、超硬ポンチ等で貫通孔３１（ビアホール）を開けた後、貫通孔３１内に導電性物質である導体ペースト３２を充填する。下層基板にキャスタレーション加工をした後、グリーンシート両面に配線パターン３３を印刷し、加熱圧着して積層形成する。その後、不要な部分を切断除去し、焼結、配線パターン上に必要なメッキを行うことによって多層配線基板が形成される。従来のセラミック多層配線基板の製造方法の一例として特開平１１‐１６３１９２号公報にその技術が開示されている。
【０００３】
図５は、図３及び図４で説明したセラミック多層配線基板に半導体素子を実装する工程を説明する図である。ウエハーテストされた半導体素子５０を用意する。所謂フリップチップボンディング法あるいはワイヤボンディング法により、半導体素子５０と多層配線基板５１（図４の３に相当）上に形成された配線パターンが接続される（実装）。封止樹脂５２を印刷、あるいは塗布し（樹脂封止）、▽印で示す所定の位置で切断し（ダイシング）、特性試験を行い（テスト）、選別し、半導体装置が完成する。
【０００４】
このような製造工程により形成される半導体装置は、ダイシング時に加わる応力のほか、半導体装置を実装基板へハンダ付けする際の熱処理により、熱膨張の違いから、封止樹脂５２が多層配線基板５１から剥離してしまうという問題があった。
【０００５】
封止樹脂が剥離してしまうという問題を解消するため、特開２００１−２９１７９２号公報には、基板に凹部を形成しその中に半導体素子を搭載する半導体装置（ＣＩＢ（ｃｈｉｐ ｉｎ ｂｏａｒｄ）構造と呼ばれる）において、多層配線基板に形成された凹部内に、凹部の底面、および／または、側面に切り込みを設けたうえで半導体素子を凹部底面の所定位置に載置し、ポッティング樹脂などで封止することを内容とする技術が開示されている。ここで凹部は、切り込みの底面の断面形状はテーパ角のついたザグリ構造であり、側面の断面形状は四角形または三角形となっている。
これらはいずれもザグリ加工によって形成されている。
【０００６】
また特許登録第３１１５８０７号には、半導体素子を搭載した基板の上下両面に、光硬化性ドライフィルム・ソルダー・レジストから成る第一の絶縁体層と第二の絶縁体層を形成した半導体装置において、第一の絶縁体層にアンカーホールを散在させて半導体搭載基板上に内有する導体回路パターンと封止樹脂の剥離を防止する技術が開示されている。
【０００７】
【特許文献１】
特開平１１−１６３１９２号公報
【特許文献２】
特開２００１−２９１７９２号公報
【特許文献３】
特許登録第３１１５８０７号
【０００８】
【発明が解決しようとする課題】
半導体素子を樹脂封止する場合、多層配線基板と封止樹脂との密着性が弱く剥離してしまうという問題があった。このような問題を解消するため多層配線基板面に別途凹部を設けて樹脂の密着性を向上させる方法も提案されているが、これらの方法は凹部を形成するための工程が追加され、コストアップとなってしまうという問題が生じていた。本発明は上記問題点を解消し、ローコストで樹脂の密着性を向上させ、封止樹脂と多層配線基板の密着性を向上させる半導体装置の製造方法を提供することを目的とする。
【０００９】
【課題を解決するための手段】
本発明は上記目的を達成するために、貫通孔を形成した後、貫通孔に導電性物質を充填し、配線パターンを形成したグリーンシートを所定枚数積層し、燒結して形成する多層配線基板を用意し、該多層配線基板上に半導体素子を実装した後、半導体素子を樹脂封止する工程を含む半導体装置の製造方法において、導電性物質を充填する貫通孔と同時に導電性物質を充填しない貫通孔を形成した前記グリーンシートを積層、燒結した前記多層配線基板を用意する工程と、該多層配線基板に形成した配線パターン上に前記半導体素子を実装する工程と、前記導電性物質を充填しない貫通孔に樹脂が充填されるように樹脂封止する工程とを含むことを特徴とするものである。
【００１０】
【発明の実施の形態】
本発明の実施形態について説明する。図１（ａ）乃至（ｄ）は本発明の実施形態に係る半導体装置の平面図とＡ−Ａ面における断面図である。図２は本発明の多層配線基板の製造工程を説明する図で、２層の積層基板の形成工程を模式的に工程順に示した図である。
【００１１】
本実施形態の多層配線基板の形成工程と従来例の形成工程との相違点は、貫通孔の加工工程と導体ペーストの充填工程である。即ち、従来例の工程フローでは貫通孔は全て導体ペーストが充填されていたが、本発明の実施形態では、上層基板に導体ペーストを充填する貫通孔（スルーホール）と同時に、導体ペーストを充填しない貫通孔（アンカーホール）を形成する点で異なる。この導体ペーストを充填しない貫通孔（アンカーホール）の形成は、導体ペーストを充填する貫通孔（スルーホール）と同時に形成するため、追加工程の必要がなく、ローコストで作製できる。この貫通孔（アンカーホール及びスルーホール）の形成方法は、同時に形成できればコストアップを抑えることができるので、金型に限らず他の方法を用いて良いことは勿論である。
【００１２】
その後、従来例同様、半導体素子を多層配線基板上に実装し、樹脂封止を行う。その結果、注入された樹脂が、導体ペーストが充填されていない貫通孔に入り込み、所謂アンカー効果により樹脂の密着性がＸ−Ｙ平面だけでなくＺ方向まで向上させることができる。
【００１３】
導体ペーストを充填しない貫通孔の形成位置は特に制限はないが、熱膨張による応力、ダイシング時の応力を考慮して搭載される半導体素子の外周や真下、または半導体装置の側面部に選定されるのが好ましい。実施例の一例を図１に示す。図において１は多層配線基板、２は外部電極、３は内部配線、４は配線パターン、５はキャスタレーション、６は貫通孔（スルーホール）、７は半導体素子、８は金属バンプ、９は封止樹脂、１０は貫通孔（アンカーホール）、１１はボンディングパッド、１２は金ワイヤを示す。
【００１４】
図１（ａ）は半導体素子７の周辺に貫通孔（アンカーホール）１０を散在させた例である。図１（ｂ）は半導体装置を個片化したときに側面に位置する位置に貫通孔（アンカーホール）を形成した例である。図１（ｃ）は特にフリップチップボンディング構造の場合に、半導体素子７の真下に相当する部分に円形または四角形の貫通孔（アンカーホール）１０を形成した例である。図１（ｄ）はワイヤボンディング法を採用した半導体装置の一例で、図１（ａ）に示した構造と同一の場合である。ワイヤボンディング法を採用した半導体装置では、上記図１（ｃ）のように貫通孔（アンカーホール）１０の位置を選定できることは言うまでもない。
【００１５】
また、本実施形態では２層の積層構造について説明したが、３層以上の多層構造にも適用することができる。特に３層以上の積層構造の場合には、半導体素子が実装される表面の層にのみ導体ペースト充填しない貫通孔を形成する場合は勿論、さらにその貫通孔の直下に別の貫通孔を形成した積層基板を積層して貫通孔を設けるようにすることもできる。一例として、貫通孔を形成した積層基板のうち、下層の貫通孔の大きさを上層の貫通孔の大きさより大きくしておくと、樹脂密着力がさらに向上させることができる。
【００１６】
【発明の効果】
以上説明したように、本発明の半導体装置製造方法によれば、多層配線基板上にスルーホール用の貫通孔と封止樹脂を密着固定させるアンカーホール用の貫通孔を同時に、同一の金型で形成するようにすると、追加の工程が不要であり、ローコストで封止樹脂と多層配線基板の密着性を向上させることができる。
【００１７】
本発明のアンカーホール用の貫通孔の形成方法は、スルーホール用の貫通孔を形成する金型にくぼみ用ピンを追加するだけでアンカーホールを形成できるため、半導体装置内の応力のかかりやすい場所を選定して効果的な剥離防止を実現できる利点がある。
【図面の簡単な説明】
【図１】本発明の実施形態に係る半導体装置の平面図および断面図である。
【図２】本発明の実施形態に係る多層配線基板の製造工程を説明する図である。
【図３】セラミック多層配線基板の製造方法を工程順に示した図である。
【図４】セラミック多層配線基板の製造方法を工程順に示した図である。
【図５】セラミック多層配線基板の半導体素子を実装する工程を説明する図である。
【符号の説明】
１：多層配線基板 、２：外部電極、３：内部配線、４：配線パターン、
５：キャスタレーション、６：貫通孔（スルーホール）、７：半導体素子、
８：金属バンプ、９：封止樹脂、１０：貫通孔（アンカーホール）、
１１：ボンディングパッド、１２：金ワイヤ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor element is mounted on a multilayer wiring board on which a wiring pattern has been formed, and is sealed with a resin.
[0002]
[Prior art]
2. Description of the Related Art In a semiconductor device having a leadless chip carrier (LCC) structure, a ceramic multilayer wiring substrate that is highly reliable and can be miniaturized is often used as a carrier substrate. 3 and 4 are views showing a method of manufacturing a general ceramic multilayer wiring board in the order of steps. As shown in the figure, for each of the upper substrate and the lower substrate, a green sheet in which ceramic raw material powder is bonded with an organic resin is prepared, and a through hole 31 (via hole) is opened with a carbide punch or the like. A conductive paste 32, which is a conductive substance, is filled. After the lower layer substrate is castellated, the wiring patterns 33 are printed on both surfaces of the green sheet, and are laminated by hot pressing. Thereafter, unnecessary portions are cut and removed, and sintering and necessary plating are performed on the wiring pattern to form a multilayer wiring board. Japanese Patent Application Laid-Open No. H11-163192 discloses the technique as an example of a conventional method for manufacturing a ceramic multilayer wiring board.
[0003]
FIG. 5 is a view for explaining a step of mounting a semiconductor element on the ceramic multilayer wiring board described in FIGS. 3 and 4. A semiconductor device 50 subjected to a wafer test is prepared. The semiconductor element 50 and the wiring pattern formed on the multilayer wiring board 51 (corresponding to 3 in FIG. 4) are connected (mounted) by a so-called flip chip bonding method or a wire bonding method. The sealing resin 52 is printed or applied (resin sealing), cut at a predetermined position indicated by a mark (dicing), a characteristic test is performed (test), and the semiconductor device is completed.
[0004]
The semiconductor device formed by such a manufacturing process is characterized in that the sealing resin 52 is removed from the multilayer wiring board 51 due to a difference in thermal expansion due to heat applied when soldering the semiconductor device to the mounting board, in addition to stress applied during dicing. There was a problem of peeling.
[0005]
In order to solve the problem that the sealing resin is peeled off, Japanese Patent Application Laid-Open No. 2001-291792 discloses a semiconductor device (chip in board (CIB) structure) in which a recess is formed in a substrate and a semiconductor element is mounted therein. ), A notch is provided in the bottom surface and / or the side surface of the concave portion formed in the multilayer wiring board, and then the semiconductor element is placed at a predetermined position on the bottom surface of the concave portion and sealed with a potting resin or the like. There is disclosed a technology that includes: Here, the recess has a counterbore structure in which the cross-sectional shape of the bottom surface of the cut has a tapered angle, and the cross-sectional shape of the side surface is a square or a triangle.
These are all formed by counterbore processing.
[0006]
Japanese Patent No. 3115807 discloses a semiconductor device in which a first insulator layer and a second insulator layer made of a photocurable dry film solder resist are formed on both upper and lower surfaces of a substrate on which a semiconductor element is mounted. In addition, there is disclosed a technique in which anchor holes are scattered in a first insulator layer to prevent peeling of a conductive circuit pattern and a sealing resin provided on a semiconductor mounting substrate.
[0007]
[Patent Document 1]
JP-A-11-163192 [Patent Document 2]
JP 2001-291792 A [Patent Document 3]
Patent Registration No. 3115807
[Problems to be solved by the invention]
When a semiconductor element is sealed with a resin, there is a problem that the adhesion between the multilayer wiring board and the sealing resin is weak and the semiconductor element is peeled off. In order to solve such a problem, a method has been proposed in which a concave portion is separately provided on the surface of the multilayer wiring board to improve the adhesiveness of the resin. However, in these methods, a step for forming the concave portion is added, thereby increasing the cost. Had the problem of becoming SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device which solves the above-mentioned problems, improves the adhesion of a resin at low cost, and improves the adhesion between a sealing resin and a multilayer wiring board.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a multilayer wiring board formed by forming a through hole, filling the through hole with a conductive material, laminating a predetermined number of green sheets on which a wiring pattern is formed, and sintering. In a method for manufacturing a semiconductor device, comprising the steps of preparing and mounting a semiconductor element on the multilayer wiring board, and sealing the semiconductor element with a resin, a through-hole not filled with a conductive substance simultaneously with a through-hole filled with a conductive substance. A step of preparing the multilayer wiring board obtained by laminating and sintering the green sheets having holes formed therein, a step of mounting the semiconductor element on a wiring pattern formed in the multilayer wiring board, and a step of not penetrating the conductive material. And sealing the resin so that the hole is filled with the resin.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described. 1A to 1D are a plan view and a cross-sectional view taken along a line AA of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a diagram for explaining a manufacturing process of the multilayer wiring board of the present invention, and is a diagram schematically showing a forming process of a two-layer laminated board in the order of the processes.
[0011]
The difference between the forming process of the multilayer wiring board of the present embodiment and the forming process of the conventional example is a process of forming a through hole and a process of filling a conductive paste. That is, in the process flow of the conventional example, all the through holes are filled with the conductive paste, but in the embodiment of the present invention, the conductive paste is not filled at the same time as the through holes (through holes) for filling the upper layer substrate with the conductive paste. The difference is that a through hole (anchor hole) is formed. This through hole (anchor hole) not filled with the conductor paste is formed simultaneously with the through hole (through hole) filled with the conductor paste, so that an additional step is not required and it can be manufactured at low cost. The method of forming the through-holes (anchor hole and through-hole) can suppress an increase in cost if they can be formed at the same time, and it goes without saying that other methods may be used instead of the mold.
[0012]
Thereafter, as in the conventional example, the semiconductor element is mounted on the multilayer wiring board, and resin sealing is performed. As a result, the injected resin enters the through-holes not filled with the conductive paste, and the adhesiveness of the resin can be improved not only in the XY plane but also in the Z direction by a so-called anchor effect.
[0013]
There is no particular limitation on the formation position of the through-hole that is not filled with the conductive paste, but it is selected on the outer periphery or directly below the semiconductor element to be mounted, or on the side surface of the semiconductor device in consideration of the stress due to thermal expansion and the stress at the time of dicing. Is preferred. FIG. 1 shows an example of the embodiment. In the figure, 1 is a multilayer wiring board, 2 is an external electrode, 3 is an internal wiring, 4 is a wiring pattern, 5 is a castellation, 6 is a through hole, 7 is a semiconductor element, 8 is a metal bump, 9 is a sealing. Stop resin, 10 denotes a through hole (anchor hole), 11 denotes a bonding pad, and 12 denotes a gold wire.
[0014]
FIG. 1A shows an example in which through holes (anchor holes) 10 are scattered around a semiconductor element 7. FIG. 1B shows an example in which a through hole (anchor hole) is formed at a position located on the side surface when the semiconductor device is singulated. FIG. 1C shows an example in which a circular or square through-hole (anchor hole) 10 is formed in a portion directly below the semiconductor element 7 particularly in the case of a flip chip bonding structure. FIG. 1D shows an example of a semiconductor device employing a wire bonding method, which is the same as the structure shown in FIG. 1A. Needless to say, in the semiconductor device employing the wire bonding method, the position of the through hole (anchor hole) 10 can be selected as shown in FIG.
[0015]
Further, in the present embodiment, the laminated structure of two layers has been described, but the present invention can be applied to a multilayer structure of three or more layers. In particular, in the case of a laminated structure of three or more layers, not only a case where a through-hole not filled with the conductive paste is formed only in the surface layer on which the semiconductor element is mounted, but also another through-hole is formed immediately below the through-hole. It is also possible to provide a through hole by laminating laminated substrates. As an example, in a laminated substrate having a through hole formed therein, if the size of the lower layer through hole is larger than the size of the upper layer through hole, the resin adhesion can be further improved.
[0016]
【The invention's effect】
As described above, according to the semiconductor device manufacturing method of the present invention, a through hole for a through hole and a through hole for an anchor hole for tightly fixing a sealing resin on a multilayer wiring board are simultaneously formed with the same mold. If it is formed, an additional step is not required, and the adhesion between the sealing resin and the multilayer wiring board can be improved at low cost.
[0017]
In the method of forming a through hole for an anchor hole according to the present invention, an anchor hole can be formed only by adding a recess pin to a mold for forming a through hole for a through hole. There is an advantage that the effective peeling prevention can be realized by selecting the above.
[Brief description of the drawings]
FIG. 1 is a plan view and a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a manufacturing process of the multilayer wiring board according to the embodiment of the present invention.
FIG. 3 is a diagram showing a method for manufacturing a ceramic multilayer wiring board in the order of steps.
FIG. 4 is a diagram showing a method for manufacturing a ceramic multilayer wiring board in the order of steps.
FIG. 5 is a diagram illustrating a step of mounting a semiconductor element of the ceramic multilayer wiring board.
[Explanation of symbols]
1: multilayer wiring board, 2: external electrode, 3: internal wiring, 4: wiring pattern,
5: castellation, 6: through hole (through hole), 7: semiconductor element,
8: metal bump, 9: sealing resin, 10: through hole (anchor hole),
11: bonding pad, 12: gold wire

Claims (1)

貫通孔を形成した後、貫通孔に導電性物質を充填し、配線パターンを形成したグリーンシートを所定枚数積層し、燒結して形成する多層配線基板を用意し、該多層配線基板上に半導体素子を実装した後、半導体素子を樹脂封止する工程を含む半導体装置の製造方法において、
導電性物質を充填する貫通孔と同時に導電性物質を充填しない貫通孔を形成した前記グリーンシートを積層、燒結した前記多層配線基板を用意する工程と、該多層配線基板に形成した配線パターン上に前記半導体素子を実装する工程と、前記導電性物質を充填しない貫通孔に樹脂が充填されるように樹脂封止する工程とを含むことを特徴とする半導体装置の製造方法。After forming the through-hole, a conductive material is filled into the through-hole, a predetermined number of green sheets having a wiring pattern formed thereon are stacked, and a multilayer wiring board is formed by sintering. A semiconductor element is formed on the multilayer wiring board. After mounting, in a method of manufacturing a semiconductor device including a step of resin sealing the semiconductor element,
A step of preparing the multilayer wiring board by laminating and sintering the green sheet formed with the through hole not filling the conductive substance at the same time as the through hole filling the conductive substance, and forming the green sheet on the wiring pattern formed on the multilayer wiring board; A method of manufacturing a semiconductor device, comprising: a step of mounting the semiconductor element; and a step of resin sealing so that a resin is filled in a through hole not filled with the conductive substance.
JP2003048859A 2003-02-26 2003-02-26 Manufacturing method of semiconductor device Pending JP2004259926A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003048859A JP2004259926A (en) 2003-02-26 2003-02-26 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003048859A JP2004259926A (en) 2003-02-26 2003-02-26 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
JP2004259926A true JP2004259926A (en) 2004-09-16

Family

ID=33114699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003048859A Pending JP2004259926A (en) 2003-02-26 2003-02-26 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP2004259926A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008177461A (en) * 2007-01-22 2008-07-31 Denso Corp Electronic apparatus and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008177461A (en) * 2007-01-22 2008-07-31 Denso Corp Electronic apparatus and manufacturing method thereof

Similar Documents

Publication Publication Date Title
JP4361826B2 (en) Semiconductor device
KR100395862B1 (en) Flip chip type semiconductor device and method for manufacturing the same
US7923367B2 (en) Multilayer wiring substrate mounted with electronic component and method for manufacturing the same
JP3813402B2 (en) Manufacturing method of semiconductor device
US6818998B2 (en) Stacked chip package having upper chip provided with trenches and method of manufacturing the same
TWI546924B (en) Method for making electronic device with cover layer with openings and related devices
JP2005108962A (en) Substrate with built-in electronic component and manufacturing method thereof
KR20050007394A (en) Semiconductor device and its manufacturing method
US6287894B1 (en) Acoustic device packaged at wafer level
KR100557516B1 (en) Fabrication method for a semiconductor csp type package
JP2009117450A (en) Module and its manufacturing method
JP2009194079A (en) Wiring substrate for use in semiconductor apparatus, method for fabricating the same, and semiconductor apparatus using the same
JP2010118589A (en) Method of manufacturing wiring board with electronic component incorporated therein
WO2005071744A1 (en) Multilayer electronic part and structure for mounting multilayer electronic part
JP5734624B2 (en) Manufacturing method of semiconductor package
JP2008294330A (en) Substrate with built-in chip
US7045393B2 (en) Method for manufacturing circuit devices
JP2005011883A (en) Wiring board, manufacturing method thereof and semiconductor device
TW200933831A (en) Integrated circuit package and the method for fabricating thereof
JP3710003B2 (en) Mounting board and manufacturing method of mounting board
JP3926736B2 (en) WIRING BOARD, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE
JP2004259926A (en) Manufacturing method of semiconductor device
JP2005322659A (en) Wiring board, its manufacturing method and semiconductor device
JP2006173389A (en) Method of manufacturing circuit board mounted with surface-mounting component
JP2011035269A (en) Semiconductor device, and method of manufacturing the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051111

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070417

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070508

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20071030