JP2004259561A - Method of manufacturing field emission type electron source - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a field emission type electron source enhancing a yield in manufacturing compared with the current method. <P>SOLUTION: A conductive layer 12a is laminated on an insulating substrate 11, and a semiconductor layer 3a is laminated on the conductive layer 12a. Then, nano-crystallization process is conducted by using an electrolyte comprising a mixed solution of hydrogen fluoride aqueous solution and ethanol and oxidization process is conducted to form a second composite nano-crystalline layer 6a. By continuously patterning the second composite nano-crystalline layer 6, the semiconductor layer 3b, and the conductive layer 12a, a pattern of a drift part 6, a polycrystalline silicon layer 3, and an lower electrode 12 is formed. An insulating layer 17 is formed on both sides of the lower electrode 12 in an oxidizing atmosphere. A surface electrode 7 is formed, and then a pad 28 is formed. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a field emission type electron source that emits an electron beam by field emission.
[0002]
[Prior art]
2. Description of the Related Art Hitherto, field emission electron sources 10 ′ and 10 ″ having the configuration shown in FIGS. 12 and 13 have been proposed as electronic devices using nanocrystalline silicon (silicon microcrystals on the order of nanometers) (for example, Patent Document 1) , Patent Document 2).
[0003]
In the field emission type electron source 10 ′ having the configuration shown in FIG. 12, a strong electric field drift layer 6 made of an oxidized porous polycrystalline silicon layer is provided on the main surface (one surface) side of an n-type silicon substrate 1 as a conductive substrate. A surface electrode 7 formed of a metal thin film (for example, a gold thin film) is formed on the strong electric field drift layer 6. An ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1, and the n-type silicon substrate 1 and the ohmic electrode 2 constitute a lower electrode 12. In the example shown in FIG. 12, a non-doped polycrystalline silicon layer 3 is interposed between the n-type silicon substrate 1 and the strong electric field drift layer 6, so that the polycrystalline silicon layer 3 and the strong electric field drift layer 6 Although an electron passing portion through which electrons pass is formed, a device in which the electron passing portion is formed only by the strong electric field drift layer 6 without interposing the polycrystalline silicon layer 3 has been proposed.
[0004]
In order to emit electrons from the field emission electron source 10 ′ having the configuration shown in FIG. 12, for example, a collector electrode 21 disposed opposite to the surface electrode 7 is provided, and a vacuum is applied between the surface electrode 7 and the collector electrode 21. In this state, a DC voltage Vps is applied between the surface electrode 7 and the lower electrode 12 so that the surface electrode 7 is on the higher potential side with respect to the lower electrode 12, and the collector electrode 21 is DC voltage Vc is applied between collector electrode 21 and surface electrode 7 so as to be on the high potential side. Here, if the DC voltage Vps is appropriately set, the electrons injected from the lower electrode 12 drift in the strong electric field drift layer 6 and are emitted through the surface electrode 7 (the dashed line in FIG. Electronic e ⁻ Shows the flow of). The thickness of the surface electrode 7 is set to about 10 to 15 nm.
[0005]
By the way, in the field emission type electron source 10 ′ having the configuration shown in FIG. 12, the lower electrode 12 is composed of the n-type silicon substrate 1 and the ohmic electrode 2, but as shown in FIG. A field emission type electron source 10 ″ in which a lower electrode 12 made of a metal thin film is formed on one surface of an insulating substrate 11 made of a glass substrate having the same has been proposed. The field emission type electron source shown in FIG. The same components as those of the electron source 10 'are denoted by the same reference numerals, and description thereof will be omitted.
[0006]
In order to emit electrons from the field emission type electron source 10 ″ having the configuration shown in FIG. 13, for example, a collector electrode 21 disposed opposite to the surface electrode 7 is provided, and a vacuum is applied between the surface electrode 7 and the collector electrode 21. In this state, a DC voltage Vps is applied between the surface electrode 7 and the lower electrode 12 so that the surface electrode 7 is on the higher potential side with respect to the lower electrode 12, and the collector electrode 21 is A DC voltage Vc is applied between the collector electrode 21 and the surface electrode 7 so as to be on the high potential side.If the DC voltage Vps is appropriately set here, electrons injected from the lower electrode 12 cause strong electric field drift. Drift through the layer 6 and emitted through the surface electrode 7 (dotted line in FIG. ⁻ Shows the flow of). The electrons that have reached the surface of the strong electric field drift layer 6 are considered to be hot electrons and are easily tunneled through the surface electrode 7 and discharged into a vacuum.
[0007]
In each of the field emission electron sources 10 ′ and 10 ″ described above, a current flowing between the surface electrode 7 and the lower electrode 12 is called a diode current Ips, and a current flowing between the collector electrode 21 and the surface electrode 7 is emitted. If the current (emission electron current) Ie is referred to (see FIGS. 12 and 13), the larger the ratio of the emission current Ie to the diode current Ips (= Ie / Ips), the higher the electron emission efficiency (= (Ie / Ips)). × 100 [%]) In the above-described field emission electron sources 10 ′ and 10 ″, the DC voltage Vps applied between the surface electrode 7 and the lower electrode 12 is reduced to a low voltage of about 10 to 20 V. The emission current Ie increases as the DC voltage Vps increases.
[0008]
When the field emission electron source 10 ″ shown in FIG. 13 is applied as an electron source of a display, for example, the configuration shown in FIG. 14 may be adopted.
[0009]
In the display shown in FIG. 14, a face plate 30 made of a flat glass substrate is arranged to face the field emission electron source 10, and a transparent conductive surface is provided on the face of the face plate 30 facing the field emission electron source 10. A collector electrode (hereinafter, referred to as an anode electrode) 21 made of a film (for example, an ITO film) is formed. Further, on the surface of the anode electrode 21 facing the field emission electron source 10, a fluorescent material formed for each pixel and a black stripe made of a black material formed between the fluorescent materials are provided. Here, the fluorescent material is applied to the surface of the anode electrode 21 facing the field emission type electron source 10, and emits visible light by the electron beam emitted from the field emission type electron source 10. The high-energy electrons emitted from the field emission electron source 10 and accelerated by the voltage applied to the anode electrode 21 collide with the fluorescent material, and R (red), G (Green) and B (blue) are used. The face plate 30 is separated from the field emission type electron source 10 by a rectangular frame (not shown), and an airtight space formed between the face plate 30 and the field emission type electron source 10 is evacuated. .
[0010]
The field emission type electron source 10 shown in FIG. 14 includes an insulating substrate 11 made of an insulating glass substrate, a plurality of lower electrodes 12 arranged on one surface of the insulating substrate 11, and a lower electrode 12. A plurality of non-doped polycrystalline silicon layers 3 formed so as to overlap with each other; a plurality of drift portions 6 each formed of an oxidized porous polycrystalline silicon layer formed so as to overlap with the polycrystalline silicon layer 3; Non-doped to fill the periphery of portion 6 (such as between adjacent drift portions 6a), the periphery of polycrystalline silicon layer 3 (such as between adjacent polycrystalline silicon layers 3), and the periphery of lower electrode 12 (such as between adjacent lower electrodes 12). Of the drift portion 6, the polycrystalline silicon layer 3, and the isolation portion 16 on the drift portion 6 and the isolation portion 16. And a plurality of surface electrodes 7 that are arrayed in a direction intersecting with the lower electrode 12 I.
[0011]
Here, in the field emission type electron source 10 shown in FIG. 14, the electron passage section 5 is constituted by the drift section 6, the polycrystalline silicon layer 3, and the separation section 16 as described above, and as shown in FIG. A plurality of lower electrodes 12 arranged on one surface of the insulating substrate 11 and a plurality of surface electrodes 7 arranged in a direction parallel to the one surface of the insulating substrate 11 in a direction perpendicular to the lower electrodes 12. And sandwich the electron passage section 5. It has been proposed that the drift portion 6 and the separation portion 16 constitute the electron passage portion 5 without interposing the polycrystalline silicon layer 3 between the drift portion 6 and the lower electrode 12.
[0012]
In this field emission type electron source 10, a plurality of lower electrodes 12 arranged on one surface of an insulating substrate 11 and a plurality of surface electrodes 7 arranged in a direction intersecting with the lower electrode 12 intersect. Since a part of the drift portion 6 is sandwiched between the corresponding portions, the combination of the surface electrode 7 and the lower electrode 12 is appropriately selected, and a voltage is applied between the selected pair to select the pair in the drift portion 6. A strong electric field acts on a portion corresponding to the intersection of the surface electrode 7 and the lower electrode 12 to emit electrons. That is, the lower electrode 12, the polycrystalline silicon layer 3 on the lower electrode 12, and the polycrystalline silicon layer are formed at lattice points of a matrix (lattice) composed of a group of the plurality of surface electrodes 7 and a group of the plurality of lower electrodes 12. 3 corresponds to the arrangement of the electron source element 10a including the drift portion 6 on the drift portion 3 and the surface electrode 7 on the drift portion 6. By selecting a set of the surface electrode 7 and the lower electrode 12 to which a voltage is applied, Electrons can be emitted from the desired electron source element 10a. As can be seen from the above description, the electron source element 10a is provided for each pixel.
[0013]
In the field emission type electron source 10 described above, as shown in FIG. 16, pads 27 are formed on both ends of the lower electrode 12 in the longitudinal direction, and pads 27 are formed on both ends of the surface electrode 7 in the longitudinal direction. 28 are formed.
[0014]
Hereinafter, a method of manufacturing the field emission electron source 10 having the configuration shown in FIG. 16 will be described with reference to FIGS.
[0015]
First, a structure shown in FIG. 17A is obtained by forming a conductive layer 12a for the lower electrode 12 on the entire surface on the one surface side of the insulating substrate 11.
[0016]
Next, unnecessary portions of the conductive layer 12a are etched using a photolithography technique and an etching technique to pattern the lower electrodes 12 each of which is a part of the conductive layer 12a. The structure shown in FIG.
[0017]
Thereafter, a semiconductor layer 3a made of a non-doped polycrystalline silicon layer serving as a basis for the drift portion 6 and the separation portion 16 constituting the electron passing portion 5 is formed on the entire surface on the one surface side of the insulating substrate 11 by plasma CVD or decompression. By forming a film by the CVD method or the like, the structure shown in FIG. 17C is obtained.
[0018]
Thereafter, unnecessary portions of the semiconductor layer 3a are etched using photolithography technology and etching technology to expose both ends of each lower electrode 12, thereby obtaining the structure shown in FIG. FIG. 18 is a cross-sectional view corresponding to the BB ′ cross-section in FIG.
[0019]
Subsequently, a mask layer 13 made of a resist layer which is opened so as to cover the surface of the portion of the semiconductor layer 3a not overlapping the lower electrode 12 and to expose the surface of the portion overlapping the lower electrode 12 is formed. The structure shown in FIG. 17D is obtained.
[0020]
Thereafter, using the mask layer 13 as a mask, a portion of the semiconductor layer 3a overlapping the lower electrode 12 is anodized to a predetermined depth in an electrolytic solution containing an aqueous solution of hydrogen fluoride, thereby forming grains of polycrystalline silicon and a large number of nanometer-order silicon. Forming a drift layer 6 by oxidizing the porous polycrystalline silicon layer containing a microcrystal by a rapid heating method or an electrochemical oxidation method, and removing the mask layer 13 As a result, the structure shown in FIG. Here, the drift portion 6 includes a polycrystalline silicon grain, a large number of nanocrystal silicon microcrystals, a thin silicon oxide film formed on the surface of each grain, and a silicon oxide film formed on the surface of each silicon microcrystal. have. The portion of the semiconductor layer 3a that overlaps the mask 13 serves as the separation portion 16, and the portion between the drift portion 6 and the lower electrode 12 serves as the polycrystalline silicon layer 3.
[0021]
Thereafter, the surface electrode 7 is formed, and then the pad 27 electrically connected to the surface electrode 7 is formed, thereby obtaining the structure shown in FIG.
[0022]
By the way, the present inventors have experimentally confirmed that the electron emission amount per unit area increases and the electron emission efficiency increases as the thickness of the drift portion 6 decreases, and the non-doped polysilicon layer is used. It is proposed to set the thickness of the semiconductor layer 3a at the time of film formation to, for example, 2 μm or less.
[0023]
However, depending on the thickness of the lower electrode 12, when the thickness of the semiconductor layer 3a is relatively small (for example, when the thickness of the semiconductor layer 3a is about 1.5 μm), it is shown in FIG. As described above, the step portion is formed without flattening the surface of the semiconductor layer 3a, and a crack running in the depth direction at the step portion in the semiconductor layer 3a occurs. Therefore, at the time of anodization, when the electrolytic solution penetrates through cracks from the surface of the semiconductor layer 3a not covered by the mask layer 13 and reaches the lower electrode 12, when the lower electrode 12 is made of glass or the like as the insulating substrate 11, When a material having low resistance to hydrogen fluoride (corrosion resistance) such as chromium or titanium is used, the insulating substrate 11 and the lower electrode 12 are corroded, and the lower electrode 12 and the semiconductor layer 3a are separated. As a result, the yield decreases, so that the above-described mask layer 13 is formed so as to cover the step portion of the semiconductor layer 3a.
[0024]
[Patent Document 1]
Japanese Patent No. 2987140 (pages 4 to 7, FIGS. 1 to 3)
[Patent Document 2]
Japanese Patent No. 311456 (Pages 10 to 14, FIGS. 1, 2, 8, and 9)
[0025]
[Problems to be solved by the invention]
By the way, in the above-described method of manufacturing the field emission type electron source 10, a portion of the semiconductor layer 3a overlapping the lower electrode 12 is anodized to a predetermined depth in an electrolytic solution containing an aqueous solution of hydrogen fluoride, thereby forming grains of polycrystalline silicon. In addition, a mask layer 13 made of a resist layer is used as a mask when forming a porous polycrystalline silicon layer containing a large number of nanometer-sized silicon microcrystals. Since the resistance is low, the electrolytic solution penetrates through the cracks in the semiconductor layer 3a and reaches the lower electrode 12 even though the mask layer 13 is provided. When a material having low resistance (corrosion resistance) to hydrogen fluoride such as chromium or titanium is used as the insulating substrate 11 or Department electrode 12 is corroded yield by peeling the lower electrode 12 and the semiconductor layer 3a decreases.
[0026]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a field emission electron source capable of improving the yield at the time of manufacturing as compared with the related art.
[0027]
[Means for Solving the Problems]
According to a first aspect of the present invention, in order to achieve the above object, a large number of electron source elements are arranged in a matrix on one surface side of an insulating substrate, and each electron source element is disposed on the one surface of the insulating substrate. A lower electrode, a surface electrode facing the lower electrode in the thickness direction of the insulating substrate, and a number of nanometer-order semiconductor microcrystals interposed between the lower electrode and the surface electrode and formed on the surface of each semiconductor microcrystal. A drift portion having a large number of insulating films having a thickness smaller than the crystal grain size of the semiconductor microcrystal, and a method for manufacturing a field emission type electron source, the method comprising: A first film formation step of stacking a conductive layer, a second film formation step of stacking a semiconductor layer serving as a basis for a drift portion on the conductive layer, and nano-crystallization of the semiconductor layer using an electrolytic solution Many nanometer-order semiconductors A nanocrystallizing step of forming a first composite nanocrystal layer having microcrystals, and forming an insulating film having a thickness smaller than the crystal grain size of the semiconductor microcrystals on the surface of each semiconductor microcrystal, thereby increasing the number of layers. An insulating film forming step of forming a second composite nanocrystal layer having a semiconductor microcrystal and a large number of insulating films, and by continuously etching unnecessary portions of the second composite nanocrystal layer and the conductive layer, respectively. A collective patterning step of patterning a drift part composed of a part of the second composite nanocrystal layer and a lower electrode composed of part of a conductive layer, respectively; and an electrode forming step of forming a surface electrode on the drift part. It is possible to prevent the conductive layer and the insulating substrate for the lower electrode from being corroded by the electrolytic solution in the nano crystallization process, and the lower electrode is separated from the insulating substrate. Peeling or can layer on the lower electrode can be prevented from peeling from the lower electrode, thereby improving the long-term reliability it is possible to improve the yield in manufacturing.
[0028]
According to a second aspect of the present invention, in the first aspect of the present invention, in the second film forming step, a mask material is disposed on a surface of a portion of the conductive layer that becomes a contact portion in each of the lower electrodes. Since the semiconductor layer is laminated on the conductive layer, if the mask material is removed after laminating the semiconductor layer on the conductive layer, the surface of a portion of the conductive layer serving as a contact portion in each of the lower electrodes is removed. Since the semiconductor layer is exposed, there is no need to separately provide a patterning step for exposing the surface of a portion serving as a contact portion in the lower electrode after laminating the semiconductor layer on the conductive layer, thereby simplifying the manufacturing process. Can be achieved.
[0029]
According to a third aspect of the present invention, in the first or second aspect of the invention, in the collective patterning step, unnecessary portions of the second composite nanocrystal layer and the conductive layer are dry-etched to form the drift portions. In addition, since the lower electrodes are formed in a pattern, the reproducibility of the shapes of the drift portions and the lower electrodes patterned in the collective patterning step can be improved.
[0030]
According to a fourth aspect of the present invention, in the third aspect of the present invention, in the first film forming step, tungsten is adopted as a material of the conductive layer laminated on the one surface of the insulating substrate, and the second Polycrystalline silicon is adopted as a material of the semiconductor layer to be laminated on the conductive layer in the film forming step, and unnecessary portions of the second composite nanocrystal layer and the conductive layer are dry-etched in the collective patterning step. In this case, since a fluorine-based gas is used as an etching gas, unnecessary portions of the second composite nanocrystal layer and the conductive layer can be continuously dry-etched without changing etching conditions, thereby improving throughput. Process management becomes easier.
[0031]
According to a fifth aspect of the present invention, in the first or second aspect of the present invention, in the collective patterning step, unnecessary portions of the second composite nanocrystal layer and the conductive layer are wet-etched to form the drift portions. Also, since the lower electrodes are formed in a pattern, a vacuum device such as a dry etching device is not required unlike the case where the unnecessary portion of the second composite nanocrystal layer and the unnecessary portion of the conductive layer are dry-etched. The cost of the device can be reduced, which is particularly advantageous when increasing the area of the insulating substrate.
[0032]
According to a sixth aspect of the present invention, in the invention of the fifth aspect, in the collective patterning step, an etching condition is set such that the lower electrode below the drift portion is side-etched, so that the surface formed in the electrode forming step is formed. Regardless of the electrode pattern, it is possible to prevent the short circuit between the surface electrode and the lower electrode.
[0033]
According to a seventh aspect of the present invention, in the first to sixth aspects of the present invention, the material of the conductive layer to be laminated on the one surface of the insulating substrate in the first film forming step is easily oxidized and is oxidized. An insulating layer made of an oxide of the conductive material is formed by oxidizing an exposed surface of the lower electrode between the collective patterning step and the electrode forming step using a conductive material having an insulating property. Since the insulating layer is formed on the exposed surface of the lower electrode before the surface electrode is formed in the electrode forming step, the insulating layer can be formed on the exposed surface of the lower electrode. Irrespective of the pattern, it is possible to prevent a short circuit between the surface electrode and the lower electrode.
[0034]
The invention according to claim 8 is the invention according to claim 1 to claim 6, wherein the material of the conductive layer to be laminated on the one surface of the insulating substrate in the first film forming step is easily oxidized and oxidized. Since the object uses a conductive material having an insulating property, and in the insulating film forming step, a rapid thermal oxidation method in an oxidizing gas atmosphere is employed, an insulating film is formed on the surface of each of the semiconductor microcrystals. In addition, since an insulating layer made of the oxide of the conductive material can be formed on the exposed surface of the lower electrode, it is not necessary to provide a separate process for forming the insulating layer on the exposed surface of the lower electrode. The number of steps can be reduced as compared with the invention of claim 7.
[0035]
According to a ninth aspect of the present invention, in the first to eighth aspects of the present invention, an insulating material that fills the periphery of each lower electrode and the periphery of each drift portion is provided between the collective patterning step and the electrode forming step. Since an insulating separation step of forming an insulating portion is provided, it is possible to prevent a short circuit between the surface electrode and the lower electrode regardless of the pattern of the surface electrode formed in the electrode forming step, and Unevenness of the exposed surface on the one surface side of the insulating substrate before the formation of the surface electrode can be reduced, and disconnection of the surface electrode can be prevented regardless of the pattern of the surface electrode.
[0036]
According to a tenth aspect of the invention, in the ninth aspect of the invention, in the insulation separating step, a photosensitive material having an insulating property is adopted as the insulating material, and the photosensitive material is applied to the one surface side of the insulating substrate. Then, since the insulating portion is formed by patterning by photolithography, the insulating portion can be formed more easily than when the insulating portion is formed using a lift-off method.
[0037]
According to an eleventh aspect of the present invention, in the ninth aspect of the invention, in the insulating isolation step, nitride is adopted as the insulating material, and nitride particles are included around each of the lower electrodes and around each of the drift portions. Since the insulating portion is formed by embedding the paste by a printing method, the insulating portion can be formed more easily than when the insulating portion is formed using a lift-off method.
[0038]
According to a twelfth aspect of the present invention, in the ninth to eleventh aspects of the present invention, after the electrode forming step, a plurality of pads electrically connected to the surface electrode are formed at positions overlapping the insulating portion. Since the step is provided, disconnection between the surface electrode and the pad can be prevented.
[0039]
According to a thirteenth aspect of the present invention, in the first to twelfth aspect of the present invention, in the nano-crystallization step, a cathode is arranged to face the semiconductor layer in the electrolytic solution so that the conductive layer serves as an anode, Since a current flows from the entire periphery of the conductive layer when a current flows between the cathode and the cathode, the conductive layer flows when a current flows between the anode and the cathode in the nanocrystallization step. The voltage drop due to the electric resistance of the first composite nanocrystal layer is reduced, and the in-plane uniformity of the first composite nanocrystal layer is improved.
[0040]
According to a fourteenth aspect, in the first to thirteenth aspects, the insulating film forming step is an electrochemical oxidation step, and the first composite nanocrystal layer is formed in an oxidizing electrolyte. After a cathode is arranged oppositely, a constant current is passed between the anode and the cathode using the conductive layer as the anode, and after the voltage between the anode and the cathode increases by a specified amount, the voltage between the anode and the cathode is increased. Since the oxidation is terminated when the current decreases to a predetermined value while maintaining the voltage after the increase, a constant current is passed between the anode and the cathode, and the voltage between the anode and the cathode increases by a specified amount. The breakdown voltage of each of the electron source elements is improved as compared with the case where the oxidation is sometimes terminated.
[0041]
According to a fifteenth aspect of the present invention, in the invention of the ninth to twelfth aspects, the drift portion patterned by the collective patterning step corresponds to the electron source element between the collective patterning step and the insulating separation step. Since an etching step of etching the portion between the portions to be exposed until the lower electrode is exposed is provided, it is possible to more reliably insulate between adjacent electron source elements and improve the electron emission characteristics of each electron source element.
[0042]
According to a sixteenth aspect, in the first aspect, a large-area substrate on which a plurality of the field emission electron sources can be formed is used as the insulating substrate before the formation of the conductive layer. Since the method further includes a dividing step of dividing the insulating substrate into a size corresponding to the field emission electron source later, the manufacturing cost can be reduced.
[0043]
According to a seventeenth aspect, in the sixteenth aspect, an etching step of exposing a part of the lower electrode by etching a part of the second composite nanocrystal layer after the insulating film forming step Therefore, there is an advantage that it is not necessary to pattern the conductive layer when forming the conductive layer.
[0044]
In the invention according to claim 18, in the invention according to claim 16, in the nanocrystallization step, the first composite nanocrystal layer is formed only in a region of the semiconductor layer corresponding to each of the field emission electron sources. Therefore, the voltage drop in the conductive layer can be reduced, and the in-plane uniformity of the first composite nanocrystal layer can be improved.
[0045]
According to a nineteenth aspect, in the sixteenth aspect, prior to the second film forming step, the conductive layer laminated on the large-area substrate in the first film forming step is formed by each of the electric field emission type. The semiconductor device further includes a separation step of electrically separating the regions corresponding to the electron sources, and in the nano crystallization step, a portion of the semiconductor layer overlapping each of the conductive layers separated in the separation step Since the first composite nanocrystal layer is individually formed, a voltage drop in the conductive layer can be reduced, and the in-plane uniformity of the first composite nanocrystal layer can be improved.
[0046]
According to a twentieth aspect of the present invention, in the nineteenth aspect, in the nano-crystallization step, a portion of the semiconductor layer that overlaps with each of the conductive layers separated in the separation step is the first composite nano-layer. Since the crystal layers are sequentially formed, power consumption in the nanocrystallization step can be reduced.
[0047]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
As shown in FIG. 4, the field emission electron source 10 of the present embodiment includes an insulating substrate 11 made of an insulating glass substrate and a plurality of strips arranged on one surface of the insulating substrate 11. Lower electrode 12, a plurality of non-doped polycrystalline silicon layers 3 formed so as to overlap with the lower electrode 12, respectively, and a composite nanocrystalline layer formed so as to overlap with the polycrystalline silicon layer 3 (described later). A plurality of drift portions 6 composed of two composite nanocrystal layers), insulating layers 17 and 17 formed on both side surfaces of the lower electrode 12 in the width direction, and a plurality of rows arranged in a direction intersecting the lower electrode 12. And the surface electrode 7. Here, part of the surface electrode 7 faces the lower electrode 12 in the thickness direction of the insulating substrate 11. The lower electrode 12 has pads 27 formed on both ends in the longitudinal direction, and the surface electrode 7 has pads 28 formed on both ends in the longitudinal direction. Further, in the present embodiment, the cross-sectional shape of the surface electrode 7 is formed in a rectangular wave shape. However, on both sides of the lower electrode 12, an oxide having a material containing the lower electrode 12 as a constituent element and having an insulating property (for example, Al ₂ O ₃ , SiO ₂ ), The surface electrode 7 and the lower electrode 12 are not short-circuited. The width of the lower electrode 12 in the width direction is slightly smaller than that of the drift portion 6, and the width of the insulating layers 17 on both sides in the width direction is substantially equal to the width of the drift portion 6.
[0048]
As a material of the lower electrode 12, a conductive material having low oxidation resistance and easily oxidized (for example, Al, highly-doped polycrystalline silicon, or the like) is used. Therefore, the above-described insulating layer 17 can be formed by oxidizing both side surfaces of the lower electrode 12. In this embodiment, the thickness of the lower electrode 12 is set to about 3000 °.
[0049]
On the other hand, if the surface of the surface electrode 7 undergoes alteration such as oxidation, the electron emission efficiency decreases. Therefore, the surface electrode 7 is made of a chemically stable precious metal material (eg, gold) having high oxidation resistance. However, the material of the surface electrode 7 is not limited to gold. The surface electrode 7 is not limited to a single-layer structure, but may have a multilayer structure. The thickness of the surface electrode 7 may be any thickness as long as electrons passing through the drift portion 6 can tunnel, and may be set to about 6 nm to 15 nm.
[0050]
The field emission type electron source 10 according to the present embodiment includes a plurality of lower electrodes 12 arranged on one surface of an insulating substrate 11 and a lower electrode 12 as in the conventional configuration shown in FIGS. Since a part of the drift portion 6 is sandwiched at a portion corresponding to an intersection with a plurality of surface electrodes 7 arranged in a direction intersecting with each other, a set of the surface electrode 7 and the lower electrode 12 is appropriately selected and selected. By applying a voltage between the pairs, a strong electric field acts on a portion corresponding to the intersection of the selected surface electrode 7 and the lower electrode 12 in the drift portion 6 to emit electrons. That is, the lower electrode 12, the polycrystalline silicon layer 3 on the lower electrode 12, and the polycrystalline silicon layer are formed at lattice points of a matrix (lattice) composed of a group of the plurality of surface electrodes 7 and a group of the plurality of lower electrodes 12. 3 corresponds to the arrangement of the electron source element 10a including the drift portion 6 on the drift portion 3 and the surface electrode 7 on the drift portion 6. By selecting a set of the surface electrode 7 and the lower electrode 12 to which a voltage is applied, Electrons can be emitted from the desired electron source element 10a. The surface electrode 7 may be formed only at a portion corresponding to the electron source element 10a, and a plurality of surface electrodes 7 arranged in a direction orthogonal to the lower electrode 12 may be electrically connected by a low-resistance bus electrode. Good.
[0051]
The drift portion 6 is formed by performing a nano crystallization process and an oxidation process described later, and as shown in FIG. 5, at least a grain of columnar polycrystalline silicon arranged on the surface side of the lower electrode 12. (Semiconductor crystal) 51, a thin silicon oxide film 52 formed on the surface of the grains 51, a number of nanometer-order silicon microcrystals (semiconductor microcrystals) 63 interposed between the grains 51, and each silicon microcrystal 63. It is considered to be composed of a large number of silicon oxide films 64 which are formed on the surface and are insulating films having a thickness smaller than the crystal grain size of the silicon microcrystal 63. Each of the grains 51 extends in the thickness direction of the lower electrode 12.
[0052]
In the electron source element 10a of the field emission electron source 10 of the present embodiment, it is considered that electron emission occurs in the following model. That is, by applying the DC voltage Vps between the surface electrode 7 and the lower electrode 12 with the surface electrode 7 being on the high potential side, electrons e are transferred from the lower electrode 12 to the drift portion 6. ⁻ Is injected. On the other hand, most of the electric field applied to the drift portion 6 is applied to the silicon oxide film 64, so that the injected electrons e ⁻ Is accelerated by the strong electric field applied to the silicon oxide film 64, and drifts in the region between the grains 51 in the drift portion 6 toward the surface in the direction of the arrow in FIG. 5 (upward in FIG. 5). And is released into a vacuum. In the drift portion 6, electrons injected from the lower electrode 12 are accelerated and drifted by the electric field applied to the silicon oxide film 64 without being scattered by the silicon microcrystal 63, and are emitted through the surface electrode 7. Since the heat generated in the drift portion 6 is radiated through the grains 51, the popping phenomenon does not occur at the time of emitting electrons, and electrons can be stably emitted. The electrons that have reached the surface of the drift portion 6 are considered to be hot electrons and are easily tunneled through the surface electrode 7 and released into a vacuum.
[0053]
Hereinafter, a method for manufacturing the field emission electron source 10 of the present embodiment will be described with reference to FIGS.
[0054]
First, a first film-forming step of laminating (film-forming) a conductive layer 12a made of an aluminum film having a predetermined thickness (for example, 3000 °) on the one surface of the insulating substrate 11 by, for example, a sputtering method is performed. 1A is obtained. The conductive layer 12a is for the lower electrode 12, and is patterned into a plurality of lower electrodes 12 in a collective patterning step described later.
[0055]
Subsequently, a second film forming step of laminating (film forming) a semiconductor layer 3a made of a non-doped polycrystalline silicon layer having a predetermined thickness (for example, 1.5 μm) on the conductive layer 12a by a plasma CVD method. As a result, the structure shown in FIG. 1B is obtained. However, in the second film forming step, a state in which a mask material (not shown) made of glass, metal, or the like is arranged on the surface of the conductive layer 12a on the surface of the contact portion of each lower electrode 12 (mask) The semiconductor layer 3a is laminated on the conductive layer 12a in a state where the material is brought into close contact. Therefore, if the mask material is removed after laminating the semiconductor layer 3a on the conductive layer 12a, the surface of the conductive layer 12a that is to be a contact portion in each lower electrode 12 will be exposed. It is not necessary to separately provide a patterning step for exposing the surface of a portion to be a contact portion in the lower electrode 12 after laminating the conductive layer on the conductive layer 12a, and the manufacturing process can be simplified. As the mask material here, for example, if a rectangular frame that covers the entire periphery of the conductive layer 12a is used, the periphery of the conductive layer 12a can be exposed as shown in FIG. The semiconductor layer 3a is the basis of the drift portion 6, and has the same configuration as the drift portion 6 by performing a nanocrystallization process and an oxidation process described later. Further, the method for forming the semiconductor layer 3a in the second film forming step is not limited to the plasma CVD method, but may be an LPCVD method, a catalytic CVD method, or the like.
[0056]
After the above-described semiconductor layer 3a is formed, by performing the above-described nanocrystallization process (nanocrystallization step), a number of grains 51 (see FIG. 5) of polycrystalline silicon and a number of silicon microcrystals 63 (see FIG. 5) 5) are formed (hereinafter referred to as a first composite nanocrystal layer), and then the above-described oxidation process is performed to convert the first composite nanocrystal layer to an electrochemical process. By forming a composite nanocrystal layer (hereinafter, referred to as a second composite nanocrystal layer) 6a having a configuration as shown in FIG. 5 by oxidation, the structure shown in FIG. 1C is obtained. In FIG. 1C, a portion of the semiconductor layer 3a below the second composite nanocrystal layer 6a is defined as a semiconductor layer 3b.
[0057]
In the nano crystallization process, an electrolytic solution composed of a mixture of a 55 wt% aqueous solution of hydrogen fluoride and ethanol in a ratio of about 1: 1 is used, the conductive layer 12a is used as an anode, and platinum is applied to the semiconductor layer 3a in the electrolytic solution. A cathode composed of electrodes is disposed opposite to each other, and while a main surface of the semiconductor layer 3a is irradiated with light by a light source composed of a 500 W tungsten lamp, a constant current (for example, a current density of 12 mA / cm ² Is passed for a predetermined time (for example, 10 seconds) to form a first composite nanocrystal layer including the polycrystalline silicon grains 51 and the silicon microcrystals 63. In the nano crystallization process, a processing tank is used in which the insulating substrate 11 can be set in such a manner that the periphery of the main surface of the semiconductor layer 3a and the exposed conductive layer 12a are sealed so as not to come into contact with the electrolytic solution. are doing. Here, in the present embodiment, the semiconductor layer 3a is stacked on the flat conductive layer 12a, and the surface of the semiconductor layer 3a is flat regardless of the thickness of the semiconductor layer 3a. Since the conventional crack (crack) does not occur, it is possible to prevent the problem that the electrolyte solution penetrates through the crack in the semiconductor layer 3a, and the conductive layer 12a for the lower electrode 12 and the insulating substrate can be prevented. 11 can be prevented from being corroded. When performing the nanocrystallization process of the present embodiment, as shown in FIG. 2 described above, the periphery of the conductive layer 12a is exposed, and the cathode faces the semiconductor layer 3a in the electrolytic solution. Since the conductive layer 12a is disposed as an anode and a current flows from the entire periphery of the conductive layer 12a when a current flows between the anode and the cathode, the current flows between the anode and the cathode in the nanocrystallization process. The voltage drop due to the electric resistance of the conductive layer 12a when a current is flowing through is reduced, and the in-plane uniformity of the first composite nanocrystal layer is improved.
[0058]
In the oxidation process, for example, 1 mol / l of H ₂ SO ₄ Using an electrolytic solution composed of a solution, the conductive layer 12a is used as an anode, and a cathode composed of a platinum electrode is opposed to the first composite nanocrystal layer in the electrolytic solution. After the current of the formation current density continues to flow and the voltage between the anode and the cathode increases by a specified amount, the voltage between the anode and the cathode is maintained at the increased voltage and the formation current density decreases to a predetermined value. The first composite nanocrystal layer is electrochemically oxidized by stopping the current supply when the second composite nanocrystal layer including the grain 51, the silicon microcrystal 63, and the silicon oxide films 52 and 64 is formed. A crystal layer 6a is formed. In this oxidation process, the formation current density changes as time elapses from the start of energization as shown by the solid line "a" in FIG. 3, and the voltage between the anode and the cathode changes by one point in FIG. It changes like "b" shown by the chain line. In this embodiment, the constant formation current density is set to 2.5 mA / cm. ² After the voltage between the anode and the cathode is increased by a specified amount to 20 V, the voltage between the anode and the cathode is maintained at 20 V and the formation current density is 0.01 A / cm. ² The power supply was stopped at the time of the rise. The electrolyte used in the above oxidation process is 1 mol / l H ₂ SO ₄ It is not limited to a solution, and various acids (for example, H ₂ SO ₄ , HNO ₃ , Aqua regia, etc.) or a solution in which an electrolyte (eg, potassium nitrate, etc.) is dissolved in an organic solvent (eg, ethylene glycol, etc.). In the present embodiment, the silicon oxide film 64 forms an insulating film, and the oxidation process is an insulating film forming step. In the present embodiment, regions other than the grains 51 and the silicon microcrystals 63 in the first composite nanocrystal layer formed by performing the above-described nanocrystallization process are amorphous regions made of amorphous silicon, In the second composite nanocrystal layer, regions other than the grains 51, the silicon microcrystals 63, and the silicon oxide films 52 and 64 are amorphous regions 65 made of amorphous silicon or partially oxidized amorphous silicon. Depending on the conditions of the conversion process, the amorphous region 65 becomes a hole, and in such a case, the first composite nanocrystalline layer can be regarded as having the same configuration as the porous polycrystalline silicon layer described in the conventional example.
[0059]
After the above-described oxidation process is completed, a plurality of drift portions 6 each composed of a part of the second composite nanocrystal layer and a polycrystal composed of a part of the semiconductor layer 3b are formed on the second composite nanocrystal layer 6a. After performing a mask layer forming step of forming an etching mask layer (not shown) for patterning the silicon layer 3 and the plurality of lower electrodes 12 each formed of a part of the conductive layer 12a, the etching mask layer is masked. By performing a batch patterning step of continuously patterning the second composite nanocrystal layer 6a, the semiconductor layer 3b, and the conductive layer 12a, the drift portion 6, the polycrystalline silicon layer 3, and the lower electrode 12 are patterned. The structure shown in FIG. 1D is obtained by removing the etching mask layer. Here, as a material of the etching mask layer, for example, a photoresist may be used. When a photoresist is used as a material of the etching mask layer, the entire surface on the one surface side of the insulating substrate 11 by spin coating is used. A resist layer is formed on the substrate, and an unnecessary portion of the resist layer is removed by a lithography technique, whereby an etching mask layer including a patterned resist layer can be formed. In the collective patterning step of the present embodiment, unnecessary portions of the second composite nanocrystal layer 6a and the conductive layer 12a are removed by wet etching. However, the width of the lower electrode 12 below the drift portion 6 is reduced. The etching conditions are set so as to be slightly smaller than the width of the portion 6 (that is, the lower electrode 12 is side-etched). If the material of the semiconductor layer 3a which is the basis of the second composite nanocrystal layer 6a is polycrystalline silicon and the material of the conductive layer 12a is aluminum, the second layer is formed by using a mixed acid of hydrofluoric acid and nitric acid. Unnecessary portions of the composite nanocrystal layer 6a, unnecessary portions of the semiconductor layer 3b, and unnecessary portions of the conductive layer 12a are continuously wet-etched, and the drift portions 6 each formed of a part of the second composite nanocrystal layer 6a, respectively. The polycrystalline silicon layer 3 composed of a part of the semiconductor layer 3b and the lower electrode 12 composed of a part of the conductive layer 12a can be pattern-formed.
[0060]
Thereafter, an oxidizing gas (for example, O ₂ Gas, N ₂ The insulating substrate 11 is heated to a predetermined substrate temperature (for example, 600 ° C.) in an atmosphere (eg, O gas) to oxidize the exposed surface of each lower electrode 12a, thereby reducing the constituent material (conductive material) of the lower electrode 12. Oxides (eg, Al ₂ O ₃ 1) is obtained by performing an insulating layer forming step of forming insulating layers 17 of the lower electrode 12 on both side surfaces in the width direction. In this insulating layer forming step, the above-described drift portion 6 is annealed in an oxidizing gas atmosphere at the same time that the insulating layer 17 is formed on the exposed surface of the lower electrode 12. The film quality of each of the silicon oxide films 52 and 64 of No. 6 is improved. Further, in the above-described insulating film forming step, an electrochemical oxidation method is employed. However, if the rapid thermal oxidation method (RTO method) in an oxygen gas atmosphere is employed in the insulating film forming step, each method may be used. When forming the silicon oxide film 64 on the surface of each of the silicon microcrystals 63, the insulating layer 17 made of an oxide of the constituent material (conductive material) of the lower electrode 12 can be formed on the exposed surface of the lower electrode 12. Therefore, there is no need to separately provide the insulating layer forming step for forming the insulating layer 17 on the exposed surface of the lower electrode 12, and the number of steps can be reduced.
[0061]
After the insulating layer 17 is formed, an electrode forming step of forming the surface electrodes 7 made of a gold thin film by, for example, a vapor deposition method is performed. Subsequently, pads 28 are formed on both ends of each surface electrode 7 and each lower electrode is formed. By performing a pad forming step of forming pads 27 on both ends of the field emitter 12, the field emission electron source 10 having the structure shown in FIG. 1 (f) is obtained.
[0062]
The field emission type electron source 10 of the present embodiment manufactured by the manufacturing method described above can prevent the problem that the electrolytic solution penetrates through the cracks formed in the semiconductor layer 3a in the nanocrystallization step. In addition, the yield during manufacturing can be improved, and long-term reliability can be improved. In addition, it is possible to prevent the conductive layer 12a for the lower electrode 12 and the insulating substrate 11 from being corroded by the electrolytic solution in the nano crystallization step, and the lower electrode 12 is peeled off from the insulating substrate 11. Also, it is possible to prevent the polycrystalline silicon layer 3 on the lower electrode 12 from peeling off from the lower electrode 12.
[0063]
Further, in the first film forming step, a conductive layer 12a to be laminated on the one surface of the insulating substrate 11 is made of a conductive material which is easily oxidized and the oxide has an insulating property. An insulating layer forming step of forming an insulating layer 17 made of a conductive material oxide by oxidizing the exposed surface of the lower electrode 12 is provided between the forming step and the surface electrode 7 in the electrode forming step. Since the insulating layer 17 can be formed beforehand on the exposed surface of the lower electrode 12, short circuit between the surface electrode 7 and the lower electrode 12 is prevented regardless of the pattern of the surface electrode 7 formed in the electrode forming step. be able to.
[0064]
In this embodiment, the drift portion 6 is formed by performing a nano-crystallization process on the semiconductor layer 3a made of a non-doped polycrystalline silicon layer and then performing an oxidation process. Alternatively, another semiconductor layer may be employed instead of the non-doped polycrystalline silicon layer. As the insulating film forming step, a nitriding process or an oxynitriding process may be adopted instead of the oxidizing process. When the nitriding process is adopted, each of the silicon oxide films 52 and 64 described in FIG. Also becomes a silicon nitride film, and when the oxynitriding process is adopted, each of the silicon oxide films 52 and 64 becomes a silicon oxynitride film. That is, when the oxidation process is adopted, the silicon oxide film 64 constitutes an insulating film formed on the surface of the silicon microcrystal 63 which is a semiconductor microcrystal, but when the nitridation process is adopted, the silicon oxide film 64 is formed. When the oxynitriding process is adopted, the silicon oxynitride film formed instead of the silicon oxide film 64 forms the insulating film.
[0065]
(Embodiment 2)
By the way, in the field emission electron source 10 of the first embodiment, since the cross-sectional shape of the surface electrode 7 is formed in a rectangular wave shape, the surface electrode 7 may be disconnected. Therefore, the surface electrode 7 is formed only at a portion corresponding to the electron source element 10a, and the surface electrodes 7 arranged in a direction intersecting the lower electrode 12 are shared by bus electrodes that can have a larger film thickness than the surface electrode 7. Although connection may be considered, the thickness of the bus electrode on both side surfaces of each drift portion 6a, both side surfaces of each polycrystalline silicon layer 3 and the side surface of each insulating layer 17 becomes thinner than other portions, resulting in disconnection. There is a risk that it will.
[0066]
On the other hand, the basic configuration of the field emission electron source 10 of the present embodiment is substantially the same as that of the first embodiment, and instead of forming the insulating layers 17 on both sides of the lower electrode 12, FIG. As shown, the width of the lower electrode 12 is made equal to the width of the drift portion 6 and the width of the polycrystalline silicon layer 3, and the periphery of the drift portion 6 (between adjacent drift portions 6 a and the like) and the periphery of the polycrystalline silicon layer 3 (adjacent polycrystalline silicon layer 3). An insulating portion 18 made of an insulating material (for example, a photosensitive material having an insulating property, a nitride having an insulating property, or the like) filling the periphery of the lower electrode 12 (e.g., between adjacent lower electrodes 12) and the periphery of the lower electrode 12. The surface electrode 7 crosses the lower electrode 12 over the drift portion 6 and the insulating portion 18 on the electron passing portion 5 including the drift portion 6, the polycrystalline silicon layer 3, and the insulating portion 18. Lined up in the direction And that point is different. Here, the thickness of the insulating portion 18 is set so that the surface of the insulating portion 18 is flush with the surface of the drift portion 6. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0067]
In the present embodiment, the insulating layer forming step of forming the insulating layer 17 by oxidizing the exposed surface of the lower electrode 12 as in the first embodiment is not required. A conductive material such as a metal or alloy such as Ti, Mo, Cr, Ta, Ni, Al, Cu, Au, and Pt, an intermetallic compound such as silicide, and highly doped polycrystalline silicon may be used. The lower electrode 12 may have a single-layer structure or a multilayer structure. In the present embodiment, as an example, a case where the material of the lower electrode 12 is W and the thickness of the lower electrode 12 is set to about 3000 ° will be described.
[0068]
Hereinafter, a method for manufacturing a field emission electron source according to the present embodiment will be described with reference to FIG.
[0069]
First, a first film forming step of laminating (forming) a conductive layer 12a made of a tungsten film having a predetermined thickness (for example, 3000 °) on the one surface of the insulating substrate 11 by, for example, a sputtering method is performed. 6A is obtained. The conductive layer 12a is for the lower electrode 12, and is patterned into a plurality of lower electrodes 12 in a collective patterning step described later.
[0070]
Subsequently, a second film forming step of laminating (film forming) a semiconductor layer 3a made of a non-doped polycrystalline silicon layer having a predetermined thickness (for example, 1.5 μm) on the conductive layer 12a by a plasma CVD method. As a result, the structure shown in FIG. 6B is obtained. However, in the second film forming step, a state in which a mask material (not shown) made of glass, metal, or the like is arranged on the surface of the conductive layer 12a on the surface of the contact portion of each lower electrode 12 (mask) The semiconductor layer 3a is laminated on the conductive layer 12a in a state where the material is brought into close contact. Therefore, if the mask material is removed after laminating the semiconductor layer 3a on the conductive layer 12a, the surface of the conductive layer 12a that is to be a contact portion in each lower electrode 12 will be exposed. It is not necessary to separately provide a patterning step for exposing the surface of a portion to be a contact portion in the lower electrode 12 after laminating the conductive layer on the conductive layer 12a, and the manufacturing process can be simplified. As the mask material here, for example, if a rectangular frame that covers the entire periphery of the conductive layer 12a is used, the periphery of the conductive layer 12a can be exposed as shown in FIG. it can. The semiconductor layer 3a is the basis of the drift portion 6, and has the same configuration as the drift portion 6 by performing the nanocrystallization process and the oxidation process described in the first embodiment. Further, the method for forming the semiconductor layer 3a in the second film forming step is not limited to the plasma CVD method, but may be an LPCVD method, a catalytic CVD method, or the like.
[0071]
After the above-described semiconductor layer 3a is formed, by performing the nano-crystallization process (nano-crystallization step) described in the first embodiment, many grains 51 (see FIG. 5) of polycrystalline silicon and many silicon A composite nanocrystal layer (hereinafter, referred to as a first composite nanocrystal layer) in which microcrystals 63 (see FIG. 5) are mixed is formed, and then the oxidation process described in the first embodiment is performed. By electrochemically oxidizing the composite nanocrystal layer of No. 1 to form a composite nanocrystal layer (hereinafter, referred to as a second composite nanocrystal layer) 6a having the configuration shown in FIG. 5, FIG. The structure shown in c) is obtained. In FIG. 6C, a portion of the semiconductor layer 3a below the second composite nanocrystal layer 6a is a semiconductor layer 3b. In this embodiment, as in the first embodiment, the semiconductor layer 3a is stacked on the flat conductive layer 12a, and the surface of the semiconductor layer 3a becomes flat regardless of the thickness of the semiconductor layer 3a. Since the semiconductor layer 3a does not have a crack (crack) unlike the related art, it is possible to prevent the problem of electrolyte infiltration through the cracks in the semiconductor layer 3a and to prevent the lower electrode 12 from being electrically conductive. Corrosion of the layer 12a and the insulating substrate 11 can be prevented.
[0072]
After the above-described oxidation process is completed, a plurality of drift portions 6 each composed of a part of the second composite nanocrystal layer and a polycrystal composed of a part of the semiconductor layer 3b are formed on the second composite nanocrystal layer 6a. After performing a mask layer forming step of forming an etching mask layer (not shown) for patterning the silicon layer 3 and the plurality of lower electrodes 12 each formed of a part of the conductive layer 12a, the etching mask layer is masked. By performing a batch patterning step of continuously patterning the second composite nanocrystal layer 6a, the semiconductor layer 3b, and the conductive layer 12a, the drift portion 6, the polycrystalline silicon layer 3, and the lower electrode 12 are patterned. The structure shown in FIG. 6D is obtained by removing the etching mask layer. Here, as a material of the etching mask layer, for example, a photoresist may be used. When a photoresist is used as a material of the etching mask layer, the entire surface on the one surface side of the insulating substrate 11 by spin coating is used. A resist layer is formed on the substrate, and an unnecessary portion of the resist layer is removed by a lithography technique, whereby an etching mask layer including a patterned resist layer can be formed. In the collective patterning step in the present embodiment, unnecessary portions of the second composite nanocrystal layer 6a, the semiconductor layers 3a and 3b, and the conductive layer 12a are removed by highly anisotropic dry etching such as reactive ion etching. The width of the lower electrode 12 below the drift portion 6 is substantially the same as the width of the drift portion 6 and the width of the polycrystalline silicon layer 3. Here, if the material of the semiconductor layer 3a which is the basis of the second composite nanocrystal layer is polycrystalline silicon and the material of the conductive layer 12a is tungsten, a fluorine-based gas (for example, SF) ₆ Gas, etc.), unnecessary portions of the second composite nanocrystal layer 6a and the conductive layer 12a can be continuously dry-etched without changing the etching conditions, thereby improving the throughput and controlling the process. Becomes easier. As described above, if the material of the semiconductor layer 3a which is the basis of the second composite nanocrystal layer 6a is polycrystalline silicon and the material of the conductive layer 12a is tungsten, a mixed acid of hydrofluoric acid and nitric acid is used. Unnecessary portions of the second composite nanocrystal layer 6a and unnecessary portions of the semiconductor layer 3b can be wet-etched to pattern-form the drift portions 6 each of which is a part of the second composite nanocrystal layer. Unnecessary portions of the conductive layer 12a may be wet-etched using the hydrogen peroxide solution with the portion 6 as a mask to pattern-form the lower electrodes 12 each formed of a part of the conductive layer 12a.
[0073]
Thereafter, an insulating material (for example, a photosensitive material having an insulating property, a nitride having an insulating property, or the like) filling the periphery of each lower electrode 12, the periphery of each polycrystalline silicon layer 3, and the periphery of each drift portion 6 is used. The structure shown in FIG. 6E is obtained by performing an insulation separation step of forming the portion 18. By providing such an insulating separation step, it is possible to prevent a short circuit between the surface electrode 7 and the lower electrode 12 irrespective of the pattern of the surface electrode 7 formed in the electrode forming step described later, Unevenness of the exposed surface on the one surface side of the insulating substrate 11 before the formation of the surface electrode 7 can be reduced, and disconnection of the surface electrode 7 can be prevented regardless of the pattern of the surface electrode 7. Incidentally, as a method of forming the insulating portion 18, a resist layer is formed from a photoresist for lift-off on the drift portion 6, and then an insulating layer is formed on the entire surface on the one surface side of the insulating substrate 11 by a vapor deposition method or the like. It is conceivable that the resist layer and the insulator layer on the resist layer are removed by a lift-off method to pattern the insulating portions 18 each of which is a part of the insulator layer. However, when such a lift-off method is employed, there is a problem that the processing becomes difficult when the insulating substrate 11 is enlarged, and a problem that the manufacturing process becomes complicated. On the other hand, in the insulation separation step of the present embodiment, when a photosensitive material having an insulating property is adopted as the insulating material, for example, the photosensitive material is applied to the one surface side of the insulating substrate 11. After that, patterning is performed by photolithography, and then heat treatment is performed to form the insulating portion 18, so that the insulating portion 18 can be formed more easily than when the insulating portion 18 is formed using a lift-off method. . Further, in the insulation separation step in this embodiment, when, for example, a nitride having an insulating property is adopted as the insulating material, the periphery of each lower electrode 12, the periphery of each polycrystalline silicon layer 3, and the Since the insulating portion 18 is formed by embedding a paste containing particles of nitride in the periphery by a printing method and then performing a heat treatment, the insulating portion 18 is formed as compared with the case where the insulating portion 18 is formed using a lift-off method. It can be easily formed.
[0074]
After the insulating portion 18 is formed, an electrode forming step of forming a surface electrode 7 made of a gold thin film by, for example, a vapor deposition method is performed. Subsequently, pads 28 are formed on both end portions of each surface electrode 7 and each lower electrode is formed. By performing a pad forming step of forming pads 27 on both ends of the electrode 12, the field emission electron source 10 having the structure shown in FIG. 6F is obtained. In the pad forming step, since the pad 28 electrically connected to the surface electrode 7 is formed at a position overlapping the insulating portion 18, disconnection between the surface electrode 7 and the pad 28 is prevented. be able to.
[0075]
The field emission type electron source 10 of the present embodiment manufactured by the manufacturing method described above can prevent the problem that the electrolytic solution penetrates through the cracks formed in the semiconductor layer 3a in the nanocrystallization step. In addition, the yield during manufacturing can be improved, and long-term reliability can be improved. In addition, it is possible to prevent the conductive layer 12a for the lower electrode 12 and the insulating substrate 11 from being corroded by the electrolytic solution in the nano crystallization step, and the lower electrode 12 is peeled off from the insulating substrate 11. Also, it is possible to prevent the polycrystalline silicon layer 3 on the lower electrode 12 from peeling off from the lower electrode 12.
[0076]
In the batch patterning step, unnecessary portions of the second composite nanocrystal layer 6a, the semiconductor layer 3b, and the conductive layer 12a are dry-etched, so that each drift portion 6, each polysilicon layer 3, and each lower electrode 12 are etched. Since the pattern is formed, the reproducibility of the shape of each drift portion 6, each polycrystalline silicon layer 3, and each lower electrode 12 patterned in the collective patterning step can be improved.
[0077]
In the above-described embodiment, the surface electrode 7 is formed in a direction intersecting the lower electrode 12, but the surface electrode 7 is formed only in a portion corresponding to the electron source element 10a, and is formed in a direction intersecting the lower electrode 12. Needless to say, the surface electrodes 7 arranged in a row may be commonly connected by a bus electrode whose film thickness can be made larger than that of the surface electrodes 7.
[0078]
(Embodiment 3)
In the field emission electron source 10 according to the second embodiment, a part of the drift portion 6 is formed between the electron source elements 10 a adjacent to each other in the longitudinal direction of the lower electrode 12. There is a possibility that electrical insulation between the adjacent electron source elements 10a becomes insufficient and crosstalk occurs. On the other hand, the field emission type electron source 10 of the present embodiment is different in that the periphery of each electron source element 10a is surrounded by an insulating portion 18 as shown in FIG. That is, the present embodiment is different from the second embodiment in that the insulating part 18 is also formed between the electron source elements 10 a adjacent to each other in the longitudinal direction of the lower electrode 12.
[0079]
The manufacturing method of the field emission electron source 10 of the present embodiment is substantially the same as the manufacturing method described in the second embodiment, and is patterned by the collective patterning step between the collective patterning step and the insulating separation step. The only difference is that an etching step of etching a portion of the drift portion 6 between the portions corresponding to the electron source elements 10a until the lower electrode 12 is exposed is provided.
[0080]
Thus, in the field emission type electron source 10 manufactured by the manufacturing method of the present embodiment, the adjacent electron source elements 10a can be more reliably insulated from each other, and the electron emission characteristics of each electron source element 10a can be improved. Can be improved.
[0081]
(Embodiment 4)
The configuration of the field emission electron source 10 of the present embodiment is the same as that of the second embodiment, except for the manufacturing method.
[0082]
In the manufacturing method of this embodiment, a large-area substrate on which a plurality of field emission electron sources 10 can be formed as shown in FIG. 9 is used as the insulating substrate 11 before the formation of the conductive layer 12a. This is also characterized in that a dividing step for dividing the insulating substrate 11 into a size corresponding to the field emission electron source 10 later is provided.
[0083]
Thus, according to the manufacturing method of the present embodiment, the manufacturing cost can be reduced. Further, the manufacturing method of the present embodiment includes an etching step of exposing a part of the lower electrode 12 by etching a part of the second composite nanocrystal layer 6 after the insulating film forming step. There is an advantage that it is not necessary to pattern the conductive layer 12a when forming the conductive layer 12a.
[0084]
By the way, in the manufacturing method of the present embodiment, before the second film forming step, the conductive layer 12a laminated on the large-area substrate (insulating substrate 11) by the first film forming step is shown in FIG. As described above, a separation step is provided in which each of the regions corresponding to each field emission type electron source 10 (in the illustrated example, four regions) is electrically separated. Since the first composite nanocrystal layer is individually formed on the portion overlapping with each of the separated conductive layers 12a, the voltage drop in the conductive layer 12a can be reduced, and the first composite nanocrystal can be reduced. The in-plane uniformity of the layer can be improved. That is, in the nanocrystallization step of the present embodiment, the first composite nanocrystal layer is formed only in a region of the semiconductor layer 3a corresponding to each of the field emission electron sources 10, so that the conductive layer 12a Voltage drop can be reduced, the in-plane uniformity of the first composite nanocrystal layer can be improved, and as a result, the in-plane uniformity of the second composite nanocrystal layer 6a can be improved. Can be.
[0085]
In the nano-crystallization step of the present embodiment, as shown in FIG. 11, a rectangular frame-shaped seal wall 41 is adhered to the front surface side of each conductive layer 12a separated in the separation step, so that 55 wt% Of the mixed solution obtained by mixing approximately 1: 1 of an aqueous hydrogen fluoride solution and ethanol, and using the conductive layer 12a as an anode, a cathode 42 formed of a platinum electrode is formed on the semiconductor layer 3a in the electrolyte B. A constant current is supplied between the anode (conductive layer 12a) and the cathode 42 from the power supply 43 while irradiating the main surface of the semiconductor layer 3a with a light source composed of a 500 W tungsten lamp (not shown) arranged oppositely. Is flowed for a predetermined time to form the first composite nanocrystal layer. However, in the nano-crystallization step of the present embodiment, the first composite nano-crystal layer is sequentially formed on a portion of the semiconductor layer 3a that overlaps each of the conductive layers 12a separated in the separation step. Power consumption in the crystallization step can be reduced.
[0086]
Note that, as in the present embodiment, a large-area substrate on which a plurality of field emission electron sources 10 can be formed is used as the insulating substrate 11 before the formation of the conductive layer 12a, and the insulating substrate is formed after the electrode forming step. The technical idea of providing a dividing step for dividing the electron beam 11 into a size corresponding to the field emission electron source 10 can be applied to other embodiments.
[0087]
【The invention's effect】
According to the invention of claim 1, a large number of electron source elements are arranged in a matrix on one surface side of an insulating substrate, and each electron source element has a lower electrode on the one surface of the insulating substrate, From the surface electrode opposed to the lower electrode in the thickness direction, the number of semiconductor microcrystals interposed between the lower electrode and the surface electrode, and a number of nanometer-order semiconductor microcrystals, and the crystal grain size of the semiconductor microcrystals formed on the surface of each semiconductor microcrystal. A method of manufacturing a field emission type electron source comprising a drift portion having a large number of insulating films having a small thickness, wherein a conductive layer for a lower electrode is laminated on the one surface of the insulating substrate. A second film-forming step of laminating a semiconductor layer serving as a basis for a drift portion on a conductive layer, and nano-crystallizing the semiconductor layer using an electrolytic solution to produce a large number of nanometer-order semiconductors. First composite having microcrystals A nano-crystallization step of forming a semiconductor crystal layer, and forming an insulating film having a thickness smaller than the crystal grain size of the semiconductor micro crystal on the surface of each semiconductor micro crystal, thereby forming a large number of semiconductor micro crystals and a large number of insulating layers. An insulating film forming step of forming a second composite nanocrystal layer having a film, and an unnecessary portion of the second composite nanocrystal layer and the conductive layer are continuously etched to form the second composite nanocrystal layer. Since the method includes a batch patterning step of patterning a drift part composed of a part and a lower electrode composed of a part of each conductive layer, and an electrode forming step of forming a surface electrode on the drift part, a lower part is formed in the nanocrystallization step. It is possible to prevent the conductive layer for the electrode and the insulating substrate from being corroded by the electrolytic solution, so that the lower electrode is peeled off from the insulating substrate or the layer on the lower electrode is a lower electrode. Peeling the can be prevented, there is an effect that can be improved long-term reliability is possible to improve the yield in manufacturing.
[0088]
According to a second aspect of the present invention, in the first aspect of the present invention, in the second film forming step, a mask material is disposed on a surface of a portion of the conductive layer that becomes a contact portion in each of the lower electrodes. Since the semiconductor layer is laminated on the conductive layer, if the mask material is removed after laminating the semiconductor layer on the conductive layer, the surface of a portion of the conductive layer serving as a contact portion in each of the lower electrodes is removed. Since the semiconductor layer is exposed, there is no need to separately provide a patterning step for exposing the surface of a portion serving as a contact portion in the lower electrode after laminating the semiconductor layer on the conductive layer, thereby simplifying the manufacturing process. There is an effect that can be achieved.
[0089]
According to a third aspect of the present invention, in the first or second aspect of the invention, in the collective patterning step, unnecessary portions of the second composite nanocrystal layer and the conductive layer are dry-etched to form the drift portions. In addition, since the lower electrodes are patterned, the reproducibility of the shapes of the drift portions and the lower electrodes patterned in the collective patterning step can be improved.
[0090]
According to a fourth aspect of the present invention, in the third aspect of the present invention, in the first film forming step, tungsten is adopted as a material of the conductive layer laminated on the one surface of the insulating substrate, and the second Polycrystalline silicon is adopted as a material of the semiconductor layer to be laminated on the conductive layer in the film forming step, and unnecessary portions of the second composite nanocrystal layer and the conductive layer are dry-etched in the collective patterning step. In this case, since a fluorine-based gas is used as an etching gas, unnecessary portions of the second composite nanocrystal layer and the conductive layer can be continuously dry-etched without changing etching conditions, thereby improving throughput. And the process management becomes easy.
[0091]
According to a fifth aspect of the present invention, in the first or second aspect of the present invention, in the collective patterning step, unnecessary portions of the second composite nanocrystal layer and the conductive layer are wet-etched to form the drift portions. Also, since the lower electrodes are formed in a pattern, a vacuum device such as a dry etching device is not required unlike the case where the unnecessary portion of the second composite nanocrystal layer and the unnecessary portion of the conductive layer are dry-etched. The cost of the device can be reduced, and this is advantageous particularly when the area of the insulating substrate is increased.
[0092]
According to a sixth aspect of the present invention, in the invention of the fifth aspect, in the collective patterning step, an etching condition is set such that the lower electrode below the drift portion is side-etched, so that the surface formed in the electrode forming step is formed. There is an effect that a short circuit between the surface electrode and the lower electrode can be prevented regardless of the electrode pattern.
[0093]
According to a seventh aspect of the present invention, in the first to sixth aspects of the present invention, the material of the conductive layer to be laminated on the one surface of the insulating substrate in the first film forming step is easily oxidized and is oxidized. An insulating layer made of an oxide of the conductive material is formed by oxidizing an exposed surface of the lower electrode between the collective patterning step and the electrode forming step using a conductive material having an insulating property. Since the insulating layer is formed on the exposed surface of the lower electrode before the surface electrode is formed in the electrode forming step, the insulating layer can be formed on the exposed surface of the lower electrode. Irrespective of the pattern, there is an effect that a short circuit between the surface electrode and the lower electrode can be prevented.
[0094]
The invention according to claim 8 is the invention according to claim 1 to claim 6, wherein the material of the conductive layer to be laminated on the one surface of the insulating substrate in the first film forming step is easily oxidized and oxidized. Since the object uses a conductive material having an insulating property, and in the insulating film forming step, a rapid thermal oxidation method in an oxidizing gas atmosphere is employed, an insulating film is formed on the surface of each of the semiconductor microcrystals. In addition, since an insulating layer made of the oxide of the conductive material can be formed on the exposed surface of the lower electrode, it is not necessary to provide a separate process for forming the insulating layer on the exposed surface of the lower electrode. Thus, there is an effect that the number of steps can be reduced as compared with the invention of claim 7.
[0095]
According to a ninth aspect of the present invention, in the first to eighth aspects of the present invention, an insulating material that fills the periphery of each lower electrode and the periphery of each drift portion is provided between the collective patterning step and the electrode forming step. Since an insulating separation step of forming an insulating portion is provided, it is possible to prevent a short circuit between the surface electrode and the lower electrode regardless of the pattern of the surface electrode formed in the electrode forming step, and Unevenness of the exposed surface on the one surface side of the insulating substrate before the formation of the surface electrode can be reduced, and disconnection of the surface electrode can be prevented regardless of the pattern of the surface electrode. .
[0096]
According to a tenth aspect of the invention, in the ninth aspect of the invention, in the insulation separating step, a photosensitive material having an insulating property is adopted as the insulating material, and the photosensitive material is applied to the one surface side of the insulating substrate. Thereafter, patterning is performed by photolithography to form an insulating portion. Therefore, there is an effect that the insulating portion can be easily formed as compared with a case where the insulating portion is formed using a lift-off method.
[0097]
According to an eleventh aspect of the present invention, in the ninth aspect of the invention, in the insulating isolation step, nitride is adopted as the insulating material, and nitride particles are included around each of the lower electrodes and around each of the drift portions. Since the insulating portion is formed by embedding the paste by the printing method, there is an effect that the insulating portion can be easily formed as compared with the case where the insulating portion is formed by using the lift-off method.
[0098]
According to a twelfth aspect of the present invention, in the ninth to eleventh aspects of the present invention, after the electrode forming step, a plurality of pads electrically connected to the surface electrode are formed at positions overlapping the insulating portion. Since the process is provided, there is an effect that disconnection between the surface electrode and the pad can be prevented.
[0099]
According to a thirteenth aspect of the present invention, in the first to twelfth aspect of the present invention, in the nano-crystallization step, a cathode is arranged to face the semiconductor layer in the electrolytic solution so that the conductive layer serves as an anode, Since a current flows from the entire periphery of the conductive layer when a current flows between the cathode and the cathode, the conductive layer flows when a current flows between the anode and the cathode in the nanocrystallization step. This has the effect of reducing the voltage drop due to the electric resistance of the first composite nanocrystal layer and improving the in-plane uniformity of the first composite nanocrystal layer.
[0100]
According to a fourteenth aspect, in the first to thirteenth aspects, the insulating film forming step is an electrochemical oxidation step, and the first composite nanocrystal layer is formed in an oxidizing electrolyte. After a cathode is arranged oppositely, a constant current is passed between the anode and the cathode using the conductive layer as the anode, and after the voltage between the anode and the cathode increases by a specified amount, the voltage between the anode and the cathode is increased. Since the oxidation is terminated when the current decreases to a predetermined value while maintaining the voltage after the increase, a constant current is passed between the anode and the cathode, and the voltage between the anode and the cathode increases by a specified amount. As compared with the case where the oxidation is sometimes terminated, there is an effect that the withstand voltage of each of the electron source elements is improved.
[0101]
According to a fifteenth aspect of the present invention, in the invention of the ninth to twelfth aspects, the drift portion patterned by the collective patterning step corresponds to the electron source element between the collective patterning step and the insulating separation step. Since an etching step for etching the portion between the portions to be exposed is performed until the lower electrode is exposed, it is possible to more reliably insulate between adjacent electron source elements and improve the electron emission characteristics of each electron source element. effective.
[0102]
According to a sixteenth aspect of the present invention, in the first aspect, a large-area substrate on which a plurality of the field emission electron sources can be formed is used as the insulating substrate before the formation of the conductive layer. Since the method further includes a dividing step of dividing the insulating substrate into a size corresponding to the field emission electron source later, there is an effect that the manufacturing cost can be reduced.
[0103]
According to a seventeenth aspect, in the sixteenth aspect, an etching step of exposing a part of the lower electrode by etching a part of the second composite nanocrystal layer after the insulating film forming step Therefore, there is an advantage that it is not necessary to pattern the conductive layer when forming the conductive layer.
[0104]
In the invention according to claim 18, in the invention according to claim 16, in the nanocrystallization step, the first composite nanocrystal layer is formed only in a region of the semiconductor layer corresponding to each of the field emission electron sources. Therefore, it is possible to reduce a voltage drop in the conductive layer and to improve an in-plane uniformity of the first composite nanocrystal layer.
[0105]
According to a nineteenth aspect, in the sixteenth aspect, prior to the second film forming step, the conductive layer laminated on the large-area substrate by the first film forming step is formed by the electric field emission type. The semiconductor device further includes a separation step of electrically separating the regions corresponding to the electron sources, and in the nano crystallization step, a portion of the semiconductor layer overlapping each of the conductive layers separated in the separation step Since the first composite nanocrystal layer is individually formed, a voltage drop in the conductive layer can be reduced, and the in-plane uniformity of the first composite nanocrystal layer can be improved. effective.
[0106]
In a twentieth aspect of the present invention, in the nineteenth aspect of the present invention, in the nano crystallization step, the first composite nano layer is formed on a portion of the semiconductor layer overlapping each of the conductive layers separated in the separation step. Since the crystal layers are sequentially formed, there is an effect that power consumption in the nano crystallization step can be reduced.
[Brief description of the drawings]
FIG. 1 is a main process sectional view for explaining a method of manufacturing a field emission electron source according to a first embodiment.
FIG. 2 is a main process plan view for explaining a method of manufacturing the field emission electron source in the above.
FIG. 3 is an explanatory diagram of a method for manufacturing the field emission electron source in the above.
FIGS. 4A and 4B show the field emission electron source in the above embodiment, wherein FIG. 4A is a schematic plan view and FIG.
FIG. 5 is a schematic configuration diagram of a main part of the field emission electron source in the above.
FIG. 6 is a cross-sectional view of a main process for describing a method for manufacturing a field emission electron source according to the second embodiment.
7A and 7B show the field emission type electron source in the above embodiment, wherein FIG. 7A is a schematic plan view, and FIG.
FIG. 8 is a schematic plan view showing a field emission electron source according to a third embodiment.
FIG. 9 is a main process plan view for describing the method for manufacturing the field emission electron source according to the fourth embodiment.
FIG. 10 is a main process plan view for describing the method for manufacturing the field emission electron source in the above.
FIG. 11 is an explanatory diagram of the method for manufacturing the field emission electron source in Embodiment 1;
FIG. 12 is an operation explanatory view of a field emission type electron source showing a conventional example.
FIG. 13 is an operation explanatory view of a field emission type electron source showing another conventional example.
FIG. 14 is a schematic configuration diagram of a display to which the above is applied.
FIG. 15 is a schematic perspective view of a field emission electron source in a display to which the above is applied.
16A and 16B show a field emission type electron source in a display to which the above is applied, FIG. 16A is a schematic plan view, FIG. 16B is a cross-sectional view taken along line AA ′ of FIG. FIG. 14 is a sectional view taken along the line B-B ′.
FIG. 17 is a main process sectional view for describing the method of manufacturing the field emission electron source in the display to which the above is applied.
FIG. 18 is a cross-sectional view showing main processes for describing a method of manufacturing the field emission electron source in the display to which the above is applied.
[Explanation of symbols]
3 Polycrystalline silicon layer
3a Semiconductor layer
3b Semiconductor layer
6 Drift section
6a Second composite nanocrystal layer
7 Surface electrode
10. Field emission electron source
10a electron source element
11 Insulating substrate
12 lower electrode
12a conductive layer
17 Insulating layer
27 pads
28 pads
51 Grain
52 silicon oxide film
63 Silicon microcrystal
64 silicon oxide film

Claims (20)

A large number of electron source elements are arranged in a matrix on one surface side of the insulating substrate, and each electron source element faces the lower electrode on the one surface of the insulating substrate and the lower electrode in the thickness direction of the insulating substrate. A surface electrode, a large number of semiconductor microcrystals interposed between the lower electrode and the surface electrode and having a film thickness smaller than the crystal grain size of the semiconductor microcrystals formed on the surface of each of the semiconductor microcrystals of the order of many nanometers and each semiconductor microcrystal. A method for manufacturing a field emission type electron source including a drift portion having an insulating film, wherein a first film forming step of laminating a conductive layer for a lower electrode on the one surface of the insulating substrate; A second film forming step of laminating a semiconductor layer serving as a basis for a drift portion on the conductive layer, and a first step of forming a plurality of semiconductor microcrystals on the order of nanometers by nanocrystallizing the semiconductor layer using an electrolytic solution. Form composite nanocrystal layers A second step of forming a second crystal having a large number of semiconductor microcrystals and a large number of insulating films by forming a nanocrystallizing step and forming an insulating film having a thickness smaller than the crystal grain size of the semiconductor microcrystals on the surface of each semiconductor microcrystal; An insulating film forming step of forming the composite nanocrystal layer, and a drift portion formed by continuously etching unnecessary portions of the second composite nanocrystal layer and the conductive layer, each of which is formed by a part of the second composite nanocrystal layer. A method of manufacturing a field emission type electron source, comprising: a collective patterning step of patterning a lower electrode formed of a part of a conductive layer; and an electrode forming step of forming a surface electrode on a drift portion. In the second film forming step, the semiconductor layer is laminated on the conductive layer in a state where a mask material is arranged on a surface of a portion of the conductive layer that becomes a contact portion in each of the lower electrodes. The method for manufacturing a field emission electron source according to claim 1. The said collective patterning process WHEREIN: The said each drift part and each said lower electrode are pattern-formed by dry-etching the unnecessary part of the said 2nd composite nanocrystal layer and the said conductive layer, The characterized by the above-mentioned. A method for manufacturing a field emission type electron source according to claim 2. The semiconductor layer, which employs tungsten as a material of the conductive layer to be laminated on the one surface of the insulating substrate in the first film forming step, and which is laminated to the conductive layer in the second film forming step Wherein polycrystalline silicon is used as a material for the second step, and in the collective patterning step, a fluorine-based gas is used as an etching gas when dry-etching unnecessary portions of the second composite nanocrystal layer and the conductive layer. The method for manufacturing a field emission electron source according to claim 3. The said collective patterning process WHEREIN: Unnecessary part of the said 2nd composite nanocrystal layer and the said conductive layer is wet-etched, and each said drift part and each said lower electrode are pattern-formed, The characterized by the above-mentioned. A method for manufacturing a field emission type electron source according to claim 2. 6. The method according to claim 5, wherein in the collective patterning step, etching conditions are set so that the lower electrode below the drift portion is side-etched. In the first film forming step, a material that is easily oxidized as the material of the conductive layer to be laminated on the one surface of the insulating substrate and the oxide is a conductive material having an insulating property; The method according to claim 1, further comprising an insulating layer forming step of oxidizing an exposed surface of the lower electrode to form an insulating layer made of an oxide of the conductive material, between the electrode forming step. 7. The method for manufacturing a field emission electron source according to any one of 6. In the first film forming step, a conductive material which is easily oxidized and the oxide has an insulating property is used as a material of the conductive layer to be laminated on the one surface of the insulating substrate, and in the insulating film forming step, 7. The method for manufacturing a field emission type electron source according to claim 1, wherein a rapid thermal oxidation method in an oxidizing gas atmosphere is employed. The method according to claim 1, further comprising an insulation separating step of forming an insulating portion made of an insulating material that fills a periphery of each of the lower electrodes and a periphery of each of the drift portions, between the collective patterning step and the electrode forming step. A method for manufacturing a field emission electron source according to any one of claims 1 to 8. In the insulating separation step, a photosensitive material having an insulating property is adopted as the insulating material, and the photosensitive material is applied to the one surface side of the insulating substrate and then patterned by photolithography to form an insulating portion. The method for manufacturing a field emission electron source according to claim 9, wherein: In the insulating separation step, a nitride containing particles of nitride is adopted by a printing method by adopting nitride as the insulating material, and surrounding the respective lower electrodes and the periphery of the respective drift portions by a printing method, thereby forming an insulating portion. The method for manufacturing a field emission electron source according to claim 9. 12. The method according to claim 9, further comprising, after the electrode forming step, a pad forming step of forming a plurality of pads electrically connected to the surface electrode at positions overlapping the insulating portion. 3. The method for manufacturing a field emission electron source according to claim 1. In the nano-crystallization step, a cathode is disposed opposite to the semiconductor layer in the electrolytic solution, the conductive layer is used as an anode, and a current flows between the anode and the cathode. The method for manufacturing a field emission electron source according to claim 1, wherein a current flows from all around. The insulating film forming step is an electrochemical oxidation step in which a cathode is disposed to face the first composite nanocrystal layer in an oxidizing electrolyte, and then the conductive layer is used as an anode and an anode and a cathode. When a constant current flows during the time, after the voltage between the anode and the cathode increases by a specified amount, when the voltage between the anode and the cathode is maintained at the increased voltage and the current decreases to a predetermined value 14. The method according to claim 1, wherein the oxidation is terminated. An etching step of etching a portion of the drift portion patterned by the batch patterning step between portions corresponding to the electron source elements until the lower electrode is exposed, between the batch patterning step and the insulation separation step; The method for manufacturing a field emission type electron source according to any one of claims 9 to 12, comprising: A large-area substrate on which a plurality of the field emission type electron sources can be formed is used as the insulating substrate before the formation of the conductive layer, and the field emission type electron source is used after the electrode forming step. 2. The method for manufacturing a field emission electron source according to claim 1, further comprising a dividing step of dividing the electron source into a size corresponding to the following. 17. The electric field emission according to claim 16, further comprising an etching step of exposing a part of the lower electrode by etching a part of the second composite nanocrystal layer after the insulating film forming step. Method of manufacturing a type electron source. 17. The field emission type according to claim 16, wherein in the nano crystallization step, the first composite nanocrystal layer is formed only in a region of the semiconductor layer corresponding to each of the field emission type electron sources. Manufacturing method of electron source. Before the second film forming step, the conductive layer laminated on the large-area substrate in the first film forming step is divided into regions corresponding to the respective field emission electron sources and electrically separated. And forming the first composite nanocrystal layer individually on a portion of the semiconductor layer that overlaps with each of the conductive layers separated in the separation process in the nanocrystallization step. 17. The method for manufacturing a field emission electron source according to claim 16, wherein: 20. The nanocrystallizing step, wherein the first composite nanocrystal layer is sequentially formed on a portion of the semiconductor layer overlapping each of the conductive layers separated in the separation step. A method for manufacturing the field emission electron source according to the above.

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