JP2004259442A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a dynamic RAM having configuration sufficiently exhibiting an hierarchial structure effect. <P>SOLUTION: A first memory array is constituted by providing a plurality of first memory cells at the intersections of a plurality of first bit lines intersecting a plurality of first sub-word lines corresponding to first main word lines. A second memory array is constituted by providing a plurality of second memory cells at the intersections of a plurality of second bit lines intersecting a plurality of second sub-word lines corresponding to second main word lines. Furthermore, a semiconductor device is provided with: a first and a second sub-common IO line extended in a first direction and connected to the plurality of first bit lines and the plurality of second bit lines, respectively; main IO lines extended in a second direction intersecting the first direction and connected, through a first and a second switch circuit, to the first and the second sub-common IO line; and a first and a second amplifier circuit between the first and the second sub-common IO line and the main IO lines. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, for example, to a large capacity dynamic RAM (random access memory) and a technique particularly effective when used for further speeding up, high integration, large scale, and low cost.

  A dynamic type having a memory array including a plurality of word lines and bit lines arranged orthogonally to each other and a large number of dynamic memory cells arranged in a grid at intersections of these word lines and bit lines as its basic constituent elements There is a semiconductor storage device such as a RAM. In recent years, high integration and large scale of dynamic RAMs and the like have been remarkable, and various technologies for further promoting such integration have been disclosed.

That is, for example, on February 24, 1993, "ISSC (International Solid-State Circuits Conference) '93 Digest of Technical Papers (Session 3) Session (Session 3). On pages 50 to 51, the main word lines are arranged in parallel with the sub word lines and at a pitch of an integral multiple of the main word lines, so that the wiring pitch of the metal wiring layer serving as the main word lines is relaxed. A so-called hierarchical word line structure has been proposed which can promote high integration. In addition, for example, Japanese Patent Publication No. 4-59712 discloses that a designated bit line is connected to a main common IO line via a relatively short sub-common IO line to reduce the load on a sense amplifier, and a dynamic RAM. A so-called hierarchical IO structure capable of speeding up a read operation such as the above has been proposed. Further, U.S. Pat. No. 5,274,595, issued Dec. 28, 1993, connects between a sub-common IO line and a main common IO line via a plurality of direct-sense type sub-amplifiers which are driven by addition. A method of increasing the speed of a dynamic RAM or the like while suppressing an increase in layout area due to the provision of a plurality of sub-amplifiers by arranging the sub-amplifiers in the intersection region of the arrangement region of the word line shunt portion and the sense amplifier is proposed. Have been.
ISSC '93 Digest of Technical Papers Session 3 (ISSC: International Solid-State Circuits Conference '93 Digest of Technical Papers Session 3), pages 50-51, February 24, 1993.

  However, in the first conventional example employing the hierarchical word line structure, a row selection signal transmitted via a main word line and a word line driving current supply signal line which is orthogonally arranged on a sub word line are transmitted. The word line drive circuit for selectively setting a corresponding sub-word line to a selected state in accordance with a word line drive current supply signal is a so-called self-boot type. A predetermined time is required until the current supply signal is set to an effective level, which limits the speeding up of the access time in a read mode such as a dynamic RAM and the like. And the load of the access time is increased, which also prevents the access time from being shortened. Further, in the second conventional example employing the hierarchical IO structure, since the word lines are not formed in a hierarchical structure, the arrangement pitch of the metal wiring layers serving as the word lines becomes difficult, thereby restricting the high integration of a dynamic RAM or the like. Receive. Further, in the third embodiment in which the sub-common IO line and the main common IO line are connected via a plurality of direct sense type sub-amplifiers which are driven by addition, the word line division by the word shunt method is performed but the hierarchical word Since a line structure is not adopted, high integration of a dynamic RAM or the like is restricted, and a sub-common IO line and a main common IO line are arranged with the same length, so that there is no substantial hierarchical IO structure.

  That is, in the conventional dynamic RAM or the like, a hierarchical structure having various effects is partially and sporadically employed, and there is no comprehensive adoption for all of the word lines, bit lines, and common IO lines. However, as a result, the effect of the hierarchical structure cannot be sufficiently brought out, and the speed up, high integration, large scale, and low cost of the dynamic RAM and the like are comprehensively limited. is there.

  An object of the present invention is to realize a dynamic RAM or the like having a configuration capable of sufficiently exhibiting the effect of the hierarchical structure, and to further increase the speed, integration, scale, and cost of the dynamic RAM as a whole. It is to plan.

  The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

  The outline of a representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a plurality of first memory cells are provided at intersections of a plurality of first bit lines intersecting with a plurality of first sub-word lines corresponding to the first main word line to form a first memory array, and a second main word is provided. A plurality of second memory cells are provided at intersections of a plurality of second bit lines intersecting with a plurality of second sub-word lines corresponding to the lines to form a second memory array, and the plurality of first bit lines and the second First and second sub-common IO lines connected to bit lines and extending in a first direction are provided, and the first and second sub-common IO lines are connected to the first and second sub-common IO lines via first and second switch circuits in the first direction. A main IO line extending in a second direction intersecting with the first and second sub-common IO lines, and first and second amplifier circuits between the main IO line and the first and second sub-common IO lines.

  A dynamic RAM having a configuration capable of sufficiently exhibiting the effect of the hierarchical structure can be obtained.

  FIG. 1 is a block diagram showing one embodiment of a dynamic RAM (semiconductor storage device) to which the present invention is applied. First, an outline of the configuration and operation of the dynamic RAM according to this embodiment will be described with reference to FIG. The circuit elements constituting each block in FIG. 1 are a known MOSFET (Metal Oxide Semiconductor Field Effect Transistor; in this specification, a MOSFET is a generic term for an insulated gate field effect transistor) integrated circuit. It is formed on one semiconductor substrate such as single crystal silicon by a manufacturing technique. In the following drawings, names of terminals and signal lines are used repeatedly as names of signals transmitted through these terminals or signal lines or wirings thereof unless otherwise specified. Further, in the following circuit diagrams, MOSFETs having an arrow at the channel (back gate) portion are of a P-channel type, and are distinguished from N-channel MOSFETs without an arrow.

  In FIG. 1, the dynamic RAM of this embodiment has four memory blocks MB0 to MB3 as its basic constituent elements, and these memory blocks are represented by an X address as shown by the memory block MB1 in FIG. It includes a pair of memory mats MATL and MATR sandwiching decoder XD, main amplifiers MAL and MAR provided corresponding to these memory mats, and Y address decoders YDL and YDR, respectively. Among them, the X address decoder XD is supplied with i + 1 bit internal address signals X0 to Xi from the X address buffer XB, and the Y address decoders YDL and YDR are supplied with i + 1 bit internal address signals Y0 to Y0 from the Y address buffer YB. Yi is commonly supplied. Further, the X address signals AX0 to AXi and the Y address signals AY0 to AYi are supplied to the X address buffer XB and the Y address buffer YB in a time division manner through address input terminals A0 to Ai. Further, main amplifiers MAL and MAR are coupled to one input / output terminal of a corresponding unit circuit of data input / output circuit IO via 8-bit internal data buses IOB0 to IOB7, and the other input / output terminals of these unit circuits are connected. The terminals are coupled to corresponding data input / output terminals IO0-IO7.

  Here, the memory mats MATL and MATR forming the memory blocks MB0 to MB3 each include 64 sub-memory mats arranged in a lattice, as described later, and these sub-memory mats are orthogonal to each other. A memory array including a predetermined number of sub-word lines and sub-bit lines, and a large number of dynamic memory cells arranged in a grid at the intersections of these sub-word lines and sub-bit lines; And a sense amplifier including a unit amplifier circuit and a column selection switch provided corresponding to the sub-bit line, and a designated sub-bit line is selected via a column selection switch. And a sub-common IO line to be electrically connected. On the upper layer of the 64 sub-memory mats arranged in a lattice, a main word line starting from the X address decoder XD and a bit line selection signal (column selection signal starting from the Y address decoder YDL or YDR) ) Are arranged orthogonal to each other, and a predetermined number of main common IO lines starting from the main amplifier MAL or MAR are arranged in parallel with these bit line selection signals. The specific configuration, operation, arrangement, and the like of the memory blocks MB0 to MB3 and the sub memory mats forming each memory block will be described later in detail.

  The X address buffer XB and the Y address buffer YB take in and hold the X address signals AX0 to AXi or the Y address signals AY0 to AYi input in a time division manner through the address input terminals A0 to Ai, and hold these X addresses. The internal address signals X0 to Xi or Y0 to Yi are formed based on the address signal or the Y address signal and supplied to the X address decoder XD or the Y address decoders YDL and YDR of the memory blocks MB0 to MB3. The uppermost bit internal address signals Xi and Yi are also supplied to the memory block selection circuit BS.

  The X address decoder XD decodes the internal address signals X0 to Xi supplied from the X address buffer XB, and selectively sets the corresponding main word line to a valid level. The Y address decoders YDL and YDR decode the internal address signals Y0 to Yi supplied from the Y address buffer YB, and selectively set corresponding bits of the bit line selection signal to an effective level, that is, a selection level. In this embodiment, the main word line is a complementary signal line including non-inverted and inverted signal lines, as described later. Further, the main word lines are arranged at a pitch X times, that is, eight times, the pitch of the sub word lines constituting the sub memory mat, and the bit line selection signals are arranged at a pitch Y times, that is, four times the sub bit line. For this reason, the sub-word line driving unit of the sub-memory mat is provided with a row selection signal transmitted through a corresponding 64-bit main word line and a sub-word line driving signal transmitted through an 8-bit sub-word line driving signal line described later. And a unit sub-word line driving circuit for selectively setting a corresponding sub-word line to a selected state in accordance with a signal, and a part of internal address signals X0 to Xi supplied to X address decoder XD includes a sub-word line driving signal. Is selectively provided as an effective level. Further, the sense amplifiers of the sub-memory mats are selectively turned on at the same time by four pairs in response to the valid level of the corresponding bit line selection signal, and connect between the corresponding four pairs of complementary bit lines and the sub-common IO lines. Includes a switch MOSFET for selectively connecting.

  Next, when the dynamic RAM is set to the write mode, the main amplifiers MAL and MAR transfer the write data supplied from the data input / output terminals IO0 to IO7 via the data input / output circuit IO and the internal data buses IOB0 to IOB7. , Via the main common IO line, the sub main amplifier and the sub common IO line, to write to the selected eight memory cells of the specified sub memory mat of the memory mat MATLAB or matr. Further, when the dynamic RAM is set to the read mode, the selected eight memory cells of the specified sub memory mat of the memory mat MATL or MATR are connected via the sub common IO line, the sub main amplifier and the main common IO line. The output read signal is amplified and transmitted to the corresponding unit circuit of the data input / output circuit IO via the internal data buses IO0 to IO7. These read signals are output from each unit circuit of the data input / output circuit IO to the outside of the dynamic RAM via the data input / output terminals IO0 to IO7.

  The memory block selection circuit BS decodes the internal address signals Xi and Yi of the most significant bits supplied from the X address buffer XB and the Y address buffer YB, and selectively sets the memory block selection signals BS0 to BS3 (not shown) to an effective level. And These memory block selection signals are supplied to corresponding memory blocks MB0 to MB3, and are provided for selectively activating them.

  The timing generation circuit TG outputs a row address strobe signal RASB supplied from the outside as a start-up control signal. The same applies hereinafter), various internal control signals are selectively formed based on the column address strobe signal CASB and the write enable signal WEB, and supplied to each section of the dynamic RAM. Further, the internal voltage generation circuit VG forms the internal voltages VCH, VCL, HVC, VB1 and VB2 based on the power supply voltage VCC and the ground potential VSS supplied as operating power from outside, and supplies them to the respective parts of the dynamic RAM. I do. Although not particularly limited, the power supply voltage VCC is set to a positive potential such as +3.3 V, and the internal voltage VCH is set to a positive potential having a relatively large absolute value such as +4 V. The internal voltage VCL is a positive potential having a relatively small absolute value such as +2.2 V, and the internal voltage HVC is an intermediate potential between the internal voltage VCL and the ground potential VSS, that is, +1.1 V. Further, the internal voltage VB1 is a negative potential having a relatively small absolute value such as -1V, and the internal voltage VB2 is a negative potential having a relatively large absolute value such as -2V.

  FIG. 2 is a substrate layout diagram of one embodiment of the dynamic RAM of FIG. The outline of the chip layout of the dynamic RAM according to this embodiment will be described with reference to FIG. In the following description of the layout, the top, bottom, left, and right of each layout surface of chips and the like are represented by the positional relationship of the corresponding layout drawings.

  In FIG. 2, the dynamic RAM of this embodiment is the base of a P-type semiconductor substrate PSUB. Further, the dynamic RAM of this embodiment employs a so-called LOC (Lead On Chip) form, and the bonding pads for connecting the inner leads and the semiconductor substrate PSUB are linearly arranged along the vertical center line of the semiconductor substrate PSUB. Placed in Therefore, a peripheral circuit PC including an X address buffer XB, a Y address buffer YB, a data input / output circuit IO, and the like is arranged near these bonding pads, that is, in the center of the semiconductor substrate PSUB. Further, memory blocks MB0 and MB1 are arranged at the upper left and upper right portions of the semiconductor substrate PSUB, respectively, and memory blocks MB2 and MB3 are arranged at the lower left and lower right portions, respectively. These memory blocks are arranged so that main common IO lines and sub-bit lines constituting each sub-memory mat are arranged in the horizontal direction in the drawing, that is, Y address decoders YDL and YDR and main amplifiers MAL and MAR are provided on semiconductor substrate PSUB. It is arranged as inside as possible. As a result, the main word lines are arranged in the vertical direction in the drawing in parallel with the sub word lines forming the sub memory mat, and the sub common IO lines forming the sub memory mat are perpendicular to the main common IO lines in the drawing. It is arranged in the direction. Thus, while arranging the main amplifiers MAL and MAR in the center of the semiconductor substrate PSUB, the main common IO lines coupled to these main amplifiers are orthogonally arranged to the sub-common IO lines, thereby realizing an effective chip layout. Can be.

  FIG. 3 is a block diagram showing one embodiment of the memory block MB0 included in the dynamic RAM of FIG. FIG. 4 is a partial block diagram of an embodiment of the sub memory mat SMR 34 and its peripheral portion included in the memory block MB0 of FIG. 3, and FIG. 5 is a partial block diagram of the embodiment. A simple connection diagram is shown. FIG. 6 is a partial circuit diagram of one embodiment of the memory array ARYR34 and its peripheral portion included in the sub memory mat SMR34 of FIG. Based on these figures, the block configuration of the memory block and the sub memory mat constituting the dynamic RAM of this embodiment, the specific configuration and operation of the memory array constituting the sub memory mat and its peripheral parts, and the features thereof Will be described. In the following description of the memory block, the memory block MB0 will be taken as an example. However, the other memory blocks MB1 to MB3 have the same configuration, and should be analogized. The following description of the sub memory mat, the memory array and the peripheral portion will be made with reference to the sub memory mat SMR34 as an example, but the other sub memory mats SMR00 to SMR33 and SMR35 to SMR77 have the same configuration. I want to analogy.

  In FIG. 3, memory block MB0 includes a pair of memory mats MATL and MATR sandwiching X address decoder XD, as described above, and each of these memory mats has 64 Sub memory mats SML00 to SML77 and SMR00 to SMR77 are included.

  In this embodiment, two sub-mats SML00-SML77 and SMR00-SMR77 constituting the memory mats MATL and MATR of the memory block MB0 are paired with two adjacent ones in the column direction, as illustrated by oblique lines in FIG. And four sets of sub-common IO lines SIO0 * to SIO3 * (here, for example, the non-inverting sub-common IO line SIO0T and the inverting sub-common IO line SIO0B are denoted by an asterisk like the sub-common IO line SIO0 *. Further, a so-called non-inverted signal or the like which is selectively set to a high level when the signal is valid is represented by adding a T to the end of its name. As a result, in the paired two sub-memory mats SMR34 and SMR35, etc., it is possible to realize defect repair in the column direction using a bit line selection signal as a unit. On the other hand, eight pairs, that is, for example, sixteen sub memory mats SMR04 to SMR74 and SMR05 to SMR75 arranged in the same row are four sets of main common IO lines MIO40 * to MIO43 * and YS40 to MY40 *. The eight bits arranged in the same row, that is, for example, the sub memory mats SMR30 to SMR37 share 64 bit line select signals represented by YS463 and 64 sets of main word lines represented by MW30 * to MW363, respectively. To share with each other. The sub-memory mats SML00 to SML77 and SMR00 to SMR77 constituting the memory mats MATL and MATR of each memory block can have a part in the row direction and the column direction as a redundant sub-memory mat. Defect relief can be realized in units of mats.

  Here, the sub-memory mats SML00 to SML77 and SMR00 to SMR77 are, as represented by the sub-memory mat SMR34 in FIG. 4, the memory array ARYR34 and the sub-word line driving units WDR34 and And a sense amplifier SAR34. Among them, the memory array ARYR34 is not particularly limited, but as illustrated in FIG. 6, substantially 512 sub-word lines SW0 to SW511 arranged in parallel in the vertical direction in FIG. Substantial 256 sets of sub bit lines SB0 * to SB255 * are arranged. At the intersections of these sub-word lines and sub-bit lines, 131,072 dynamic memory cells each composed of an information storage capacitor and an address selection MOSFET are arranged in a lattice pattern. Thus, each of sub memory mats SML00 to SML77 and SMR00 to SMR77 has a storage capacity of so-called 128 kilobits. Further, each of the memory blocks MB0 to MB3 has a storage capacity of 128 kg × 64 × 2, that is, a so-called 16 Mbit, and the dynamic RAM has a storage capacity of 16 M × 4, that is, a so-called 64 Mbit. Is done.

  Next, as illustrated in FIG. 6, the sub-word line driving unit WDR34 includes 256 unit sub-word line driving circuits USWD0 and USWD2 provided corresponding to the even-numbered sub-word lines SW0, SW2 to SW510 of the memory array ARYR34. Or USWD 510. The output terminals of these unit sub-word line drive circuits are connected above to corresponding even-numbered sub-word lines SW0, SW2 to SW510 of memory array ARYR34, and below thereof, to corresponding even-numbered sub-memory mats SMR33 of adjacent sub-memory mats SMR33. Numbered sub-word lines SW0, SW2 through SW510 are coupled. The input terminals above the unit sub-word line driving circuits USWD0, USWD2 to USWD 510 constituting the sub-word line driving unit WDR34 are commonly coupled in order of four each, and then commonly coupled to the corresponding main word lines MW30 * to MW363 *. You. The input terminals therebelow are sequentially and commonly coupled to every fourth and then commonly to the corresponding sub-word line drive signal lines DX40, DX42, DX44 and DX46.

  On the other hand, the odd-numbered sub-word lines SW1, SW3 to SW511 forming the memory array ARYR34 are provided above the unit sub-word line driving circuits USWD1, USWD3 to USWD 511 corresponding to the sub-word line driving unit WDR35 of the adjacent sub-memory mat SMR35. Connected to output terminal. The output terminals of these unit sub-word line drive circuits are connected above them to odd-numbered sub-word lines SW1, SW3 to SW511 constituting the memory array ARYR35 of the sub-memory mat SMR35. The upper input terminals of the unit sub-word line driving circuits USWD1, USWD3 to USWD 511 constituting the sub-word line driving unit WDR35 are commonly coupled four by one, and then sequentially coupled to the corresponding main word lines MW30 * to MW363 *. . The lower input terminals are sequentially coupled in common every fourth and then commonly coupled to the corresponding sub-word line drive signal lines DX41, DX43, DX45 and DX47.

  The unit sub-word line driving circuits UsWD0, Uswd2 to Uswd510 and Uswd1, Uswd3 to Uswd511 of the sub-word line driving units WDR34 and WDR35 have the corresponding main word lines MW30 * to MW363 * at the effective level and the corresponding sub-word line driving signal DX40, When DX42 to DX46 or DX41, DX43 to DX47 is set to the valid level, the corresponding sub word lines SW0, SW2 to SW510 or SW1, SW3 to SW511 of the memory arrays ARYR33 and ARYR34 or ARYR34 and ARYR35 are selectively selected. Level.

  As is apparent from the above, in the dynamic RAM of this embodiment, for example, the 512 sub-word lines SW0 to SW511 constituting the sub-memory mat SMR34 have a pair of sub-word line driving units provided on both sides thereof, that is, on the upper and lower sides. The sub-memory mat SMR34 is coupled to the corresponding unit sub-word line driving circuits of the WDR 34 and the WDR 35, and the sub-memory mat SMR 34 requires substantially two sub-word line driving units. As described above, since it is shared by the corresponding sub-bit lines of two sub-memory mats adjacent in the column direction, the serial number of the sub-word line driving unit and the serial number of the sub-memory mat are made to correspond to each other. . On the other hand, when attention is paid to the memory array ARYR34 of the sub-memory mat SMR34, the unit sub-word line driving circuits of the corresponding sub-word line driving units WDR34 and WDR35 are arranged alternately below or above the sub-word lines SW0 to SW511. , And the eight corresponding main word lines MW30 * to MW363 * are sequentially shared. As a result, each unit sub-word line drive circuit may be arranged at twice the pitch of the sub-word line, and each main word line may be arranged at a pitch X times the sub-word line, that is, eight times the pitch of the sub-word line. Thereby, the arrangement pitch of the unit sub-word line drive circuit and the complementary main word line can be reduced, and the high integration and large scale of the dynamic RAM can be promoted. The specific configuration and operation of the unit sub-word line driving circuits USWD0 to USWD 511 constituting the sub-word line driving unit WDR34 and the like will be described later in detail. The connection form will be further clarified with reference to FIGS.

  Next, the sub-bit lines SB0 * to SB255 * forming the memory array ARYR34 of the sub-memory mat SMR34 are via the N-channel type shared MOSFETs NA and NB which receive the shared control signal SH3L at their gates on the right side. Sense amplifier SAR34 is coupled to corresponding unit circuits USA0 and USA3 to USA252 and USA255, and to the left thereof senses adjacent submemory mat SMR44 via a similar shared MOSFET whose gate receives shared control signal SH4R in common. The amplifiers SAR44 are coupled to corresponding unit circuits USA1 and USA2 to USA253 and USA254. The unit circuits USA0 and USA3 of the sense amplifier SAR34 further have a memory array ARYR24 of an adjacent sub memory mat SMR24 via N-channel type shared MOSFETs NC and ND which receive a shared control signal SH3R at their gates on the right side. , And the unit circuits USA1 and USA2 of the sense amplifier SAR35, on the left side thereof, via a similar shared MOSFET which receives the shared control signal SH4L at its gate in common with the sub-bit lines SB0 * and SB3 *. It is coupled to corresponding sub-bit lines SB1 * and SB2 * of memory array ARYR44.

  To the unit circuits of the sense amplifiers SAR34 and SAR44, the corresponding bit line selection signals YS40 to YS463 are sequentially and commonly supplied four by four. In addition, as will be described later, these unit circuits include a unit amplifier circuit having a pair of CMOS inverters cross-coupled and a pair of switch MOSFETs (columns) commonly receiving bit line select signals YS40 to YS463 corresponding to their gates. Selection switch). Of these, each unit amplifier circuit is selectively activated by supplying operating power through a common source line (not shown), and a corresponding sub-bit line is selected from a memory cell coupled to the selected sub-word line. The small read signal output through the amplifier is amplified to be a high-level or low-level binary read signal. The switch MOSFET pair of each unit circuit is selectively turned on four by four when the corresponding bit line selection signals YS40 to YS463 are set to the effective level, and the corresponding four sets of sub-bit lines of the memory array ARYR34 are The sub-common IO lines SIO0 * to SIO3 * are selectively connected.

  The sub-common IO lines SIO0 * and SIO1 * are shared by two sub-memory mats SMR34 and SMR35 adjacent in the column direction, as illustrated in FIG. Of these, two sets of sub-common IO lines SIO0 * and SIO1 * are arranged on the right side of these sub-memory mats, that is, in the sense amplifiers SAR34 and SAR35, and the remaining two sets of sub-common IO lines SIO2 * and SIO3 * are These are arranged on the left side of these sub memory mats, that is, in the sense amplifiers SAR44 and SAR45. Further, the sub-common IO line SIO0 * is selectively connected to the main-common IO line MIO40 * via the sub-main amplifier SMA of the sense amplifier driver SDR34 provided at the lower right of the sub-memory mat SMR34, and the sub-common IO line SIO1 * Is selectively connected to the main common IO line MIO41 * via the sub main amplifier of the sense amplifier driver SDR35 provided at the lower right of the sub memory mat SMR35. Further, the sub-common IO line SIO2 * is selectively connected to the main common IO line MIO42 * via the sub-main amplifier of the sense amplifier driving unit SDR45 provided at the lower right of the sub memory mat SMR45, and the sub-common IO line SIO3 * Are selectively connected to a main common IO line MIO43 * via a sub main amplifier of a sense amplifier driving section SDR46 provided at the lower right of the sub memory mat SMR46.

  As is apparent from the above description, in the dynamic RAM of this embodiment, for example, 256 sets of sub bit lines SB0 * to SB255 * forming the sub memory mat SMR34 are provided with a pair of sense amplifiers provided on both sides, that is, on the left and right sides. The sub-memory mat SMR34 is coupled to the corresponding unit circuits of the SAR34 and the SAR44, and the sub-memory mat SMR34 substantially requires two sense amplifiers. Since the two sub memory mats are shared, the serial number of the sense amplifier and the serial number of the sub memory mat are made to correspond to each other. On the other hand, when attention is paid to the memory array ARYR34 of the sub-memory mat SMR34, the corresponding unit circuits of the sense amplifiers are alternately arranged on the right or left side of the sub-bit lines SB0 * to SB255 *, and four by four. The corresponding bit line selection signals YS40 to YS463 are shared. Therefore, each unit circuit of the sense amplifier may be arranged at twice the pitch of the sub-bit line, and each bit line selection signal may be arranged at a pitch Y times the sub-bit line, that is, four times the pitch of the sub-bit line. . As a result, the arrangement pitch of the unit circuit of the sense amplifier and the bit line selection signal can be reduced, and the high integration and large scale of the dynamic RAM can be promoted. The specific configurations of the sense amplifiers SAR34 and SAR44 and the unit circuits USA0 to USA255 will be described later in detail. The connection form will be further clarified with reference to FIGS.

  In the dynamic RAM of this embodiment, the memory mats MATL and MATR forming the memory blocks MB0 to MB3 are each divided into 64 sub-memory mats SML00 to SML77 or SMR00 to SMR77 and are unitized. These sub-memory mats are arranged in a lattice like a memory cell, and their sub-word lines, sub-bit lines and sub-common IO lines are connected to main word lines, bit line selection signals or main common IO lines arranged in an upper layer. Selectively connected and selectively activated. As will be apparent to those skilled in the art, dividing the memory mat into a number of sub-memory mats and unitizing them increases the degree of freedom with respect to the memory mat, that is, the mat configuration of the dynamic RAM. And contribute to shortening its development period. Further, since the unitization into the sub memory mat is performed while adopting the hierarchical structure comprehensively for all of the word lines, the bit lines, and the common IO lines, a dynamic RAM capable of sufficiently exhibiting the effect of the hierarchical structure is provided. To realize high speed, high integration, large scale, and low cost of the dynamic RAM as a whole.

  FIG. 7 shows a partial circuit diagram and a signal waveform diagram of the first embodiment of the sub-word line driving unit WDR34 included in the sub-memory mat SMR34 of FIG. FIG. 8 is a partial circuit diagram and a signal waveform diagram of a second embodiment of the sub-word line driving unit WDR34 included in the sub-memory mat SMR34, and FIG. 9 is a third embodiment thereof. 3 is a partial circuit diagram and a signal waveform diagram. With reference to these drawings, the specific configuration and operation of the sub-word line drive unit constituting the sub-memory mat of the dynamic RAM according to the present embodiment and the features thereof will be described. Note that the following description of the sub-word line drive unit will be made by taking the sub-word line drive unit WDR34 of the sub-memory mat SMR34 as an example. The following description of the unit sub-word line driving circuits USWD0 to USWD510 constituting the sub-word line driving unit WDDR34 can be made by taking the unit sub-word line driving circuit USWD0 as an example. Since it has the same configuration as this, please analogy.

  In FIG. 7, the sub-word line drive unit WDR34 includes 256 unit sub-word line drive circuits USWD0, USWD2 to USWD 510 provided corresponding to the even-numbered sub-word lines SW0, SW2 to SW510 constituting the memory array ARYR34. Each of the unit sub-word line drive circuits of the first and second sub-word line drive circuits USWD0 is a P-channel MOSFET P1 (first circuit) provided between the corresponding sub-word line drive signal line DX40 and the sub-word line SW0. MOSFET) and an N-channel MOSFET N1 (second MOSFET) provided between the corresponding sub-word line SW0 and the ground potential VSS. The gates of these MOSFETs P1 and N1 are coupled to the inverted signal line of the corresponding main word line MW30 *, that is, the inverted main word line MW30B. Unit sub-word line drive circuit USWD0 further includes an N-channel MOSFET N2 (third MOSFET) provided in parallel with MOSFET P1, and the gate of MOSFET N2 has a non-inverted signal line of corresponding main word line MW30 *, that is, a non-inverted signal line. Coupled to main word line MW30T.

  Here, the non-inverted main word line MW30T is set to an invalid level such as the ground potential VSS, that is, 0 V when not selected, and to an effective level such as the internal voltage VCH, that is, +4 V when selected. The inverted main word line MW30B is set to an invalid level such as the internal voltage VCH when not selected, and to an effective level such as the ground potential VSS when selected. Further, sub-word line drive signal DX40 has an invalid level such as ground potential VSS when not selected, and has an effective level such as internal voltage VCH when selected. As described above, the internal voltage VCH is formed based on the power supply voltage VCC by the internal voltage generating circuit VG incorporated in the dynamic RAM, and has a relatively stable potential of + 4V.

  When the corresponding non-inverted main word line MW30T and inverted main word line MW30B are set to the invalid level, in the unit sub-word line drive circuit USWD0, both the MOSFETs P1 and N2 are turned off and the MOSFET N1 is turned on. Therefore, the sub-word line SW0 is set to a non-selection level such as the ground potential VSS regardless of the level of the corresponding sub-word line drive signal DX40.

  On the other hand, when the corresponding non-inverted main word line MW30T and inverted main word line MW30B are set to the valid level, in the unit sub-word line drive circuit USWD0, the MOSFET N1 is turned off, and the MOSFETs P1 and N2 are turned on instead. . Therefore, sub-word line SW0 is set to a selected level such as internal voltage VCH in response to the valid level of corresponding sub-word line drive signal DX40, and is set to a non-selected level such as ground potential VSS in response to the invalid level. .

  As described above, the unit sub-word line driving circuit USWD0 and the like constituting the sub-word line driving section WDR34 and the like of the dynamic RAM according to the present embodiment do not adopt the self-boot type and are so-called CMOS (complementary MOS) static type driving circuits. Therefore, the main word line MW30 * and the like and the sub word line drive signal DX40 and the like can be simultaneously set to the effective level, and the access time in the read mode of the dynamic RAM can be shortened correspondingly.

  As shown in FIG. 8, the unit sub-word line drive circuits including the unit sub-word line drive circuit USWD0 are provided between the corresponding non-inverted main word line MW30T and the sub-word line SW0, and correspond to the gates thereof. P-channel MOSFET P1 receiving sub-word line drive signal DX40, and a gate provided in parallel between sub-word line SW0 and ground potential VSS, and its gate is coupled to corresponding sub-word line drive signal line DX40 and inverted main word line MW30B, respectively. It can be constituted by N-channel MOSFETs N1 and N2, and as shown in FIG. 9, provided between the corresponding non-inverted sub-word line drive signal line DX40T and sub-word line SW0, and the gate thereof is connected to the corresponding inverted main word line MW30B. P-channel MOS coupled ETP1 and N-channel MOSFETs N1 and N2 which are provided in parallel between sub-word line SW0 and ground potential VSS and whose gates are coupled to corresponding inverted main word line MW30B and inverted sub-word line drive signal DX40B, respectively. it can. Further, the unit sub-word line drive circuit USWD0 can be also formed by a normal two-input CMOS NOR gate or the like. In this case, both the main word line and the sub-word line drive signal can be made into a single signal line. Thus, the required number of wirings can be further reduced, and the dynamic RAM can be further highly integrated.

  FIG. 10 is a partial circuit diagram of the first embodiment of the sense amplifier SAR34 and the sense amplifier driving unit SDR34 included in the sub memory mat SMR34 of FIG. FIG. 11 is a partial circuit diagram of a second embodiment of the sense amplifier driver SDR34 included in the sub memory mat SMR34 of FIG. 4, and FIG. 12 is a circuit diagram of the sense amplifier driver SDR34 of FIGS. A signal waveform diagram of one embodiment of the amplifier driver SDR34 is shown. FIG. 13 is a partial circuit diagram of a third embodiment of the sense amplifier driver SDR34 included in the sub memory mat SMR34 of FIG. 4, and FIG. 14 is a signal waveform of one embodiment. The figure is shown. With reference to these drawings, the specific configuration and operation of the sense amplifier and the sense amplifier driving unit included in the sub-memory mat of the dynamic RAM according to the present embodiment and the features thereof will be described. Note that the following description of the sense amplifier, its unit circuit, and the sense amplifier driver will be made by taking the sense amplifier SAR34 of the sub memory mat SMR34, its unit circuit USA0, and the sense amplifier driver SDR34 as examples. The unit circuit and the sense amplifier driving unit have the same configuration as those of the embodiments, and should be analogized.

  In FIG. 10, the sense amplifier SAR34 includes 128 unit circuits USA0, USA3 to USA252, USA255. The left input terminal of each of these unit circuits has an N-channel type shared MOSFET NA commonly receiving at its gate an inverted signal of the inverted shared control signal SH3LB by the inverter V1 of the sense amplifier driver SDR34, that is, a non-inverted shared control signal SH3L. Via NB, it is coupled to corresponding sub-bit lines SB0 *, SB3 * through SB252 *, SB255 * of the memory array ARYR34. Of the memory array ARYR24 of the adjacent sub-memory mat SMR24 via N-channel type shared MOSFETs NC and ND commonly receiving the inverted signal by the inverter V3, that is, the non-inverted shared control signal SH3R. SB0 *, SB3 * through SB252 *, is coupled to the SB255 *.

  As a result, the dynamic RAM adopts the shared sense method, and the unit circuits USA0, USA3 to USA252, and USA255 of the sense amplifier SAR34 include the memory arrays ARYR34 and SMR24 of the pair of sub memory mats SMR34 and SMR24 arranged adjacent to each other. Shared by ARYR24. Then, when the inverted shared control signal SH3LB is set to the low level and the non-inverted shared control signal SH3L is set to the high level, the corresponding sub-bit lines SB0 *, SB3 of the memory array ARYR34 arranged on the left side via the shared MOSFETs NA and NB. * To SB252 * and SB255 *, and are disposed on the right side through shared MOSFETs NC and ND when the inverted shared control signal SH3RB is at a low level and the non-inverted shared control signal SH3R is at a high level. It is selectively connected to corresponding sub-bit lines SB0 *, SB3 * through SB252 *, SB255 * of memory array ARYR24.

  Here, each of the unit circuits constituting the sense amplifier SAR34 is a pair of CMOSs composed of a P-channel MOSFET P2 and an N-channel MOSFET N3 and a P-channel MOSFET P3 and an N-channel MOSFET N4, as represented by the unit circuit USA0 in FIG. Unit amplifier circuits having inverters cross-coupled, and N provided between the non-inverted and inverted input / output nodes of these unit amplifier circuits and the non-inverted and inverted signal lines of sub-common IO line SIO0 * or SIO1 *, respectively. A bit line precharge circuit including a pair of channel-type switch MOSFETs (column selection switches) N8 and N9 and three N-channel MOSFETs N5 to N7 connected in series and parallel.

  Of these, the sources of the MOSFETs P2 and P3 forming the unit amplifier circuit are commonly coupled to a common source line (drive signal line) PP, and the commonly coupled sources of the MOSFETs N3 and N4 are commonly coupled to a common source line PN. . The common source line PP is coupled to a drive voltage supply line CPP4 via a P-channel type drive MOSFET P4 constituting the sense amplifier drive circuit SAD of the sense amplifier drive unit SDR34, and the common source line PN is connected to an N-channel type drive MOSFET NE. To the drive voltage supply line CPN4. Further, between the common source lines PP and PN, there is provided a common IO line precharge circuit in which three N-channel MOSFETs NF to NH are connected in series and parallel. The gate of the drive MOSFET P4 forming the sense amplifier drive circuit SAD is coupled to the sense amplifier control signal line SAP3, and the gate of the drive MOSFET NE is coupled to the sense amplifier control signal line SAN3. Further, an inverted signal of the internal control signal PC for precharge control by the inverter V2, that is, an inverted internal control signal PCB is commonly supplied to the gates of the MOSFETs NF to NH constituting the common IO line precharge circuit.

  As a result, the unit amplifier circuit of each unit circuit of the sense amplifier SAR34 receives the valid levels of the sense amplifier control signals SAP3 and SAN3, turns on the drive MOSFETs P4 and NE of the sense amplifier drive circuit SAD, and turns on the drive voltage supply lines CPP4 and NE3. A predetermined operating power is supplied from CPN 4 via common source lines PP and PN to selectively operate, and 256 memory cells coupled to a selected sub-word line of memory array ARYR34 or ARYR24. The small read signals output via the corresponding sub-bit lines SB0 * and SB2 * and the like are respectively amplified to obtain high-level or low-level binary read signals.

  Next, the gates of the switch MOSFETs N8 and N9 constituting each unit circuit of the sense amplifier SAR34 are sequentially and commonly coupled in pairs, and a corresponding bit line selection signal YS40 and the like are supplied from the Y address decoder YD. As described above, the bit line selection signal YS40 and the like are also supplied to the gates of two pairs of switch MOSFETs such as the unit circuits USA1 and USA2 of the sense amplifier SAR44 provided on the left side of the memory array ARYR34. As a result, the switch MOSFETs N8 and N9 of each unit circuit are turned on selectively and two pairs at a time when the corresponding bit line select signals YS40 to YS463 are set to the valid level, and the corresponding switch in the memory array ARYR34 or ARYR24. The two sets of sub-bit lines and the sub-common IO lines SIO0 * and SIO1 * are selectively connected.

  On the other hand, the inverted precharge control signal PCB is commonly supplied to the gates of the MOSFETs N5 to N7 constituting the bit line precharge circuit of each unit circuit of the sense amplifier SAR34. The MOSFETs N5 to N7 are selectively turned on in response to the valid level of the inversion precharge control signal PCB, that is, the high level. The non-inverting and inverting signal lines of the corresponding sub-bit lines of the memory array ARYR34 or ARYR24 are short-circuited and equalized.

  In this embodiment, the memory mats MATL and MATR constituting the memory blocks MB0 to MB3 have an internal voltage VCL having a relatively small absolute value such as +2.2 V in order to miniaturize elements such as memory cells. The ground potential VSS, that is, 0 V is used as its operation power supply, and the unit amplifier circuit forming the sense amplifier SAR34 also uses the internal voltage VCL and the ground potential VSS supplied via the common source lines PP and PN as its operation power supply. However, the dynamic RAM of this embodiment employs a so-called overdrive method, and the power supply voltage VCC, that is, +3.3 V is supplied to the common source line PP only for a predetermined period at the beginning when the sense amplifier SAR34 is activated. As a result, the rise of the amplification operation of the unit amplifier circuit of the sense amplifier is accelerated, and the read operation of the dynamic RAM is accelerated.

  Here, the overdrive method of the sense amplifier will be briefly described based on the signal waveform diagram of FIG. In FIG. 12, the sense amplifier control signal SAP3 has the power supply voltage VCC, ie, + 3.3V, as its invalid level, and the ground potential VSS, ie, 0V, as its effective level. The sense amplifier control signal SAN3 sets the ground potential VSS to its invalid level and the power supply voltage VCC to its effective level. The drive voltage supply line CPP4 is supplied with the power supply voltage VCC when not selected and for a predetermined time after the sense amplifier control signals SAP3 and SAN3 are set to the valid level, and after the predetermined time elapses, the internal voltage VCL is applied. That is, +2.2 V is supplied. The ground potential VSS is constantly supplied to the drive voltage supply line CPN4. The precharge control signal PC (not shown) is set to an effective level such as the ground potential VSS at a predetermined timing when the sense amplifier SAR34 is deactivated, and becomes an invalid level such as the power supply voltage VCC when activated. It is said.

  When the sense amplifier control signals SAP3 and SAN3 are set to the invalid level and the sense amplifier SAR34 is deactivated, the drive MOSFETs P4 and NE constituting the sense amplifier drive circuit SAD are turned off in the sense amplifier drive section SDR34. The MOSFETs NF to NH constituting the common IO line precharge circuit are simultaneously turned on in response to the valid level of the precharge control signal PC. As a result, the common source lines PP and PN are equalized to the intermediate potential between the internal voltage VCL and the ground potential, that is, the internal voltage HVC via the MOSFETs NF to NH, and the unit circuits USA0 and the like of the sense amplifier SAR34 are all inactivated. You. At this time, in the memory array ARYR34 or ARYR24, the non-inverted and inverted signal lines of the sub-bit lines SB0 * to SB255 * are equalized via the bit line precharge circuit of the corresponding unit circuit of the sense amplifier SAR34, so that the internal voltage HVC is applied. Pre-charged to an intermediate level.

  On the other hand, when the sense amplifier control signals SAP3 and SAN3 are set to the valid level, in the sense amplifier driving unit SDR34, the MOSFETs NF to NH constituting the common IO line precharge circuit are turned off, and the sense amplifier driving circuit SAD is turned on instead. The drive MOSFETs P4 and NE that constitute the transistor are turned on. Therefore, a drive voltage such as the power supply voltage VCC is first supplied to the common source line PP from the drive voltage supply line CPP4 via the drive MOSFET P4, and after a predetermined time, a drive voltage such as the internal voltage VCL is supplied. You. Further, the ground potential VSS is supplied to the common source line PN via the drive voltage supply line CPN4. As a result, the unit amplifier circuit constituting each unit circuit of the sense amplifier SAR34 is brought into the operating state, and is output from the memory cell coupled to the selected sub-word line of the memory array ARYR34 or ARYR24 to the corresponding sub-bit line SB0 * or the like. These small read signals are amplified to obtain high-level or low-level binary read signals. Note that the power supply voltage VCC for overdrive is supplied to the common source line PP at the beginning of the activation of the sense amplifier SAR34, so that the rise of the amplifying operation of the unit amplifier circuit is accelerated. In the read mode, the access time is shortened.

  By the way, in the embodiment of FIG. 12, the overdrive of the sense amplifier is realized by temporarily setting the drive voltage supplied via the drive voltage supply line CPP4 to the power supply voltage VCC, as shown in FIG. As described above, by providing three drive voltage supply lines to which the power supply voltage VCC, the internal voltage VCL, and the ground potential VSS are constantly supplied, a similar overdrive can be realized. That is, in FIG. 13, P-channel type drive MOSFETs P8 and P9 constituting the sense amplifier drive circuit SAD are provided between the common source line PP and the power supply voltage VCC and the internal voltage VCL, respectively. An N-channel drive MOSFET NE is provided between the gate and the potential VSS. The sense amplifier control signals SAP31 and SAP32 are supplied to the gates of the drive MOSFETs P8 and P9, respectively, and the sense amplifier control signal SAN3 is supplied to the gate of the drive MOSFET NE. In this embodiment, as shown in FIG. 14, the sense amplifier control signal SAP31 is set to an effective level at the same time as the sense amplifier control signal SAN3, and is returned to an invalid level when a predetermined time has elapsed. Further, the sense amplifier control signal SAP32 is set to the effective level at the same time when the sense amplifier control signal SAP31 is returned to the invalid level when a predetermined time has elapsed since the sense amplifier control signals SAP31 and SAN3 were set to the effective level. As a result, the power supply voltage VCC is supplied to the common source line PP as the drive voltage for a predetermined period from when the sense amplifier control signal SAP31 is set to the valid level to when the sense amplifier control signal SAP32 is set to the valid level. Thus, overdrive of the sense amplifier similar to that of FIG. 12 can be realized.

  On the other hand, in the dynamic RAM of this embodiment, the refresh operation of the memory cells proceeds in units of eight sub-memory mats SMR00 to SMR07 to SMR70 to SMR77 arranged in the same row. At this time, the sense amplifier control signals SAP0 to SAP7 and SAN0 to SAN7 are sequentially set to an effective level as the refresh operation proceeds. For example, the refresh operation of the sub memory mats SMR30 to SMR37 is completed and the sub memory mats SMR40 to SMR47 are completed. , The sense amplifier control signals SAP3 and SAN3 are set to an effective level simultaneously with the next sense amplifier control signals SAP4 and SAN4 for a predetermined period, and so-called charge reuse refresh is performed. As a result, electric charges corresponding to the drive voltage VCL or VSS charged in the common source lines PP and PN of the sense amplifiers SAR30 to SAR37 are transferred to the sense amplifiers SAR30 to SAR37 via the drive voltage supply lines CPP0 to CPP7 and CPN0 to CPN7. It is transmitted to the common source lines PP and PN and reused. As a result, the amount of charge of the drive voltage to be supplied via the drive voltage supply lines CPP0 to CPP7 and CPN0 to CPN7 is saved again, and the power consumption of the dynamic RAM is reduced.

  Returning to the description of FIG. The sense amplifier driving section SDR34 of this embodiment further includes a sub main amplifier SMA including a pair of N-channel type read differential MOSFETs NP and NQ and a pair of write switch MOSFETs NL and NM, and three P-channel MOSFETs P5 to P5. P7 and two sub-common IO line precharge circuits in which N-channel MOSFETs NI to NK are respectively connected in series and parallel. Among these, the inverted signal of the internal control signal PC by the inverter V2, that is, the inverted internal control signal PCB is commonly supplied to the gates of the MOSFETs NI to NK constituting one sub-common IO line precharge circuit, and the other sub-common IO line The internal control signal PCS is commonly supplied to the gates of the MOSFETs P5 to P7 constituting the precharge circuit. Thus, when the dynamic RAM is set to the write mode, the MOSFETs NI to NK are selectively turned on when the internal control signal PC is at a low level, that is, when the inverted internal control signal PCB is at a high level, and the sub-common IO line SIO0 Equalize the non-inverted and inverted signal lines of * to the internal voltage HVC. Further, when the dynamic RAM is set to the read mode, the MOSFETs P5 to P7 are selectively turned on when the internal control signal PCS is set to the low level, and connect between the non-inverted and inverted signal lines of the sub-common IO line SIO0 *. Equalize to internal voltage VCL.

  On the other hand, the drains and sources of the write switch MOSFETs NL and NM constituting the sub main amplifier SMA are respectively coupled to the inverted and non-inverted signal lines of the main common IO line MIO40 * and the sub common IO line SIO0 *. The internal control signal WE3 is commonly supplied. The drains of the read differential MOSFETs NP and NQ are coupled to the non-inverted and inverted signal lines of the main common IO line MIO40 * via the N-channel MOSFETs NN and NO, respectively. Is coupled to the ground potential VSS through the drive MOSFET NR. The gates of the differential MOSFETs NP and NQ are coupled to the inverted and non-inverted signal lines of the sub-common IO line SIO0 *, respectively, and the internal control signal RE3 is commonly supplied to the gates of the MOSFETs NN, NO and NR. When the dynamic RAM is selected in the write mode, the internal control signal WE3 is selectively set to a high level such as the internal voltage VCL at a predetermined timing, and the internal control signal RE3 is selected in the read mode. When the state is set, it is selectively set to a high level at a predetermined timing.

  As a result, the write switches MOSFET NL and NM of the sub main amplifier SMA are selectively turned on when the dynamic RAM is selected in the write mode and the internal control signal WE3 is set to the high level. The write signal supplied via the main common IO line MIO40 * is transmitted to the sub-common IO line SIO0 *. These write signals are written from the sub-common IO line SIO0 * to the selected memory cell of the memory array ARYR34 via the corresponding unit circuit of the sense amplifier SAR34.

  On the other hand, among the read differential MOSFETs NP and NQ constituting the sub main amplifier SMA, the dynamic RAM is selected in the read mode, and the MOSFETs NN, NO and NR are turned on in response to the high level of the internal control signal RE3. At this time, a so-called pseudo direct type differential amplifier circuit is selectively formed together with these MOSFETs, output from the selected memory cell of the memory array ARYR34, amplified by the corresponding unit amplifier circuit of the sense amplifier SAR34, and further connected to the sub-common IO line. The binary read signal output via SIO0 * is further amplified and transmitted to the corresponding main common IO line MIO40 *. As described above, the sub-common IO line SIO0 * is shared by two sub-memory mats SMR34 and SMR35 adjacent in the column direction, and has a wiring length corresponding to the width of these sub-memory mats in the bit line direction. Short. Further, the binary read signal output from the corresponding unit amplifier circuit of the sense amplifier SAR34 to the sub-common IO line SIO0 * is further amplified by the differential amplifier circuit of the sub-main amplifier SMA centering on the read differential MOSFETs NP and NQ. The signal is transmitted to main common IO line MIO40 * having a relatively long wiring length.

  As a result, in this embodiment, while reducing the load on each unit amplifier circuit of the sense amplifier SAR34 at the time of column selection, the read signal of the selected memory cell can be effectively transferred to the main common IO line MIO40 *, that is, the main amplifier. The data can be transmitted to the corresponding unit circuit of the MAR, whereby the access time in the read mode of the dynamic RAM can be shortened. In this embodiment, the sense amplifier drive circuit SAD34 including the sub main amplifier SMA is arranged in an intersecting region of the arrangement region of the sense amplifier SAR34 and the like and the arrangement region of the sub word line driver WDR34 and the like, as described later. Therefore, the access time can be shortened while suppressing an increase in the layout area.

  By the way, when the wiring length of the main common IO line MIO40 * or the like is relatively short or its load capacity does not matter, the sub main amplifier SMA is used for writing and reading as illustrated in FIGS. It can be constituted only by the switch MOSFETs NL and NM which are also used.

  FIG. 15 is a plan view showing an embodiment of the memory array ARYR34 of the sub-memory mat SMR34 of FIG. FIG. 16 is a partial plan view showing one embodiment of the sub-word line driver WDR34 included in the sub-memory mat SMR34 of FIG. 4, and FIG. 17 shows the sense amplifier SAR34 and the sense amplifier driver. A plan view of one embodiment of the SDR 34 is shown. With reference to these drawings, the planar arrangement and the characteristics of the metal wiring layer in the sub memory mat SMR34 and its peripheral portion will be described. Needless to say, the following description regarding the metal wiring layer can be applied to other sub-memory mats other than the sub-memory mat SMR34.

  In FIG. 15, the dynamic RAM of this embodiment has three metal wiring layers M1 to M3 made of aluminum or the like. Of these, the third metal wiring layer M3, which is the uppermost layer, mainly includes the bit line selection signals YS40 to YS40 arranged in the horizontal direction of the drawing, that is, in parallel with the sub bit lines and across a plurality of sub memory mats. YS463 and the like, sub-word line drive signals DX40 to DX47 and the like, main common IO lines MIO40 * to MIO43 * and the like, and drive voltage supply lines CPP2, CPN2, CPP4 and CPN4, etc. The second metal wiring layer M2 is mainly used. Inverted shared control signals such as main word lines MW30 * to MW363 *, sub common IO lines SIO0 * to SIO3 *, etc., arranged in the vertical direction of the drawing, that is, in parallel with the sub word lines and between a plurality of sub memory mats. Sense amplifier drive signal lines SAP3 to SAP4 and lines SH3LB to SH4LB and SH3RB to SH4RB and the like. SAN3~SAN4 like, as well as the internal control signal line PC, PCS, WE3~WE4, used as such RE3～RE4. The first metal wiring layer M1, which is the lowermost layer, is used as a wiring between elements such as MOSFETs constituting each circuit.

  In this embodiment, the main word line MW30 * composed of the second metal wiring layer M2, that is, the non-inverted main word line MW30T and the inverted main word line MW30B are connected to the gate of the first layer as illustrated in FIG. The sub-word lines SW0 to SW7 of the memory array ARYR34 composed of the layer FG are arranged at a pitch eight times as large as the subword lines SW0 to SW7 with a sufficient margin. One of the sub-word line drive signal lines DX40, DX42, DX44, DX46, etc., which is made up of a third metal wiring layer M3 and is divided into two right portions (not shown), is a P-channel constituting the sub-word line drive unit WDR34. The MOSFETs are arranged in parallel on the MOSFET forming region, and the other is arranged in parallel on the N-channel MOSFET forming region constituting the sub-word line driving unit WDR34. In the middle of these sub-word line drive signal lines, a supply wiring for supplying a substrate potential, that is, an internal voltage VCH to an N-well region serving as a P-channel MOSFET formation region is similarly formed by a third metal wiring layer M3. Is done. Further, in the lower layer, a first-layer metal wiring layer M1 forms a coupling line for commonly coupling even-numbered sub-word lines SW0, SW2, SW4, SW6, and the like of the adjacent memory arrays ARYR34 and ARYR33. .

  On the other hand, as illustrated in FIG. 17, the bit line selection signal YS40 or the like formed of the third metal wiring layer M3 includes the sub bit lines SB0 * to SB3 * of the memory array ARYR34 formed of the second gate layer SG. The pitch is four times that of the non-inverting sub-bit lines SB0T to SB3T and the inverting SB0B to SB3B, that is, substantially eight times, and is arranged with a sufficient margin. The main common IO lines MIO40 *, that is, the non-inverted main common IO lines MIO40T and MIO40B, and the drive voltage supply lines CPP4 and CPN4 formed of the third metal wiring layer M3 are connected to the sub-word line drive units WDR24 and WDR34 and the sense amplifier drive. Inverted shared, such as sub-common IO lines SIO0 * and SIO1 *, which are arranged on the arrangement region of the section SDR34 and the like and are composed of the second metal wiring layer M2, that is, non-inverted sub-common IO lines SIO0T and SIO1T and inverted sub-common IO lines SIO0B and SIO1B. The control signal lines SH3LB and SH3RB to SH4RB and the like, the sense amplifier drive signal lines SAP3 and SAN3 and the like, and the internal control signal lines PC, PCS, WE3 and RE3 and the like correspond to the sense amplifier SAR34 and the sense amplifier driver SDR34. It is placed in the placement area. As a result, signal lines for transmitting signals over a plurality of sub-memory mats are efficiently arranged using three metal wiring layers, thereby improving the layout efficiency of the sub-memory mats and thus the dynamic RAM.

  In the dynamic RAM according to this embodiment, as described above, the main word line MW30 composed of the second-layer metal wiring layer M2 or the third-layer metal wiring layer M3 and particularly related to a highly integrated memory array is used. Since * to MW363 * and the like and bit line selection signals YS40 to YS463 and the like are arranged with a sufficient margin, these metal wiring layers are patterned without using a so-called phase shift mask, thereby reducing the cost of the dynamic RAM. Is achieved.

  FIG. 18 is a plan view showing a first embodiment of a memory array and peripheral portions constituting each sub-memory mat of the dynamic RAM shown in FIG. 1, and FIG. 21 is a sectional view of the first embodiment. The figure is shown. FIG. 19 is a plan view showing a second embodiment of a memory array and peripheral portions constituting each sub memory mat of the dynamic RAM shown in FIG. 1, and FIG. A sectional structural view is shown. Further, FIG. 20 is a plan layout view of a third embodiment of a memory array and peripheral portions constituting each sub memory mat of the dynamic RAM of FIG. 1, and FIG. A sectional structural view is shown. With reference to these figures, the outline of the dynamic RAM, particularly the well structure, the substrate voltage and the characteristics thereof will be described with reference to these figures. In the following embodiments, the well structure and the substrate voltage of the dynamic RAM are symbolically expressed irrespective of the arrangement of the substrate of the dynamic RAM described so far, mainly for the purpose of easily explaining the well structure and the substrate voltage. In the following description, first, the first embodiment of FIGS. 18 and 21 will be described in detail, and the second embodiment of FIGS. 19 and 22 and the third embodiment of FIGS. 20 and 23 will be described. Will add the explanation only for the parts different from this.

  In FIGS. 18 and 21, the dynamic RAM has a P-type semiconductor substrate PSUB to which an internal voltage VB1 having a relatively small absolute value, such as -1V, as a negative potential is applied. Further, a memory cell MC constituting the memory array ARY1, that is, an N-channel MOSFET serving as an address selection MOSFET is formed in a P well region PW1 provided on the semiconductor substrate PSUB and in a region where the corresponding sense amplifier SA1 is disposed. The memory cells MC constituting the memory array ARY2 forming a pair, that is, N-channel MOSFETs serving as address selection MOSFETs are also formed in the P well region PW2 provided on the semiconductor substrate PSUB and in the region where the corresponding sense amplifier SA1 is disposed. Is done. The internal voltage VB1 is supplied as a substrate voltage to the P well regions PW1 and PW2, and this internal voltage VB1 becomes the substrate voltage of the semiconductor substrate PSUB as it is.

  Similarly, a memory cell MC constituting the memory array ARY3, that is, an N-channel MOSFET serving as an address selection MOSFET is provided on the semiconductor substrate PSUB and in a region provided with the corresponding sense amplifier SA2 and the sub-word line drive unit WD1. An N-channel MOSFET formed in the well region PW3 and serving as an address selection MOSFET of the memory cell MC forming the paired memory array ARY4 is also provided in the region where the sense amplifier SA2 and the sub-word line driver WD2 are arranged. It is formed in the well region PW4. The internal voltage VB1 is supplied to the P well regions PW3 and PW4 as a substrate voltage.

  N-channel MOSFETs (NMOS) constituting the sense amplifier SA1 or SA2 are formed at the right ends of the P well regions PW1 and PW3 and at the left ends of the P well regions PW2 and PW4, respectively. N well regions NW1 and NW2 each having a power supply voltage VCC as a substrate voltage are provided between P well regions PW1 and PW2 and between PW3 and PW4, respectively. In these N well regions, sense amplifiers SA1 or SA2 are provided. Are formed, respectively. An N-well region NW9 for blocking is provided outside the P-well regions PW1 and PW3, and an N-well region NW10 for blocking is provided outside the P-well regions PW2 and PW4.

  Similarly, an N-channel MOSFET forming the sub-word line driver WD1 is formed at the upper end of the P-well region PW3, and an N-channel MOSFET forming the sub-word line driver WD2 is formed at the upper end of the P-well region PW4. It is formed. N well regions NW3 and NW4 each having an internal voltage VCH as a substrate voltage are provided between P well regions PW1 and PW3 and between PW2 and PW4, and a sub word line driver is provided in these N well regions. P-channel MOSFETs constituting WD1 or WD2 are respectively formed. An N well region NW13 for blocking is provided outside the P well regions PW1 and PW2, and an N well region NW14 is provided outside the P well regions PW3 and PW4.

  On the other hand, a P-channel MOSFET constituting peripheral circuit PC is formed in N-well region NW5 provided on semiconductor substrate PSUB, and an N-channel MOSFET is formed in P-well region PW5 provided in relatively deep N-well region DNW1. Formed. An N-well region NW11 for blocking is formed on the right outside of the P-well region PW5, and a power supply voltage VCC serving as a substrate voltage via the N-well region NW11 and the N-well region NW5 in the deep N-well region DNW1. Is supplied. The ground potential VSS is supplied to the P well region PW5 as a substrate voltage.

  Further, a P-channel MOSFET forming data input / output circuit IO is formed in N-well region NW6 provided on semiconductor substrate PSUB, and an N-channel MOSFET is formed in P-well provided in relatively deep N-well region DNW2. It is formed in the region PW6. A blocking P-well region PW13 is formed on the left outside of the N-well region NW6, and a blocking N-well region NW12 is formed on the right outside of the P-well region PW6. Power supply voltage VCC serving as a substrate voltage is supplied to deep N well region DNW2 via N well region NW12 and N well region NW6. The P well region PW6 is supplied with an internal voltage VB2 having a relatively large absolute value of a negative potential, such as -2V, as a substrate voltage.

  As described above, the dynamic RAM of this embodiment has a so-called triple well structure, and includes the N-channel MOSFETs serving as the memory cells MC of the memory arrays ARY1 to ARY4, the sense amplifiers SA1 to SA2, and the sub-word line driving units WD1 and WD2. The N-channel MOSFET to be formed is formed in the same P-well region, and a cut-off region for separating the well regions is not required, whereby the chip size of the dynamic RAM can be reduced. In addition, the N-well regions NW1 and NW2 of the sense amplifiers SA1 to SA2, for example, the formation regions of the P-channel MOSFETs for driving the common source lines, use the power supply voltage VCC as the substrate voltage, so that latch-up at power-on, which will be described later, is performed. Danger can be eliminated. However, although the substrate effect is small for the P-channel MOSFET in the sense amplifier section, the potential difference between the ground potential VSS as the source potential and the internal voltage VB1 as the substrate voltage is 1 V for the N-channel MOSFET, and the threshold voltage is It becomes large and affects the operation of the sense amplifier. Further, since the P-well regions PW1 to PW4, which are the formation regions of the memory arrays ARY1 to ARY4, are formed directly on the semiconductor substrate PSUB, fluctuations in the substrate voltage of the semiconductor substrate PSUB due to the operation of the data input / output circuit IO, etc. Noise is transmitted to the memory cells as it is, and since no cutoff region is provided between the memory arrays ARY1 to ARY4 and the sense amplifiers SA1 to SA2, noise due to the operation of the sense amplifiers SA1 to SA2 is reduced. Is transmitted to

  Next, in the case of the second embodiment shown in FIGS. 19 and 22, the dynamic RAM uses a P-type semiconductor substrate PSUB to which the ground potential VSS is applied as its base. The memory cell MC constituting the memory array ARY1, that is, the N-channel MOSFET serving as the address selection MOSFET is arranged in the relatively deep N well region DNW3 to which the internal voltage VCH, that is, the word line selection potential is applied, and the corresponding sense amplifier SA1 is arranged. The memory cells MC forming the paired memory array ARY2, that is, the N-channel MOSFETs serving as the address selection MOSFETs, which are formed in the P-well region PW1 provided to penetrate the region, are also located in the deep N-well region DNW3. It is formed in a P-well region PW2 provided to enter the arrangement region of the amplifier SA1. A negative potential having a relatively small absolute value, that is, an internal voltage VB1 is supplied as a substrate voltage to P well regions PW1 and PW2.

  Similarly, a memory cell MC constituting the memory array ARY3, that is, an N-channel MOSFET serving as an address selection MOSFET is provided in the deep N-well region DNW3 and in a region where the corresponding sense amplifier SA2 and sub-word line driver WD1 are disposed. An N-channel MOSFET formed in the P-well region PW3 and serving as an address selection MOSFET of the memory cell MC forming the paired memory array ARY4 is also located in the deep N-well region DNW3, and also has a sense amplifier SA2 and a sub-word line driver. It is formed in a P-well region PW4 provided to enter the arrangement region of WD2. An internal voltage VB1 of -1 V is supplied as a substrate voltage to P well regions PW3 and PW4.

  At the right ends of the P well regions PW1 and PW3 and at the left ends of the P well regions PW2 and PW4, N-channel MOSFETs forming the sense amplifier SA1 or SA2 are formed, respectively. Further, N well regions NW1 and NW2 are provided between the P well regions PW1 and PW2 and between PW3 and PW4, respectively. In these N well regions, P channel MOSFETs constituting the sense amplifier SA1 or SA2 are respectively provided. It is formed. Further, an internal voltage VCH of +4 V is supplied as a substrate voltage to these N well regions NW1 and NW2, and this becomes the substrate voltage of the deep N well region DNW3 as it is.

  Similarly, an N-channel MOSFET forming the sub-word line driver WD1 is formed at the upper end of the P-well region PW3, and an N-channel MOSFET forming the sub-word line driver WD2 is formed at the upper end of the P-well region PW4. It is formed. N well regions NW3 and NW4 each having an internal voltage VCH as a substrate voltage are provided between P well regions PW1 and PW3 and between PW2 and PW4, and a sub word line driver is provided in these N well regions. P-channel MOSFETs constituting WD1 or WD2 are respectively formed.

  On the other hand, a P-channel MOSFET constituting the peripheral circuit PC is formed in an N-well region NW5 provided on the semiconductor substrate PSUB, and the N-channel MOSFET is formed in a P-well region PW5 also provided on the semiconductor substrate PSUB. Is done. Power supply voltage VCC is supplied to N well region NW5 as a substrate voltage. Further, the ground potential VSS is supplied to the P-well region PW5 as a substrate voltage, and this becomes the substrate voltage of the semiconductor substrate PSUB as it is.

  As described above, in the case of this embodiment, the N-channel MOSFETs constituting the memory cells MC of the memory arrays ARY1 to ARY4 and the N-channel MOSFETs constituting the sense amplifiers SA1 to SA2 and the sub-word line driving units WD1 and WD2 are the same P-channel MOSFETs. Formed in the well region, a cut-off region for separating the well regions is not required, so that the chip size is reduced and the P-well regions PW1 to PW4 and the N-well regions NW1 to NW4 which are regions for forming these circuits are formed. Are formed in the N well region DNW3, which is relatively deep, so that a variation in the substrate voltage of the semiconductor substrate PSUB can be prevented from becoming noise and transmitted to the memory cells of the memory arrays ARY1 to ARY4. However, the N well regions NW1 and NW2, which are the formation regions of the P-channel MOSFETs forming the sense amplifiers SA1 to SA2, use the internal voltage VCH as the substrate voltage. During the low period, for example, a current flows from the source diffusion layer of the P-channel MOSFET receiving the power supply voltage VCC to the N-well region, and in the worst case, there is a risk of a latch-up state. Further, the N-well regions NW1 and NW2 use the internal voltage VCH as the substrate voltage, and the P-well regions PW1 to PW4, which are the N-channel MOSFET formation regions, use the internal voltage VB1 as the substrate voltage. Both the body effect and the threshold voltage increase, which affects the operation of the sense amplifier. Furthermore, since no cutoff region is provided between the memory arrays ARY1 to ARY4 and the sense amplifiers SA1 to SA2, noise accompanying the simultaneous activation of the sense amplifiers SA1 to SA2 is transmitted to the memory cells. .

  Lastly, in the case of the third embodiment shown in FIGS. 20 and 23, the N-channel MOSFETs forming the sense amplifiers SA1 and SA2 are independent of each other on the semiconductor substrate PSUB, although this is basically similar to the second embodiment. The P well regions PW11 and PW12 provided as above are used as formation regions. Ground potential VSS is supplied as a substrate voltage to these P well regions PW11 and PW12. An N well region NW16 is provided as a blocking region between the P well regions PW11 and PW12 and the P well region PW7 where the memory arrays ARY1 and ARY3 are formed.

  From these facts, in this embodiment, although the chip size is slightly increased by providing the cutoff region, the P channel and the sense amplifier SA1 and SA2 constituting the sense amplifiers SA1 and SA2 are maintained while maintaining the features of the second embodiment. The operation of the sense amplifiers SA1 and SA2 can be speeded up by eliminating the substrate effect of the N-channel MOSFET, and the noise associated with the operation of these sense amplifiers can be prevented from being transmitted to the memory cells. Can be eliminated.

The operational effects obtained from the above embodiment are as follows. That is,
(1) A memory mat such as a dynamic RAM is formed by combining a memory array including sub-word lines and sub-bit lines arranged orthogonally to each other and dynamic memory cells arranged in a lattice at the intersections of these sub-word lines and sub-bit lines. A sub-word line driving unit including a unit sub-word line driving circuit provided corresponding to the sub-word line; a sense amplifier including a unit amplifier circuit and a column selection switch provided corresponding to the sub-bit line; A plurality of sub-memory mats each having a sub-common IO line selectively connected via a selection switch are divided and unitized, and these sub-memory mats are arranged in a lattice shape, and are orthogonally arranged on the upper layer. A main word line and a column selection signal line to be arranged, and a designated sub-common I By forming a main common IO line or the like to which lines are selectively connected, the hierarchical structure is comprehensively adopted for all of the word lines, bit lines and common IO lines, and the effect of the hierarchical structure is fully exhibited. It is possible to realize a dynamic RAM or the like having a different configuration.

  (2) In the above item (1), the unit sub-word line drive circuits are alternately arranged on both sides of the sub-word line and at twice the pitch thereof, and the unit amplifier circuits and the column selection switches are alternately arranged on both sides of the sub-bit line. They are arranged at twice the pitch, the unit sub-word line drive circuit is shared by two adjacent sub-memory mats in the column direction, and the unit amplifier circuit and the column selection switch are shared by two adjacent sub-memory mats in the row direction. This makes it possible to reduce the chip size of the dynamic RAM and the like while relaxing the arrangement pitch of the unit sub-word line drive circuit, the unit amplifier circuit, and the column selection switch.

  (3) In the above items (1) and (2), the main word lines and the column selection signal lines are arranged at a pitch that is an integral multiple of the sub word line and the sub bit line, respectively, so that the arrangement pitch of these signal lines is reduced. it can.

  (4) In the above items (1) to (3), each unit sub-word line driving circuit of the sub-word line driving unit is provided between the sub-word line driving signal line and the corresponding sub-word line, and the gate thereof corresponds to the main word. A P-channel type first MOSFET coupled to the inverted signal line of the line, and an N-channel provided between the corresponding sub-word line and the ground potential, the gate of which is coupled to the inverted signal line of the corresponding main word line So-called CMOS static type including a second MOSFET of a type and an N-channel type third MOSFET provided in a form parallel to the first MOSFET and having a gate coupled to a non-inverting signal line of a corresponding main word line. The drive circuit speeds up the operation of selecting a sub-word line, thereby shortening the access time of a dynamic RAM or the like. It can speed up.

  (5) In the above items (1) to (4), a sub-main amplifier for selectively connecting a designated sub-common IO line and a main common IO line is connected to a sub-common IO line corresponding to the gate thereof. A read-out differential MOSFET coupled to the non-inverted and inverted signal lines and having their drains coupled to the inverted and non-inverted signal lines of the corresponding main common IO line, respectively, and non-inverted signals of the sub-common IO line and the main common IO line A so-called pseudo direct sense type sub-amplifier including a write switch MOSFET provided between lines and between inverted signal lines, and by arranging the sub-amplifier in an intersecting region of a sub-word line driver and a sense amplifier, a memory array unit is provided. Read operation of dynamic RAM etc. without increasing the layout area of It can speed up.

  (6) In the above items (1) to (5), the main common IO line and the semiconductor are arranged by arranging the main common IO line in an upper layer of the sub-word line drive unit arrangement area and orthogonal to the sub-common IO line. The main amplifier arranged at the center of the substrate can be effectively coupled.

  (7) In the above items (1) to (6), the sense amplifier drive unit for selectively transmitting the operating power supplied through the drive voltage supply line to the unit amplifier circuit of the sense amplifier is driven by a sub-word line drive. By arranging the sense amplifier driver and related signal lines effectively by arranging them in the intersecting region of the arrangement region of the unit and the sense amplifier, the chip size of a dynamic RAM or the like can be reduced.

  (8) In the above item (7), by driving the unit amplifier circuit of the sense amplifier by the overdrive method, the rise of the operation can be sped up, and the read operation of the dynamic RAM or the like can be sped up.

  (9) In the above items (7) and (8), the electric power supplied to the drive signal line is sequentially transferred to the drive signal line of the sense amplifier to be operated next through predetermined switch means. By employing the use refresh method, the operating current at the time of refresh operation of a dynamic RAM or the like can be reduced, and its power consumption can be reduced.

  (10) In the above items (1) to (9), a sub-bit line of a designated sub-memory mat shared and designated by a predetermined number of sub-memory mats continuously arranged in a row direction in a dynamic RAM or the like is selectively provided. And the required number of unit amplifier circuits and column selection switches for sense amplifiers is reduced by providing a unit amplifier circuit and column selection switches for sense amplifiers corresponding to these main bit lines. However, it is possible to reduce the size of a chip such as a dynamic RAM and the cost thereof.

  (11) In the above items (1) to (10), by using a predetermined number of sub-memory mats in the row and column directions as redundant sub-memory mats, it is possible to efficiently realize defect relief in units of sub-memory mats.

  (12) In the above items (1) to (11), the sense amplifier control signal line for selectively connecting the drive signal line and the drive voltage supply line is arranged above the sense amplifier arrangement region. By arranging the sub-word line drive signal line, the main common IO line, and the drive voltage supply line in the upper layer of the arrangement region of the sub-word line drive section, these signal lines can be efficiently arranged, and the chip size can be reduced.

  (13) In the above items (1) to (12), the main word line, the driving signal line, the sense amplifier control signal, and the like are formed by the second metal wiring layer, and the column selection signal line, the sub word line driving signal line, By forming the main common IO line, the drive voltage supply line, and the like by the third metal wiring layer, these signal lines can be efficiently arranged by utilizing the multilayer wiring, and the chip size can be reduced.

  (14) In the above items (1) to (13), the cost of a dynamic RAM or the like can be reduced by patterning the second and third metal wiring layers without using a phase shift mask. Can be.

  (15) In the above items (1) to (14), a dynamic RAM or the like has a triple well structure, a relatively small negative potential is applied as a substrate voltage of a P-type semiconductor substrate, and a memory array, a sense amplifier and a sub-word line are applied. An N-channel MOSFET forming a driving unit is formed in a P-well region on a P-type semiconductor substrate, and an N-channel MOSFET forming a peripheral circuit is connected to a ground potential in a relatively deep N-well region to which a power supply voltage is applied. An N-channel MOSFET formed in the applied P-well region and constituting a data input / output circuit is supplied with a ground potential or a relatively large negative absolute potential in a relatively deep N-well region to which a power supply voltage is applied. Forming a well region between the memory array and a sense amplifier or a sub-word line driving unit Eliminating the blocking region for, it is possible to reduce the chip size of such dynamic RAM, it is possible to eliminate the risk of latch-up at particular power-on.

  (16) In the above items (1) to (14), the dynamic RAM or the like has a triple well structure, a ground potential is applied as a substrate voltage of a P-type semiconductor substrate, and a memory array, a sense amplifier, and a sub-word line driver are provided. An N-channel MOSFET is formed in a P-well region to which a relatively small absolute value of a negative potential is applied in a relatively deep N-well region to which a word line selection potential is applied, and an N-channel MOSFET constituting a peripheral circuit is formed. A MOSFET is formed in a P-well region on a P-type semiconductor substrate, and an N-channel MOSFET constituting a data input / output circuit is connected to a ground potential or a relatively large absolute value in a relatively deep N-well region to which a power supply voltage is applied. The memory array and the sense amplifier or the sub-word line driving unit are formed in the P well region to which the negative potential of In addition to eliminating the cutoff region for isolating the well region, the chip size of the dynamic RAM or the like can be reduced, and the fluctuation of the substrate voltage in the P-type semiconductor substrate becomes noise and is transmitted to the memory cells forming the memory array. Can be prevented.

  (17) In the above items (1) to (14), the dynamic RAM or the like has a triple-well structure, a ground potential is applied as a substrate voltage of a P-type semiconductor substrate, and an N constituting a memory array and a sub-word line driver is formed. A channel MOSFET is formed in a P-well region to which a relatively small absolute value of a negative potential is applied in a relatively deep N-well region to which a word line selection potential is applied, and an N-channel constituting a sense amplifier and a peripheral circuit is formed. A MOSFET is formed in a P-well region on a P-type semiconductor substrate, and an N-channel MOSFET constituting a data input / output circuit is connected to a ground potential or a relatively large absolute value in a relatively deep N-well region to which a power supply voltage is applied. Is formed in the P-well region to which the negative potential is applied, so that the fluctuation of the substrate voltage in the P-type semiconductor substrate causes noise and Te is transmitted to the memory cell, along with noise associated with operation of the sense amplifier can be prevented from being transmitted to the memory cell, it can be eliminated the risk of latch-up, especially at power-on.

  (18) According to the above items (1) to (17), it is possible to increase the speed, the degree of integration, the scale, and the cost of the dynamic RAM and the like as a whole.

  As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and may be variously modified without departing from the gist thereof. Needless to say. For example, in FIG. 1, the dynamic RAM can include an arbitrary number of memory blocks, and its bit configuration is also arbitrary. Further, the power supply voltage VCC can take an arbitrary potential, and the specific potentials of the internal voltages VCH, VCL, HVC, VB1 and VB2 formed by the internal voltage generating circuit VG are not restricted by this embodiment. Furthermore, various embodiments can be adopted for the block configuration of the dynamic RAM, the names and combinations of the start control signals, the configuration of each memory block, and the like.

  In FIG. 2, the substrate layout of the dynamic RAM, the shape of the semiconductor substrate, and the like are not restricted by this embodiment. 3 and 4, each of the memory blocks MB0 to MB3 can have an arbitrary number of sub-memory mats, and the combination of pairs of the sub-memory mats, the arrangement direction of each signal line, and the like may vary. It can take the form. 5 and 6, the relationship between the unit sub-word line driving circuit of the sub-word line driving unit and the sub-word line of the memory array, and the relationship between the unit circuit of the sense amplifier and the sub-bit line of the memory array can take various combinations. The main word line may be provided corresponding to, for example, four sub-word lines, or the bit line selection signal may be provided corresponding to, for example, eight sets of sub-bit lines.

  7 to 9, each unit sub-word line driving circuit of the sub-word line driving unit may be constituted by, for example, a two-input CMOS NOR gate receiving a main word line MW30 and sub-word line driving signals DX40 to DX43. In this case, the main word line becomes a single signal line, so that the arrangement pitch of the main word lines can be further reduced. The specific configuration of the unit sub-word line drive circuit can take various embodiments. In FIG. 10, the sense amplifier does not require the use of the shared sense method. In FIGS. 10, 11, and 13, the drive MOSFETs P4, P8, P9, and NE constituting the sense amplifier drive circuit SAD may be replaced with a plurality of drive MOSFETs in a parallel form. The specific configuration of the sense amplifier SAR34, the sense amplifier driver SDR34, and the like, the conductivity type of the MOSFET, and the like can take various embodiments.

  15 to 17, the arrangement positions and the order of the signal lines, the number of metal wiring layers and the like, the method of using the same, and the like are not restricted by this embodiment. 18 to 23, a ground potential VSS can be supplied as a substrate voltage to a P well region PW6 serving as a formation region of a data input / output circuit IO, and a deep N well region DNW2 is provided therebelow. Is not an essential condition of the dynamic RAM. Further, various embodiments can be adopted for the specific well structure, substrate voltage, combination thereof, and the like in each example.

  In the above description, the case where the invention made by the present inventor is mainly applied to a dynamic RAM, which is the application field as the background, has been described. However, the present invention is not limited thereto. It can be applied to various memory integrated circuits such as a type RAM and a digital integrated circuit incorporating such a memory integrated circuit. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor memory device in which a hierarchical structure of at least a word line, a bit line, and a common IO line is effective, and to a device and a system incorporating such a semiconductor memory device.

  The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application. That is, a memory mat such as a dynamic RAM is formed by sub-word lines and sub-bit lines arranged orthogonally to each other, and a memory array including dynamic memory cells arranged in a grid at the intersections of these sub-word lines and sub-bit lines; A sub-word line driving unit including a unit sub-word line driving circuit provided corresponding to a sub-word line; a sense amplifier including a unit amplifying circuit and a column selection switch provided corresponding to a sub-bit line; A plurality of sub-memory mats, each having a sub-common IO line selectively connected via a switch, and divided into a plurality of sub-memory mats, and these sub-memory mats are arranged in a grid pattern, Arranged at a pitch that is an integral multiple of the sub-word line and sub-bit line A main word line and column selection signal lines, Sabukomon IO line specified forms the main common IO lines are selectively connected.

  Each of the unit sub-word line driving circuits of the sub-word line driving section is provided between a sub-word line driving signal line and a corresponding sub-word line, and has a gate coupled to an inverted signal line of a corresponding main word line. A first MOSFET, an N-channel type second MOSFET provided between a corresponding sub-word line and a ground potential and having a gate coupled to an inverted signal line of a corresponding main word line, and a first MOSFET And a so-called CMOS static type driving circuit including an N-channel type third MOSFET provided in parallel with a gate connected to a non-inverting signal line of a corresponding main word line, and a designated sub-common IO line Sub-amplifier for selectively connecting the sub-com- mon amplifier to the main common IO line A read-out differential MOSFET coupled to the non-inverted and inverted signal lines of the IO line and having their drains coupled to the inverted and non-inverted signal lines of the main common IO line, respectively; A so-called pseudo direct type sense amplifier including write switch MOSFETs provided between signal lines and between inverted signal lines, respectively, is arranged in an intersecting region of the arrangement region of the sub-word line driver and the sense amplifier.

  As a result, the row select signal transmitted through the main word line and the sub-word line drive signal transmitted through the sub-word line drive signal line are first converted to the unit sub-word line drive circuit by employing the CMOS static drive circuit. At the same time, the effective level is set to enable the sub-word line selecting operation to be performed at high speed. The adoption of the pseudo direct sense type sub-amplifier for the sub-main amplifier and the arrangement in the crossing region thereof allow the dynamic area without increasing the layout area of the memory array. The reading operation of the type RAM or the like can be sped up.

  Furthermore, the hierarchical structure is comprehensively adopted for all of the word lines, bit lines, and common IO lines to realize a dynamic RAM or the like having a configuration capable of sufficiently exhibiting the effects of the hierarchical structure. High speed, high integration, large scale, and low cost of a RAM and the like can be achieved.

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied. FIG. 2 is a board layout diagram showing one embodiment of the dynamic RAM of FIG. 1. FIG. 2 is a block diagram showing one embodiment of a memory block included in the dynamic RAM of FIG. 1. FIG. 4 is a partial block diagram showing one embodiment of a sub memory mat included in the memory block of FIG. 3; FIG. 5 is a partial connection diagram illustrating an embodiment of the sub memory mat of FIG. 4. FIG. 5 is a partial circuit diagram showing one embodiment of a memory array and a peripheral portion included in the sub memory mat of FIG. 4. FIG. 5 is a partial circuit diagram and a signal waveform diagram illustrating a first example of a sub-word line driving unit included in the sub-memory mat of FIG. 4; FIG. 9 is a partial circuit diagram and a signal waveform diagram showing a second embodiment of the sub-word line drive section included in the sub-memory mat of FIG. FIG. 9 is a partial circuit diagram and a signal waveform diagram showing a third embodiment of the sub-word line driving unit included in the sub-memory mat of FIG. FIG. 5 is a partial circuit diagram illustrating a first embodiment of a sense amplifier and a sense amplifier driver included in the sub memory mat of FIG. 4. FIG. 9 is a partial circuit diagram illustrating a second embodiment of the sense amplifier driver included in the sub memory mat of FIG. 4. FIG. 12 is a signal waveform diagram illustrating one embodiment of the sense amplifier driving unit of FIGS. 10 and 11. FIG. 13 is a partial circuit diagram illustrating a third embodiment of the sense amplifier driving unit included in the sub memory mat of FIG. 4. FIG. 14 is a signal waveform diagram illustrating one embodiment of the sense amplifier driving unit of FIG. 13. FIG. 5 is a plan layout view showing one embodiment of a memory array of a sub memory mat of FIG. 4 and a metal wiring layer in a peripheral portion. FIG. 5 is a partial plan view showing one embodiment of a sub-word line driving unit included in the sub-memory mat of FIG. 4; FIG. 5 is a partial plan layout diagram showing one embodiment of a sense amplifier and a sense amplifier driving unit included in the sub memory mat of FIG. 4. FIG. 2 is a symbolic plan view showing a first embodiment of a memory array and a peripheral portion constituting a sub memory mat of the dynamic RAM of FIG. 1. FIG. 2 is a symbolic plan view showing a second embodiment of a memory array and a peripheral portion constituting a sub memory mat of the dynamic RAM of FIG. 1. FIG. 9 is a symbolic plan view showing a third embodiment of a memory array and a peripheral portion constituting a sub memory mat of the dynamic RAM of FIG. 1. FIG. 19 is a sectional structural view showing one embodiment of the memory array and the peripheral portion of FIG. 18. FIG. 20 is a sectional structural view showing one embodiment of the memory array and the peripheral portion of FIG. 19; FIG. 21 is a sectional structural view showing one embodiment of the memory array and peripheral portions of FIG. 20.

Explanation of reference numerals

MB0 to MB3: memory block, MATL, MATR: memory mat, XD: X address decoder, XB: X address buffer, YDL, YDR: Y address decoder, YB: Y address Buffer, BS: memory block selection circuit, MAL, MAR: main amplifier, IO: data input / output circuit, TG: timing generation circuit, VG: internal voltage generation circuit. PSUB: P-type semiconductor substrate, PC: Peripheral circuit SML00 to SML77, SMR00 to SMR77: Sub memory mat, ARYR00 to ARYR77: Memory array, WDR00 to WDR78: Subword line drive, SAR00 SAR87: sense amplifier, SDR00 to SDR87: sense amplifier drive unit MW30 * to MW363 *: main word line, SW0 to SW511: subword line, USWD: unit subword line drive circuit, SB0 * To SB255 *: Sub bit line, USA: Sense amplifier unit circuit, YS40 to YS463: Bit line selection signal, SIO0 * to SIO3 *: Subcommon IO line, MIO00 * to MIO03 *, MIO20 * ~ MIO23 *, MIO40 * ~ MI 43 *, MIO60 * to MIO63 *: Main common IO line, DX40 to DX47: Subword line drive signal, SH3L, SH3R: Shared control signal USWD0 to USWD511: Unit subword line drive circuit, USA0 USA255: Unit sense amplifier SAD: Sense amplifier drive circuit, SAP3, SAN3: Sense amplifier control signal line, CPP2, CPP4, CPN2, CPN4: Sense amplifier drive voltage supply line, PP, PN ..Common source line, SMA ... Sub main amplifier, WE3, RE3, WRE3 ... Sub main amplifier control signal line, SH3LB, SH3RB ... Inverted shared control signal line, PC, PCS ... Precharge Internal control signal lines for control SAP31, SAP32 ... P1-P7 P-channel MOSFET, N1-NR N-channel MOSFET, V1-V3 Inverter M1-M3 Metal wiring layer, FG, SG ... Gate layer ARY1- ARY4: memory array, WD1 to WD2: sub-word line driver, SA1 to SA2: sense amplifier, DNW1 to DNW5: relatively deep N-well region, NW1 to NW16 ... relatively shallow N Well region, PW1 to PW15: relatively shallow P well region, MC: memory cell, PMOS: P-channel MOSFET, NMOS: N-channel MOSFET.

Claims (9)

A first main word line, a plurality of first sub word lines provided corresponding to the first main word line, a plurality of first bit lines intersecting the plurality of first sub word lines, and a plurality of first bit lines; A first memory array having a plurality of first memory cells provided at intersections of a sub-word line and the plurality of first bit lines;
A second main word line, a plurality of second sub word lines provided corresponding to the second main word line, a plurality of second bit lines intersecting the plurality of second sub word lines, and a plurality of second bit lines; A second memory array having a plurality of second memory cells provided at intersections of a sub-word line and the plurality of second bit lines;
A first sub-common IO line connected to the plurality of first bit lines and extending in a first direction;
A second sub-common IO line connected to the plurality of second bit lines and extending in the first direction;
A main IO line connected to the first and second sub-common IO lines and extending in a second direction crossing the first direction;
A plurality of first switch circuits provided between each of the plurality of first bit lines and the first sub-common IO line;
A plurality of second switch circuits provided between each of the plurality of second bit lines and the second sub-common IO line;
A first amplifier circuit provided between the first sub-common IO line and the main IO line, for amplifying a signal transmitted through the first sub-common IO line;
A semiconductor device comprising: a second amplifier circuit provided between the second sub-common IO line and the main IO line, for amplifying a signal transmitted through the second sub-common IO line. In claim 1,
A first region and a second region forming a square;
A third region provided between the first region and the second region along one side of the second region and forming a rectangle having a long side in the first direction;
A fourth region provided along the other side of the second region facing one side of the second region and forming a rectangle having a long side in the first direction;
A fifth region provided along the first and second regions and forming a rectangle having a long side in the second direction so as to have a region intersecting with the third and fourth regions;
The first area includes the first memory array,
The second area includes the second memory array,
The third region is provided corresponding to each of the plurality of first bit lines, and includes a plurality of first sense amplifiers for amplifying a signal read from the plurality of first bit lines to a first voltage. , The plurality of first switch circuits, and the first sub-common IO line,
The fourth region is provided corresponding to each of the plurality of second bit lines, and a plurality of second sense amplifiers for amplifying a signal read from the plurality of second bit lines to the first voltage. , The plurality of second switch circuits, and the second sub-common IO line,
The fifth area includes the main IO line,
A region where the third region and the fifth region intersect includes the first amplifier circuit;
A semiconductor device including the second amplifier circuit in a region where the fourth region and the fifth region intersect. In claim 2,
The first amplifier circuit includes a first MOSFET having a gate connected to the first sub-common IO line, and outputs an amplified signal from a drain of the first MOSFET.
The semiconductor device, wherein the second amplifier circuit includes a second MOSFET having a gate connected to the second sub-common IO line, and outputs an amplified signal from a drain of the second MOSFET. In any of claims 2 or 3,
A region where the third region and the fifth region intersect includes a first sense amplifier driving circuit for supplying the first voltage to the plurality of first sense amplifiers;
A semiconductor device including a second sense amplifier driving circuit for supplying the first voltage to the plurality of second sense amplifiers in a region where the fourth region and the fifth region intersect. In claim 4,
The first sense amplifier driving circuit supplies a second voltage higher than the first voltage at the start of the operation of the plurality of first sense amplifiers, and supplies the first voltage after a predetermined period has elapsed
The semiconductor device, wherein the second sense amplifier driving circuit supplies the second voltage when the plurality of second sense amplifiers start operating, and supplies the first voltage after a lapse of a predetermined period. In any one of claims 1 to 5,
A plurality of first sub-word line driving circuits provided between the first main word line and each of the plurality of first sub-word lines;
A plurality of second sub-word line driving circuits provided between the second main word line and each of the plurality of second sub-word lines;
The semiconductor device, wherein each of the plurality of first and second sub-word line drive circuits is a CMOS static drive circuit. In any one of claims 1 to 6,
A plurality of Y selection lines respectively provided for controlling conduction states of the plurality of first and second switch circuits;
The first main word line and the plurality of Y selection lines intersect on the first memory array;
The semiconductor device, wherein the second main word line and the plurality of Y selection lines cross on the second memory array. In claim 7,
The main IO line and the plurality of Y selection lines are formed in the same wiring layer,
A semiconductor device in which the first and second main word lines and the first and second sub-common IO lines are formed in the same wiring layer. A hierarchical word line having a word line driving circuit, and a hierarchical IO line having a bit line, a sub-common IO line, and a main common IO line;
A semiconductor device having an amplifier between the sub-common IO line and the main common IO line.

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