JP4485551B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, for example, a large-capacity dynamic RAM (random access memory) and a technology that is particularly effective when used for further higher speed, higher integration, larger scale, and lower cost.

  A dynamic type including a plurality of word lines and bit lines arranged orthogonal to each other and a memory array including a large number of dynamic type memory cells arranged in a lattice form at intersections of these word lines and bit lines. There are semiconductor memory devices such as RAM. In recent years, the dynamic RAM and the like have been highly integrated and large-scaled, and various techniques for further promoting this are being disclosed.

That is, for example, “International Solid-State Circuits Conference (ISSCC) '93 Digest Of Technical Papers Session (Session 3)” dated February 24, 1993. On pages 50 to 51, the main word lines are arranged in parallel to the sub word lines and at an integer multiple pitch, thereby reducing the wiring pitch of the metal wiring layer serving as the main word lines, and the dynamic RAM, etc. A so-called hierarchical word line structure has been proposed that can promote higher integration of the device. For example, Japanese Patent Publication No. 4-59712 discloses a dynamic RAM that reduces the load on a sense amplifier by connecting a designated bit line to a main common IO line via a relatively short sub-common IO line. A so-called hierarchical IO structure that can speed up read operations such as the above has been proposed. Furthermore, in US Pat. No. 5,274,595 dated December 28, 1993, the sub-common IO line and the main common IO line are connected via a plurality of direct sense sub-amplifiers that are driven by addition, and these A method for increasing the speed of dynamic RAMs and the like while suppressing the increase in layout area due to the provision of a plurality of sub-amplifiers by arranging the sub-amplifier in the intersection region of the word line shunt portion and the sense amplifier arrangement region is proposed Has been.
IS S.C.'93 Digest of Technical Papers Session 3 (ISSCC: International Solid-State Circuits '93 Digest of Technical Papers Session 3) pp. 50-51, Feb. 24, 1993 Japanese Examined Patent Publication No. 4-59712 US Pat. No. 5,274,595

  However, in the first conventional example adopting the hierarchical word line structure, the row selection signal transmitted via the main word line and the word line drive current supply signal line arranged orthogonal to the sub word line are transmitted. The word line drive circuit for selectively setting the corresponding sub word line in accordance with the word line drive current supply signal to be selected is a so-called self-boot type, so that the main word line is driven to the effective level and then the word line drive is performed. A predetermined time is required until the current supply signal becomes an effective level. This restricts the speeding up of the access time in the read mode of the dynamic RAM and the like, and the common IO line is not a hierarchical structure. As a result, the speed of the access time is hindered. Further, in the second conventional example adopting the above hierarchical IO structure, the arrangement pitch of the metal wiring layers serving as the word lines becomes difficult because the word lines are not made into the hierarchical structure, thereby restricting the high integration of the dynamic RAM and the like. Receive. Furthermore, in the third embodiment in which the sub-common IO line and the main common IO line are connected via a plurality of direct-sense sub-amplifiers that are added and driven, the word lines are divided by the word shunt method, but the hierarchical word Since the line structure is not adopted, the high integration of the dynamic RAM or the like is restricted, and the sub-common IO line and the main common IO line are arranged with the same length, so that a substantial hierarchical IO structure is not obtained.

  That is, in the conventional dynamic RAM and the like, a hierarchical structure having various effects is partially and sporadically adopted, and a comprehensive adoption for all of the word lines, bit lines, and common IO lines is not seen. However, as a result, the effect as a hierarchical structure cannot be sufficiently obtained, and the speed, high integration, large scale, and low cost of the dynamic RAM etc. are restricted as a whole. is there.

  The object of the present invention is to realize a dynamic RAM having a structure capable of fully exhibiting the effects of the hierarchical structure, and further increase the speed, integration, scale and cost of the dynamic RAM, etc. Is to plan.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, the plurality of first and second sub word lines are provided corresponding to the main word line. A plurality of first and second memory cells are provided at intersections of the plurality of first and second bit lines intersecting with the first and second sub-word lines, respectively, thereby constituting first and second memory arrays. The sub-common IO line is connected to the plurality of first and second bit lines and extends in the first direction. The main IO line is connected to the sub-common IO line and extends in the second direction intersecting the first direction. A plurality of first and second switch circuits are provided between each of the plurality of first and second bit lines and the sub-common IO line. The amplifier circuit is provided between the sub-common IO line and the main IO line, and amplifies the signal transmitted through the sub-common IO line. The length of the sub-common IO line is shorter than the length of the main IO line.

  It is possible to obtain a dynamic RAM having a configuration that can sufficiently exhibit the effects of the hierarchical structure.

  FIG. 1 is a block diagram showing an embodiment of a dynamic RAM (semiconductor memory device) to which the present invention is applied. The outline of the configuration and operation of the dynamic RAM of this embodiment will be described first with reference to FIG. 1 is a known MOSFET (metal oxide semiconductor field effect transistor. In this specification, a MOSFET is a generic name for an insulated gate field effect transistor) integrated circuit. It is formed on a single semiconductor substrate such as single crystal silicon by a manufacturing technique. In the following drawings, the names of terminals and signal lines are used repeatedly as names of signals transmitted through these terminals or signal lines or their wirings, unless otherwise specified. Further, in the following circuit diagrams, MOSFETs with an arrow attached to the channel (back gate) portion are P-channel type, and are distinguished from N-channel MOSFETs without an arrow.

  In FIG. 1, the dynamic RAM of this embodiment has four memory blocks MB0 to MB3 as its basic components, and these memory blocks are represented by an X address as represented by the memory block MB1 in the figure. A pair of memory mats MATL and MATR sandwiching the decoder XD, main amplifiers MAL and MAR provided corresponding to these memory mats, and Y address decoders YDL and YDR are included. Among these, the X address decoder XD is supplied with i + 1 bit internal address signals X0 to Xi from the X address buffer XB, and the Y address decoders YDL and YDR are supplied with i + 1 bit internal address signals Y0 to Y0. Yi is supplied in common. Further, the X address signals AX0 to AXi and the Y address signals AY0 to AYi are supplied to the X address buffer XB and the Y address buffer YB via the address input terminals A0 to Ai in a time division manner. Further, main amplifiers MAL and MAR are coupled to one input / output terminal of a corresponding unit circuit of data input / output circuit IO via 8-bit internal data buses IOB0 to IOB7, and the other input / output terminals of these unit circuits are connected. The terminals are coupled to corresponding data input / output terminals IO0-IO7.

  Here, the memory mats MATL and MATR constituting the memory blocks MB0 to MB3 each include 64 sub-memory mats arranged in a lattice shape, as will be described later, and these sub-memory mats are orthogonal to each other. A memory array including a predetermined number of sub word lines and sub bit lines and a large number of dynamic memory cells arranged in a lattice at intersections of these sub word lines and sub bit lines, and a sub word line of the memory array. A sub-word line driving unit including a unit sub-word line driving circuit provided, a unit amplifier circuit provided corresponding to the sub-bit line and a sense amplifier including a column selection switch, and a designated sub-bit line is selected via the column selection switch Sub-common IO lines connected to each other. Further, on the upper layer of the 64 sub-memory mats arranged in a lattice pattern, a main word line starting from the X address decoder XD and a bit line selection signal (column selection signal starting from the Y address decoder YDL or YDR) are provided. Lines) are arranged orthogonal to each other, and a predetermined number of main common IO lines starting from the main amplifier MAL or MAR are arranged in parallel with these bit line selection signals. The specific configuration, operation, arrangement, and the like of the memory blocks MB0 to MB3 and the sub memory mats constituting each memory block will be described in detail later.

  The X address buffer XB and the Y address buffer YB capture and hold the X address signals AX0 to AXi or the Y address signals AY0 to AYi that are input in a time division manner via the address input terminals A0 to Ai. Internal address signals X0 to Xi or Y0 to Yi are formed based on the address signal or Y address signal and supplied to the X address decoder XD or Y address decoders YDL and YDR of the memory blocks MB0 to MB3. Note that the internal address signals Xi and Yi of the most significant bit are also supplied to the memory block selection circuit BS.

  The X address decoder XD decodes the internal address signals X0 to Xi supplied from the X address buffer XB, and alternatively sets the corresponding main word line to an effective level. The Y address decoders YDL and YDR decode the internal address signals Y0 to Yi supplied from the Y address buffer YB, and alternatively set the corresponding bits of the bit line selection signal to the effective level, that is, the selection level. In this embodiment, the main word line is a complementary signal line composed of non-inverted and inverted signal lines, as will be described later. The main word lines are arranged at a pitch X times that of the sub word lines constituting the sub memory mat, that is, eight times, and the bit line selection signals are arranged at a pitch Y times that of the sub bit lines, that is, four times. For this reason, the sub word line driving unit of the sub memory mat drives the row selection signal transmitted via the corresponding 64-bit main word line and the sub word line driving transmitted via the 8-bit sub word line driving signal line described later. A unit subword line driving circuit for selectively selecting a corresponding subword line in accordance with the signal, and some of the internal address signals X0 to Xi supplied to the X address decoder XD are those subword line driving signals. Is selectively used to make it an effective level. The sense amplifiers of the sub memory mats are selectively turned on in response to the effective level of the corresponding bit line selection signal, and four pairs are simultaneously turned on, and between the corresponding four complementary bit lines and the sub-common IO lines. A switch MOSFET for selectively connecting is included.

  Next, the main amplifiers MAL and MAR receive write data supplied from the data input / output terminals IO0 to IO7 via the data input / output circuit IO and the internal data buses IOB0 to IOB7 when the dynamic RAM is in the write mode. Then, data is written to selected eight memory cells of the designated sub memory mat of the memory mat MATL or MATR via the main common IO line, the sub main amplifier, and the sub common IO line. When the dynamic RAM is set to the read mode, the selected eight memory cells of the designated sub memory mat of the memory mat MATL or MATR are connected via the sub common IO line, the sub main amplifier, and the main common IO line. The output read signal is amplified and transmitted to the corresponding unit circuit of the data input / output circuit IO via the internal data buses IO0 to IO7. These read signals are output to the outside of the dynamic RAM from each unit circuit of the data input / output circuit IO via the data input / output terminals IO0 to IO7.

  The memory block selection circuit BS decodes the internal address signals Xi and Yi of the most significant bits supplied from the X address buffer XB and the Y address buffer YB, and selectively selects memory block selection signals BS0 to BS3 (not shown) to an effective level. And These memory block selection signals are supplied to the corresponding memory blocks MB0 to MB3 and are used for selectively activating them.

  The timing generation circuit TG is supplied with a row address strobe signal RASB supplied as an activation control signal from the outside (here, an inverted signal or the like that is selectively set to a low level when it is valid is indicated by B at the end of its name). The same applies hereinafter), and various internal control signals are selectively formed based on the column address strobe signal CASB and the write enable signal WEB, and supplied to each part of the dynamic RAM. The internal voltage generation circuit VG forms internal voltages VCH, VCL, HVC, VB1 and VB2 based on the power supply voltage VCC and the ground potential VSS supplied as operation power from the outside, and supplies them to each part of the dynamic RAM. To do. Although not particularly limited, the power supply voltage VCC is set to a positive potential such as + 3.3V, and the internal voltage VCH is set to a positive potential having a relatively large absolute value such as + 4V. The internal voltage VCL is a positive potential having a relatively small absolute value such as + 2.2V, and the internal voltage HVC is an intermediate potential between the internal voltage VCL and the ground potential VSS, that is, + 1.1V. Further, the internal voltage VB1 is a negative potential having a relatively small absolute value such as −1V, and the internal voltage VB2 is a negative potential having a relatively large absolute value such as −2V.

  FIG. 2 shows a substrate layout of one embodiment of the dynamic RAM of FIG. The outline of the chip layout of the dynamic RAM of this embodiment will be described with reference to FIG. In the following description regarding the layout, the top, bottom, left, and right of each placement surface such as a chip are represented by the positional relationship of the corresponding placement diagram.

  In FIG. 2, the dynamic RAM of this embodiment is the base of a P-type semiconductor substrate PSUB. Further, the dynamic RAM of this embodiment adopts a so-called LOC (Lead On Chip) form, and the bonding pad for connecting the inner lead and the semiconductor substrate PSUB is linear along the vertical center line of the semiconductor substrate PSUB. Placed in. Therefore, in the vicinity of these bonding pads, that is, in the central portion of the semiconductor substrate PSUB, the peripheral circuit PC including the X address buffer XB, the Y address buffer YB, the data input / output circuit IO, and the like is disposed. Furthermore, memory blocks MB0 and MB1 are respectively arranged on the upper left and upper right of the semiconductor substrate PSUB, and memory blocks MB2 and MB3 are respectively arranged on the lower left and lower right. In these memory blocks, the main common IO line and the sub bit lines constituting each sub memory mat are arranged in the horizontal direction in the figure, that is, the Y address decoders YDL and YDR and the main amplifiers MAL and MAR are provided on the semiconductor substrate PSUB. Arranged as much as possible inside. As a result, the main word line is arranged in the vertical direction in the figure in parallel with the sub word line constituting the sub memory mat, and the sub common IO line constituting the sub memory mat is perpendicular to the main common IO line and perpendicular to the figure. The shape is arranged in the direction. As a result, the main amplifiers MAL and MAR are arranged in the central portion of the semiconductor substrate PSUB, and the main common IO lines coupled to these main amplifiers are arranged orthogonal to the sub-common IO lines, thereby realizing an effective chip layout. Can do.

  FIG. 3 shows a block diagram of an embodiment of the memory block MB0 included in the dynamic RAM of FIG. 4 shows a partial block diagram of an embodiment of the sub memory mat SMR 34 and its peripheral part included in the memory block MB0 of FIG. 3, and FIG. 5 shows a partial block diagram of the embodiment. A simple connection diagram is shown. Further, FIG. 6 shows a partial circuit diagram of an embodiment of the memory array ARYR 34 and its peripheral part included in the sub memory mat SMR 34 of FIG. Based on these drawings, the block configuration of the memory block and the sub memory mat constituting the dynamic RAM of this embodiment, the specific configuration and operation of the memory array constituting the sub memory mat and its peripheral part, and its features A part of will be described. The following description regarding the memory block will be made by taking the memory block MB0 as an example, but the other memory blocks MB1 to MB3 have the same configuration as this, and should be analogized. Further, the following description of the sub memory mat, the memory array, and the peripheral portion will be made with the sub memory mat SMR34 as an example, but the other sub memory mats SMR00 to SMR33 and SMR35 to SMR77 have the same configuration. I want to analogize.

  In FIG. 3, the memory block MB0 includes a pair of memory mats MATL and MATR that sandwich the X address decoder XD, as described above, and each of these memory mats has 64 pieces arranged in an 8 × 8 grid. Sub memory mats SML00 to SML77 and SMR00 to SMR77 are included.

  In this embodiment, the sub memory mats SML00 to SML77 and SMR00 to SMR77 constituting the memory mats MATL and MATR of the memory block MB0 are two pairs adjacent to each other in the column direction as illustrated by diagonal lines in FIG. And four sets of sub-common IO lines SIO0 * to SIO3 * (in this case, for example, the non-inverted sub-common IO line SIO0T and the inverted sub-common IO line SIO0B are combined and denoted by * as the sub-common IO line SIO0 *. Also, a so-called non-inverted signal or the like that is selectively set to a high level when it is valid is represented by adding a T to the end of its name, and so on. Thereby, in the two sub memory mats SMR 34 and SMR 35 that make a pair, defect repair in the column direction in units of the bit line selection signal can be realized. On the other hand, 8 pairs, for example, 16 sub-memory mats SMR04 to SMR74 and SMR05 to SMR75 arranged in the same row have four sets of main common IO lines represented by main common IO lines MIO40 * to MIO43 * and YS40 to Eight, that is, sub memory mats SMR30 to SMR37, for example, which share a 64-bit bit line selection signal typified by YS463 and are arranged in the same row, have 64 sets of main word lines typified by MW30 * to MW363. Share each. The sub memory mats SML00 to SML77 and SMR00 to SMR77 constituting the memory mats MATL and MATR of each memory block can have a part of the row direction and the column direction as redundant sub memory mats. Defect relief in units of mats can be realized.

  Here, sub memory mats SML00 to SML77 and SMR00 to SMR77 are representatively shown as sub memory mat SMR34 of FIG. 4, and memory array ARYR34 and sub word line drive units WDR34 provided below and to the right thereof are provided. Each includes a sense amplifier SAR34. Of these, the memory array ARYR 34 is not particularly limited, but, as illustrated in FIG. 6, substantially 512 sub-word lines SW <b> 0 to SW <b> 511 arranged in parallel to the vertical direction in the figure and the horizontal direction. Substantially 256 sets of sub-bit lines SB0 * to SB255 * are arranged. At intersections of these sub-word lines and sub-bit lines, substantially 131,072 dynamic memory cells including information storage capacitors and address selection MOSFETs are arranged in a lattice pattern. Thereby, each of the sub memory mats SML00 to SML77 and SMR00 to SMR77 has a so-called 128 kilobit storage capacity. Each of the memory blocks MB0 to MB3 has a storage capacity of 128 kg × 64 × 2, that is, a so-called 16 megabit, and the dynamic RAM has a storage capacity of 16 mega × 4, that is, a so-called 64 megabit. Is done.

  Next, as illustrated in FIG. 6, the sub word line driving unit WDR 34 includes 256 unit sub word line driving circuits USWD 0 and USWD 2 provided corresponding to the even-numbered sub word lines SW 0, SW 2 to SW 510 of the memory array ARYR 34. Or USWD510. The output terminals of these unit sub-word line driving circuits are coupled to the corresponding even-numbered sub-word lines SW0, SW2 to SW510 in the memory array ARYR 34 at the upper part thereof, and the corresponding even-numbered sub-memory mat SMR 33 in the lower part thereof. Coupled to numbered sub-word lines SW0, SW2 to SW510. The input terminals above the unit sub word line drive circuits USWD0, USWD2 to USWD 510 constituting the sub word line drive unit WDR34 are commonly coupled in sequence four by four and then sequentially coupled to the corresponding main word lines MW30 * to MW363 *. The In addition, the input terminals below are sequentially commonly coupled every four, and then sequentially coupled to the corresponding sub word line drive signal lines DX40, DX42, DX44 and DX46.

  On the other hand, the odd-numbered sub word lines SW1, SW3 to SW511 constituting the memory array ARYR34 are disposed above the corresponding unit sub word line drive circuits USWD1, USWD3 to USWD511 of the sub word line drive unit WDR35 of the adjacent sub memory mat SMR35. Coupled to the output terminal. The output terminals of these unit sub word line driving circuits are coupled to the odd numbered sub word lines SW1, SW3 to SW511 constituting the memory array ARYR35 of the sub memory mat SMR35 above the unit sub word line driving circuit. The upper input terminals of the unit sub word line drive circuits USWD1, USWD3 to USWD 511 constituting the sub word line drive unit WDR35 are commonly coupled in sequence by four and then sequentially coupled to the corresponding main word lines MW30 * to MW363 *. . In addition, the input terminals below are sequentially coupled every four in turn, and then commonly coupled to the corresponding sub word line drive signal lines DX41, DX43, DX45 and DX47.

  The unit sub word line drive circuits USWD0, USWD2 to USWD 510 and USWD1, USWD3 to USWD 511 of the sub word line drive units WDR34 and WDR35 have the corresponding main word lines MW30 * to MW363 * at the effective level and the corresponding sub word line drive signals DX40, When DX42 to DX46 or DX41, DX43 to DX47 are set to the valid level, the corresponding sub-word lines SW0, SW2 to SW510 or SW1, SW3 to SW511 corresponding to the memory arrays ARYR33 and ARYR34 or ARYR34 and ARYR35 are selectively selected. Level.

  As is apparent from the above, in the dynamic RAM of this embodiment, for example, the 512 sub word lines SW0 to SW 511 constituting the sub memory mat SMR34 are provided on the both sides, that is, a pair of sub word line driving units provided on the upper and lower sides. Coupled to the corresponding unit subword line driving circuits of WDR34 and WDR35, the sub memory mat SMR34 substantially requires two subword line driving units, but each unit subword line driving circuit of the subword line driving unit includes: As described above, since it is shared by the corresponding sub-bit lines of two sub-memory mats adjacent in the column direction, the additional number of the sub-word line driver and the additional number of the sub-memory mat are made to correspond to each other. . On the other hand, when attention is paid to the memory array ARYR34 of the sub memory mat SMR34, the corresponding unit sub word line drive circuits of the sub word line drive units WDR34 and WDR35 are alternately and alternately arranged below or above the sub word lines SW0 to SW511. The main word lines MW30 * to MW363 * corresponding to the eight are sequentially shared. As a result, each unit sub word line driving circuit may be arranged at a pitch twice as large as the sub word line, and each main word line may be arranged at a pitch X times that of the sub word line, that is, eight times. As a result, the arrangement pitch of the unit sub-word line driving circuit and the complementary main word line can be relaxed, and higher integration and larger scale of the dynamic RAM can be promoted. The specific configuration and operation of the unit sub word line drive circuits USWD0 to USWD 511 constituting the sub word line drive unit WDR34 and the like will be described in detail later. Further, the connection form will be further clarified by referring to FIG. 3 to FIG.

  Next, the sub bit lines SB0 * to SB255 * constituting the memory array ARYR34 of the sub memory mat SMR34 are connected to the right side thereof via N-channel type shared MOSFETs NA and NB that receive the shared control signal SH3L in common at their gates. Sense amplifiers of adjacent sub-memory mats SMR44 are coupled to corresponding unit circuits USA0 and USA3 to USA252 and USA255 of the sense amplifier SAR34, and on the left side thereof through a similar shared MOSFET that commonly receives a shared control signal SH4R at its gate. Coupled to the corresponding unit circuits USA1 and USA2 through USA253 and USA254 of the amplifier SAR44. The unit circuits USA0 and USA3 and the like of the sense amplifier SAR34 are further arranged on the right side of the memory array ARYR24 of the adjacent sub memory mat SMR24 via N-channel type shared MOSFETNC and ND that receive the shared control signal SH3R in common at their gates. Are connected to the corresponding sub-bit lines SB0 * and SB3 *, etc., and the unit circuits USA1 and USA2 etc. of the sense amplifier SAR35 are connected to the left via a similar shared MOSFET that commonly receives the shared control signal SH4L at their gates. Coupled to corresponding sub-bit lines SB1 * and SB2 * of memory array ARYR44.

  Four corresponding bit line selection signals YS40 to YS463 are sequentially supplied in common to each unit circuit of the sense amplifiers SAR34 and SAR44. Further, as will be described later, these unit circuits include a unit amplifier circuit in which a pair of CMOS inverters are cross-coupled with each other and a pair of switch MOSFETs (columns) that commonly receive bit line selection signals YS40 to YS463 corresponding to their gates. Selection switch). Among these, each unit amplifier circuit is selectively activated by operating power supplied through a common source line (not shown), and the corresponding sub-bit line is selected from the memory cell coupled to the selected sub-word line. A minute read signal output via the signal is amplified to obtain a binary read signal of high level or low level. Further, the switch MOSFET pairs of each unit circuit are selectively turned on by four pairs when the corresponding bit line selection signals YS40 to YS463 are set to the effective level, and the corresponding four sub bit lines of the memory array ARYR34 The sub-common IO lines SIO0 * to SIO3 * are selectively connected.

  The sub-common IO lines SIO0 * and SIO1 * are shared by two sub-memory mats SMR34 and SMR35 adjacent in the column direction as illustrated in FIG. Of these, two sets of sub-common IO lines SIO0 * and SIO1 * are arranged on the right side of these sub-memory mats, that is, in the sense amplifiers SAR34 and SAR35, and the remaining two sets of sub-common IO lines SIO2 * and SIO3 * are Arranged on the left side of these sub memory mats, that is, in the sense amplifiers SAR44 and SAR45. Further, the sub-common IO line SIO0 * is selectively connected to the main common IO line MIO40 * via the sub-main amplifier SMA of the sense amplifier driver SDR34 provided at the lower right of the sub-memory mat SMR34, and the sub-common IO line SIO1. * Is selectively connected to the main common IO line MIO41 * via the sub main amplifier of the sense amplifier driving unit SDR35 provided at the lower right of the sub memory mat SMR35. The sub-common IO line SIO2 * is selectively connected to the main common IO line MIO42 * via the sub-main amplifier of the sense amplifier driver SDR45 provided at the lower right of the sub-memory mat SMR45, and the sub-common IO line SIO3 *. Are selectively connected to the main common IO line MIO43 * via the sub main amplifier of the sense amplifier driver SDR 46 provided at the lower right of the sub memory mat SMR 46.

  As is apparent from the above, in the dynamic RAM of this embodiment, for example, the 256 sets of sub bit lines SB0 * to SB255 * constituting the sub memory mat SMR34 have a pair of sense amplifiers provided on both sides, that is, left and right. The sub-memory mat SMR 34 substantially requires two sense amplifiers coupled to the corresponding unit circuits of the SAR 34 and the SAR 44, but each unit circuit of each sense amplifier is adjacent in the row direction as described above. Therefore, the numbering of the sense amplifier and the numbering of the submemory mat are intentionally matched to correspond to each other. On the other hand, when attention is paid to the memory array ARYR34 of the sub memory mat SMR34, the corresponding unit circuits of the sense amplifiers are alternately arranged on the right or left side of the sub bit lines SB0 * to SB255 *, and four in turn. Corresponding bit line selection signals YS40 to YS463 are shared. Therefore, each unit circuit of the sense amplifier may be arranged at a pitch twice as large as that of the sub-bit line, and each bit line selection signal may be arranged at a pitch of Y times that of the sub-bit line, that is, four times. . As a result, the arrangement pitch of the unit circuit of the sense amplifier and the bit line selection signal can be relaxed, and high integration and large scale of the dynamic RAM can be promoted. The specific configurations of the sense amplifiers SAR34 and SAR44 and the unit circuits USA0 to USA255 will be described later in detail. Further, the connection form will be further clarified by referring to FIG. 3 to FIG.

  In the dynamic RAM of this embodiment, the memory mats MATL and MATR constituting the memory blocks MB0 to MB3 are divided into 64 sub memory mats SML00 to SML77 or SMR00 to SMR77, respectively, and unitized. These sub memory mats are arranged like a memory cell in a grid pattern, and the sub word lines, sub bit lines and sub common IO lines are connected to the main word line, bit line selection signal or main common IO line arranged in the upper layer. Selectively connected and selectively activated. As is apparent to engineers working in the field, dividing a memory mat into a number of sub-memory mats to form a unit gives a degree of freedom regarding the memory mat, that is, the dynamic RAM mat configuration. Increase and contribute to shortening its development period. Further, the unitization into sub memory mats is performed while comprehensively adopting a hierarchical structure for all of the word lines, bit lines, and common IO lines, so that a dynamic RAM that can fully exhibit the effects of the hierarchical structure. As a result, the dynamic RAM can be speeded up, highly integrated, large-scaled, and low in cost.

  FIG. 7 shows a partial circuit diagram and a signal waveform diagram of the first embodiment of the sub word line driving unit WDR 34 included in the sub memory mat SMR 34 of FIG. FIG. 8 shows a partial circuit diagram and a signal waveform diagram of the second embodiment of the sub word line drive unit WDR34 included in the sub memory mat SMR34, and FIG. 9 shows the third embodiment. A partial circuit diagram and a signal waveform diagram are shown. Based on these drawings, the specific configuration and operation of the sub word line driving unit constituting the sub memory mat of the dynamic RAM of this embodiment and its features will be described. The following description regarding the sub word line drive unit will be made by taking the sub word line drive unit WDR 34 of the sub memory mat SMR 34 as an example, but the other sub word line drive units have the same configuration as this, and should be analogized. The following description of the unit sub word line drive circuits USWD0 to USWD510 constituting the sub word line drive unit WDR34 will be made by taking the unit sub word line drive circuit USWD0 as an example. Since this is the same configuration, analogy.

  In FIG. 7, the sub word line driving unit WDR 34 includes 256 unit sub word line driving circuits USWD 0, USWD 2 to USWD 510 provided corresponding to the even-numbered sub word lines SW 0, SW 2 to SW 510 constituting the memory array ARYR 34. Each of the unit sub word line driving circuits is represented by a P channel MOSFET P1 (first channel) provided between the corresponding sub word line driving signal line DX40 and the sub word line SW0, as represented by the unit sub word line driving circuit USWD0. MOSFET) and an N-channel MOSFET N1 (second MOSFET) provided between the corresponding sub word line SW0 and the ground potential VSS. The gates of these MOSFETs P1 and N1 are coupled to the inverted signal line of the corresponding main word line MW30 *, that is, the inverted main word line MW30B. The unit sub word line drive circuit USWD0 further includes an N-channel MOSFET N2 (third MOSFET) provided in parallel with the MOSFET P1, and the gate of the MOSFET N2 is a non-inverted signal line of the corresponding main word line MW30 *, that is, a non-inverted line. Coupled to main word line MW30T.

  Here, the non-inverted main word line MW30T is set to an invalid level such as the ground potential VSS, that is, 0V when not selected, and is set to an effective level such as the internal voltage VCH, that is, + 4V, when selected. Inverted main word line MW30B is set to an invalid level such as internal voltage VCH when not selected, and is set to an effective level such as ground potential VSS when selected. Further, the sub word line drive signal DX40 is set to an invalid level such as the ground potential VSS when not selected, and is set to an effective level such as the internal voltage VCH when selected. As described above, the internal voltage VCH is formed based on the power supply voltage VCC by the internal voltage generation circuit VG built in the dynamic RAM, and is set to a relatively stable potential of + 4V.

  When the corresponding non-inverted main word line MW30T and inverted main word line MW30B are set to the invalid level, in the unit sub word line drive circuit USWD0, the MOSFETs P1 and N2 are both turned off and the MOSFET N1 is turned on. Therefore, the sub word line SW0 is set to a non-selection level such as the ground potential VSS regardless of the level of the corresponding sub word line drive signal DX40.

  On the other hand, when the corresponding non-inverted main word line MW30T and inverted main word line MW30B are set to the effective level, in the unit sub word line drive circuit USWD0, the MOSFET N1 is turned off and the MOSFETs P1 and N2 are turned on instead. . Therefore, sub word line SW0 is set to a selection level such as internal voltage VCH in response to the effective level of corresponding sub word line drive signal DX40, and is set to a non-selection level such as ground potential VSS in response to the invalid level. .

  As described above, the unit sub-word line drive circuit USWD0 and the like constituting the sub-word line drive unit WDR34 and the like of the dynamic RAM of this embodiment is a so-called CMOS (complementary MOS) static drive circuit that does not adopt the self-boot form. Therefore, the main word line MW30 * and the like and the sub word line drive signal DX40 and the like can be simultaneously set to effective levels, and accordingly, the access time in the read mode of the dynamic RAM can be increased.

  The unit sub word line drive circuit including the unit sub word line drive circuit USWD0 is provided between the corresponding non-inverted main word line MW30T and the sub word line SW0 and corresponds to the gate thereof, as shown in FIG. A P-channel MOSFET P1 that receives the sub-word line drive signal DX40 and a gate connected to the corresponding sub-word line drive signal line DX40 and inverted main word line MW30B are provided in parallel between the sub-word line SW0 and the ground potential VSS. N channel MOSFETs N1 and N2 can be used, and as shown in FIG. 9, the gate is provided between the corresponding non-inverted sub word line drive signal line DX40T and the sub word line SW0, and the gate thereof corresponds to the corresponding inverted main word line MW30B. P-channel MOS coupled It is also configured by ETP1 and N-channel MOSFETs N1 and N2 which are provided in parallel between the sub word line SW0 and the ground potential VSS and whose gates are respectively coupled to the corresponding inverted main word line MW30B and inverted sub word line drive signal DX40B. it can. Further, the unit sub-word line drive circuit USWD0 can also be configured by a normal 2-input CMOS NOR gate or the like, but in this case, both the main word line and the sub-word line drive signal can be a single signal line. As a result, the required number of wirings can be further reduced, and the dynamic RAM can be further highly integrated.

  FIG. 10 shows a partial circuit diagram of the first embodiment of the sense amplifier SAR34 and the sense amplifier driver SDR34 included in the sub memory mat SMR34 of FIG. FIG. 11 shows a partial circuit diagram of the second embodiment of the sense amplifier driver SDR34 included in the sub memory mat SMR34 of FIG. 4, and FIG. 12 shows the sense of FIG. 10 and FIG. A signal waveform diagram of an embodiment of the amplifier driver SDR34 is shown. Further, FIG. 13 shows a partial circuit diagram of the third embodiment of the sense amplifier driver SDR34 included in the sub memory mat SMR34 of FIG. 4, and FIG. 14 shows signal waveforms of the embodiment. The figure is shown. Based on these drawings, the specific configuration and operation of the sense amplifier and the sense amplifier drive unit included in the sub-memory mat of the dynamic RAM of this embodiment and its features will be described. The following description regarding the sense amplifier and its unit circuit and the sense amplifier drive unit will be made by taking the sense amplifier SAR34 of the sub memory mat SMR34 and its unit circuit USA0 and the sense amplifier drive unit SDR34 as an example. Since the unit circuit and the sense amplifier drive unit have the same configuration as those of these embodiments, it should be analogized.

  In FIG. 10, the sense amplifier SAR34 includes 128 unit circuits USA0, USA3 to USA252, USA255. An input terminal on the left side of these unit circuits has an N-channel type shared MOSFETNA that commonly receives an inverted signal by the inverter V1 of the sense amplifier driver SDR34 of the inverted shared control signal SH3LB, that is, a non-inverted shared control signal SH3L, at its gate. NB is coupled to corresponding sub-bit lines SB0 *, SB3 * to SB252 *, SB255 * of memory array ARYR34 via NB, and its right input terminal has a sense amplifier driver SDR34 of inverted shared control signal SH3RB at its gate. Sub-bits corresponding to the memory array ARYR24 of the adjacent sub-memory mat SMR24 via N-channel type shared MOSFETs NC and ND that commonly receive the inverted signal by the inverter V3, that is, the non-inverted shared control signal SH3R. SB0 *, SB3 * through SB252 *, is coupled to the SB255 *.

  As a result, the dynamic RAM adopts the shared sense system, and the unit circuits USA0, USA3 to USA252, USA255 of the sense amplifier SAR34 are arranged in a memory array ARYR34 of a pair of sub memory mats SMR34 and SMR24 arranged adjacent to each other. Shared by ARYR 24. When the inverted shared control signal SH3LB is set to the low level and the non-inverted shared control signal SH3L is set to the high level, the corresponding sub bit lines SB0 * and SB3 of the memory array ARYR34 disposed on the left side via the shared MOSFETs NA and NB. * Or selectively connected to SB252 *, SB255 *, when the inverted shared control signal SH3RB is set to low level and the non-inverted shared control signal SH3R is set to high level, it is arranged on the right side via the shared MOSFET NC and ND It is selectively connected to the corresponding sub bit lines SB0 *, SB3 * to SB252 *, SB255 * of the memory array ARYR24.

  Here, each of the unit circuits constituting the sense amplifier SAR34 is represented by a pair of CMOSs including a P-channel MOSFET P2 and an N-channel MOSFET N3, and a P-channel MOSFET P3 and an N-channel MOSFET N4, as representatively shown by the unit circuit USA0 in FIG. N amplifiers provided between the unit amplifier circuits in which inverters are cross-coupled, and the non-inverted and inverted input / output nodes of these unit amplifier circuits and the non-inverted and inverted signal lines of the sub-common IO line SIO0 * or SIO1 *, respectively. It includes a bit line precharge circuit including a pair of channel type switch MOSFETs (column selection switches) N8 and N9, and three N channel MOSFETs N5 to N7 connected in series-parallel.

  Among these, the sources of MOSFETs P2 and P3 constituting the unit amplifier circuit are commonly coupled to a common source line (drive signal line) PP, and the commonly coupled sources of MOSFETs N3 and N4 are commonly coupled to a common source line PN. . The common source line PP is coupled to the drive voltage supply line CPP4 via the P-channel type drive MOSFET P4 constituting the sense amplifier drive circuit SAD of the sense amplifier drive unit SDR34, and the common source line PN is connected to the N-channel type drive MOSFET NE. Is coupled to the drive voltage supply line CPN4. Further, a common IO line precharge circuit in which three N-channel MOSFETs NF to NH are connected in series and parallel is provided between the common source lines PP and PN. The gate of the drive MOSFET P4 constituting the sense amplifier drive circuit SAD is coupled to the sense amplifier control signal line SAP3, and the gate of the drive MOSFET NE is coupled to the sense amplifier control signal line SAN3. Further, an inverted signal of the internal control signal PC for precharge control by the inverter V2, that is, an inverted internal control signal PCB, is commonly supplied to the gates of the MOSFETs NF to NH constituting the common IO line precharge circuit.

  Thus, the unit amplifier circuit of each unit circuit of the sense amplifier SAR34 receives the effective levels of the sense amplifier control signals SAP3 and SAN3, and the drive MOSFETs P4 and NE of the sense amplifier drive circuit SAD are turned on, and the drive voltage supply line CPP4 and A predetermined operation power is supplied from the CPN4 via the common source lines PP and PN, so that the operation state is selectively activated. From 256 memory cells coupled to the selected sub word line of the memory array ARYR34 or ARYR24 The minute read signals output via the corresponding sub-bit lines SB0 * and SB2 * are amplified, respectively, to obtain high-level or low-level binary read signals.

  Next, two pairs of gates of the switch MOSFETs N8 and N9 constituting each unit circuit of the sense amplifier SAR34 are commonly coupled in sequence, and the corresponding bit line selection signal YS40 and the like are supplied from the Y address decoder YD. As described above, the bit line selection signal YS40 and the like are also supplied to the gates of the two pairs of switch MOSFETs such as the unit circuits USA1 and USA2 of the sense amplifier SAR44 provided on the left side of the memory array ARYR34. As a result, the switch MOSFETs N8 and N9 of each unit circuit are turned on selectively and two pairs at a time when the corresponding bit line selection signals YS40 to YS463 are set to the effective level, and the corresponding memory array ARYR34 or ARYR24 corresponds. The two sub bit lines and the sub-common IO lines SIO0 * and SIO1 * are selectively connected.

  On the other hand, the inverted precharge control signal PCB is commonly supplied to the gates of the MOSFETs N5 to N7 constituting the bit line precharge circuit of each unit circuit of the sense amplifier SAR34. The MOSFETs N5 to N7 are selectively turned on in response to the effective level of the inverted precharge control signal PCB, that is, the high level, and between the non-inverted and inverted input / output nodes of the unit amplifier circuit of the corresponding unit circuit of the sense amplifier SAR34. The non-inverted and inverted signal lines of the corresponding sub-bit lines of the memory array ARYR 34 or ARYR 24 are short-circuited and equalized.

  In this embodiment, the memory mats MATL and MATR constituting the memory blocks MB0 to MB3 have an internal voltage VCL having a relatively small absolute value such as +2.2 V in order to miniaturize elements including memory cells. The unit potential circuit constituting the sense amplifier SAR 34 uses the internal voltage VCL and the ground potential VSS supplied via the common source lines PP and PN as its operating power supply. However, the dynamic RAM of this embodiment employs a so-called overdrive system, and the power source voltage VCC, that is, +3.3 V is supplied to the common source line PP only for a predetermined period when the sense amplifier SAR 34 is activated. As a result, the rise of the amplification operation of the unit amplifier circuit of the sense amplifier is accelerated, and the read operation of the dynamic RAM is accelerated.

  Here, the overdrive system of the sense amplifier will be briefly described with reference to the signal waveform diagram of FIG. In FIG. 12, the sense amplifier control signal SAP3 has the power supply voltage VCC, that is, + 3.3V as its invalid level, and the ground potential VSS, that is, 0V, as its effective level. The sense amplifier control signal SAN3 sets the ground potential VSS to its invalid level and the power supply voltage VCC to its valid level. The drive voltage supply line CPP4 is supplied with the power supply voltage VCC at the time of non-selection and until a predetermined time elapses after the sense amplifier control signals SAP3 and SAN3 are set to the effective level, and after the predetermined time elapses, the internal voltage VCL That is, + 2.2V is supplied. The ground potential VSS is constantly supplied to the drive voltage supply line CPN4. A precharge control signal PC (not shown) is set to an effective level such as the ground potential VSS at a predetermined timing when the sense amplifier SAR 34 is inactivated, and an invalid level such as the power supply voltage VCC when the sense amplifier SAR 34 is activated. It is said.

  When the sense amplifier control signals SAP3 and SAN3 are set to an invalid level and the sense amplifier SAR34 is inactivated, the drive MOSFETs P4 and NE constituting the sense amplifier drive circuit SAD are turned off in the sense amplifier drive unit SDR34. The MOSFETs NF to NH constituting the common IO line precharge circuit are simultaneously turned on in response to the effective level of the precharge control signal PC. As a result, the common source lines PP and PN are equalized to an intermediate potential between the internal voltage VCL and the ground potential, that is, the internal voltage HVC, via the MOSFETs NF to NH, and all the unit circuits USA0 and the like of the sense amplifier SAR34 are made inoperative. The At this time, in the memory array ARYR34 or ARYR24, the non-inverted and inverted signal lines of the sub bit lines SB0 * to SB255 * are equalized through the bit line precharge circuit of the corresponding unit circuit of the sense amplifier SAR34, and the internal voltage HVC Pre-charged to an intermediate level.

  On the other hand, when the sense amplifier control signals SAP3 and SAN3 are set to an effective level, the MOSFETs NF to NH constituting the common IO line precharge circuit are turned off in the sense amplifier drive unit SDR34. The driving MOSFETs P4 and NE to be configured are turned on. For this reason, the common source line PP is first supplied with a drive voltage such as the power supply voltage VCC from the drive voltage supply line CPP4 via the drive MOSFET P4, and is supplied with a drive voltage such as the internal voltage VCL after a predetermined time has elapsed. The Further, the ground potential VSS is supplied to the common source line PN via the drive voltage supply line CPN4. As a result, the unit amplifier circuit constituting each unit circuit of the sense amplifier SAR34 is activated, and is output from the memory cell coupled to the selected subword line of the memory array ARYR34 or ARYR24 to the corresponding subbit line SB0 * or the like. Each of the minute read signals is amplified to obtain a high level or low level binary read signal. It should be noted that the power supply voltage VCC for overdrive is supplied to the common source line PP at the beginning of the activation of the sense amplifier SAR34, thereby speeding up the amplifying operation of the unit amplifier circuit. The access time in the read mode is increased.

  In the embodiment of FIG. 12, overdrive of the sense amplifier is realized by temporarily setting the drive voltage supplied via the drive voltage supply line CPP4 to the power supply voltage VCC, as shown in FIG. As described above, the same overdrive can be realized by providing three drive voltage supply lines to which the power supply voltage VCC, the internal voltage VCL, and the ground potential VSS are constantly supplied. That is, in FIG. 13, P-channel type drive MOSFETs P8 and P9 constituting the sense amplifier drive circuit SAD are provided between the common source line PP, the power supply voltage VCC and the internal voltage VCL, respectively, and the common source line PN and the ground. An N-channel type driving MOSFET NE is provided between the potential VSS. Among these, the sense amplifier control signals SAP31 and SAP32 are supplied to the gates of the drive MOSFETs P8 and P9, respectively, and the sense amplifier control signal SAN3 is supplied to the gate of the drive MOSFET NE. In this embodiment, as shown in FIG. 14, the sense amplifier control signal SAP31 is set to the valid level simultaneously with the sense amplifier control signal SAN3, and is returned to the invalid level when a predetermined time has elapsed. The sense amplifier control signal SAP32 is set to the effective level at the same time as the sense amplifier control signal SAP31 is returned to the invalid level when a predetermined time elapses after the sense amplifier control signals SAP31 and SAN3 are set to the effective level. As a result, the power source voltage VCC is supplied to the common source line PP as a drive voltage for a predetermined period from when the sense amplifier control signal SAP31 is set to the effective level to when the sense amplifier control signal SAP32 is set to the effective level. As a result, the same overdrive of the sense amplifier as in FIG. 12 can be realized.

  On the other hand, in the dynamic RAM of this embodiment, the refresh operation of the memory cells proceeds in units of eight sub memory mats SMR00 to SMR07 to SMR70 to SMR77 arranged in the same row. At this time, the sense amplifier control signals SAP0 to SAP7 and SAN0 to SAN7 are sequentially set to valid levels as the refresh operation proceeds. For example, the refresh operation of the sub memory mats SMR30 to SMR37 is completed, and the sub memory mats SMR40 to SMR47. , The sense amplifier control signals SAP3 and SAN3 are set to an effective level simultaneously with the next sense amplifier control signals SAP4 and SAN4 for a predetermined period, and so-called charge reuse refresh is performed. Thereby, charges corresponding to the drive voltage VCL or VSS charged to the common source lines PP and PN of the sense amplifiers SAR30 to SAR37 are transferred to the sense amplifiers SAR30 to SAR37 via the drive voltage supply lines CPP0 to CPP7 and CPN0 to CPN7. It is transmitted to the common source lines PP and PN and reused. As a result, the charge amount of the drive voltage to be supplied via the drive voltage supply lines CPP0 to CPP7 and CPN0 to CPN7 is saved again, and the power consumption of the dynamic RAM can be reduced.

  Returning to the description of FIG. The sense amplifier driver SDR34 of this embodiment further includes a sub main amplifier SMA including a pair of N-channel type differential MOSFETs NP and NQ for reading and a pair of write switch MOSFETs NL and NM, and three P-channel MOSFETs P5 to P5. P7 and N-channel MOSFETs NI to NK are respectively provided with two sub-common IO line precharge circuits formed by series-parallel coupling. Among these, the inverted signal of the internal control signal PC by the inverter V2, that is, the inverted internal control signal PCB, is commonly supplied to the gates of the MOSFETs NI to NK constituting one of the sub-common IO line precharge circuits. An internal control signal PCS is commonly supplied to the gates of the MOSFETs P5 to P7 constituting the precharge circuit. As a result, when the dynamic RAM is set to the write mode, the MOSFETs NI to NK are selectively turned on when the internal control signal PC is set to the low level, that is, the inverted internal control signal PCB is set to the high level, and the sub-common IO line SIO0. The non-inverted and inverted signal lines of * are equalized to the internal voltage HVC. Further, when the dynamic RAM is set to the read mode, the MOSFETs P5 to P7 are selectively turned on when the internal control signal PCS is set to the low level, and between the non-inverted and inverted signal lines of the sub-common IO line SIO0 *. Equalize to internal voltage VCL.

  On the other hand, the drains and sources of the write switch MOSFETs NL and NM constituting the sub-main amplifier SMA are coupled to the inverted and non-inverted signal lines of the main common IO line MIO40 * and the sub-common IO line SIO0 *, respectively. An internal control signal WE3 is supplied in common. The drains of the read differential MOSFETs NP and NQ are coupled to the non-inverted and inverted signal lines of the main common IO line MIO40 * via the N-channel MOSFETs NN and NO, respectively, and the commonly coupled source is an N-channel type. Are coupled to the ground potential VSS via the driving MOSFETNR. The gates of the differential MOSFETs NP and NQ are coupled to the inverted and non-inverted signal lines of the sub-common IO line SIO0 *, respectively, and the internal control signal RE3 is commonly supplied to the gates of the MOSFETs NN, NO, and NR. The internal control signal WE3 is selectively set to a high level such as the internal voltage VCL at a predetermined timing when the dynamic RAM is selected in the write mode, and the internal control signal RE3 is selected in the read mode. When the state is set, it is selectively set to the high level at a predetermined timing.

  As a result, the write switch MOSFETs NL and NM of the sub-main amplifier SMA are selectively turned on when the dynamic RAM is selected in the write mode and the internal control signal WE3 is set to the high level, and from the main amplifier MAR. A write signal supplied via the main common IO line MIO40 * is transmitted to the sub-common IO line SIO0 *. These write signals are written from the sub-common IO line SIO0 * to the selected memory cell of the memory array ARYR34 via the corresponding unit circuit of the sense amplifier SAR34.

  On the other hand, the read differential MOSFETs NP and NQ constituting the sub-main amplifier SMA are selected in the read mode in the dynamic RAM and the MOSFETs NN, NO and NR are turned on in response to the high level of the internal control signal RE3. At the same time, a so-called pseudo-direct differential amplifier circuit is selectively formed together with these MOSFETs, and is output from the selected memory cell of the memory array ARYR 34 and is amplified by the corresponding unit amplifier circuit of the sense amplifier SAR 34, and also the sub-common IO line The binary read signal output via SIO0 * is further amplified and transmitted to the corresponding main common IO line MIO40 *. As described above, the sub-common IO line SIO0 * is shared by two sub-memory mats SMR34 and SMR35 adjacent in the column direction, and the wiring length thereof is a comparison corresponding to the width of these sub-memory mats in the bit line direction. Short. The binary read signal output from the corresponding unit amplifier circuit of the sense amplifier SAR34 to the sub-common IO line SIO0 * is further amplified by the differential amplifier circuit centered on the differential MOSFETs NP and NQ for reading of the sub-main amplifier SMA. And transmitted to the main common IO line MIO40 * having a relatively long wiring length.

  As a result, in this embodiment, the read signal of the selected memory cell is effectively transferred to the main common IO line MIO40 *, that is, the main amplifier while reducing the load on each unit amplifier circuit of the sense amplifier SAR34 at the time of column selection. It can be transmitted to the unit circuit corresponding to the MAR, and thereby the access time in the read mode of the dynamic RAM can be increased. In this embodiment, the sense amplifier drive circuit SAD34 including the sub main amplifier SMA is arranged in an intersection region between the arrangement region of the sense amplifier SAR34 and the like and the arrangement region of the sub word line drive unit WDR34 and the like, as will be described later. Therefore, it is possible to increase the access time while suppressing an increase in the layout area.

  By the way, when the wiring length of the main common IO line MIO40 * or the like is relatively short or the load capacity is not a problem, the sub main amplifier SMA is used for writing and reading as illustrated in FIGS. The switch MOSFETs NL and NM that are also used can be used.

  FIG. 15 shows a plan layout view of one embodiment of the memory array ARYR 34 of the sub memory mat SMR 34 of FIG. 4 and a metal wiring layer in the periphery thereof. FIG. 16 is a partial plan view showing an example of the sub word line driving unit WDR 34 included in the sub memory mat SMR 34 of FIG. 4. FIG. 17 shows the sense amplifier SAR 34 and the sense amplifier driving unit. A plan layout of one embodiment of the SDR 34 is shown. With reference to these drawings, the planar arrangement of the sub-memory mat SMR 34 and its peripheral portion, particularly the metal wiring layer, and its features will be described. Needless to say, the following description regarding the metal wiring layer can be applied to other sub memory mats except the sub memory mat SMR34.

  In FIG. 15, the dynamic RAM of this embodiment has three metal wiring layers M1 to M3 made of aluminum or the like. Among these, the third metal wiring layer M3 as the uppermost layer is mainly arranged in the horizontal direction in the drawing, that is, in parallel with the sub bit lines and between the plurality of sub memory mats. YS463 etc., sub word line drive signals DX40 to DX47 etc., main common IO lines MIO40 * to MIO43 * etc. and drive voltage supply lines CPP2, CPN2, CPP4 and CPN4 etc. are used. Inverted shared control signals such as main word lines MW30 * to MW363 *, sub-common IO lines SIO0 * to SIO3 *, etc. arranged in the vertical direction in FIG. Sense amplifier drive signal lines SAP3 to SAP4 and lines SH3LB to SH4LB and SH3RB to SH4RB, etc. SAN3~SAN4 like, as well as the internal control signal line PC, PCS, WE3~WE4, used as such RE3～RE4. Note that the first metal wiring layer M1, which is the lowest layer, is used as an inter-element wiring such as a MOSFET constituting each circuit.

  In this embodiment, the main word line MW30 * consisting of the second metal wiring layer M2, that is, the non-inverted main word line MW30T and the inverted main word line MW30B, etc. are formed as shown in FIG. The memory array ARYR 34 formed of the layer FG is arranged with a sufficient margin at a pitch eight times that of the sub word lines SW0 to SW7 and the like. Further, one of the sub word line drive signal lines DX40, DX42, DX44 and DX46, etc., which is composed of the third metal wiring layer M3 and is branched into two in the right part (not shown), is a P channel constituting the sub word line drive unit WDR34. The other is arranged in parallel on the formation region of the MOSFET, and the other is arranged in parallel on the formation region of the N-channel MOSFET constituting the sub word line drive unit WDR34. In the middle of these sub-word line drive signal lines, a supply wiring for supplying a substrate potential, that is, an internal voltage VCH, is similarly formed by a third-layer metal wiring layer M3 to an N well region, which is a P channel MOSFET formation region. Is done. In the lower layer, a coupling wiring for commonly coupling the even-numbered sub word lines SW0, SW2, SW4, and SW6 of the adjacent memory arrays ARYR34 and ARYR33 is formed by the first metal wiring layer M1. .

  On the other hand, the bit line selection signal YS40 or the like made of the third metal wiring layer M3 is, as illustrated in FIG. 17, the sub bit lines SB0 * to SB3 * of the memory array ARYR34 made of the second gate layer SG. The non-inverted sub-bit lines SB0T to SB3T and the inverted SB0B to SB3B are arranged with a sufficient margin with a pitch of 4 times, that is, substantially 8 times. Further, the main common IO line MIO40 *, that is, the non-inverted main common IO lines MIO40T and MIO40B, and the drive voltage supply lines CPP4 and CPN4, which are composed of the third-layer metal wiring layer M3, are driven by the sub word line drive units WDR24 and WDR34 and the sense amplifier. Sub-common IO lines SIO0 * and SIO1 *, that is, non-inverted sub-common IO lines SIO0T and SIO1T and inverted sub-common IO lines SIO0B and SIO1B, etc., which are arranged on the arrangement region of the part SDR34 and the like and are composed of the second metal wiring layer M2. The control signal lines SH3LB and SH3RB to SH4RB, the sense amplifier drive signal lines SAP3 and SAN3, and the internal control signal lines PC, PCS, WE3, and RE3 It is placed in the placement area. As a result, the signal lines for transmitting signals over the plurality of sub memory mats are efficiently arranged using the three metal wiring layers, thereby improving the layout efficiency of the sub memory mat and the dynamic RAM.

  In the dynamic RAM of this embodiment, as described above, the main word line MW30, which is composed of the second-layer metal wiring layer M2 or the third-layer metal wiring layer M3, which is particularly related to a highly integrated memory array. Since * ~ MW363 * and the like and bit line selection signals YS40 to YS463 are arranged with sufficient margin, these metal wiring layers are patterned without using a so-called phase shift mask, thereby reducing the cost of the dynamic RAM. Is planned.

  FIG. 18 is a plan layout view of the first embodiment of the memory array and the peripheral portion constituting each sub memory mat of the dynamic RAM of FIG. 1, and FIG. 21 is a sectional view of the embodiment. The figure is shown. FIG. 19 is a plan view showing the layout of the second embodiment of the memory array and the peripheral portion constituting each sub memory mat of the dynamic RAM of FIG. 1, and FIG. A cross-sectional structure diagram is shown. Further, FIG. 20 shows a plan layout view of a third embodiment of the memory array and the peripheral portion constituting each sub memory mat of the dynamic RAM of FIG. 1, and FIG. 23 shows one embodiment of the memory array. A cross-sectional structure diagram is shown. Based on these drawings, the outline of the well structure, the substrate voltage, and the characteristics of the dynamic RAM of this embodiment will be described. The following embodiments are expressed symbolically regardless of the substrate layout of the dynamic RAM described so far, with the main purpose of explaining the well structure and substrate voltage of the dynamic RAM in an easy-to-understand manner. In the following description, the details of the first embodiment of FIGS. 18 and 21 will be described first, and then the second embodiment of FIGS. 19 and 22 and the third embodiment of FIGS. 20 and 23 will be described. Will add explanation only for the different parts.

  18 and 21, the dynamic RAM uses as its base a P-type semiconductor substrate PSUB to which an internal voltage VB1 that is a negative potential having a relatively small absolute value such as −1V is applied. In addition, the memory cell MC constituting the memory array ARY1, that is, the N channel MOSFET serving as the address selection MOSFET is formed in the P well region PW1 provided on the semiconductor substrate PSUB and entering the arrangement region of the corresponding sense amplifier SA1, A memory cell MC constituting the paired memory array ARY2, that is, an N-channel MOSFET serving as an address selection MOSFET is also formed in a P well region PW2 provided on the semiconductor substrate PSUB and entering the arrangement region of the corresponding sense amplifier SA1. Is done. An internal voltage VB1 is supplied as a substrate voltage to the P well regions PW1 and PW2, and this internal voltage VB1 becomes the substrate voltage of the semiconductor substrate PSUB as it is.

  Similarly, an N-channel MOSFET serving as a memory cell MC constituting the memory array ARY3, that is, an address selection MOSFET, is provided on the semiconductor substrate PSUB and into the arrangement region of the corresponding sense amplifier SA2 and the sub word line driving unit WD1. An N-channel MOSFET that is formed in the well region PW3 and serves as an address selection MOSFET of the memory cell MC constituting the memory array ARY4 that forms a pair is also provided in the arrangement region of the sense amplifier SA2 and the sub word line drive unit WD2. It is formed in well region PW4. Internal voltage VB1 is supplied as a substrate voltage to P well regions PW3 and PW4.

  N-channel MOSFETs (NMOS) constituting the sense amplifiers SA1 or SA2 are formed at the right end portions of the P well regions PW1 and PW3 and the left end portions of the P well regions PW2 and PW4, respectively. Further, between the P well regions PW1 and PW2 and between PW3 and PW4, N well regions NW1 and NW2 having a power supply voltage VCC as a substrate voltage are provided, respectively, and in these N well regions, sense amplifiers SA1 or SA2 are provided. P-channel MOSFETs (PMOS) constituting each of these are formed. A blocking N well region NW9 is provided outside the P well regions PW1 and PW3, and a blocking N well region NW10 is also provided outside the P well regions PW2 and PW4.

  Similarly, an N-channel MOSFET constituting the sub word line driver WD1 is formed at the upper end of the P well region PW3, and an N channel MOSFET constituting the sub word line driver WD2 is formed at the upper end of the P well region PW4. It is formed. Further, between the P well regions PW1 and PW3 and between PW2 and PW4, there are provided N well regions NW3 and NW4 having the internal voltage VCH as a substrate voltage, respectively, and in these N well regions, sub word line driving units are provided. P-channel MOSFETs constituting WD1 or WD2 are formed. A blocking N well region NW13 is provided outside the P well regions PW1 and PW2, and an N well region NW14 is provided outside the P well regions PW3 and PW4.

  On the other hand, the P channel MOSFET constituting the peripheral circuit PC is formed in the N well region NW5 provided on the semiconductor substrate PSUB, and the N channel MOSFET is formed in the P well region PW5 provided in the relatively deep N well region DNW1. Formed. A blocking N well region NW11 is formed on the right outer side of the P well region PW5. A power supply voltage VCC serving as a substrate voltage is provided in the deep N well region DNW1 via the N well region NW11 and the N well region NW5. Is supplied. A ground potential VSS is supplied as a substrate voltage to the P well region PW5.

  Further, the P channel MOSFET constituting the data input / output circuit IO is formed in the N well region NW6 provided on the semiconductor substrate PSUB, and the N channel MOSFET is provided in the P well provided in the relatively deep N well region DNW2. It is formed in region PW6. A blocking P well region PW13 is formed on the left outer side of the N well region NW6, and a blocking N well region NW12 is formed on the right outer side of the P well region PW6. A power supply voltage VCC serving as a substrate voltage is supplied to the deep N well region DNW2 through the N well region NW12 and the N well region NW6. The P-well region PW6 is supplied with the internal voltage VB2, which is a negative potential having a relatively large absolute value, such as −2V, as the substrate voltage.

  As described above, the dynamic RAM according to this embodiment adopts a so-called triple well structure, and includes N-channel MOSFETs, sense amplifiers SA1 to SA2, and sub word line driving units WD1 and WD2 that become memory cells MC of the memory arrays ARY1 to ARY4. The N-channel MOSFET to be formed is formed in the same P-well region, and a blocking region for separation between well regions is not necessary, thereby reducing the chip size of the dynamic RAM. Further, for example, the N well regions NW1 and NW2 serving as the formation regions of the P channel MOSFETs for driving the common source line of the sense amplifiers SA1 to SA2 use the power supply voltage VCC as a substrate voltage, so that latchup at the time of power-on described later is performed. Risk can be eliminated. However, although the substrate effect is small for the P-channel MOSFET of the sense amplifier section, the potential difference between the ground potential VSS as the source potential and the internal voltage VB1 as the substrate voltage is 1 V for the N-channel MOSFET, and the threshold voltage is Increases and affects the operation of the sense amplifier. Further, the P well regions PW1 to PW4, which are the formation regions of the memory arrays ARY1 to ARY4, are directly formed on the semiconductor substrate PSUB, so that the substrate voltage of the semiconductor substrate PSUB due to the operation of the data input / output circuit IO is changed. The noise is transmitted to the memory cell as it is, and since no blocking region is provided between the memory arrays ARY1 to ARY4 and the sense amplifiers SA1 to SA2, noise due to the operation of the sense amplifiers SA1 to SA2 is detected in the memory cell. Is transmitted to.

  Next, in the case of the second embodiment shown in FIGS. 19 and 22, the dynamic RAM uses a P-type semiconductor substrate PSUB to which the ground potential VSS is applied as its base. The N-channel MOSFET serving as the memory cell MC, that is, the address selection MOSFET constituting the memory array ARY1, is arranged in the relatively deep N well region DNW3 to which the internal voltage VCH, that is, the word line selection potential is applied, and the corresponding sense amplifier SA1. An N channel MOSFET which is formed in a P well region PW1 provided in the region and constitutes a pair of the memory array ARY2, ie, an address selection MOSFET, is also in the deep N well region DNW3. It is formed in a P well region PW2 provided so as to enter the arrangement region of the amplifier SA1. A relatively small negative potential, that is, the internal voltage VB1, is supplied to the P well regions PW1 and PW2 as a substrate voltage.

  Similarly, an N channel MOSFET serving as a memory cell MC constituting the memory array ARY3, that is, an address selection MOSFET, is provided in the deep N well region DNW3 and into the arrangement region of the corresponding sense amplifier SA2 and sub word line drive unit WD1. The N channel MOSFET formed in the P well region PW3 and serving as the address selection MOSFET of the memory cell MC constituting the paired memory array ARY4 is also located in the deep N well region DNW3 and also in the sense amplifier SA2 and the sub word line driving unit. It is formed in a P well region PW4 provided so as to enter the arrangement region of WD2. An internal voltage VB1 of −1 V is supplied as a substrate voltage to the P well regions PW3 and PW4.

  N-channel MOSFETs constituting the sense amplifiers SA1 or SA2 are formed at the right end portions of the P well regions PW1 and PW3 and the left end portions of the P well regions PW2 and PW4, respectively. Further, N well regions NW1 and NW2 are provided between the P well regions PW1 and PW2 and between PW3 and PW4, respectively, and P channel MOSFETs constituting the sense amplifier SA1 or SA2 are respectively provided in these N well regions. It is formed. Further, an internal voltage VCH of +4 V is supplied as a substrate voltage to these N well regions NW1 and NW2, and this becomes the substrate voltage of the deep N well region DNW3 as it is.

  Similarly, an N-channel MOSFET constituting the sub word line driver WD1 is formed at the upper end of the P well region PW3, and an N channel MOSFET constituting the sub word line driver WD2 is formed at the upper end of the P well region PW4. It is formed. Further, between the P well regions PW1 and PW3 and between PW2 and PW4, there are provided N well regions NW3 and NW4 having the internal voltage VCH as a substrate voltage, respectively, and in these N well regions, sub word line driving units are provided. P-channel MOSFETs constituting WD1 or WD2 are formed.

  On the other hand, the P channel MOSFET constituting the peripheral circuit PC is formed in the N well region NW5 provided on the semiconductor substrate PSUB, and the N channel MOSFET is also formed in the P well region PW5 provided on the semiconductor substrate PSUB. Is done. The power supply voltage VCC is supplied as a substrate voltage to the N well region NW5. Further, the ground potential VSS is supplied to the P well region PW5 as the substrate voltage, which becomes the substrate voltage of the semiconductor substrate PSUB as it is.

  As described above, in this embodiment, the N-channel MOSFETs serving as the memory cells MC of the memory arrays ARY1 to ARY4 and the N-channel MOSFETs constituting the sense amplifiers SA1 to SA2 and the sub word line driving units WD1 and WD2 are the same P. Formed in the well region, a blocking region for separating the well regions is not required, the chip size is reduced, and the P well regions PW1 to PW4 and the N well regions NW1 to NW4 that form these circuits are formed. Is formed in the relatively deep N well region DNW3, so that the fluctuation of the substrate voltage of the semiconductor substrate PSUB can be prevented from being transmitted to the memory cells of the memory arrays ARY1 to ARY4 as noise. However, the N well regions NW1 and NW2, which are the formation regions of the P channel MOSFETs constituting the sense amplifiers SA1 to SA2, use the internal voltage VCH as the substrate voltage, so that the potential of the internal voltage VCH is higher than the power supply voltage VCC when the power is turned on. During the low period, for example, current flows from the source diffusion layer of the P-channel MOSFET receiving the power supply voltage VCC to the source to the N-well region, and in the worst case, there is a risk that a latch-up state occurs. Further, the N well regions NW1 and NW2 use the internal voltage VCH as the substrate voltage, and the P well regions PW1 to PW4 used as the N channel MOSFET formation regions use the internal voltage VB1 as the substrate voltage, thereby allowing the P channel and N channel MOSFETs to be formed. Both substrate effects increase and the threshold voltage increases, affecting the operation of the sense amplifier. Furthermore, since no blocking region is provided between the memory arrays ARY1 to ARY4 and the sense amplifiers SA1 to SA2, noise due to the simultaneous activation of the sense amplifiers SA1 to SA2 is transmitted to the memory cells. .

  Finally, in the case of the third embodiment shown in FIGS. 20 and 23, the N-channel MOSFETs constituting the sense amplifiers SA1 and SA2 are basically independent of the semiconductor substrate PSUB. The P well regions PW11 and PW12 provided in this manner are used as formation regions. A ground potential VSS is supplied as a substrate voltage to these P well regions PW11 and PW12. An N well region NW16 is provided as a blocking region between the P well regions PW11 and PW12 and the P well region PW7 in which the memory arrays ARY1 and ARY3 are formed.

  From these facts, in this embodiment, although the chip size is slightly increased by providing the blocking region, the P channel and the sense amplifiers SA1 and SA2 constituting the sense amplifiers SA1 and SA2 are maintained while maintaining the features of the second embodiment. By eliminating the substrate effect of the N-channel MOSFET, the operation of the sense amplifiers SA1 and SA2 can be speeded up, noise caused by the operation of these sense amplifiers is prevented from being transmitted to the memory cells, and there is a risk of latch-up. Can be eliminated.

  The effects obtained from the above embodiments are as follows. (1) A memory including a memory mat such as a dynamic RAM including sub-word lines and sub-bit lines arranged orthogonal to each other and dynamic memory cells arranged in a lattice at intersections of these sub-word lines and sub-bit lines. An array; a sub word line driving unit including a unit sub word line driving circuit provided corresponding to the sub word line; a unit amplifier circuit provided corresponding to the sub bit line; a sense amplifier including a column selection switch; and a designated sub bit line Are divided into a plurality of sub-memory mats each having sub-common IO lines selectively connected via a column selection switch, and these sub-memory mats are arranged in a lattice pattern and are orthogonal to each other on the upper layer. Main word line and column selection signal line By forming the main common IO line etc. to which the sub-common IO lines are selectively connected, the hierarchical structure is comprehensively adopted for all of the word lines, bit lines and common IO lines, and the effect of the hierarchical structure is sufficient. Thus, a dynamic RAM or the like having a configuration capable of exhibiting the above can be realized.

  (2) In the above item (1), the unit sub-word line driving circuits are alternately arranged on both sides of the sub-word line at a pitch twice that of the unit, and the unit amplifier circuits and the column selection switches are alternately arranged on both sides of the sub-bit line. The unit sub word line drive circuit is shared by two sub memory mats adjacent in the column direction, and the unit amplifier circuit and the column selection switch are shared by two sub memory mats adjacent in the row direction. As a result, the chip size of the dynamic RAM or the like can be reduced while relaxing the arrangement pitch of the unit sub word line driving circuit, the unit amplifier circuit, and the column selection switch.

  (3) In the above items (1) and (2), the main word line and the column selection signal line are arranged at an integer multiple pitch of the sub word line and the sub bit line, respectively, thereby relaxing the arrangement pitch of these signal lines. it can.

  (4) In the above items (1) to (3), each unit sub word line driving circuit of the sub word line driving unit is provided between the sub word line driving signal line and the corresponding sub word line, and the gate thereof corresponds to the main word. P-channel type first MOSFET coupled to the inverted signal line of the line, and N channel provided between the corresponding sub word line and the ground potential and having its gate coupled to the inverted signal line of the corresponding main word line So-called CMOS static type including a second MOSFET of the type and an N-channel third MOSFET which is provided in parallel with the first MOSFET and whose gate is coupled to the non-inverted signal line of the corresponding main word line By using the drive circuit, the sub-word line selection operation is speeded up. It can speed up.

  (5) In the above items (1) to (4), the sub-main amplifier for selectively connecting the designated sub-common IO line and the main common IO line is connected to the sub-common IO line corresponding to the gate. Read differential MOSFETs coupled to non-inverted and inverted signal lines, respectively, the drains of which are coupled to the inverted and non-inverted signal lines of the corresponding main common IO line, and non-inverted signals of the sub-common IO line and the main common IO line, respectively. A so-called pseudo direct sense type sub-amplifier including a write switch MOSFET provided between the lines and between the inverted signal lines, and arranged in an intersection region of the sub-word line drive unit and the sense amplifier arrangement region, thereby the memory array unit. Read operations such as dynamic RAM without increasing the layout area It can speed up.

  (6) In the above items (1) to (5), the main common IO line and the semiconductor are arranged by arranging the main common IO line in an upper layer of the arrangement region of the sub word line driving unit and orthogonal to the sub common IO line. A main amplifier disposed in the center of the substrate can be effectively coupled.

  (7) In the above items (1) to (6), the sense amplifier driving unit for selectively transmitting the operation power supplied via the driving voltage supply line to the unit amplifier circuit of the sense amplifier is driven by the sub word line. By arranging in the crossing region of the unit and the sense amplifier arrangement region, the sense amplifier driving unit and related signal lines can be effectively arranged, and the chip size of the dynamic RAM or the like can be reduced.

  (8) In the above item (7), by driving the unit amplifier circuit of the sense amplifier by the overdrive method, the rise of the operation can be accelerated, and the read operation of the dynamic RAM or the like can be accelerated.

  (9) In the above items (7) and (8), the charge re-transmission for sequentially transmitting the operation power transmitted to the drive signal line to the drive signal line of the sense amplifier to be activated next through a predetermined switch means. By adopting the use refresh method, the operating current during the refresh operation of the dynamic RAM or the like can be reduced, and the power consumption can be reduced.

  (10) In the above items (1) to (9), a sub-bit line of a sub-memory mat that is shared and specified by a predetermined number of sub-memory mats arranged continuously in the row direction is selectively selected in the dynamic RAM or the like. The number of sense amplifier unit amplifier circuits and column selection switches required can be reduced by providing the main bit lines connected to the main amplifier and the unit amplifier circuits and column selection switches of the sense amplifiers corresponding to these main bit lines. In addition, it is possible to reduce the chip size and cost of the dynamic RAM or the like.

  (11) In the above items (1) to (10), by using a predetermined number of sub memory mats in the row and column directions as redundant sub memory mats, it is possible to efficiently realize defect relief in units of sub memory mats.

  (12) In the above items (1) to (11), the sense amplifier control signal line for selectively connecting the drive signal line and the drive voltage supply line is arranged in the upper layer of the sense amplifier arrangement region. By arranging the sub word line drive signal line, the main common IO line and the drive voltage supply line in the upper layer of the arrangement area of the sub word line drive unit, these signal lines can be arranged efficiently and the chip size can be reduced.

  (13) In the above items (1) to (12), the main word line, the drive signal line, the sense amplifier control signal and the like are formed by the second metal wiring layer, and the column selection signal line, the sub word line drive signal line, By forming the main common IO line, the drive voltage supply line, and the like by the third metal wiring layer, these signal lines can be efficiently arranged utilizing the multilayer wiring, and the chip size can be reduced.

  (14) In the above items (1) to (13), the metal wiring layers of the second layer and the third layer are patterned without using a phase shift mask, thereby reducing the cost of the dynamic RAM or the like. Can do.

  (15) In the above items (1) to (14), the dynamic RAM or the like has a triple well structure, a relatively small negative potential is applied as the substrate voltage of the P-type semiconductor substrate, and the memory array, sense amplifier, and sub-word line An N-channel MOSFET that constitutes a driving unit is formed in a P-well region on a P-type semiconductor substrate, and an N-channel MOSFET that constitutes a peripheral circuit has a ground potential in a relatively deep N-well region to which a power supply voltage is applied. A ground potential in a relatively deep N well region to which a power supply voltage is applied or a relatively large negative potential is applied to an N-channel MOSFET that is formed in an applied P well region and constitutes a data input / output circuit. By forming in the P well region, the well region is separated between the memory array and the sense amplifier or sub word line drive unit. Eliminating the blocking region for, it is possible to reduce the chip size of such dynamic RAM, it is possible to eliminate the risk of latch-up at particular power-on.

  (16) In the above items (1) to (14), the dynamic RAM or the like has a triple well structure, a ground potential is applied as the substrate voltage of the P-type semiconductor substrate, and the memory array, sense amplifier, and sub-word line driving unit are The N-channel MOSFET to be formed is formed in a P-well region to which a relatively small negative potential of an absolute value is applied in a relatively deep N-well region to which a word line selection potential is applied, and the N-channel constituting the peripheral circuit A MOSFET is formed in a P-well region on a P-type semiconductor substrate, and an N-channel MOSFET constituting a data input / output circuit is a ground potential or a relatively large absolute value in a relatively deep N-well region to which a power supply voltage is applied. Of the memory array and sense amplifier or sub-word line drive unit This eliminates the blocking region for isolating the well region, thereby reducing the chip size of the dynamic RAM and the like, and fluctuations in the substrate voltage in the P-type semiconductor substrate are transmitted to the memory cells constituting the memory array as noise. Can be prevented.

  (17) In the above items (1) to (14), the dynamic RAM or the like has a triple well structure, a ground potential is applied as the substrate voltage of the P-type semiconductor substrate, and N constituting the memory array and the sub word line drive unit A channel MOSFET is formed in a P well region to which a relatively small negative potential is applied in a relatively deep N well region to which a word line selection potential is applied, and constitutes a sense amplifier and a peripheral circuit. A MOSFET is formed in a P-well region on a P-type semiconductor substrate, and an N-channel MOSFET constituting a data input / output circuit is a ground potential or a relatively large absolute value in a relatively deep N-well region to which a power supply voltage is applied. Variation in the substrate voltage in the P-type semiconductor substrate is caused by noise. Te is transmitted to the memory cell, along with noise associated with operation of the sense amplifier can be prevented from being transmitted to the memory cell, it can be eliminated the risk of latch-up, especially at power-on.

  (18) According to the above items (1) to (17), it is possible to achieve a high speed, high integration, large scale and low cost of a dynamic RAM or the like as a whole.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the dynamic RAM can include an arbitrary number of memory blocks, and the bit configuration is also arbitrary. Further, the power supply voltage VCC can take any potential, and the specific potentials of the internal voltages VCH, VCL, HVC, VB1 and VB2 formed by the internal voltage generation circuit VG are not restricted by this embodiment. Furthermore, the block configuration of the dynamic RAM, the names and combinations of the activation control signals, the configuration of each memory block, and the like can take various embodiments.

  In FIG. 2, the substrate layout of the dynamic RAM, the shape of the semiconductor substrate, and the like are not restricted by this embodiment. 3 and 4, each of the memory blocks MB0 to MB3 can include an arbitrary number of sub memory mats, and combinations of sub memory mat pairs, arrangement directions of signal lines, and the like can be variously implemented. Can take form. 5 and 6, the relationship between the unit sub word line driving circuit of the sub word line driving unit and the sub word line of the memory array and the relationship between the unit circuit of the sense amplifier and the sub bit line of the memory array can take various combinations. Further, the main word line may be provided corresponding to, for example, four sub word lines, or the bit line selection signal may correspond to, for example, eight sets of sub bit lines.

  7 to 9, each unit sub word line driving circuit of the sub word line driving unit may be constituted by a two-input CMOS NOR gate that receives, for example, a main word line MW30 and sub word line driving signals DX40 to DX43. In this case, the main word line becomes a single signal line, whereby the arrangement pitch of the main word lines can be further relaxed. The specific configuration of the unit sub-word line driving circuit can take various embodiments. In FIG. 10, the sense amplifier does not make it necessary to adopt the shared sense method. In FIG. 10, FIG. 11 and FIG. 13, the drive MOSFETs P4, P8, P9 and NE constituting the sense amplifier drive circuit SAD may be replaced with a plurality of drive MOSFETs each in parallel form. The specific configurations of the sense amplifier SAR34 and the sense amplifier driver SDR34, the conductivity type of the MOSFET, and the like can take various embodiments.

  15 to 17, the arrangement position and order of the signal lines, the number of metal wiring layers and the use method thereof are not limited by this embodiment. 18 to 23, a ground potential VSS can be supplied as a substrate voltage to a P well region PW6 which is a formation region of the data input / output circuit IO, and a deep N well region DNW2 is provided in a lower layer thereof. However, this is not a prerequisite for dynamic RAM. Furthermore, the specific well structure, the substrate voltage, the combination thereof, and the like in each embodiment can take various embodiments.

  In the above description, the case where the invention made mainly by the present inventor is applied to the dynamic RAM, which is the field of use behind the present invention, has been described. However, the present invention is not limited to this. The present invention can also be applied to various memory integrated circuits such as type RAMs and digital integrated circuits incorporating such memory integrated circuits.

  The present invention can be widely applied to a semiconductor memory device in which the hierarchical structure of at least word lines, bit lines, and common IO lines is effective, and a device and system incorporating such a semiconductor memory device.

1 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied. FIG. 2 is a substrate layout diagram showing an example of the dynamic RAM of FIG. 1. FIG. 2 is a block diagram showing an example of a memory block included in the dynamic RAM of FIG. 1. FIG. 4 is a partial block diagram showing an example of a sub memory mat included in the memory block of FIG. 3. FIG. 5 is a partial connection diagram illustrating an example of the sub memory mat of FIG. 4. FIG. 5 is a partial circuit diagram illustrating an embodiment of a memory array and a peripheral portion included in the sub memory mat of FIG. 4. FIG. 5 is a partial circuit diagram and signal waveform diagram showing a first embodiment of a sub word line driving unit included in the sub memory mat of FIG. 4. FIG. 5 is a partial circuit diagram and a signal waveform diagram showing a second embodiment of a sub word line driving unit included in the sub memory mat of FIG. 4. FIG. 5 is a partial circuit diagram and a signal waveform diagram showing a third embodiment of a sub word line driving unit included in the sub memory mat of FIG. 4. FIG. 5 is a partial circuit diagram illustrating a first embodiment of a sense amplifier and a sense amplifier driver included in the sub memory mat of FIG. 4. FIG. 5 is a partial circuit diagram illustrating a second embodiment of a sense amplifier driving unit included in the sub memory mat of FIG. 4. FIG. 12 is a signal waveform diagram illustrating an example of the sense amplifier driver of FIGS. 10 and 11. FIG. 5 is a partial circuit diagram illustrating a third embodiment of a sense amplifier driving unit included in the sub memory mat of FIG. 4. FIG. 14 is a signal waveform diagram illustrating an example of the sense amplifier driver of FIG. 13. FIG. 5 is a plan layout view showing an example of a memory array of the sub memory mat of FIG. 4 and a metal wiring layer in a peripheral portion. FIG. 5 is a partial plan view showing one embodiment of a sub word line driving unit included in the sub memory mat of FIG. 4. FIG. 5 is a partial plan view showing an embodiment of a sense amplifier and a sense amplifier driving unit included in the sub memory mat of FIG. 4. FIG. 2 is a symbolic plane layout diagram showing a first embodiment of a memory array and a peripheral part constituting a sub memory mat of the dynamic RAM of FIG. 1. FIG. 3 is a symbolic plan layout view showing a second embodiment of a memory array and a peripheral part constituting a sub memory mat of the dynamic RAM of FIG. 1. FIG. 5 is a symbolic plan layout diagram showing a third embodiment of the memory array and the peripheral portion constituting the sub memory mat of the dynamic RAM of FIG. FIG. 19 is a cross-sectional structure diagram illustrating an example of the memory array and the peripheral portion in FIG. 18. FIG. 20 is a cross-sectional structure diagram illustrating an example of the memory array and the peripheral portion in FIG. 19. FIG. 21 is a cross-sectional structure diagram illustrating an example of the memory array and the peripheral portion in FIG. 20.

Explanation of symbols

MB0 to MB3 ... memory block, MATL, MATR ... memory mat, XD ... X address decoder, XB ... X address buffer, YDL, YDR ... Y address decoder, YB ... Y address Buffer, BS ... Memory block selection circuit, MAL, MAR ... Main amplifier, IO ... Data input / output circuit, TG ... Timing generation circuit, VG ... Internal voltage generation circuit. PSUB ... P-type semiconductor substrate, PC ... peripheral circuit.
SML00 to SML77, SMR00 to SMR77 ... sub memory mat, ARYR00 to ARYR77 ... memory array, WDR00 to WDR78 ... sub word line drive unit, SAR00 to SAR87 ... sense amplifier, SDR00 to SDR87 ... sense Amplifier drive unit.
MW30 * to MW363 * ... main word line, SW0 to SW511 ... sub word line, USWD ... unit sub word line drive circuit, SB0 * to SB255 * ... sub bit line, USA ... sense amplifier unit circuit , YS40 to YS463 ... bit line selection signals, SIO0 * to SIO3 * ... sub-common IO lines, MIO00 * to MIO03 *, MIO20 * to MIO23 *, MIO40 * to MIO43 *, MIO60 * to MIO63 * ... Main common IO line, DX40 to DX47, sub-word line drive signal, SH3L, SH3R, shared control signal.
USWD0 to USWD511, unit sub-word line drive circuit, USA0 to USA255, unit sense amplifier.
SAD ... sense amplifier drive circuit, SAP3, SAN3 ... sense amplifier control signal line, CPP2, CPP4, CPN2, CPN4 ... sense amplifier drive voltage supply line, PP, PN ... common source line, SMA ... Sub-main amplifiers, WE3, RE3, WRE3 ... Sub-main amplifier control signal lines, SH3LB, SH3RB ... Inverted shared control signal lines, PC, PCS ... Precharge control internal control signal lines.
SAP31, SAP32 ... sense amplifier control signals.
P1-P7 ... P-channel MOSFET, N1-NR ... N-channel MOSFET, V1-V3 ... Inverter.
M1 to M3: metal wiring layer, FG, SG: gate layer.
ARY1 to ARY4... Memory array, WD1 to WD2... Sub word line drive unit, SA1 to SA2... Sense amplifier, DNW1 to DNW5... Relatively deep N well region, NW1 to NW16. Shallow N well region, PW1 to PW15... Relatively shallow P well region, MC... Memory cell, PMOS... P channel MOSFET, NMOS.

Claims (1)

A main word line extending in a first direction, provided corresponding to said main word line, intersects the plurality of first sub-word lines that Mashimasu extending in the first direction, and said plurality of first sub-word line A first memory array having a plurality of first bit lines extending in a second direction, and a plurality of first memory cells provided at intersections of the plurality of first sub-word lines and the plurality of first bit lines;
The main word line provided corresponding, and a plurality of second sub-word lines that Mashimasu extending in the first direction, a plurality second extending in the second direction crossing the plurality of second sub-word lines A second memory array having a bit line and a plurality of second memory cells provided at intersections of the plurality of second sub-word lines and the plurality of second bit lines;
A first Sabukomon IO line extending to the connected first direction and said plurality of first bit lines,
A second sub-common IO line connected to the plurality of second bit lines and extending in the first direction;
A main common IO line connected to the first and second sub-common IO lines and extending in the second direction;
A plurality of first switch circuits provided between each of the plurality of first bit lines and the first sub-common IO line;
A plurality of second switch circuits provided between each of the second bit lines and the second sub-common IO line;
A first amplifying circuit provided between the first sub-common IO line and the main common IO line for amplifying a signal transmitted through the first sub-common IO line;
A second amplifying circuit provided between the second sub-common IO line and the main common IO line for amplifying a signal transmitted through the second sub-common IO line;
First extending over the first memory array in the second direction and controlling the first switch circuit to selectively connect a plurality of first bit lines to a first sub-common IO line. A column selection signal line;
A second memory array extending in the second direction on the second memory array and controlling the second switch circuit to selectively connect a plurality of second bit lines to a second sub-common IO line; A column selection signal line;
The main common IO line and the first and second column selection signal lines are formed of the same wiring layer,
The main word line and the first and second sub-common IO lines are formed in the same wiring layer,
The main word line and the first column selection signal line intersect on the first memory array, and the main word line and the second column selection signal line intersect on the second memory array. A featured semiconductor device.

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