JP2867774B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a wiring layout and structure of a dynamic semiconductor memory device (hereinafter referred to as a dynamic RAM).

[0002]

2. Description of the Related Art A memory cell array of a conventional dynamic RAM has, for example, word lines WL0 to WL5 as shown in FIG.
, Bit lines BL0 to BL7, and memory cells MC00 to MC53 arranged at the intersection thereof, and word lines WL
0 to 5 are usually polycrystalline silicon having a layer resistance of several tens Ω or
It consisted of a laminated film of metal silicide having a layer resistance of several Ω and polycrystalline silicon. In order to reduce the substantial word resistance from the demand for high speed, the word line W
Metal lines WO0'-5 'represented by aluminum are run at the same pitch along L0-5, and word lines WL0-5 and metal lines WL0'-5' are connected at regular intervals, respectively. 'To 5' were connected to the output terminals of the row decoder.

As the degree of integration increases, the wiring pitch becomes smaller, while the memory cell becomes a three-dimensional structure such as a stack in order to secure a capacity, and the metal wirings WL0 'to 5'.
In a dynamic RAM of 16 M or more, the level difference between the wirings running on the memory cells inside and outside of the memory cell array is as large as 1 μm to 1.5 μm. Therefore, lithography requires a large focus margin. In addition, since etching of metal wiring generally has a low selectivity with respect to a resist, the resist must be thickly applied. For this reason, compared to the formation of word lines WL0 to 5 made of polycrystalline silicon, metal silicide, or the like, metal lines WL0 'to 5'
Is very difficult, and the technology such as in-cell contact has advanced, so that the size of the memory cell has been determined by the processing limit of the metal wirings WL0 'to 5'.

[0004]

In the above-described conventional dynamic RAM, metal wiring must be formed on a memory cell at the same pitch as that of a word line. The size of the cell is limited by the processing limit of the metal wiring passing over the memory cell, which hinders the reduction of the memory cell.

[0005]

The semiconductor memory device according to the present invention is divided so that wiring delay due to the resistance of the word line does not matter even if the word line is not lined with metal wiring, and the word line is driven. A first metal wiring connected to each of the divided word lines, and running in parallel with the word line on the memory cell at a pitch of twice or more. The word line is selected by a second metal wiring running perpendicular to the word line on the word line drive circuit.

[0006]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
FIG. 2 is a circuit diagram of a word line drive circuit used in the present invention, represented by 3a in FIG. The memory cell array is divided into a plurality of blocks in the direction of dividing the word lines, and word line driving circuits 3a to d, 4a to d, and 5a to d are arranged on both sides of all the blocks, and each word line is alternately arranged. It is connected to word line drive circuits 3a-d, 4a-d, 5a-d. Word lines WL00-B3 are bit lines B
The memory cells MC00 to MC2 are arranged at the intersections with L0 to L5, but when the word lines are formed of a stacked film of silicide and polycrystalline silicon, the word lines have a length that intersects with 256 bit lines. It is desirable to do the following. To select a word line drive circuit, complementary signals XSW0 to XSW0 and XSW0 to XSW2 run from the row decoder on the memory cell array in parallel with the word line at twice the pitch, and the word line drive circuits 3 to d, 4a-d and 5a-d, respectively. Further, the word line drive current supply signal RA0
3 run vertically on the word line drive circuit with respect to the word line, and the RA0 and RA2 signals are applied to the word line drive circuits 3a, 3a.
4a, 5a, 3c, 4c, and 5c, the RA1 signal and RA2
Signals are alternately input to 3b, 4b, 5b, 3d, 4d, and 5d, respectively.

The word line driving circuits 3a-d, 4a-d, 5
a to d are composed of two self-boot type driving circuits. FIG. 3 is a waveform chart showing the operation of the word line drive circuit used in the present invention. For example, if XSW0 and RA0 are selected, XSW0. The N-type transistors Q23 and Q26 are turned off by the XSW0 signal, and the nodes 21 and 22 are turned off.
Rises from the power supply potential to near the potential dropped by the threshold voltage of N-type transistors Q22 and Q25, and then RA0 rises to the boosted potential, whereby the potential at node 21 rises to a potential higher than RA0 due to capacitive coupling. , Word line WL
00 rises to the same potential as RA0. At this time, 3a
Not only in 3c, the potential of WL02 similarly rises, and memory cells MC00, MC01, and MC02 are selected.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention. FIG. 5 is a circuit diagram of a word line drive circuit used in the present invention represented by 3a in FIG. The memory cell array is divided into a plurality of blocks in the direction of dividing the word lines, and the word line driving circuits 3a to 8d are arranged on both sides of all the blocks, and each word line is alternately connected to the word line driving circuits 3a to 8d. It is connected. In order to select a word line driving circuit, XSW0 to XSW0 are output from the row decoder.
5 runs in parallel on the memory cell array at twice the pitch of the word lines, and the word line driving circuits 3a-d, 4a-
d, 5a-d, 6a-6d, 7a-7d, 8a-8d, respectively. Also, word line drive current supply signals RA0-1 run on the word line drive circuit perpendicularly to the word lines, and the RA0 signal is applied to word line drive circuits 3a-8.
a, 3c-8c, RA1 signal is 3b-8b, 3d-8
d are input alternately.

The word line driving circuits 3a to 8d are composed of two driving circuits having a CMOS structure. FIG. 6 is a waveform chart showing the operation of the word line drive circuit used in the present invention. For example, if XSW0 and RA0 are selected, XSW0
The N-type transistor Q52 is turned off by the signal, the gate potential of the P-type transistor Q51 becomes the ground potential, and RA0 rises to the boosted potential.
1 is turned on, and the word line WL01 rises to the same potential as RA0. At this time, the potential of WL02 similarly increases not only at 3a but also at 3c. In this embodiment, since the word line drive circuit has a CMOS configuration, it is not necessary to make the output of the row decoder a complementary signal, and the word line drive circuit can be selected with the minimum number of signal lines.

[0010]

As described above, according to the present invention, the metal wirings running on the memory cell array are formed at a pitch twice or more as large as the word lines. Memory cells can be reduced in size.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a word line drive circuit according to the first embodiment.

FIG. 3 is a wave diagram of signals of respective parts showing an operation when a word line is activated in the first embodiment.

FIG. 4 is a circuit diagram of a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a word line drive circuit according to a second embodiment.

FIG. 6 is a waveform chart of signals of respective parts showing an operation when a word line is activated in the second embodiment.

FIG. 7 is a circuit diagram of a conventional example.

[Explanation of symbols]

1 row decoder 2a, 2b, 2c, 2d Word line drive current supply circuit 3a, 3b, 3c, 3d, 4a, 4b, 4c, 4d, 5
a, 5b, 5c, 5d, 6a, 6b, 6c, 6d, 7
a, 7b, 7c, 7d, 8a, 8b, 8c, 8d Word line drive circuits WL0, WL1, WL2, WL3, WL4, WL5, W
L00, WL02, WL11, WL13, WL20, W
L22, WL31, WL33, WL40, WL42, W
L51, WL53, WL60, WL62, WL71, W
L73, WL80, WL82, WL91, WL93, W
LA0, WLA2, WLB1, WLB3 Word line WL0 'to WL5' Word line lining metal wiring XSW0, XSW1, XSW2, XSW3, XSW4
XSW5, XSW0, XSW1, XSW2, XSW3
XSW4, XSW5 row decode signals MC00, MC01, MC02, MC10, MC11,
MC12, MC20, MC21, MC22, MC30,
MC31, MC32, MC40, MC41, MC42,
MC50, MC51, MC52, MC60, MC61,
MC62, MC70, MC71, MC72, MC80,
MC81, MC82, MC90, MC91, MC92,
MCA0, MCA1, MCA2, MCB0, MCB1,
MCB2 memory cells Q21, Q22, Q23, Q24, Q25, Q26, Q
52 N-type transistor Q51 P-type transistor

Claims (7)

(57) [Claims] 1. A row decoder for driving a pair of complementary selection signal lines, a word line drive current supply circuit for driving a word line drive current supply signal line, and the pair of select signal lines and the word line drive current supply A word line driving current supply signal connected to a signal line, wherein one of the pair of selection signal lines is at a predetermined logic level and the other is at a logic level different from the predetermined logic level. And a word line drive circuit for supplying a drive current supplied from the line to the word line. 2. The word line according to claim 1, wherein the word line is formed of a stacked film of polycrystalline silicon and metal silicide.
The semiconductor memory device according to claim 1. 3. The word line drive circuit, comprising: a first transistor of one conductivity type connected between the word line drive current supply signal line and the word line; and a transistor connected between the word line and a reference potential. And a second transistor of one conductivity type connected to the first transistor. The conduction state of the first transistor is controlled based on a logic level of the one of the pair of selection signal lines. 3. The semiconductor memory device according to claim 1, wherein a conduction state of the second transistor is controlled based on a logic level of the other one of the pair of selection signal lines. . 4. The first and second transistors are both N-type MOS transistors, and the one of the pair of select signal lines is connected to the first select signal line via a self-boot circuit. 4. The transistor according to claim 3, wherein the other select signal line of the pair of select signal lines is directly connected to a gate electrode of the second transistor. Semiconductor memory device. 5. A row decoder, a plurality of pairs of selection signal lines driven by the row decoder and each extending in one direction, a plurality of word line driving current supply circuits, and the plurality of word line driving circuits. A plurality of word line drive current supply signal lines respectively driven by a current supply circuit and laid so as to extend in directions different from the one direction, and a corresponding pair of select signal lines of the plurality of pairs of select signal lines And a plurality of word line drive circuits respectively connected to corresponding ones of the plurality of word line drive current supply signal lines, and the one direction respectively driven by the plurality of word line drive circuits. And a plurality of word lines that are laid and extended in a direction. Each of the plurality of word line driving circuits is configured such that one of the corresponding pair of selection signal lines has a predetermined logic. Logic level and the other being a logic level different from the predetermined logic level,
A drive current supplied from the corresponding word line drive current supply signal line is supplied to the corresponding word line, and the other of the corresponding pair of select signal lines is at the predetermined logic level, and Prohibits the drive current supplied from the corresponding word line drive current supply signal line from being supplied to the corresponding word line in response to the different logic levels, and the plurality of pairs of selection signals The semiconductor memory device according to claim 1, wherein a wiring pitch of the lines is at least twice a wiring pitch of the plurality of word lines. 6. Each of the plurality of word line drive circuits is a first conductivity type first M connected between the corresponding word line drive current supply signal line and the corresponding word line.
An OS transistor, the second MOS transistor of one conductivity type connected between the corresponding word line and a first reference potential, and a gate connected to the other of the pair of corresponding selection signal lines; And a third MOS transistor of the one conductivity type, connected between the gate of the first MOS transistor and the one of the corresponding pair of select signal lines and having a gate connected to a second reference potential. 6. The semiconductor memory device according to claim 5, comprising a transistor. 7. A row decoder, a plurality of selection signal lines driven by the row decoder, a plurality of word line drive current supply circuits, and a plurality of words each driven by the plurality of word line drive current supply circuits. A line drive current supply signal line, and a plurality of the plurality of select signal lines connected to a corresponding one of the plurality of select signal lines and a corresponding one of the plurality of word line drive current supply signal lines, respectively. A word line drive circuit, comprising a plurality of word lines each driven by the plurality of word line drive circuits,
Each of the plurality of word line drive circuits includes a first MOS transistor of one conductivity type connected between the corresponding word line drive current supply signal line and the corresponding word line; A second MOS transistor of a reverse conductivity type connected between the first MOS transistor and a reference potential;
And means for commonly connecting the corresponding selection signal line to the gate of the second MOS transistor.