JP2755232B2 - Non-volatile semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory, and more particularly, to a nonvolatile semiconductor memory in which a field effect transistor having a floating gate is arranged as a memory cell.

[0002]

2. Description of the Related Art A general example of a conventional nonvolatile semiconductor memory in which a field effect transistor having a floating gate is a memory cell (hereinafter, referred to as a memory cell transistor) and arranged in a matrix is shown in FIG. (B).

In this nonvolatile semiconductor memory, a plurality of memory cell transistors (T11 to MT24...) Arranged in a matrix in a row direction and a column direction, and the plurality of memory cell transistors (MT11 to MT24. )
A plurality of word lines (WL1, WL2,...) Connected to the control gates of the corresponding memory cell transistors and provided to select these memory cell transistors on a row-by-row basis when selected. And a plurality of memory cell transistors (MT11 to MT24.
.) And a plurality of bit lines (BL1 to BL4...) For transferring the storage information of the memory cell transistors in the selected state of the corresponding column, and a plurality of memory cell transistors (MT11 to MT11). MT24...) Are divided into sets of two adjacent rows, and a plurality of sources are provided corresponding to each of the sets and commonly connected to the sources of the memory cell transistors of the corresponding set of two rows. .. (SL12, SL34,...).

The structure of this nonvolatile semiconductor memory is as shown in FIGS. 5 (b) and 6 (a) and 6 (b).
Each of the bit lines (BL1 to BL4,...) Is formed on the substrate SB as a buried diffusion layer including the drain diffusion region of each of the memory cell transistors in the corresponding column, and each of the source lines (SL12, SL34,. , Two in the same row of a corresponding set of two columns of memory cell transistors.
Each of the memory cell transistors (MT11 to MT24...) Has a floating gate (eg, FG11) formed as a buried diffusion layer including a source diffusion region shared by each memory cell transistor. The same source diffusion region (source line) with the same width
A corresponding word line (eg, WL1) is formed over the channel region (eg, CA11) from the channel region (eg, CA11) between the drain region and the drain diffusion region (eg, bit line). A control gate (CG11 or the like) is formed so as to protrude to the side, and has a structure in which the floating gate and the word line and the control gate face each other at a fixed interval.

Next, the operation of the nonvolatile semiconductor memory will be described.

A plurality of word lines (WL1, WL2,...)
.) Becomes a selected level (for example, WL1), the memory cell transistors (MT11 to MT14,...) Of the row corresponding to the word line (WL1) of this selected level.
・) Is selected for each line. As a result, the bit lines (BL1 to BL4...) And the source lines (SL12, S
L34,...), A read current flows according to the storage information of the selected memory cell transistors (MT11 to MT14...). Source line (SL12, SL
34,...) Each have two memory cell transistors (MT11, MT12 / MT13, MT14 /.
.), The read currents of these two memory cell transistors flow.

The read current flowing through the bit lines (BL1 to BL4...) Is detected, amplified, and output by a sense amplifier (not shown) connected to these bit lines.

[0008]

In the above-mentioned conventional non-volatile semiconductor memory, one memory cell transistor (MT11 to MT24...)
And the source line is formed as a buried diffusion layer on the substrate SB, so that its resistance value is relatively high, and two of the selected states connected to the same source line are selected. There is a problem that the storage information of the memory cell transistor is the same information and the voltage drop of the source line greatly differs depending on whether the memory cell transistor is on or off, and the operating margin for a read circuit such as a sensor amplifier is reduced by that much, In addition, there is a problem that the read current is limited due to the effect of the voltage drop of the source line, and high-speed operation cannot be performed. In addition, the size of the floating gate of each memory cell transistor is limited in order to maintain the interval between adjacent floating gates, and the coupling capacitance between the corresponding word line and control gate is limited. There is a problem that a high voltage is required when writing or erasing information to or from a transistor, and it is difficult to reduce the voltage.

It is an object of the present invention to provide a nonvolatile semiconductor device capable of increasing a read operation margin by reducing a voltage drop of a source line and increasing an operation speed by increasing a read current. A second object of the present invention is to provide a nonvolatile semiconductor memory in which the coupling capacitance between a floating gate, a word line, and a control gate is increased to facilitate low voltage operation.

[0010]

A nonvolatile semiconductor memory according to the present invention comprises a plurality of first memory cell transistors having floating gates arranged in a matrix in a row direction and a column direction, and a plurality of the first memory cell transistors. A plurality of second memory cell transistors each having a floating gate provided in proximity to the same layer and corresponding to each of the memory cell transistors, and provided corresponding to each row of the plurality of first memory cell transistors; A plurality of first word lines connected to the control gates of the first memory cell transistors in the corresponding row to select the first memory cell transistors on a row-by-row basis when at the selected level; A memory cell transistor is provided corresponding to each row and connected to the control gate of the second memory cell transistor in the corresponding row to select the memory cell transistor. A plurality of second word lines for selecting these second memory cell transistors in a row unit at the time of each row, and a plurality of second word lines provided corresponding to respective columns of the plurality of first memory cell transistors. A plurality of first bit lines for transmitting storage information of the selected first memory cell transistor, and a plurality of first bit lines provided corresponding to each column of the plurality of second memory cell transistors, respectively, for selecting a corresponding column. A plurality of second bit lines for transmitting storage information of a second memory cell transistor;
And a plurality of source lines provided corresponding to each column of the second memory cell transistor and commonly connected to the sources of the first and second memory cell transistors in the corresponding column, and the plurality of the second lines in accordance with a row address signal. A row selection circuit for setting one of the first and second word lines to a selection level. Further, each of the plurality of first and second bit lines is formed as a buried diffusion layer including the drain diffusion region of each memory cell transistor in the corresponding column, and each of the plurality of source lines is formed in the first and second bits of the corresponding column. It is formed and formed as a buried diffusion layer including a source diffusion region of each of the second memory cell transistors.

The floating gate of each of the plurality of first and second memory cell transistors is opposed to the corresponding word line and control gate at a predetermined interval, and the corresponding first bit line, source line and The floating gates of the plurality of first and second memory cell transistors are formed over a region opposed to the region where the second bit line is formed, and the floating gates of the plurality of first and second memory cell transistors are connected to the region where the corresponding first and second word lines are formed. The first and second floating gates are formed over a region opposed to each other and at a predetermined interval, and the floating gate and the first and second word lines are disposed between the floating gate and the first and second word lines. And the first and second
And a counter electrode formed to be connected to one of the word lines and having a function as a control gate.

In addition, one bit line is provided in place of the first and second bit lines adjacent to each other between adjacent columns of the plurality of first and second memory cell transistors.
The bit lines are configured to be shared between adjacent columns.

[0013]

Embodiments of the present invention will now be described with reference to the drawings.

FIGS. 1A and 1B are a circuit diagram and a schematic diagram showing a first embodiment of the present invention, and FIGS.
(B) is a cross-sectional view showing the structure of this embodiment.

In the first embodiment, a plurality of first memory cell transistors (MT11, MT13, MT13) having floating gates arranged in a matrix in the row and column directions are provided.
, MT21, MT23,...) And a plurality of second memory cell transistors (MT12, MT14, MT22,. M2
,...) And a plurality of first memory cell transistors (MT11, MT13, MT21, MT23,...)
Of the corresponding row provided corresponding to each row of
A plurality of first word lines (WL11, WL11, WL11, WL2) which are connected to the control gates of the memory cell transistors and select the first memory cell transistors in a row unit at the selected level.
, And a plurality of second memory cell transistors (MT12, MT14, MT22, MT24,...).
..) are connected to the control gates of the second memory cell transistors in the corresponding row and set to select the second memory cell transistors on a row-by-row basis at the selected level. The second word line (WL
12, WL22,...) And a plurality of first memory cell transistors (MT11, MT13, MT21, MT2).
,...) Corresponding to each of the columns and formed in the substrate SB as a buried diffusion layer including the drain diffusion region of each of the first memory cell transistors of the corresponding column, and the first state of the selected state of the corresponding column A plurality of first bit lines (BL1, BL
, And a plurality of second memory cell transistors (MT12, MT14, MT22, MT24,...)
Of the second memory cell transistor in the selected state of the corresponding column formed on the substrate SB as a buried diffusion layer corresponding to each of the columns and including the drain diffusion region of the second memory cell transistor of the corresponding column. , A plurality of second bit lines (BL2, BL4,...)
And a plurality of first and second memory cell transistors (M
T11 to MT24...)) And a substrate S as a buried diffusion layer including a source diffusion region shared by the first and second memory cell transistors of the corresponding column.
B, a plurality of source lines (SL12, SL34,
..) And one of the plurality of first and second word lines (WL11 to WL22...) By a row address signal.
And a row selection circuit (not shown) having a book as a selection level.

In the structure of the first embodiment, the first and second bit lines (BL1 to BL4...) And the source lines (SL12, SL34,. The floating gate (FG11 etc.) of each of the first and second memory cell transistors (MT11 to MT24...) Has the same width as the corresponding word line and the corresponding source diffusion region ( A channel region (CA) between a source line) and a drain diffusion region (bit line)
11) is formed so as to face the corresponding word line and control gate at a predetermined interval from the formation region of the first bit line including the region including the first bit line to the formation region of the second bit line. I have.

Next, the operation of the first embodiment will be described.

When one of the plurality of first and second word lines (WL11 to WL22...) (For example, the first word line WL11) becomes a selection level by the row selection circuit, this selection is made. Level (first) word line (W
L11), the (first) memory cell transistors (MT11, MT13,...) In the row corresponding to the row are selected in row units. As a result, the (first) bit lines (BL1, BL3,...) Corresponding to the selected (first) memory cell transistors (MT11, MT13,...).
.) And source lines (SL12, SL23, ...)
These (first) memory cell transistors (MT11,
MT13,...) Flows according to the stored information.

At this time, the source lines (SL12, SL3
The other (second) memory cell transistor (MT12, MT14,...) Connected to the control gate of the other (second) word line (WL12) is connected to the non-selection level. And is in a non-selected state, the source lines (SL12, SL34,...) Have (first)
The memory cell transistors (MT11, MT13,...)
・) Only one read current flows. That is, 1
Only one of the first and second memory cell transistors sharing one source line is in a selected state and the other is in a non-selected state, so that one memory cell transistor is read to one source line. Only current flows. Therefore,
Since the difference in the voltage drop of the source line and the voltage drop itself due to the difference in the stored information (on or off) of the memory cell transistor can be reduced (1/1 of the conventional example).
2) The read operation margin can be increased, and the read current per memory cell transistor can be increased within a range where the read operation margin is sufficient, so that the operation speed can be increased.

In the first embodiment, the floating gate (FG11) of one memory cell transistor (eg, MT11) is connected from the first bit line (BL1) to the second bit line (BL2). Since it is formed on the upper side, its area is larger than that of the conventional example, and the coupling capacitance with the corresponding word line (WL11) and control gate (CG11) can be increased (2.5 times that of the conventional example). The voltage at the time of writing and erasing information to and from the memory cell transistor can be reduced, and the voltage can be easily reduced.

FIGS. 3A to 3C are a schematic layout view and a sectional view showing a second embodiment of the present invention.

FIG. 1 is a circuit diagram of the second embodiment.
Although not different from the first embodiment shown in (a), in the structure, the word lines (WL11 to WL22...), The floating gates (FG11 etc.), the control gates (CG11 etc.) Different from the embodiment.

In the second embodiment, the floating gate (F) of the first memory cell transistor (eg, MT11) is used.
G11) is connected to the corresponding first and second word lines (WL1).
1, WL12) over the region opposed to the formation region,
And an adjacent second memory cell transistor (for example, M
The channel region (CA11) on the first bit line (BL1) and between the first bit line (BL1) and the source line (SL12) is maintained at a predetermined distance from the floating gate of T12). It is formed in the area combined with the area including
The floating gate (FG12) of the second memory cell transistor (e.g., MT12) extends over a region opposed to a region where the corresponding first and second word lines (WL11, WL12) are formed, and is adjacent to the first memory. A channel on the second bit line (BL2) and a channel between the second bit line (BL2) and the source line (SL12) so as to keep a predetermined distance between the floating gates of the cell transistors (MT11, MT13). It is formed in a region including the region including the region (CA12). Then, the floating gates (FG11, FG1) of these first and second memory cell transistors
2) and the first and second word lines, each of which is opposed to each of the floating gates at a predetermined interval, and corresponding to the corresponding word line (WL11 on the FG11 side) by a contact CT.
1, the counter electrodes (CGP11, CGP) connected to the WL12) and including a function as a control gate.
12) is provided.

Also in the second embodiment, since the area of the floating gate is larger than that of the conventional example, and the opposing electrodes which are connected to the corresponding word lines and are opposed to each other at a predetermined interval are provided. The coupling capacitance with the electrode, and thus the coupling capacitance with respect to the word line, can be increased (more than twice as large as that of the conventional example), and the voltage can be easily reduced as in the first embodiment.

The floating gate (FG) of the first and second memory cell transistors (eg, MT11 and MT12).
11, FG12) are formed over the corresponding first and second word lines (WL11, WL12), and a predetermined interval is provided between these floating gates. The positions of the contacts CT connecting the two word lines are shifted from each other, and the provision of the contacts is not affected by the adjacent contacts. Therefore, if the adjacent word lines and contacts are kept at a predetermined distance from each other, the width of the word lines other than the contact portions can be reduced, and the pitch of the word lines can be reduced accordingly, and 1
There is an advantage that the chip area can be reduced as compared with the embodiment.

3A to 3C, the channel region (C) of the memory cell transistor (eg, MT11) is shown.
A11) is provided between the portion of the bit line (BL1) corresponding to the region where the contact CT is provided and the portion of the source line (SL12) corresponding to this bit line portion. Any location is possible under the floating gate between the bit line and the source line, and the present invention is not limited to this. The area of the channel region can be set arbitrarily within this range.

FIGS. 4A and 4B are a circuit diagram and a schematic layout diagram showing a third embodiment of the present invention.

This third embodiment is shown in FIG.
(B) and the first embodiment shown in FIGS. 2 (a) and 2 (b) is different from the first embodiment in that a plurality of first and second memory cell transistors (MT11 to MT24...) One bit line (BL2) instead of the first and second bit lines (eg, BL2, BL3) adjacent to each other
3) is provided, and this one bit line is shared between adjacent columns.

In order to arrange the first and second bit lines adjacent to each other between adjacent columns, the first and second memory cell transistor columns and the second memory cell transistor column must be connected to each other. May be alternately arranged. With this arrangement, adjacent first and second memory cell transistors in the same row are not simultaneously selected.

In the third embodiment, since the number of bit lines between adjacent columns is one, the area of the floating gate is smaller than in the first and second embodiments, and the coupling capacitance to the word line is also small. Although smaller, it is larger than the conventional example (1.5 times that of the conventional example), and as in the first and second embodiments, the read operation margin can be increased, the operation speed can be increased, and In addition to being easy to lower the voltage, the number of bit lines can be reduced to almost half that of the conventional example and the first and second embodiments, and the chip area can be reduced accordingly.

[0031]

As described above, according to the present invention, a plurality of first memory cells are provided in close proximity to a plurality of first memory cell transistors arranged in a matrix. A plurality of first word lines corresponding to each row of cell transistors and a plurality of second word lines corresponding to each row of a plurality of second memory cell transistors are provided, and the plurality of first and second word lines are provided. And a plurality of bit lines corresponding to each column of the plurality of first and second memory cell transistors are provided, and the first and second memory cells of the corresponding column are provided. By providing a structure in which a source line shared by the second memory cell transistors is provided, one source line is provided with one of the first and second memory cell transistors sharing the same. Since only one read current of one memory cell transistor flows, the voltage drop and the difference between the source lines can be reduced, so that the read operation margin can be increased, and moreover, one memory cell transistor per one memory cell transistor can be used. Since the read current can be increased in a range where a read operation margin can be sufficiently provided, the operation speed can be increased, and the area of the floating gate can be increased, so that the coupling between the word line and the control gate can be increased. The capacity can be increased, the voltage at the time of writing and erasing can be reduced, and therefore, there is an effect that the voltage can be easily reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram and a layout schematic diagram showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing the structure of the embodiment shown in FIG.

FIG. 3 is a schematic layout view and a cross-sectional view illustrating a structure according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram and a layout schematic diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram and a schematic diagram showing an example of a conventional nonvolatile semiconductor memory.

FIG. 6 is a cross-sectional view showing a structure of the nonvolatile semiconductor memory shown in FIG.

[Explanation of symbols]

BL1 to BL4, BL01, BL23, BL45 Bit lines CA11, CA12, CA21, CA22 Channel regions CG11, CG21 Control gates CGP11, CGP12, CGP21, CGP22
Counter electrode CT Contact FG11, FG12, FG21, FG22 Floating gate MT11 to MT14, MT21 to MT24 Memory cell transistor SL12, SL34 Source line WL1, WL2, WL11, WL12, WL21, WL
22 word lines

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/115 G11C 16/02 H01L 21/8247 H01L 29/788 H01L 29/792

Claims (5)

(57) [Claims] 1. A plurality of first memory cell transistors having floating gates arranged in a matrix in a row direction and a column direction, and respectively corresponding to the plurality of first memory cell transistors and adjacent to the same layer. A plurality of second memory cell transistors each having a floating gate provided therein, and a control gate of a first memory cell transistor in a corresponding row provided corresponding to each row of the plurality of first memory cell transistors. And a plurality of first word lines for connecting the first memory cell transistors to the selected state on a row-by-row basis at a selection level, and a plurality of first word lines provided corresponding to each row of the plurality of second memory cell transistors. The second memory cell transistors are connected to the control gates of the second memory cell transistors in the corresponding row and are connected to the control gates at the selected level. Multiple second units to be selected in units
And a plurality of first bit lines provided corresponding to each column of the plurality of first memory cell transistors and transmitting storage information of the first memory cell transistor in a selected state of the corresponding column. A plurality of second bit lines provided corresponding to each column of the plurality of second memory cell transistors and transmitting storage information of the second memory cell transistor in a selected state of the corresponding column; A plurality of source lines provided corresponding to each column of the plurality of first and second memory cell transistors and commonly connected to the sources of the first and second memory cell transistors in the corresponding column; A row selection circuit for setting one of the plurality of first and second word lines to a selection level. 2. The method according to claim 1, wherein each of the plurality of first and second bit lines is formed as a buried diffusion layer including a drain diffusion region of each of the memory cell transistors in a corresponding column, and each of the plurality of source lines is formed in a corresponding column. 2. The nonvolatile semiconductor memory according to claim 1, wherein said nonvolatile semiconductor memory is formed as a buried diffusion layer including a source diffusion region of each of said first and second memory cell transistors. 3. A floating gate of each of the plurality of first and second memory cell transistors is opposed to a corresponding word line and control gate at a predetermined interval, and has a corresponding first gate.
3. The non-volatile semiconductor memory according to claim 2, wherein the non-volatile semiconductor memory is formed over a region opposed to a region where the bit line, the source line and the second bit line are formed. 4. The floating gate of each of the plurality of first and second memory cell transistors is connected to a corresponding first and second memory cell transistor.
Is formed over a region opposed to the region where the word line is formed and at a predetermined interval between the first and second floating gates, and is formed between the floating gate and the first and second word lines. 3. The counter electrode according to claim 2, further comprising: a counter electrode facing the floating gate at a predetermined interval and connected to one of the first and second word lines, the counter electrode including a function as a control gate. Non-volatile semiconductor memory. 5. A first and a second memory cell transistor adjacent to each other between adjacent columns of a plurality of first and second memory cell transistors.
2. The nonvolatile semiconductor memory according to claim 1, wherein one bit line is provided in place of said one bit line, and said one bit line is shared between adjacent columns.