JP2004258683A - Active matrix type liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix type liquid crystal display device which has no flicker on its display screen and can reduce a flicker level. <P>SOLUTION: In the active matrix type liquid crystal display device, two signals which are the output of a shift register of a gate line driving circuit and the output of a delay circuit delaying the output of the shift register by a certain time or three signals which are the two signals and the output of a shift register as a trailing stage are inputted to logical operation circuits provided by gate stages, three different voltage stages are exclusively selected according to the arithmetic result of the logical operation circuit, and voltages in the selected voltage stages are applied to gate lines. A punch-through voltage of a pixel can be held constant in the screen, so a voltage applied to liquid crystal becomes constant and the uniform screen having no place dependency of luminance in itself is obtained. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to an active matrix liquid crystal display device using a thin film transistor or the like as a switching element.

  2. Description of the Related Art Conventionally, liquid crystal display devices that display visual information using electro-optical characteristics of liquid crystals have been used in a wide variety of applications, such as computer image output devices, portable televisions, video projectors, and viewfinders of video cameras.

Among these liquid crystal display devices, a circuit configuration of an active matrix liquid crystal display device using thin film transistors as an active element includes a source line driver circuit 201 and a gate line driver circuit 202, as shown in the block diagram of FIG. The pixel matrix 203 is formed on the same transparent insulating substrate 204.
The pixel matrix 203 includes a plurality of source lines X ₁ , X ₂ , X ₃ ... Connected to the source line driving circuit 201 and a plurality of gate lines Y ₁ , Y connected to the gate line driving circuit 202. _2, Y ₃ and ..., and a plurality of these pixels P _11, which is formed at each intersection of the gate lines and source lines, P ₁₂ ..., to each pixel P _11, P ₁₂ ... Has a thin film transistor 205 and a liquid crystal cell 206.

  An equivalent circuit configuration of the liquid crystal display device having the above configuration will be described with reference to FIG. FIG. 2 illustrates an equivalent circuit configuration of an active matrix liquid crystal display device. The equivalent circuit is roughly divided into a source line driving circuit 301, a gate line driving circuit 302, and a pixel matrix 303. The source line driving circuit 301 is applied to an X-side shift register 304 for transmitting a latch signal in time series, a buffer 305 for amplifying and rectifying the latch signal, and a video signal line 306. Analog switches 307 and 307 'for sampling and holding the video signal on the source lines 308 and 308' according to the latch signal sent from the buffer 305. Here, the X-side shift register 304 is configured with a basic cell 334 including a clocked inverter 331 defined by a clock CLX, a clocked inverter 332 defined by a clock CLX *, and an inverter 333 as a unit. .

  On the other hand, the gate line driving circuit 302 includes a Y-side shift register 309 for transmitting a latch signal in time series, and an amplifying and rectifying the latch signal, and transmitting the same to the gate lines 311 and 311 ′. And a buffer 310. Here, the Y-side shift register 309 includes a basic cell 339 including a clocked inverter 335 defined by a clock CLY, a clocked inverter 336 defined by a clock CLY *, an inverter 337, and a NOR gate 338. Is configured.

  Also, the pixel matrix 303 includes thin film transistors 312, 312 '... Connected to the source lines 308, 308'... And gate lines 311, 311 '. It is composed of

Next, an example of a method for driving the liquid crystal display device illustrated in the equivalent circuit diagram in FIG. 2 will be described with reference to FIGS. FIG. 3 shows the voltages at points P ₁ , P ₂ , Q ₁ , Q ₂ , R ₁ , R ₂ , and V ₁ in FIG. 2 in time series. CLX represents the clock of the X-side shift register, and has a phase opposite to that of CLX *. Similarly, CLY represents a clock of the Y-side shift register, and has a phase opposite to that of CLY *. Here, CLX * and CLY * are not shown.

The driving method will be described in order. First, the Y-side shift register 309 outputs a pulse having a half width of the cycle of the clocks CLY, CLY * to the buffer 310 according to the timings of the clocks CLY, CLY *. I do. The buffer 310 amplifies and tunes the pulse, and outputs a gate selection pulse 401 to the gate line 311 (P ₁ ). While the gate selection pulse 401 is at the selection level, the plurality of thin film transistors 312 and 312 ′ connected to the gate line 311 are turned on and connected to the plurality of thin film transistors 312 and 312 ′ connected to the gate line 311. The source lines 303 and 303 'are electrically connected to the liquid crystal cells 313 and 313'. At this time, the X-side shift register 304 outputs a pulse having the same width as the clock cycle to the buffer 305 in accordance with the timing of the clocks CLX and CLX *. The pulse is amplified and rectified to output a sample-and-hold signal 403 to the analog switch 307 (Q ₁ ). The analog switch 307 converts the video signal 405 of the video signal line 306 (V ₁ ) according to the pulse. The sample and hold is performed on the source line 308 (R ₁ ). At this time, since the plurality of thin film transistors 312 connected to the gate line 311 are in a conductive state as described above, the signal held on the source line 308 is written to the liquid crystal cell 313. Similarly, the analog switch 307 'samples and holds the video signal 405 on the source line 308'. As a result, a signal sampled and held on the source line 308 'is written into the liquid crystal cell 313'. By repeating this on the source line drive circuit 301 side, the video signal 405 can be written to the liquid crystal cells of a plurality of pixels connected to the gate line 311.

  Next, after the gate selection pulse 401 becomes the non-selection level, the gate line driving circuit 302 outputs a gate selection pulse 402. When the source line driving circuit 301 is driven in the same manner as described above while the gate selection pulse 402 is at the selection level, the video signal 405 is applied to the liquid crystal cells of a plurality of pixels connected to the gate line 311 ′. Can write.

  By repeating the above operation, a video signal can be written in the liquid crystal cell unit of each pixel, and an image is obtained by changing the polarization state of each liquid crystal cell according to the signal written in the liquid crystal cell. be able to.

  In the above-described active matrix type liquid crystal display device, it is known that flicker occurs on the display screen when the delay of the gate line is relatively large. This is a phenomenon that is visually recognized as a difference in the transmittance of the liquid crystal cell because there is a liquid crystal cell in which the average value of the voltage applied to the liquid crystal is not 0. This flicker not only lowers display quality but also has a deep relationship with liquid crystal burn-in. Generally, liquid crystals need to be driven by alternating current. If the average value of the AC waveform does not become 0, that is, DC is applied to the liquid crystal, which causes a burn-in of the liquid crystal. In other words, the occurrence of flicker on the display screen means that the burn-in of the liquid crystal is likely to occur.

Now, why a liquid crystal cell in which the average value of the voltage applied to the liquid crystal does not become 0 occurs will be described below with reference to FIGS. Here, a case where an N-type thin film transistor is used for the pixel transistors 501 and 501 'will be described. Further, for simplification of explanation, by grounding the source lines 506, 506 ', and, when no voltage is applied to the liquid crystal cells of a pixel, clogging point C ₁ and point C ₂ ground level and equipotential It is assumed that

First, a phenomenon in which the voltage applied to the liquid crystal drops at the end of the selection period of the gate selection pulse, that is, a so-called penetration voltage will be described. The punch-through voltage means that the gate selection pulse 502 applied to a certain gate line 503 changes from a voltage level at which the pixel transistors 501 and 501 ′ are turned on to a voltage level at which the pixel transistors 501 and 501 ′ are turned on. The charge written to the pixel electrode escapes due to the coupling capacitance 505, 505 'between the liquid crystal cell 503 and the liquid crystal cells 504, 504', and the voltage applied to the liquid crystal is reduced. Here, the coupling capacitances 505 and 505 'mainly include a capacitance component C _gd between the gate electrodes of the pixel transistors 501 and 501' and the drain electrodes connected to the pixel electrodes of the liquid crystal cells 504 and 504 '. And a parallel capacitance component C _{gd ′} between the pixel electrodes of the liquid crystal cells 504 and 504 ′ and the gate line 503. Among them, the capacitance component C _gd changes depending on the voltage V _gd applied between the gate electrode and the drain electrode, and in the case of FIG. 4, is applied between the gate electrode and the drain electrode. As the voltage V _gd increases, the capacitance component C _gd increases.

  At this time, if a gate selection pulse with no delay is ideally input to the pixel transistor, the punch-through voltage ΔV can be expressed by Expression 1.

Here, C _all represents all capacitance components electrically connected to the pixel electrode. The transient response of the voltage applied to the liquid crystal in an ideal state without this delay will be described with reference to FIG. FIG. 5 shows the voltage on the vertical axis and the time on the horizontal axis. When the ideal gate selection pulse 611 with no delay in Equation 1 is input, the applied voltage of the liquid crystal shows a transient response represented by a curve 621. The penetration voltage at this time is ΔV.
However, actually, a delay occurs in the gate selection pulse due to the resistance of the gate line and the capacitance of the gate line, and V _gd and C _{gd in} Expression 1 change in time series according to the delayed gate selection pulse. Therefore, the amount of penetration voltage varies depending on the degree of delay of the gate selection pulse. Hereinafter, a process in which the penetration voltage ΔV causes a difference depending on the degree of delay will be specifically described. First, when the gate selection pulse 502 is input to the gate line 503, the gate selection pulse 502 passes through a first low-pass filter 508 equivalently represented by the resistance of the gate line 503 and the capacitance parasitic on the gate line 503. The first delay pulse 510 is input to the pixel transistor 501 (point G ₁ ). At this time, a high-pass filter is formed by the coupling capacitance 505 between the points G ₁ and C ₂ and the resistance between the source and the drain of the pixel transistor. In the high-pass filter, since the coupling capacitance 505 and the resistance of the pixel transistor change in a time series with the waveform of the gate selection pulse, the cutoff frequency inevitably changes in a time series. At this time, in the first delay pulse, the high-frequency component existing in the ideal gate selection pulse is cut off by passing through the first low-pass filter 508. As a result, punch-through voltage △ V ₁ at point C ₁ is less than the punch-through voltage △ V at no gate selection pulse delay described above. The state of the transient response at this time will be schematically described with reference to FIG. Curve 612 represents a first delay pulse input to the point G _1, the transient response of the voltage of the curve 622 is the point C _1, that is, represents the voltage applied to the liquid crystal.

Similarly, a second delay pulse 511 is input to the gate electrode (point G ₂ ) of the pixel transistor 501 ′ through the first low-pass filter 508 and the second low-pass filter 509. You. At this time, in the second delay pulse 511, high-frequency components existing even in the first delay pulse 510 are also cut off by passing through the second low-pass filter 509, so that the penetration voltage ΔV ₂ Is still smaller than ΔV ₁ . The state of the transient response at this time will be schematically described with reference to FIG. Curve 613 represents the second delay pulse input point G _2, curve 623 represents the transient response of the voltage at point C _2, i.e. the voltage applied to the liquid crystal.

  As a result, the penetration voltage becomes non-uniform in a plurality of pixels connected to one certain gate line, and the average value of the voltage applied to the liquid crystal is not constant. For this reason, it is impossible to set all the average values of the voltages applied to the liquid crystal to 0, and pixels in which the average value of the applied voltages is not 0 are visually recognized as flicker. Actually, it has been found that if the average value of the liquid crystal applied voltage is so small that it cannot be visually recognized as the difference in transmittance of the liquid crystal cell, it is not visually recognized as flicker.

  Therefore, in order to prevent flicker, the delay of the gate line is reduced, that is, the pass band of the low-pass filter parasitic on the gate line is shifted to the high frequency side, and the high-frequency component passing through the low-pass filter is reduced. It is necessary to increase the difference in penetration voltage to reduce the difference. As this method, a method of reducing the resistance of the gate line and a method of reducing the parasitic capacitance of the gate line can be easily considered. In the former method, there is a method in which the material of the gate line is changed to a material having a low resistance, for example, a metal thin film in the process. However, since the process is often complicated, there are many methods which cannot be practically applied. The latter method can be considered to increase the thickness of the insulating film on the gate line, change the insulating film on the gate line to a material having a lower relative permittivity, change the layout, and reduce the parasitic capacitance on the gate line. In reality, the parasitic capacitance of the gate line tends to increase as the definition of the liquid crystal display device increases, and it is extremely difficult to reduce the parasitic capacitance of the gate line while maintaining the definition. Therefore, it can be said that these methods of reducing the delay of the gate line are clearly effective but not easy to realize.

  In addition, a method of reducing the relative value of the punch-through voltage by reducing the absolute value of the punch-through voltage in order to prevent the flicker from being visually recognized may be considered. Specifically, a gate line driving circuit is used to reduce a parasitic capacitance component between a gate electrode of each pixel and a drain electrode connected to the pixel electrode, or to change a gate line from a selected state to a non-selected state. A method of reducing the wave height of the voltage waveform applied to the gate line by lowering the power supply voltage of itself is conceivable. The former method cannot be solved only by devising the design in consideration of the fact that the capacitance component tends to extremely increase with higher definition of pixels. On the other hand, the latter method can surely reduce the difference in the punch-through voltage, but the current consumption increases correspondingly because charge and discharge are repeated for all the parasitic capacitances of the power supply of the gate line drive circuit. There is a disadvantage that.

  Therefore, in the present invention, a method for solving the above-mentioned problem by a design and driving method and obtaining a liquid crystal display device without flicker will be described.

The liquid crystal device of the present invention is an active matrix type liquid crystal device having a plurality of gate lines and source lines, wherein an inverter for driving a gate line sets a first state of the inverter when the gate line is selected. With respect to a current flowing between a voltage source and the gate line, a current flowing between the second voltage source of the inverter and the gate line when the gate line is in a non-selected state is reduced. , Is constituted. In the above liquid crystal device, a cut-off frequency f _L1 when the inverter is equivalently represented as a first low-pass filter, and a gate line between a pixel closest to the gate line driving circuit and a pixel farthest from the gate line driving circuit. The cutoff frequency f _L2 when the parasitic capacitance and the parasitic resistance existing in the form of a distributed constant are equivalently represented as a second low-pass filter, and when the pixel is equivalently represented as a first high-pass filter. a cut-off frequency f _H of, it is preferable that the f _H <f _L2 <f _L1 the relationship does not hold between. In the above liquid crystal device, a cut-off frequency f _L1 when the inverter is equivalently represented as a first low-pass filter, and a gate line between a pixel closest to the gate line driving circuit and a pixel farthest from the gate line driving circuit. The cutoff frequency f _L2 when the parasitic capacitance and the parasitic resistance existing in the form of a distributed constant are equivalently represented as a second low-pass filter, and when the pixel is equivalently represented as a first high-pass filter. a cut-off frequency f _{H of, f H <f L1 <f} L2 the relationship between, or f _H <f _L1, and also so that the f _L1 and f _L2 so that holds the relationship that is substantially identical good. In the above liquid crystal device, when the resistance between the gate line and the second voltage source when the gate line is deselected is R, and the total parasitic capacitance of the inverter is C, the resistance R is represented by R It is preferable that the relationship of <1 / (2π × C × f _L2 ) is not established. In the above liquid crystal device, when the resistance between the gate line and the second voltage source when the gate line is deselected is R, and the total parasitic capacitance of the inverter is C, the resistance R is represented by R A relationship of> 1 / (2π × C × f _L2 ) or a relationship of R and 1 / (2π × C × f _L2 ) may be established. In the above liquid crystal device, when a complementary inverter is used as the inverter and an N-type transistor is used as a switching element of a pixel, the ON current in the linear region of the P-type transistor constituting the complementary inverter is reduced by N. In the case where a P-type transistor is designed as a switching element of a pixel, the ON-state current of the N-type transistor constituting the complementary inverter is reduced in the linear region of the N-type transistor. It is preferable to design the complementary inverter so as to reduce the ON current in the linear region of the P-type transistor.

Further, the liquid crystal device of the present invention is an active matrix type liquid crystal device having a plurality of gate lines and source lines, wherein a first low voltage is provided between a gate line driving circuit and a pixel closest to the gate line driving circuit. A band-pass filter is provided. In the above liquid crystal device, the cutoff frequency when the cutoff frequency f _{L3 of} the first low pass filter and the inverter driving the gate line of the gate line drive circuit are equivalently represented as a second low pass filter. The frequency f _L1 and the parasitic capacitance and the parasitic resistance existing in the form of a distributed constant in the gate line between the pixel closest to the gate line driving circuit and the pixel farthest from the pixel are equivalently represented as a third low-pass filter. Between the cut-off frequency f _L2 at the time and the cut-off frequency f _H when the pixel is equivalently represented as a second high-pass filter, f _L1 > f _L3 or f _L1 and f _L3 are substantially the same. Preferably, f _L2 > f _L3 or f _L2 and f _L3 are substantially the same, and the relationship of f _L1 > f _L2 is preferably satisfied. In the above liquid crystal device, the cutoff frequency when the cutoff frequency f _{L3 of} the first low pass filter and the inverter driving the gate line of the gate line drive circuit are equivalently represented as a second low pass filter. The frequency f _L1 and the parasitic capacitance and the parasitic resistance existing in the form of a distributed constant on the gate line between the pixel closest to the gate line driving circuit and the pixel farthest from the pixel are equivalently represented as a third low-pass filter. a cut-off frequency f _L2 of the time was, the pixels and cut-off frequency f _H when equivalently expressed as a second high-pass filter, is _{f H <f L3 <f L2} <f L1 the relationship between It is preferable to be satisfied. In the liquid crystal device described above, the first low-pass filter may include a capacitor and a resistor. In the above liquid crystal device, the first low-pass filter may include a transistor that is always in a conductive state and a power supply line that keeps the transistor in a conductive state. In the above liquid crystal device, when an N-type transistor is used as a switching element of a pixel, it is preferable to use a P-type transistor as the transistor that is always in a conductive state. In the above liquid crystal device, when a P-type transistor is used as a switching element of a pixel, it is preferable to use an N-type transistor as the transistor that is always in a conductive state. In the above liquid crystal device, the first low-pass filter may be constituted by an active filter.

In addition, a resistive modulation circuit is provided between a gate line drive circuit and a pixel closest to the gate line drive circuit, and a wiring for transmitting a resistance modulation signal for controlling the resistance of the resistance modulation element is provided. Resolve. Further, a transistor is used for the resistance modulation circuit, and a gate electrode of the transistor is connected to the wiring, and the resistance modulation signal flowing through the wiring exceeds a threshold voltage of the transistor to make the transistor conductive. Further effects can be obtained by vibrating two or more voltage states. Further, in the resistance modulation signal, when the gate line is changed from the selected state to the non-selected state, the voltage state is changed stepwise from the highest voltage state to the lowest voltage state among the two or more voltage states. Thus, a further effect can be obtained. More specifically, the output of the shift register of the gate line driving circuit, the output of the delay circuit for delaying the output of the shift register for a predetermined time, and the output of the next shift register if necessary, And then exclusively selects three different voltage states based on the operation result of the logical operation circuit, and finally applies the voltage of the selected voltage state to the gate line It is characterized by doing. Further, the three different voltage states are first and second voltage states applied by a positive power supply and a negative power supply used for driving a shift register, a logical operation circuit, a delay circuit, and the like, and a voltage of the positive power supply. A further effect can be obtained by the three states, that is, the third state which is lower than the voltage of the negative power supply. In these, the input / output terminal of the delay circuit is connected to the input of an EXOR gate, the output terminal of the EXOR gate and the output of the EXOR gate of the next gate stage are connected to the input terminal of a NAND gate, An output terminal controls a conduction state between an output terminal of the delay circuit and a gate line of an N-type transistor for controlling conduction state between the output terminal and the gate line, and a conduction state between the power supply line in the third voltage state and the gate electrode. A further effect can be obtained by connecting to the gate electrode of the P-type transistor.
Further, a signal for controlling the delay time of the delay circuit is internally generated in the gate line drive circuit, or a signal for controlling the delay time of the delay circuit is generated outside the gate line drive circuit, A new effect can be obtained by providing a signal wiring connected to the delay circuit and controlling the delay period of the delay circuit through the signal wiring.

  In the active matrix type liquid crystal display device employing the above means, the penetration voltage of the pixel can be kept constant in the screen, so that the voltage applied to the liquid crystal becomes constant, and the location-dependent luminance in the plane depends on the location. No uniform screen can be obtained. In addition, a very high-quality image free of flicker and image sticking on the display screen can be obtained. As a result, defective display due to flicker can be reliably eliminated, so that the yield of the liquid crystal display device can be substantially improved, and the manufacturing cost can be reduced. In addition, since the DC component applied to the liquid crystal cell can be minimized from design measures, it is possible to minimize the burn-in of the liquid crystal and provide a highly reliable liquid crystal display device with little time-series change. can do.

  Next, an embodiment of the present invention will be described below.

In the active matrix type liquid crystal display device embodying the present invention, the circuit configuration is the same as that of the conventional example, and therefore will be described with reference to FIGS. 1, 2 and 3. FIG. 1 is a diagram illustrating the circuit configuration. In the active matrix type liquid crystal display device of the present invention, at least the pixel matrix 203 and the source line drive circuit 201 and the gate line drive circuit 202 are formed on the same transparent insulating substrate 204. The pixel matrix 203 includes a plurality of source lines X ₁ , X ₂ , X ₃ ... Connected to the source line driving circuit 201 and a plurality of gate lines Y ₁ , Y connected to the gate line driving circuit 202. _2, Y ₃ and ..., and a plurality of these pixels P _11, which is formed at each intersection of the gate lines and source lines, P ₁₂ ..., to each pixel P _11, P ₁₂ ... Has a thin film transistor 205 and a liquid crystal cell 206.

  An equivalent circuit of the liquid crystal display device having the above circuit configuration will be described with reference to FIG. FIG. 2 is a diagram illustrating an equivalent circuit of an active matrix type liquid crystal display device. The equivalent circuit is roughly divided into a source line driving circuit 301, a gate line driving circuit 302, and a pixel matrix 303. The source line driving circuit 301 includes an X-side shift register 304 for transmitting a latch signal in time series, a buffer 305 for amplifying and rectifying the latch signal, and a video signal on a video signal line 306. Analog switches 307 and 307 'sample and hold the source lines 308 and 308' in accordance with the latch signal sent from the buffer 305. Here, the X-side shift register 304 is configured with a basic cell 334 including a clocked inverter 331 defined by a clock CLX, a clocked inverter 332 defined by a clock CLX *, and an inverter 333 as a unit. .

  On the other hand, the gate line driving circuit 302 includes a Y-side shift register 309 for transmitting a latch signal in time series, and an amplifying and rectifying the latch signal, and transmitting the same to the gate lines 311 and 311 ′. And a buffer 310. Here, the Y-side shift register 309 includes a basic cell 339 including a clocked inverter 335 defined by a clock CLY, a clocked inverter 336 defined by a clock CLY *, an inverter 337, and a NOR gate 338. Is configured.

  The pixel matrix 303 includes thin film transistors 312 and 312 'connected to the source lines 308 and 308' and gate lines 311 and 311 'and liquid crystal cells 313 and 313'.

Next, an example of a method for driving the liquid crystal display device illustrated in the equivalent circuit diagram in FIG. 2 will be described with reference to FIGS. FIG. 3 shows the voltages at points P ₁ , P ₂ , Q ₁ , Q ₂ , R ₁ , R ₂ , and V ₁ in FIG. 2 in time series. CLX represents the clock of the X-side shift register, and has a phase opposite to that of CLX *. Similarly, CLY represents a clock of the Y-side shift register, and has a phase opposite to that of CLY *. Here, CLX * and CLY * are not shown.

The driving method will be described in order. First, the Y-side shift register 309 outputs a pulse having a half width of the cycle of the clocks CLY, CLY * to the buffer 310 according to the timings of the clocks CLY, CLY *. I do. The buffer 310 amplifies and tunes the pulse, and outputs a gate selection pulse 401 to the gate line 311 (P ₁ ). While the gate selection pulse 401 is at the selection level, the plurality of thin film transistors 312 and 312 ′ connected to the gate line 311 are turned on and connected to the plurality of thin film transistors 312 and 312 ′ connected to the gate line 311. The source line 303 is electrically connected to the liquid crystal cell 313, and the gate line 303 'is electrically connected to the liquid crystal cell 313'. At this time, the X-side shift register 304 outputs a pulse having the same width as the clock cycle to the buffer 305 in accordance with the timing of the clocks CLX and CLX *. The pulse is amplified and rectified to output a sample-and-hold signal 403 to the analog switch 307 (Q ₁ ). The analog switch 307 converts the video signal 405 of the video signal line 306 (V ₁ ) according to the pulse. The sample and hold is performed on the source line 308 (R ₁ ). At this time, since the plurality of thin film transistors 312 connected to the gate line 311 are in a conductive state as described above, the signal held on the source line 308 is written to the liquid crystal cell 313. Similarly, the analog switch 307 'samples and holds the video signal 405 on the source line 308'. As a result, a signal sampled and held on the source line 308 'is written into the liquid crystal cell 313'. By repeating this on the source line drive circuit 301 side, the video signal 405 can be written to the liquid crystal cells of a plurality of pixels connected to the gate line 311.

  Next, after the gate selection pulse 401 becomes the non-selection level, the gate line driving circuit 302 outputs a gate selection pulse 402. When the source line driving circuit 301 is driven in the same manner as described above while the gate selection pulse 402 is at the selection level, the video signal 405 is applied to the liquid crystal cells of a plurality of pixels connected to the gate line 311 ′. Can write.

  By repeating the above operation, it becomes possible to write a video signal for each liquid crystal cell of each pixel, and obtain an image by changing the polarization state of each liquid crystal cell according to the signal written to the liquid crystal cell. Can be.

  As described above, in the active matrix type liquid crystal display device having the above configuration, the flicker is generated on the display screen because the penetration voltage cannot be constant in the plane. In a liquid crystal display device in which flicker is visually recognized, the penetration voltage is the largest in the liquid crystal cell of the pixel closest to the gate line driving circuit, and the penetration voltage is the smallest in the liquid crystal cell of the pixel farthest from the gate line driving circuit. I have. If the difference in the penetration voltage is visually recognized as flicker when it is large enough to be recognized as the difference in transmittance of the liquid crystal cell, the difference in the penetration voltage may be reduced to such an extent that flicker cannot be visually recognized. Will be. That is, it is possible to make the penetration voltage constant by increasing the penetration voltage in the pixel having the small penetration voltage, or reducing the penetration voltage in the pixel having the large penetration voltage.

  In the first embodiment, a method of obtaining a flicker-free liquid crystal display device by limiting the resistance of an inverter that directly drives a gate line of a gate line driving circuit when a gate line shifts from a selected state to a non-selected state. Will be described.

  FIG. 6 is an equivalent circuit diagram of a gate line driving circuit and a pixel matrix of a liquid crystal display device using the first embodiment extracted for one gate line.

Here, the operation of the gate line driving circuit will be described focusing on the operation of an inverter that directly drives a gate line. Here, it is assumed that this gate line 704 is currently in a non-selected state and is just before shifting to a selected state. First, the inverter 703 outputs a signal for setting the gate line 704 to a selected state according to the latch signal 702 output from the shift register portion of the gate line driver circuit 701. Hereinafter, the selected state refers to a state in which the gate line 704 is applied to a voltage at which the thin film transistors 706 and 706 ′ connected to the gate line 704 are turned on. At this time, the resistance of the P-type thin film transistor R _P of the inverter 703, and the resistance of the N-type thin film transistor and R _N holds the relation R _N >> R _P, the inverter 703 to the P-type thin film transistor from the power supply wiring line V _dd Through the gate line 704, a current I _P for charging a charge flows. Next, in response to the latch signal 702, the inverter 703 outputs a signal for setting the gate line to a non-selected state. Hereinafter, the non-selected state refers to a state in which the gate line 704 is applied to a voltage that turns off the thin film transistors 706 and 706 ′ connected to the gate line 704. In this case, the thin film transistor of the resistance of the inverter 703 R _P >> R _N relationship holds is, current in inverter 703 to release the charge stored in the gate line 704 to the ground line GND via the N-type thin film transistor I _N flows. The gate line 704 in the non-selected state in this way receives the latch signal 702 output from the shift register unit of the gate line driving circuit 701 and holds the non-selected state until the gate line 704 is again in the selected state.

In the first embodiment, the gate line driving circuit for the above operation, by limiting the resistance R _N of the N-type thin film transistor in a non-selected state in conditions described below, a penetration voltage previously described by each pixel Can be constant.

First, when there is a first pixel 705 closest to the gate line driver circuit 701 and a second pixel 705 ′ farthest from the gate line driving circuit 701, a gate existing in a distributed constant type between the first pixel 705 and the second pixel 705 ′. The resistance of the line 704 and the parasitic capacitance of the gate line 704 are equivalently represented as a low-pass filter 707 having a cutoff frequency f _L2 . Further, the inverter 703 in the non-selected state, and the resistance R _N of the capacitor C _INV and N-type thin film transistor parasitic on the inverter 703, and shall be expressed as a low-pass filter equivalently cutoff frequency f _L1 . Further, the first pixel 705 is equivalently provided as a high-pass filter 148 having a cutoff frequency f _H and comprising a resistance of the thin film transistor 706 and a capacitance between a drain electrode and a gate electrode connected to the pixel electrode of the thin film transistor 706. it can be represented, a second pixel 705 similarly 'also high-pass filter 148 of the cut-off frequency f _H' and what can be equivalently represented as.

When the equivalent circuit diagram of FIG. 6 is further simplified using these filters, it can be replaced with the equivalent circuit diagram shown in FIG. In FIG. 7, a low-pass filter 801 with a cut-off frequency f _L1 equivalently represents the inverter 703, a high-pass filter 803 with a cut-off frequency f _H equivalently represents the first pixel 705, and likewise a cut-off frequency f _{The H} high-pass filter 804 equivalently represents the second pixel 705 '. The low-pass filter 802 having the cutoff frequency f _{L2 is} the low-pass filter 707 of the distributed constant type between the first pixel 705 and the second pixel 705 ′ described above. The output signal of the inverter 703 input to the circuit represented by each of these filters is represented as a signal source 804.

In the first embodiment, when the relationship of f _L1> f _H and f _L2> f _H is made up in this equivalent circuit, the cutoff frequency f _L2 of the cut-off frequency f _L1 of the low-pass filter 801 low-pass filter 802 And the low-pass filter 801 of the inverter 703 so that the relationship of f _L1 ≒ f _L2 holds, or the relationship of f _L1 <f _L2 holds, or at least f _L1 >> f _L2. design.

Hereinafter, the meaning of f _L1 ≒ f _L2 > f _H will be described with reference to FIG. FIG. 8A shows the frequency characteristics of the respective filters when the conventional relationship of f _L1 > f _L2 > f _H holds, and FIG. 8B shows f _L1 1f _L2 > f _{H of the} first embodiment. Represents the frequency characteristic of each filter when the relationship holds. FIG. 8C shows frequency characteristics at points P ₃₁ and P ₃₂ in FIG. 7 when the conventional relationship of f _L1 > f _L2 > f _H is satisfied, and FIG. 8D shows the first embodiment. 7 shows the frequency characteristics at points P ₃₁ and P ₃₂ in FIG. 7 when the relationship f _L1 ≒ f _L2 > f _H holds. 8 (a) to 8 (d), the ordinate represents the amplification factor as a dB value, and the abscissa represents the frequency. FIG. 8E shows the voltage waveforms at points P ₃₁ and P ₃₂ in FIG. 7 and the penetration voltages ΔV ₁ and ΔV ₂ when the conventional relationship of f _L1 > f _L2 > f _H holds. FIG. 8F shows the voltage waveforms and the penetration voltages ΔV ₁ ′ and ΔV ₂ ′ at points P ₃₁ and P ₃₂ in FIG. 7 when the relationship f _L1 ≒ f _L2 > f _H holds in the first embodiment. Represents 8 (e) and 8 (f), the vertical axis represents voltage, and the horizontal axis represents time. As shown in FIG. 8A, when the conventional relationship of f _L1 > f _L2 > f _H is established between the respective filters, a point P ₃₁ passing through the low-pass filter 801 and the high-pass filter 803 is obtained. If, when comparing the frequency characteristics in the low-pass filter 801 and the low-pass filter 802 and the high-pass filter 803 'and P ₃₂ that has passed through, at P _31, as shown in FIG. 8 (c) passing frequency band of the P ₃₂ compared to the pass frequency band becomes narrow, therefore punch-through voltage △ V ₁ at P _31, as shown in FIG. 8 (e) is greater than the punch-through voltage △ V ₂ at P _32. When the difference between ΔV ₁ and ΔV ₂ is such that it is visually recognized as a difference in transmittance of liquid crystal in the pixel portion, flicker is visually recognized on the screen of the liquid crystal display device. On the other hand, when the relationship of f _L1 ≒ f _L2 > f _H is established between the respective filters as shown in FIG. 8B, comparing the frequency characteristics at P ₂₁ and P ₂₂ with FIG. As shown in FIG. 8C, the difference in the pass frequency band advances in a direction smaller than that in FIG. 8C, and therefore, as shown in FIG. 8F, the difference between the penetration voltages ΔV ₁ ′ and ΔV ₂ ′ decreases. . When the difference between △ V ₁ ′ and △ V ₂ ′ is such that the difference between the transmittances of the liquid crystal of the pixel portion cannot be visually recognized, flicker is not visually recognized on the screen of the liquid crystal display device.

Further, when the relationship of f _L1 <f _L2 holds, before the signal is input to the low-pass filter 802, the low-pass filter 801 cuts off the frequency components higher than the cutoff frequency f _{L1. L2} hardly functions as a high-frequency cutoff filter. For this reason, the punch-through voltages at P ₃₁ and P ₃₂ are inevitably almost equal, and a liquid crystal display device without flicker can be realized.

Above, wherein has been described can be realized a liquid crystal display device without flicker when the low-pass filters 801 and 802 f _L1 ≒ f _L2 or f _L1 <f _L2 becomes relationship holds, at least f _L1 >> f _L2 If the inverter 703 constituting the low-pass filter 801 is designed so that the relationship does not hold, the flicker level itself can be reduced, so that the yield during display inspection can be substantially improved.

Well Here, the be composed of a capacitor C _INV low-pass filter 801 is parasitic to the resistor R _N and the inverter of N-type thin film transistor of the inverter 703 in the non-selected state mentioned before. In the design, no problem consider the cut-off frequency f _L1 of the low-pass filter 801 which represents the said inverter 703 equivalently equals _{1 / (2π × R N ×} C INV). These, and the pixel closest to the gate line driving circuit, a cutoff frequency f _L2 of the low-pass filter 802 of the distributed constant type formed on the gate lines between the farthest pixel from the gate line driving circuit, R _N , R between the _{C inv N ≒ 1 / (2π} × C inv × f L2) so as relationship holds, or _{R N> 1 / (2π ×} C inv × f L2) becomes such that the relationship is established R _N By designing the liquid crystal display device, a liquid crystal display device without flicker can be realized. Or, by designing at least _{R N << 1 / (2π ×} C inv × f L2) of so as not to establish the relationship R _N, it is possible to realize a liquid crystal display device with low flicker level. Although previously added here, the resistor R _N instead should be infinite value, the inverse of the cutoff frequency f _L1, i.e. one period of the frequency _{f L1 (2π × R N ×} C INV) is, there It is necessary that the period be sufficiently shorter than the period given to keep the pixel group connected to one gate line in the selected state.

As described above, in order to realize a liquid crystal display device free from flicker from the design it is necessary to increase the resistance R _N of the N-type thin film transistor of the inverter 703 in a non-selected state. In contrast, the resistance R _P of the P-type thin film transistor in the selected state delays to influence the degree, that as low is better possible is evident at the time of the selected state of the gate lines from the non-selected state. Therefore, more specifically, it is necessary to intentionally unbalance the design sizes of the N-type thin film transistor and the P-type thin film transistor of the inverter that directly drives the gate line of the gate line driving circuit. Normally, when designing an inverter using complementary transistors, the manufacturing process and design size are optimized so that the resistance in the linear region of the N-type transistor is the same as the resistance in the linear region of the P-type transistor. Become By doing so, the performance of the transistor can be maximized. In Example 1 In contrast, in only an inverter for driving a gate line of the gate line driving circuit directly, the resistance R _N in the linear region of the N-type thin film transistor to the resistance R _P in the linear region of the P-type thin film transistor Design to be large. More specifically, a flicker-free liquid crystal display device can be realized only by a very simple design change, such as increasing the channel length or shortening the channel width of the N-type thin film transistor of the inverter.

  As described above, in the first embodiment, the inverter using the complementary transistor is directly used as the inverter for directly driving the gate line of the gate line driving circuit. However, the gate line driving circuit using the push-pull type inverter or the like is similarly described. Applicable. In the first embodiment, the thin film transistor is used as the driving circuit element and the switching element of the pixel. However, as long as the same operation is performed, for example, a MOS field effect transistor or an SOI field effect transistor Or the like may be used.

  In a second embodiment, a method for realizing a liquid crystal display device free from flicker by providing a low-pass filter between a gate line driving circuit and a pixel will be described.

FIG. 9 is an equivalent circuit diagram in which a gate line driving circuit and a pixel matrix of a liquid crystal display device using the second embodiment are extracted for one gate line. Here, a low-pass filter 123 having a cutoff frequency f _L3 is provided between an inverter 122 that directly drives a gate line of the gate line driving circuit 121 and a first pixel 124 closest to the gate line driving circuit 121. At this time, between the first pixel 124 closest to the gate line driving circuit 121 and the second pixel 124 ′ farthest from the gate line driving circuit 121, a distributed constant low-pass of cut-off frequency f _L2. The resistance of the gate line 125 and the parasitic capacitance of the gate line 125 that can be equivalently expressed as a filter exist in a distributed manner.

When the liquid crystal display device having the configuration shown in FIG. 9 is simplified by using the above-described respective filters in the same manner as in the first embodiment, it can be replaced with an equivalent circuit diagram shown in FIG. Here, the inverter 122, a resistor R _N in a non-selected state of the N-type thin film transistors forming the inverter, the low-pass filter 141 of the capacitor C cutoff composed of a _INV frequency f _L1 parasitic on the inverter as a replacement, also replaced the first pixel and the second pixel as each high-pass filter 144 and 144 of the cut-off frequency f _H '.

  At this time, if the low-pass filter 141 and the low-pass filter 142 are collectively represented as a synthesis filter 143, this is equivalent to FIG. 7 used in the description of the first embodiment. Accordingly, by providing the low-pass filter 142 between the gate line driving circuit and the first pixel without changing the design of the inverter that directly drives the gate line of the gate line driving circuit from the conventional one. Thus, it can be said that the same effect as in the first embodiment can be obtained.

Hereinafter, the second embodiment will be described in more detail. In the second embodiment, the range of the cutoff frequency f _L3 of the low-pass filter 142 is defined as follows. First, the cut-off frequency f _L1 of the low-pass filter 141 equivalent to the inverter 122 in the unselected state and the cut-off frequency f _L3 of the low-pass filter 142 newly provided in the second embodiment. _{Satisfies the} relationship of f _L1 > f _L3 , or at least the relationship of f _L1 Lf _L3, and the cutoff frequency of the synthesis filter 143 equivalently representing the two low-pass filters 141 and 142 is the cutoff frequency f _L3 Needs to be heavily dependent on This is because the cutoff frequency f _L3 of the low-pass filter 142 newly provided in the second embodiment is arbitrarily designed so that the pass band of the signal is not changed until the output signal 146 is input to the pixel closest to the gate line. Is required to be controlled. Further, the cut-off frequency f _{L2 of the} distributed constant type low-pass filter 145 that is equivalently parasitic on the gate line over a plurality of pixels, and the low-pass filter 142 newly provided in the second embodiment. It is necessary that the relationship of f _L2 > f _L3 , or at least the relationship of f _L2 Lf _L3, be established with the cut-off frequency f _L3 . This relationship can be explained in the same manner as in the first embodiment. In other words, in order to minimize the frequency components cut off by the distributed constant type low-pass filter 145, before outputting the signal to the distributed constant type low-pass filter 145, that is, the gate line driving circuit is most required. This means that it is necessary to cut off a frequency component lower than the cut-off frequency f _L2 of the distributed constant type low-pass filter before outputting the signal to a close pixel.

Here, in a conventional liquid crystal display device having flicker, that is, a liquid crystal display device having a penetration voltage difference, a low-pass filter equivalent to an inverter that directly drives a gate line of a gate line driving circuit. Is lower than the gate line driving circuit because the cut-off frequency of the distributed constant type low-pass filter that is equivalently parasitically formed on the gate line across a plurality of pixels is lower than the cut-off frequency of As described above, the absolute value of the penetration voltage becomes smaller for a pixel, and as a result, the difference in the penetration voltage is visually recognized as flicker. When this is applied to the second embodiment, the cutoff frequency f _L1 of the low-pass filter 141 equivalently configured to the inverter 122 and the gate line extending between a plurality of pixels are equivalently configured to be parasitic. The relationship of f _L1 > f _L2 holds between the cut-off frequencies f _L2 of the distributed constant type low-pass filter 145. Furthermore, in the liquid crystal display device in which this penetration voltage occurs in the first place, the cut-off frequency of the high-pass filter equivalently representing each pixel is lower than the cut-off frequency of each low-pass filter parasitic on the gate line, or at least. It must be close to the cutoff frequency of each low-pass filter.

Summarizing the above conditions, in order to obtain a liquid crystal display device having no flicker, in the second embodiment, the relationship of f _L1 > f _L2 > f _L3 > f _H is established between the cut-off frequencies of the respective filters. Ideally, the cut-off frequency f _L3 of the newly provided low-pass filter 142 is designed, but if at least all of the above conditions can be satisfied, the flicker level of the liquid crystal display device is surely reduced. Therefore, occurrence of defective display related to flicker can be reduced.

  Now, how the low-pass filter is specifically configured will be described below with reference to FIG. FIG. 11 schematically illustrates a liquid crystal display device using the second embodiment, which is schematically extracted for one gate line.

  First, FIG. 11A shows a configuration in which a low-pass filter 164 including a resistor and a capacitor is provided between a gate line driving circuit 161 and a pixel group 167. In this case, the cutoff frequency of the low-pass filter 164 can be determined by designing the resistance and the capacitance. Here, the low-pass filter 164 is formed of a distributed constant type, but may be a lumped constant type low-pass filter.

  Next, FIG. 2B shows that a low-pass filter 165 using a P-type thin film transistor whose gate electrode is applied with a ground potential is provided between the gate line driving circuit 162 and the pixel group 168. . Equivalently, it can be seen that this low-pass filter 165 is composed of the resistance of the P-type thin film transistor and the parasitic capacitance of the P-type thin film transistor. In this case, the resistance and the parasitic capacitance can be arbitrarily determined by a method such as changing a channel width, a channel length, a gate oxide film thickness or the like of the P-type thin film transistor, or a method of connecting a plurality of the P-type thin film transistors in parallel. It is possible to design, and thus, the cutoff frequency of the low-pass filter 165 can be determined. Although a P-type thin film transistor is shown here, it may be a transistor such as an N-type thin film transistor or a diode capable of realizing the same function, or a combination of a plurality of transistors such as a transmission gate. May be used. However, when an N-type transistor is used as a switching element of a pixel group, a P-type transistor is used. When a P-type transistor is used as a switching element of a pixel group, an N-type transistor is used as the low-pass filter. It will be described below that more effects can be obtained by using. Here, the description will be made on the assumption that a P-type transistor is used as the low-pass filter as shown in FIG. The P-type thin film transistor is always in a conductive state because its gate electrode is applied with a voltage of the ground potential. However, even though they are in the same conduction state, the resistance between the drain electrode and the source electrode changes according to the voltage of the signal passing through it, and the closer the voltage of the signal becomes to the ground potential, the more the resistance between the drain electrode and the source electrode becomes. Resistance will increase. That is, the resistance of the P-type thin film transistor in the non-selected state is higher than the resistance of the P-type thin film transistor in the selected state. Therefore, a signal delay when shifting from the non-selected state to the selected state is reduced. The delay at the time of transition from the selected state to the non-selected state can be reduced. Accordingly, a difference in punch-through voltage at the end of the gate line selection period can be reduced without increasing the delay time of the gate line selection signal at the start of gate line selection, and a liquid crystal display device free from flicker can be obtained. Can be. The same can be said for a case where a P-type transistor is used for the pixel group and an N-type transistor is used as the low-pass filter.

  FIG. 11C shows that a low-pass filter 166 including an operational amplifier, a resistor, and a capacitor is provided between the gate line driving circuit 163 and the pixel group 169. In this case, the cutoff frequency of the low-pass filter 166 can be determined mainly by designing the resistance and the capacitance. The cutoff frequency of the low-pass filter 166 can also be determined by a method of designing various characteristics such as input / output impedance and frequency characteristics of the operational amplifier itself. Here, an active filter using an operational amplifier has been described as an example, but the circuit need not be an operational amplifier as long as the circuit has a similar function.

In a third embodiment, a method for obtaining a flicker-free liquid crystal display device by providing a resistance modulation circuit between a gate line driving circuit and a pixel group and a driving method thereof will be described. FIG. 12 shows an example of the third embodiment, in which a liquid crystal display device is replaced as an equivalent circuit along a gate line 183. In the third embodiment, a resistance modulation circuit 185 composed of an N-type thin film transistor is provided between the gate line driving circuit 181 and the pixel group 184. The resistance value of the resistance modulation circuit 185 is controlled by a resistance modulation signal output from a voltage source 186. In the figure, the resistance modulation signal is input to the gate electrode of the N-type thin film transistor to reduce the resistance. Modulated.
Next, a driving method of the liquid crystal display device of FIG. 12 will be described with reference to a time chart of FIG. It is 13 to showing the voltage waveforms at respective points _{P 31, P 32, P 33} , P 34 in FIG. 12. Here, the signal appearing at the point P ₃₁ is a latch signal for driving the final inverter for driving the gate line of the gate line driving circuit 181 directly, the signal appearing at the point P ₃₂ is the output signal from the last inverter. The signal appearing at the point P ₃₃ is the resistance modulation signal for controlling the resistance modulation circuit 185, which changes between two voltage states higher than the threshold voltage of the N-type thin film transistor used in the resistance modulation circuit 185. It is changing. Furthermore, represent the final voltage applied to the gate electrode of the pixel groups is the signal appearing at the point P _34. First, in order to start writing to the pixel group, a signal of a voltage level for turning on a thin film transistor used as a switching element of the pixel group connected to the gate line 183 is output from the gate line driving circuit 181. . Substantially simultaneously the voltage at the point P ₃₂ to a voltage that drops to the ground potential at this time point P ₃₁ rises to the power supply voltage, will charge the gate line 183 (P ₃₄₎ so as to the pixel group into a conductive state . At this point, since the resistance modulating signal appearing at the point P ₃₃ is taking a voltage state of lower one of voltages of the two voltage states, the resistance modulation circuit 185 has become a relatively high resistance conductive state The voltage (P ₃₄ ) finally applied to the gate electrode of the pixel group is accompanied by a delay. After that, until the video signal is input to the signal line 187, that is, before the video signal input period 226 starts, the resistance modulation signal (P ₃₃ ) takes the higher voltage state of the two voltage states. By doing so, the resistance of the N-type thin film transistor of the resistance modulation circuit 185 is sufficiently reduced, the voltage applied to the gate line is saturated to the power supply voltage, and the thin film transistor used as the switching element of the pixel group is brought into a completely conductive state. To Next, after the video signal input from the signal line 187 is written to the liquid crystal cell of each pixel in the video signal input period 226, the resistance modulation signal (P ₃₃ ) is again applied to the voltage of the two voltage states. Wait for the selection period 226 to end with the lower voltage state. At the same time when the selection period 226 ends, the gate line drive circuit 181 outputs a voltage level signal (P ₃₂ ) for insulating a thin film transistor used as a switching element of the pixel group 184 connected to the gate line 183. I do. However, at this time, since the resistance modulation element 186 is in a conductive state with a relatively high resistance, a delay occurs in the signal here, and the voltage (P ₃₄ ) finally applied to the gate line gradually decreases. In terms of frequency, a high-frequency component that causes a punch-through voltage is cut off, and in addition to this, the same conditions as those in the first and second embodiments are applied to the resistance modulation circuit of the present embodiment. By doing so, a liquid crystal display device without flicker can be obtained.

  In the liquid crystal display device according to the third embodiment, when the conventional method of lowering the power supply voltage of the gate line driving circuit only at the end of the selection of the gate line is used, the total capacitance parasitic to the power supply of the gate line driving circuit is reduced. Compared to the current consumption required for charging / discharging, only the same number of thin film transistors as the number of gate lines need be charged / discharged, so that the same effect can be obtained with much smaller current consumption.

  In the fourth embodiment, the output of the shift register of the gate line driving circuit, the output of the delay circuit for delaying the output of the shift register for a fixed time, and the output of the next-stage shift register if necessary are provided for each stage. A method for realizing a flicker-free liquid crystal display device by applying the three-state voltage exclusively to the gate line after the input to the logical operation circuit will be described in detail.

FIG. 14 is a block diagram for comprehensively explaining the fourth embodiment. This diagram is roughly divided into a gate line drive circuit 241, a pixel group 248, and three power supply lines 249, 250, and 251. The gate line driving circuit 241 includes a shift register 242, a delay circuit 243, a logical operation circuit 244, and power switches 245, 246, and 247 for exclusively selecting three power lines. At this time, the power supply line 249 is applied by the positive power supply 252 to the voltage V _dd for making the pixel group conductive, and the power supply line 250 is applied by the negative power supply 253 to the voltage V _ss for making the pixel group insulative. , is applied to the V _rr by the voltage source 254 of the high voltage V _rr than further power supply line 251 is lower V _ss than V _dd. A power switch 245 is provided to control the conduction between the power supply line 249 and the gate line. A power switch 246 is provided to control the conduction between the power supply line 250 and the gate line. The switch 247 is provided to control a conduction state between the power supply line 251 and the gate line.

The flow of this block diagram is shown below, following the order of operation of the gate line drive circuit. First, it is assumed that a selection signal for selecting a gate line is output from the shift register 242 as in the related art. At this time, the selection signal, the selection signal delayed for a predetermined time through the delay circuit 243, and the output of the next stage of the shift register 242 are input to the logical operation circuit 244. At this time, since the next-stage gate line has not been selected yet, the output of the next stage of the shift register 242 is in a non-selected state. In this state, the logical operation circuit 244 makes only the switch 245 connected to the power supply line 249 conductive. Thus, the gate line is applied with the voltage _Vdd , and the pixel group connected to the gate line becomes conductive. By sending a video signal to the signal line connected to the pixel group in this state, a signal can be written to the liquid crystal cell of the pixel group connected to the gate line. Next, after the writing to the pixel is completed, a non-selection signal for setting the gate line to a non-selection state is output from the shift register 242. At this time, the non-selection signal, the selection signal delayed by a predetermined time through the delay circuit 243, and the output of the next stage of the shift register 242 are input to the logical operation circuit 244. At this time, a selection signal for setting the next-stage gate line to the selected state is output to the output of the next stage of the shift register 242. Considering this state in more detail, first, although the non-selection signal from the shift register 242 is input to the delay circuit 243, the output is delayed, so that the output of the delay circuit 243 is in the selected state. It turns out that it will be in the state of being left. Hereinafter, a period in which this state is established is referred to as a waiting period. At this time, a non-selection signal for setting the gate line to a non-selection state from the shift register, a selection signal for setting the next-stage gate line to the selection state, and a delay circuit 243 during a waiting period are supplied from the shift register. , A selection signal that is still in a selected state is input. As a result of the logical operation, the logical operation circuit 244 turns on only the power switch 247 and keeps applying the gate line to the voltage _Vrr during the waiting period. Next, when the output of the delay circuit 243 becomes non-selected after the waiting period, the logic operation circuit 244 turns on only the power switch 246 and keeps applying the gate line to the voltage V _ss . By repeating the above for each gate line, all the gate lines can be selected.

Now, let us summarize the time-series change of the voltage applied to the gate line. First, the gate line is selected and applied to a voltage _Vdd . Next, the waiting period is applied at the same time as the selection period ends, and the voltage is applied to the voltage _Vrr . Finally the wait period ends at the same time the gate line is applied to the voltage V _ss is deselected.
In this way, the difference from the conventional driving method is that the voltage does not immediately become the voltage V _ss when the selection period ends, but after the voltage once falls to the voltage V _rr lower than the voltage V _{dd and} higher than the voltage V _ss , _ss . By performing such driving, the falling signal applied to the gate line from the gate line driving circuit when the gate line is changed from the selected state to the non-selected state can be moderated. Focusing on the frequency component of the signal as in the above-described embodiment, the high-frequency component of the falling signal is reduced, and the absolute value of the punch-through voltage can be reduced. That is, flicker of the liquid crystal display device can be eliminated.
A liquid crystal display device that realizes the fourth embodiment and its operation will be specifically described below. FIG. 15 is an equivalent circuit diagram showing one example of the fourth embodiment. The gate line driving circuit 261 includes a shift register 268, a delay circuit 263, a two-input EXOR gate 264, a two-input NAND gate 265, an N-type thin film transistor 266, a P-type thin film transistor 267, and a power supply line 269. You. First, the delay circuit 263 is connected to the signal output terminal of the shift register 268, and the input terminal and the output terminal of the delay circuit 263 are connected to the two input terminals of the EXOR gate 264, respectively. On the other hand, the output terminal of the delay circuit 263 is connected to one drain electrode of the N-type thin film transistor so as to control the conduction state via the N-type thin film transistor 266 between the delay circuit 263 and the gate line 270. Further, the output terminal of the EXOR gate 264 and the output terminal of the next EXOR gate 264 ′ are connected to two input terminals of the NAND gate 265, respectively. Further, the output terminal of the NAND gate 265 is connected to the gate electrode of the N-type thin film transistor 266, and the output of the NAND gate 265 controls the conduction between the gate line 270 and the delay circuit 263. The output terminal of the NAND gate 265 is also connected to a gate electrode of a P-type thin film transistor 267 provided to control a conduction state between the power supply line 269 and the gate line 270. By repeating this for each stage of the gate line driving circuit, a gate line driving circuit 261 shown in FIG. 15 is obtained.

Next, the operation of this gate line driving circuit will be briefly described with reference to FIGS. 15 and 16 together with the time charts shown in FIGS. FIG. 16 is a time chart showing a time-series change in voltage at points P _{41 to} P ₄₈ indicated by black circles in FIG. Here, as can be seen from the voltage waveforms at P ₄₁ and P ₄₂ , it is assumed that the selection signals output to each stage by the shift register are separated in time series for each stage.

First, in the initial state, the output from the shift register 268 is at the low level, and since the same potential is maintained before and after the delay circuit 263 (P ₄₁ , P ₄₃ ), the output from the EXOR gate 264 ( P ₄₅₎ also has a low level. Similarly, the output (P ₄₆ ) from the next-stage EXOR gate 264 ′ is also at the low level. Therefore, the output of the NAND gate 265 that receives the outputs from the two EXOR gates is at a high level, the P-type thin film transistor 267 is insulated, the N-type thin film transistor 266 is in a conductive state, and the delay circuit 263 It becomes the output of the low level (P ₄₃₎ that is applied to the gate line 270 (P _48).

Beating this equilibrium, suppose selection pulse from the shift register 268 is output to the point P _41. First, the input terminal (P ₄₁ ) of the delay circuit 263 is at a high level, but the output terminal (P ₄₃ ) of the delay circuit 263 is still at a low level due to signal delay by the delay circuit 263. Therefore, the EXOR gate 264 using the input / output signal of the delay circuit 263 as an input signal outputs a high-level signal (P ₄₅ ). At this time, the EXOR gate at the next stage keeps outputting a low-level signal (P ₄₆ ) because there is no change in its two input terminals. Therefore, the NAND gate 265 receiving the output signals of the two EXOR gates as an input signal continues to output a high level signal, keeps the N-type thin film transistor 266 conductive, and outputs the output (P ₄₃₎ from the delay circuit 263. ) Continues to pass through the gate line (P ₄₈ ). Thereafter, even after the end of the waiting period determined by the delay time of the delay circuit 263, the potential of the input / output terminal of the delay circuit 263 becomes equipotential, and the output (P ₄₅ ) of the EXOR gate outputs a low-level signal again. Otherwise, the output signal (P ₄₃ ) from the delay circuit 263 continues to be applied to the gate line 270, and the gate line 270 is applied to a high-level voltage. The group of pixels connected to it is made conductive.

Then, after writing the video signal to the pixel group, a low-level signal (P ₄₁ ) that ends the selection period of the gate line 271 is output from the shift register 268. At the same time, the output (P ₄₂ ) of the next stage of the shift register 268 goes high in order to select the gate line of the next stage. This moment, to enter the waiting period of the delay circuit 263, EXOR gates 264 and the next stage of the EXOR gate 264 'both outputs a high level (P _45, P _46). In response to this, the NAND gate 265 in which both the input signals are at the high level outputs the signal at the low level (P ₄₇ ), and the gate line 270 and the delay circuit 263 have been kept conductive until now. The N-type thin film transistor 266 is set in an insulating state. Conversely, the P-type thin film transistor 267, which has been in the insulating state, is turned on, and the potential applied to the power supply line 269 is applied to the gate line 270 during the waiting period of the delay circuit 263 ( P ₄₈ ). At about the same time that the waiting period ends and the input / output signals of the delay circuit 263 become equipotential, the outputs (P ₄₅ and P ₄₆ ) of the two EXOR gates 264 and 264 ′ both become low level again, The output (P ₄₇ ) of the NAND gate 265 using them as input signals returns to the high level again. That is, this is the same as returning to the initial state again, and a low-level signal from the delay circuit 263 is applied to the gate line 270. That is, the state returns to the initial state at the same time as the end of the waiting period of the delay circuit 263. On the other hand, as for the gate line at the next stage, a high-level signal is applied at the same time as the end of the waiting period of the delay circuit, and it can be seen that the selection of the gate line is repeated. By repeating this further before the gate line driving circuit, the gate line driving circuit of the fourth embodiment can be operated.

  Now, let us consider the correspondence between the equivalent circuit diagram of FIG. 15 and the block diagram of FIG. Although there are three power lines 252, 253, 254 in the block diagram of FIG. 14, you will first notice that only one power line 269 is found in the equivalent circuit diagram of FIG. Here, it is obvious that the power supply line 251 corresponds to the power supply line 269, but the other two power supply lines are not eliminated. The presence of two positive and negative voltage sources for driving the shift register 268, NAND gate, EXOR gate, etc., which is omitted in FIG. 15, is obvious from the existence of the voltages corresponding to the high level and the low level described above. Will. In other words, the positive voltage source and the power supply line that output the voltage corresponding to the high level are the voltage source 252 and the power supply line 249 in FIG. 14, and output the voltage corresponding to the low level. The negative voltage source corresponds to the voltage source 253 and the power supply line 250 in FIG.

  As described above, in the fourth embodiment, the circuit of the fourth embodiment is incorporated in the gate line driving circuit 241. However, a circuit having a similar configuration is provided, for example, immediately before the pixel group 243. No problem. As for the delay circuit, for example, a delay circuit that causes a delay between input and output by connecting a plurality of inverters may be used, or a constant circuit such as a delay circuit that uses the release time of the charge stored in the capacitor. Any delay circuit may be used as long as the delay time can be secured. Further, a wiring for transmitting a signal for controlling the delay time from the outside to the delay circuit may be newly provided.

FIG. 9 is a diagram illustrating a configuration of a conventional liquid crystal display device. FIG. 11 is an equivalent circuit diagram illustrating a conventional liquid crystal display device. FIG. 9 illustrates an example of a conventional method for driving a liquid crystal display device. FIG. 9 is a diagram illustrating a conventional liquid crystal display device, which is equivalently extracted for one gate line. FIG. 9 is a diagram illustrating a transient response of a voltage applied to liquid crystal of a conventional liquid crystal display device. FIG. 3 is a diagram illustrating an example of a first embodiment of the present invention. FIG. 7 is a diagram illustrating a first embodiment of the present invention in FIG. 6 as a simplified equivalent circuit. FIG. 4 is a diagram for describing a condition to be satisfied according to the first embodiment of the present invention. FIG. 8A is a diagram showing the relationship between the frequency characteristics of the conventional frequency filters. FIG. 8B is a diagram illustrating a relationship between frequency characteristics of each frequency filter in the first embodiment. FIG. 8C is a diagram showing a relationship between frequency characteristics at points P ₁ and P ₂ after passing through each frequency filter when the condition of FIG. 8A is satisfied. FIG. 8D is a diagram illustrating a relationship between frequency characteristics at points P ₁ and P ₂ after passing through each frequency filter when the condition of FIG. 8B is satisfied. FIG. 8E is a diagram illustrating voltage waveforms at points P ₁ and P ₂ after passing through each frequency filter when the condition of FIG. 8A is satisfied. FIG. 8F is a diagram illustrating voltage waveforms at points P ₁ and P ₂ after passing through each frequency filter when the condition of FIG. 8B is satisfied. FIG. 8 is a diagram illustrating an example of a second embodiment of the present invention. FIG. 10 is a diagram for explaining a second embodiment of the present invention in FIG. 9 as a simplified equivalent circuit. FIG. 9 is a diagram illustrating a specific example of Embodiment 2 of the present invention. FIG. 11A is a diagram illustrating a specific example using a low-pass filter including a resistor and a capacitor. FIG. 11B is a diagram illustrating a specific example using a low-pass filter composed of a thin film transistor. FIG. 11C illustrates a specific example using a low-pass filter including an operational amplifier, a capacitor, and a resistor. FIG. 13 is a diagram illustrating an example of a third embodiment of the present invention. FIG. 13 is a diagram illustrating an example of a driving method according to a third embodiment in FIG. 12. FIG. 14 is a diagram illustrating an example of a fourth embodiment of the present invention. FIG. 14 is a diagram illustrating an example of a fourth embodiment of the present invention. FIG. 14 is a diagram illustrating an example of a driving method according to a fourth embodiment of the present invention.

Explanation of reference numerals

201 ... source line driver circuit 202 ... gate line driver circuit 203 ... pixel matrix 204 ... transparent insulating substrate 205 ... TFT 206 ... liquid crystal cell _{X 1, X 2, X 3} · · source lines _{Y 1, Y 2, Y 3} ··· gate lines 301 ... source line driver circuit 302 ... gate line driver circuit 303 ... pixel matrix 304 ... X-side shift register 305 .. · X side buffer 306 ··· video signal lines 307 and 307 '· · · analog switches 308 and 308' ··· source line 309 ··· Y side shift register 310 ··· Y side buffer 311 and 311 '··· -Gate lines 312, 312 '... Thin-film transistors 313, 313' ... Liquid crystal cell 331 ... Defined by clock CLX Clocked inverter 332: Clocked inverter specified by clock CLX * 333: Inverter 334: Basic cell of X-side shift register 335: Clocked inverter 336 specified by clock CLY Clocked inverter 337 ・ ・ ・ Inverter 338 ・ ・ ・ NOR logic gate 339 ・ ・ ・ Basic cell of Y-side shift register 341 ・ ・ ・ Start pulse input terminal of X-side shift register 342 ・ ・ ・Start pulse input terminal 344 for Y-side shift register Video signal input terminal CLX, CLX * Clock CLX and clock CLX *
CLY, CLY * ... clock CLY and clock CLY *
P ₁ , P ₂ ... Point P ₁ and points P ₂ Q ₁ , Q ₂ ... In the equivalent circuit of FIG. 2 Points Q ₁ and Q ₂ R ₁ , R _2. Point R in the equivalent circuit of FIG.
₁ and point R ₂ V ₁ ... Point V _{1 in} the equivalent circuit of FIG.
P ₁ , P ₂ ... Point P ₁ and points P ₂ Q ₁ , Q ₂ ... In the equivalent circuit of FIG. 2 Points Q ₁ and Q ₂ R ₁ , R _2. Point R 401 in the equivalent circuit of FIG. 2... Voltage waveform at point P1 in FIG. 2 402... Voltage waveform at point P2 in FIG. 2 403... Voltage waveform at point Q1 in FIG. The voltage waveform 405 at the point Q2 in FIG. 2 405 The voltage waveform 406 at the point V1 in FIG. 2 407 The voltage waveform 407 at the point R1 in FIG. 2 408 ··· Video center 411 ··· Voltage waveform of clock CLY in FIG. 2 412 ··· Voltage waveform of clock CLX in FIG. 2 501 and 501 ′ ··· Pixel transistor 502 ··· Gate selection pulse 503 ··· Gate Lines 504, 504 ': Liquid crystal cell 505, 505': Gate line 5 ... First low-pass filter 509... Second low-pass filter 510... First delay pulse 511. 2 delayed pulses C ₁ , C ₂ , G ₁ , G ₂ ... Points C ₁ , C ₂ , G ₁ , G ₂ 601... Time axis 602... Gate selection pulse in the equivalent circuit diagram of FIG. .. 603... Liquid crystal application voltage 611... Ideally there is no delay in gate selection pulse 612 ・ ・ ・ gate selection pulse at point G ₁ in FIG. 4 613 ・ ・ ・ gate selection pulse at point G ₂ in FIG. 621... Liquid crystal applied voltage waveform when a gate selection pulse without ideal delay is input 622... Liquid crystal applied voltage waveform at point C ₁ in FIG. 4 623 ・ ・ ・ at point C ₂ in FIG. Liquid crystal applied voltage waveform 701 ··· Gate line driving circuit 702 ··· Latch signal for driving final inverter 703 of gate line driving circuit 701 ··· Final inverter for directly driving gate line 704 of gate line driving circuit 701 ··· Gate line 705 ... Pixels 705 ′ closest to the gate line driving circuit 701. Pixels 706, 706 ′ farthest from the gate line driving circuit 701. Pixel transistors 707... Gate lines between the pixels 705 and 705 ′. capacitance and resistance V _dd · · · positive supply voltage parasitic distributed constant shape in R _N, R _P · · · N-type constituting the final inverter 703, the resistance I _P of the P-type thin film transistor, I _N · · · last inverter Current flowing in N-type and P-type thin film transistors constituting 703 GND: ground power supply 801, 802: low-pass filter Motor 803,803 '... high-pass filter 804 output signal of the last inverter ... gate line driving circuit 901 ... frequency axis 902 ... Axis 903 ... point P which represents the gain of each frequency filter _1, the frequency characteristic 907 of the low-pass filter 801 of the voltage waveform 906 ... 7 in the axial 904 ... time representing the gain of the signal at the point P ₂ axes 905 ... point P _1, the point P ₂・ ・ ・ ・ ・ ・ Frequency characteristics of the low-pass filter 802 in FIG. 7 908 ・ ・ ・ ・ ・ ・ frequency characteristics of the high-pass filters 803 and 803 ′ in FIG. 909 ・ ・ ・ frequency characteristics at point P ₁ 910 ・ ・ ・ point P ₂ voltage waveform 912 voltage waveform 121 ... gate line driving circuit at the ... point P ₂ 122, ... of the gate line 125 directly of the gate line driving circuit 122 in the frequency characteristic 911 ... point P ₁ in Last inverter to be driven 123... Newly provided low-pass filters 124 and 124 ′. First pixel, second pixel 125... Gate lines 141 and 142... Low-pass filter 143. A synthesis filter 144, 144 ′, which is a combination of the low-pass filter 141 and the low-pass filter 142, and a high-pass filter 145, a low-pass filter 146, an output signal 161, of the final inverter; 162, 163 gate line drive circuit 164 low-pass filter composed of capacitance and resistance 165 low-pass filter composed of P-type thin film transistor 166 operational amplifier, capacitance and resistance 167, 168, 169 ... Pixel matrix 181 ... Gate line drive Circuit 182 ... final inverter of the output signal 183 ... gate lines 184 ... pixel matrix 185, ... N-type thin film transistor using resistance modulation circuit 186 ... resistor modulation source 187 ... signal line P _31, at _{P 32, P 33, P 34} ··· point _{P 31, P 32, P 33} , P 34 221 point P ₃₂ of the voltage waveform 222 ... 12 at a point P ₃₁ of ... 12 voltage waveform 225 ... gate line selection period at the point P ₃₄ of the voltage waveform 224 ... 12 at a point P ₃₃ of the voltage waveform 223 ... 12 226 ... video signal input period 241 .. A gate line driving circuit 242 shift register 243 delay circuit 244 logical operation circuit 245 switch 246 for controlling the conduction between the power supply line 249 and the gate line 246 power supply 250 and the power supply line of the switch 248 ... pixel matrix 249 ... voltage V _dd of controlling electrical continuity between the switch 247 ... power supply line 251 and the gate line for controlling the conduction state between the gate line 250 ... power supply line of voltage V _ss 251 ... power supply line of voltage V _rr 252 ... voltage source of voltage V _dd 253 ... voltage source of voltage V _ss 254 ... voltage source of voltage V _rr 261, a gate line drive circuit 262, a pixel matrix 263, a delay circuit 264, 264 ', an EXOR gate 265, a NAND gate 266, an N-type thin film transistor 267, a P-type thin film transistor 268 ... shift registers 269 ... power supply line 270 ... gate lines _{P 41, P 42, P 43} , P 44, P 45, P 46, P 47, P 48 · · Equivalent points of the circuit, the point P _41, the point P _42, the point P _43, the point P _44, the point P _45, the point P _46, the point P _47, at a point P ₄₁ of the point P ₄₈ 281 · · · 15 Voltage waveform 282… Voltage waveform at point P ₄₂ in FIG. 15 283… Voltage waveform at point P ₄₃ in FIG. 15 284… Voltage waveform at point P ₄₄ in FIG. The voltage waveform at the point P ₄₅ 286 ・ ・ ・ The voltage waveform at the point P ₄₆ in FIG. 15 287 ・ ・ ・ The voltage waveform at the point P ₄₇ in FIG.

Claims (2)

An active matrix liquid crystal display device having a plurality of gate lines and a plurality of source lines, and a plurality of pixels formed corresponding to intersections of the gate lines and the source lines,
A gate line drive circuit that drives each of the gate lines includes an inverter,
A second voltage of the inverter when the gate line is in a non-selection state, with respect to a current flowing between the first voltage source of the inverter when the gate line is in the selected state and the gate line. A current flowing between the source and the gate line, and
A resistance R between the second voltage source and the gate line when the gate line is in a non-selected state, a total capacitance C parasitic to the inverter, a pixel closest to the gate line driving circuit, Between the cutoff frequency f _L2 when the parasitic capacitance and the parasitic resistance existing in the form of a distributed constant in the gate line between the distant pixel and the gate line are equivalently represented as a second low-pass filter;
An active matrix type liquid crystal characterized in that a relationship of R> 1 / (2π × C × f _L2 ) or a relationship of R and 1 / (2π × C × f _L2 ) is substantially the same. Display device. The inverter is a complementary inverter,
When an N-type transistor is used as a switching element of each pixel,
The complementary inverter is configured such that the ON current in the linear region of the N-type transistor is smaller than the ON current in the linear region of the P-type transistor forming the complementary inverter,
When a P-type transistor is used as a pixel switching element,
Configuring the complementary inverter such that the ON current in the linear region of the P-type transistor is smaller than the ON current in the linear region of the N-type transistor forming the complementary inverter;
The active matrix type liquid crystal display device according to claim 1, wherein:

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