JP3858932B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to an active matrix liquid crystal device using a thin film transistor or the like as a switching element and a driving method of the liquid crystal device.

  2. Description of the Related Art Conventionally, liquid crystal display devices that display visual information using the electro-optical characteristics of liquid crystals have been used in a wide variety of applications such as computer image output devices, portable televisions, video projectors, and video camera viewfinders.

Among these liquid crystal display devices, the circuit configuration of an active matrix type liquid crystal display device using thin film transistors as active elements includes a source line driver circuit 201 and a gate line driver circuit 202, as shown in a block diagram in FIG. The pixel matrix 203 is formed on the same transparent insulating substrate 204.
Among them, the pixel matrix 203 includes a plurality of source lines X ₁ , X ₂ , X ₃ ... Connected to the source line drive circuit 201 and a plurality of gate lines Y ₁ , Y connected to the gate line drive circuit 202. ₂ , Y ₃ ... And a plurality of pixels P ₁₁ , P ₁₂ ... Formed at the intersections of these gate lines and source lines, and each pixel P ₁₁ , P ₁₂ . Has a thin film transistor 205 and a liquid crystal cell 206.

  An equivalent circuit configuration of the liquid crystal display device having the above configuration will be described with reference to FIG. FIG. 2 is a diagram illustrating an equivalent circuit configuration of an active matrix liquid crystal display device. The equivalent circuit is roughly divided into a source line driver circuit 301, a gate line driver circuit 302, and a pixel matrix 303. The source line driving circuit 301 is applied to an X-side shift register 304 for sending out a latch signal in time series, a buffer 305 for amplifying and harmonizing the latch signal, and a video signal line 306. It comprises analog switches 307 and 307 ′ for sampling and holding the video signal on the source lines 308 and 308 ′ in accordance with the latch signal sent from the buffer 305. Here, the X-side shift register 304 is configured with a basic cell 334 including a clocked inverter 331 defined by a clock CLX, a clocked inverter 332 defined by a clock CLX *, and an inverter 333 as a unit. .

  On the other hand, the gate line driving circuit 302 amplifies and waves the Y-side shift register 309 for sending the latch signal in time series, and sends the latch signal to the gate lines 311 and 311 ′. And a buffer 310. Here, the Y-side shift register 309 includes a basic cell 339 including a clocked inverter 335 defined by the clock CLY, a clocked inverter 336 defined by the clock CLY *, an inverter 337, and a NOR gate 338. Configured.

  The pixel matrix 303 includes thin film transistors 312, 312 ′ and liquid crystal cells 313, 313 ′ connected to the source lines 308, 308 ′ and gate lines 311, 311 ′. It consists of.

Next, an example of a method for driving the liquid crystal display device shown in the equivalent circuit diagram of FIG. 2 will be described with reference to FIGS. FIG. 3 shows the voltages at points P ₁ , P ₂ , Q ₁ , Q ₂ , R ₁ , R ₂ , and V ₁ in FIG. 2 in time series. CLX represents the clock of the X-side shift register, and has a phase relationship opposite to that of CLX *. Similarly, CLY represents the clock of the Y-side shift register, and has a reverse phase relationship with CLY *. Here, CLX * and CLY * are not shown.

The driving method will be described in order. First, the Y-side shift register 309 outputs a pulse having a width of ½ of the cycle of the clocks CLY and CLY * to the buffer 310 in accordance with the timing of the clocks CLY and CLY *. To do. The buffer 310 amplifies and waves the pulse and outputs a gate selection pulse 401 to the gate line 311 (P ₁ ). While the gate selection pulse 401 is at the selection level, the plurality of thin film transistors 312 and 312 ′ connected to the gate line 311 are in a conductive state and connected to the plurality of thin film transistors 312 and 312 ′ connected to the gate line 311. The source lines 303 and 303 ′ and the liquid crystal cells 313 and 313 ′ are electrically connected. At this time, the X-side shift register 304 outputs a pulse having the same width as the clock cycle to the buffer 305 in accordance with the timing of the clocks CLX and CLX *. The pulse is amplified and harmonized, and a sample and hold signal 403 is output to the analog switch 307 (Q ₁ ). The analog switch 307 outputs the video signal 405 of the video signal line 306 (V ₁ ) according to the pulse. Sample and hold the source line 308 (R ₁ ). At this time, as described above, since the plurality of thin film transistors 312 connected to the gate line 311 are in a conductive state, a signal held in the source line 308 is written in the liquid crystal cell 313. Similarly, the analog switch 307 ′ samples and holds the video signal 405 on the source line 308 ′. As a result, a sampled and held signal is written to the source line 308 ′ in the liquid crystal cell 313 ′. By repeating this on the source line driver circuit 301 side, the video signal 405 can be written into the liquid crystal cells of a plurality of pixels connected to the gate line 311.

  Next, after the gate selection pulse 401 becomes a non-selection level, the gate selection pulse 402 is output from the gate line driving circuit 302. When the source line driving circuit 301 is driven in the same manner as described above while the gate selection pulse 402 is at the selection level, the video signal 405 is supplied to the liquid crystal cells of a plurality of pixels connected to the gate line 311 ′. Can write.

  By repeating the above operations, it becomes possible to write a video signal in units of liquid crystal cells of each pixel, and an image is obtained by changing the polarization state of each liquid crystal cell according to the signal written to the liquid crystal cell. be able to.

  In the above active matrix liquid crystal display device, it is known that flicker occurs on the display screen when the delay of the gate line is relatively large. This is a phenomenon that is visually recognized as a difference in transmittance of the liquid crystal cell because there is a liquid crystal cell in which the average value of the voltage applied to the liquid crystal is not zero. This flicker not only degrades the display quality, but also has a deep relationship with liquid crystal burn-in. In general, liquid crystals need to be driven with alternating current. When the average value of the AC waveform does not become zero, that is, a direct current is applied to the liquid crystal, which causes liquid crystal burn-in. That is, the occurrence of flicker on the display screen means that liquid crystal burn-in easily occurs.

The reason why a liquid crystal cell in which the average value of the voltage applied to the liquid crystal does not become zero will be described below with reference to FIGS. Here, a case where N-type thin film transistors are used for the pixel transistors 501 and 501 ′ will be described. For simplification of description, when the source lines 506 and 506 ′ are grounded and no voltage is applied to the liquid crystal cell of the pixel, that is, the points C ₁ and C ₂ are equal to the ground level. Assuming that

First, a phenomenon in which the voltage applied to the liquid crystal decreases at the end of the selection period of the gate selection pulse, so-called punch-through voltage, will be described. This punch-through voltage means that at the moment when a gate selection pulse 502 applied to a certain gate line 503 changes from a voltage level at which the pixel transistors 501 and 501 ′ are in a conductive state to a voltage level at which the pixel transistors 501 and 501 ′ are in an insulating state. This is the voltage at which the electric charge written in the pixel electrode escapes due to the coupling capacitances 505 and 505 ′ between the liquid crystal cells 504 and 504 ′, and the voltage applied to the liquid crystal decreases. Here, the coupling capacitors 505 and 505 ′ mainly include capacitance components C _gd between the gate electrodes of the pixel transistors 501 and 501 ′ and the drain electrodes connected to the pixel electrodes of the liquid crystal cells 504 and 504 ′. The pixel electrode of the liquid crystal cells 504 and 504 ′ and a parallel capacitance component C _gd ′ between the gate line 503 and the liquid crystal cells 504 and 504 ′. Among these, the capacitance component C _gd varies depending on the voltage V _gd applied between the gate electrode and the drain electrode, and in the case of FIG. 4, it is applied between the gate electrode and the drain electrode. As the voltage V _gd increases, the capacitance component C _gd increases.

  At this time, if a gate selection pulse without an ideal delay is input to the pixel transistor, the punch-through voltage ΔV can be expressed by Equation 1.

Here, C _all represents all capacitance components electrically connected to the pixel electrode. The transient response of the applied voltage of the liquid crystal in an ideal state without delay will be described with reference to FIG. In FIG. 5, the vertical axis represents voltage and the horizontal axis represents time. When the gate selection pulse 611 having ideal delay according to Equation 1 is input, the voltage applied to the liquid crystal exhibits a transient response represented by a curve 621. The punch-through voltage at this time is ΔV.

However, in practice, the gate selection pulse is delayed due to the resistance of the gate line and the capacitance associated with the gate line, and V _gd and C _{gd in} Equation 1 change in time series according to the delayed gate selection pulse. Therefore, the amount of punch-through voltage varies depending on the degree of delay of the gate selection pulse. Hereinafter, a process in which a difference occurs in the penetration voltage ΔV depending on the degree of delay will be described in detail. First, when the gate selection pulse 502 is input to the gate line 503, it passes through the first low-pass filter 508 equivalently expressed by the resistance of the gate line 503 and the capacitance parasitic on the gate line 503. The first delay pulse 510 is input to the pixel transistor 501 (point G ₁ ). At this time, a high-pass filter is formed by the coupling capacitance 505 between the point G ₁ and the point C ₂ and the resistance between the source and drain of the pixel transistor. In the high-pass filter, since the coupling capacitor 505 and the resistance of the pixel transistor change in time series with the waveform of the gate selection pulse, the cutoff frequency inevitably changes in time series. At this time, the first delayed pulse passes through the first low-pass filter 508 so that the high-frequency component present in the ideal gate selection pulse is blocked. As a result, punch-through voltage △ V ₁ at point C ₁ is less than the punch-through voltage △ V at no gate selection pulse delay described above. The state of the transient response at this time will be schematically described with reference to FIG. Curve 612 represents the first delayed pulse input at point G ₁ and curve 622 represents the voltage transient response at point C ₁ , ie, the voltage applied to the liquid crystal.

Similarly, a second delay pulse 511 is input to the gate electrode (point G ₂ ) of the pixel transistor 501 ′ through the first low-pass filter 508 and the second low-pass filter 509. The At this time, in the second delayed pulse 511, the high-frequency component that exists even in the first delayed pulse 510 is blocked by the passage of the second low-pass filter 509, and thus the punch-through voltage ΔV _2. Is still smaller than ΔV ₁ . The state of the transient response at this time will be schematically described using FIG. Curve 613 represents the second delayed pulse input at point G ₂ , and curve 623 represents the voltage transient response at point C ₂ , that is, the voltage applied to the liquid crystal.

  As a result, the penetration voltage is non-uniform in a plurality of pixels connected to a certain gate line, and the average value of the voltage applied to the liquid crystal is not constant. For this reason, it becomes impossible to make all the average values of the voltages applied to the liquid crystal zero, and pixels where the average value of the applied voltages is not zero are visually recognized as flicker. Actually, it is known that flicker is not visually recognized if the average value of the liquid crystal applied voltage is so small that it cannot be visually recognized as a difference in transmittance of the liquid crystal cell.

  Therefore, in order not to make flicker visible, the delay of the gate line is reduced, that is, the pass band of the low pass filter parasitic to the gate line is shifted to the high frequency side, and the high frequency component passing through the low pass filter is reduced. It is necessary to increase and reduce the difference in punch-through voltage. As this method, a method of reducing the resistance of the gate line and a method of reducing the parasitic capacitance in the gate line can be easily considered. In the former method, there is a method of changing the material of the gate line to a low resistance material such as a metal thin film in a process, but there are many methods that cannot be practically applied because the process is often complicated. The latter method can increase the thickness of the insulating film on the gate line, change the insulating film on the gate line to one with a low relative dielectric constant, change the layout to reduce the parasitic capacitance on the gate line, etc. Actually, the parasitic capacitance of the gate line tends to increase as the definition of the liquid crystal display device increases, and it is extremely difficult to reduce the parasitic capacitance of the gate line while maintaining the definition. Therefore, it can be said that the method of reducing the delay of these gate lines is clearly effective but not easy to realize.

  In addition, in order not to make flicker visible, a method of reducing the relative difference of the punch-through voltage by reducing the absolute value of the punch-through voltage can be considered. Specifically, the gate line driving circuit is used to reduce the parasitic capacitance component between the gate electrode of each pixel and the drain electrode connected to the pixel electrode, or to change the gate line from a selected state to a non-selected state. A method of reducing the wave height of the voltage waveform applied to the gate line by reducing the power supply voltage of the device itself can be considered. The former method cannot be solved only by design contrivance in view of the fact that the capacitive component generally tends to increase extremely as the pixel becomes higher in definition. On the other hand, the latter method can surely reduce the difference in the penetration voltage, but the current consumption increases correspondingly because charging and discharging are repeated for all the capacitances parasitic on the power supply of the gate line driving circuit. Has the disadvantages.

  Therefore, in the present invention, a method for solving the above-described problems by a design and driving method and obtaining a liquid crystal display device without flicker will be described.

  In the liquid crystal device of the present invention, a plurality of gate lines, a plurality of source lines, a plurality of pixels formed corresponding to intersections of the gate lines and the source lines, and the gate lines are selected. Or a gate line driving circuit for supplying a non-selection signal for deselecting each of the gate lines, wherein the gate line driving circuit includes the selection circuit. A shift register for generating a signal or the non-selection signal, and a transistor provided between the shift register and each of the gate lines. The transistor has a resistance modulation signal input to a gate electrode of the transistor. As a result, the resistance value between the shift register and each gate line when the gate line is changed from the selected state to the non-selected state is selected. Characterized in that it is controlled to be higher than the resistance value in the state.

  The liquid crystal device of the present invention is the above-described liquid crystal device, wherein the gate line driving circuit includes a shift register that generates the selection signal or the non-selection signal, and the high-frequency component reduction unit includes the shift It is a low-pass filter provided between a register and each gate line.

  The liquid crystal device of the present invention is the above-described liquid crystal device, wherein the gate line driving circuit includes a shift register that generates the selection signal or the non-selection signal, and the high-frequency component reduction unit includes the shift It is a resistance modulation circuit provided between a register and each gate line, the resistance value of which is controlled by a resistance modulation signal when each gate line is changed from a selected state to a non-selected state.

  The liquid crystal device according to the present invention is the above-described liquid crystal device, wherein the resistance modulation circuit is a transistor provided between the shift register and each gate line, and the resistance modulation signal is a gate electrode of the transistor. It is characterized by being input to.

  The liquid crystal device according to the present invention is the above-described liquid crystal device, wherein the high-frequency component reducing unit changes the gate line to the gate line when the gate line is changed from the selected state to the non-selected state. It is a potential applying means for making the potential lower than the selected potential for making the selected state and higher than the unselected potential for making each of the gate lines unselected.

  The liquid crystal device of the present invention is the above-described liquid crystal device, wherein the gate line driving circuit includes a shift register that generates the selection signal or the non-selection signal, a delay unit that delays an output of the shift register, A logic operation circuit to which an output of the shift register, an output of the delay means, and an output of the next stage of the shift register are input, and a first power supply to which a selection potential for setting each gate line to a selected state is applied A line, a second power supply line to which a non-selection potential that makes each gate line non-selection is applied, and a selection potential that makes each gate line select state and is non-selection A third power supply line to which a potential higher than a non-selection potential to be set is applied, and an output of the logic operation circuit, the first power supply line, the second power supply line, and the third power supply line One of the exclusive And having a power switch for selecting the.

  The liquid crystal device of the present invention is the above-described liquid crystal device, wherein the gate line driving circuit includes a shift register that generates the selection signal or the non-selection signal, a delay unit that delays an output of the shift register, The output of the shift register, the EXOR circuit to which the output of the delay means is input, the output of the EXOR circuit, the NAND circuit to which the output of the EXOR circuit in the next stage is input, and the gate lines are selected. A power line applied with a potential lower than a selected potential and higher than a non-selected potential that makes each gate line in a non-selected state, and controlled by the output of the NAND circuit, and the output of the power line and the delay circuit A circuit for connecting one of the gate lines to each of the gate lines.

  The liquid crystal device driving method of the present invention includes a plurality of gate lines and a plurality of source lines, a plurality of pixels formed corresponding to intersections of the gate lines and the source lines, and the gate lines. A driving method of an active matrix type liquid crystal device having a selection signal for selecting a state or a gate line driving circuit for supplying a non-selection signal for deselecting each of the gate lines. When changing from the selected state to the non-selected state, the potential change of the gate line is moderated.

  The liquid crystal device driving method of the present invention includes a plurality of gate lines and a plurality of source lines, a plurality of pixels formed corresponding to intersections of the gate lines and the source lines, and the gate lines. A driving method of an active matrix type liquid crystal device having a selection signal for selecting a state or a gate line driving circuit for supplying a non-selection signal for deselecting each of the gate lines. When switching from the selected state to the non-selected state, each gate line is set to a potential lower than the selected potential for setting each gate line to the selected state and higher than the non-selected potential for setting each gate line to the non-selected state. The non-selected state is set later.

The liquid crystal device according to the present invention is an active matrix type liquid crystal device having a plurality of gate lines and source lines, and the inverter that drives the gate lines selects the first of the inverters when the gate lines are selected. A current flowing between the second voltage source of the inverter and the gate line when the gate line is set to a non-selected state is reduced with respect to a current flowing between the voltage source and the gate line. Is constructed. In the above liquid crystal device, the cut-off frequency f _L1 when the inverter is equivalently expressed as a first low-pass filter, and the gate line between the pixel closest to the gate line driving circuit and the pixel farthest from the gate line driving circuit. The cutoff frequency f _L2 when the parasitic capacitance and parasitic resistance existing in a distributed constant form are equivalently expressed as the second low-pass filter, and the pixel is equivalently expressed as the first high-pass filter It is preferable that the relationship of f _H <f _L2 <f _L1 does not hold between the cutoff frequency f _H of the two. In the above liquid crystal device, the cut-off frequency f _L1 when the inverter is equivalently expressed as a first low-pass filter, and the gate line between the pixel closest to the gate line driving circuit and the pixel farthest from the gate line driving circuit. The cutoff frequency f _L2 when the parasitic capacitance and parasitic resistance existing in a distributed constant form are equivalently expressed as the second low-pass filter, and the pixel is equivalently expressed as the first high-pass filter The relationship of f _H <f _L1 <f _L2 , or the relationship of f _H <f _L1 and f _L1 and f _L2 being substantially the same may be established between the cutoff frequency f _{H of} good. In the above liquid crystal device, when the resistance between the second voltage source when the gate line is brought into a non-selected state is R and the total capacitance parasitic to the inverter is C, the resistance R is expressed as R It is preferable that the relationship <1 / (2π × C × f _L2 ) does not hold. In the above liquid crystal device, when the resistance between the second voltage source when the gate line is brought into a non-selected state is R and the total capacitance parasitic to the inverter is C, the resistance R is expressed as R A relationship of> 1 / (2π × C × f _L2 ) or a relationship in which R and 1 / (2π × C × f _L2 ) are substantially the same may be established. In the above liquid crystal device, when a complementary inverter is used as the inverter and an N-type transistor is used as a switching element of the pixel, N is applied to the ON current in the linear region of the P-type transistor constituting the complementary inverter. In the case where a P-type transistor is used as a switching element of a pixel, the ON-current in the linear region of the N-type transistor constituting the complementary inverter is reduced. The complementary inverter is preferably designed so as to reduce the on-current in the linear region of the P-type transistor.

The liquid crystal device of the present invention is an active matrix type liquid crystal device having a plurality of gate lines and source lines, and includes a first low line between a gate line driving circuit and a pixel closest to the gate line driving circuit. A band-pass filter is provided. In the above liquid crystal device, the cutoff frequency f _{L3 of} the first low-pass filter and the cutoff when the inverter that drives the gate line of the gate line driving circuit is equivalently expressed as a second low-pass filter. Parasitic capacitance and parasitic resistance existing in a distributed constant form on the gate line between the frequency f _L1 and the pixel nearest to the gate line driving circuit and the farthest pixel are equivalently expressed as a third low-pass filter. F _L1 > f _L3 or f _L1 and f _L3 are substantially the same between the cut-off frequency f _L2 at the time and the cut-off frequency f _H when the pixel is equivalently represented as the second high-pass filter. In addition, it is preferable that f _L2 > f _L3 or f _L2 and f _L3 are substantially the same and the relationship f _L1 > f _L2 is established. In the above liquid crystal device, the cutoff frequency f _{L3 of} the first low-pass filter and the cutoff when the inverter that drives the gate line of the gate line driving circuit is equivalently expressed as a second low-pass filter. The frequency f _L1 and the parasitic capacitance and parasitic resistance existing in a distributed constant form on the gate line between the pixel closest to the gate line driving circuit and the pixel farthest from the gate line driving circuit are equivalently expressed as a third low-pass filter. Between the cut-off frequency f _L2 and the cut-off frequency f _H when the pixel is equivalently expressed as a second high-pass filter, there is a relationship of f _H <f _L3 <f _L2 <f _L1. It is preferable to make it hold. In the above liquid crystal device, the first low-pass filter may be composed of a capacitor and a resistor. In the above liquid crystal device, the first low-pass filter may be configured by a transistor that is always in a conductive state and a power supply line that keeps the transistor in a conductive state. In the above liquid crystal device, when an N-type transistor is used as a switching element of a pixel, it is preferable to use a P-type transistor as the transistor that is always in a conductive state. In the above liquid crystal device, when a P-type transistor is used as a switching element of a pixel, it is preferable to use an N-type transistor as the transistor that is always in a conductive state. In the above liquid crystal device, the first low-pass filter may be constituted by an active filter.

  Further, this problem can be solved by providing a resistance modulation circuit between the gate line driving circuit and the pixel closest to the gate line driving circuit, and further providing a wiring for transmitting a resistance modulation signal for controlling the resistance of the resistance modulation element. Resolve. Further, a transistor is used for the resistance modulation circuit, and the gate electrode of the transistor is connected to the wiring, and the resistance modulation signal flowing through the wiring exceeds the threshold voltage of the transistor to make the transistor conductive. Further effects can be obtained by oscillating two or more voltage states. Further, in the resistance modulation signal, when the gate line is changed from the selected state to the non-selected state, the voltage state is changed stepwise from the highest voltage state to the lowest voltage state among the two or more voltage states. Further effects can be obtained. More specifically, the output of the shift register of the gate line driving circuit, the output of the delay circuit that delays the output of the shift register for a predetermined time, and the output of the next-stage shift register, if necessary, for each gate stage. After the input to the logic operation circuit provided in the circuit, three different voltage states are exclusively selected based on the operation result of the logic operation circuit, and finally the voltage of the selected voltage state is applied to the gate line. It is characterized by doing. Further, the three different voltage states are based on the first and second voltage states applied by a positive power source and a negative power source used for driving a shift register, a logic operation circuit, a delay circuit, and the like, and the voltage of the positive power source. A further effect can be obtained by the three states of the third voltage state which is lower and higher than the voltage of the negative power source. In these, the input / output terminal of the delay circuit is connected to the input of the EXOR gate, the output terminal of the EXOR gate and the output of the EXOR gate of the next gate stage are connected to the input terminal of the NAND gate, The output terminal controls the conduction state between the gate electrode of the N-type transistor for controlling the conduction state between the output terminal of the delay circuit and the gate line, and the power supply line in the third voltage state and the gate electrode. Further effects can be obtained by connecting to the gate electrode of the P-type transistor.

  Further, a signal for controlling the delay time of the delay circuit is internally generated in the gate line driving circuit, or a signal for controlling the delay time of the delay circuit is generated outside the gate line driving circuit, and the delay circuit A new effect can be obtained by providing a signal wiring connected to and controlling the delay period of the delay circuit through the signal wiring.

  In an active matrix liquid crystal display device that employs the above means, the pixel penetration voltage can be kept constant in the screen, so that the voltage applied to the liquid crystal is constant, and the in-plane brightness depends on the location. No uniform screen can be obtained. In addition, it is possible to obtain a very high-quality image that eliminates flicker and burn-in on the display screen. As a result, defective display products related to flicker can be surely eliminated, so that the yield of the liquid crystal display device can be substantially improved and the manufacturing cost can be reduced. In addition, since the direct current component applied to the liquid crystal cell can be minimized from design measures, liquid crystal burn-in can be minimized, and a highly reliable liquid crystal display device with little time series change is provided. can do.

  Next, embodiments of the present invention will be described below.

  In the active matrix type liquid crystal display device embodying the present invention, the circuit configuration is the same as that shown in the conventional example, and therefore will be described with reference to FIGS.

FIG. 1 is a diagram for explaining the circuit configuration. In the active matrix liquid crystal display device of the present invention, the source line driver circuit 201 and the gate line driver circuit 202 and at least the pixel matrix 203 are formed on the same transparent insulating substrate 204. Among them, the pixel matrix 203 includes a plurality of source lines X ₁ , X ₂ , X ₃ ... Connected to the source line drive circuit 201 and a plurality of gate lines Y ₁ , Y connected to the gate line drive circuit 202. ₂ , Y ₃ ... And a plurality of pixels P ₁₁ , P ₁₂ ... Formed at the intersections of these gate lines and source lines, and each pixel P ₁₁ , P ₁₂ . Has a thin film transistor 205 and a liquid crystal cell 206.

  An equivalent circuit of the liquid crystal display device having the above circuit configuration will be described with reference to FIG. FIG. 2 illustrates an equivalent circuit of an active matrix liquid crystal display device. The equivalent circuit is roughly divided into a source line driver circuit 301, a gate line driver circuit 302, and a pixel matrix 303. The source line driver circuit 301 includes an X-side shift register 304 for sending out a latch signal in time series, a buffer 305 for amplifying and harmonizing the latch signal, and a video signal on the video signal line 306. It comprises analog switches 307 and 307 ′ that sample and hold the source lines 308 and 308 ′ in accordance with the latch signal sent from the buffer 305. Here, the X-side shift register 304 is configured with a basic cell 334 including a clocked inverter 331 defined by a clock CLX, a clocked inverter 332 defined by a clock CLX *, and an inverter 333 as a unit. .

  On the other hand, the gate line driving circuit 302 amplifies and waves the Y-side shift register 309 for sending the latch signal in time series, and sends the latch signal to the gate lines 311 and 311 ′. Buffer 310. Here, the Y-side shift register 309 includes a basic cell 339 including a clocked inverter 335 defined by the clock CLY, a clocked inverter 336 defined by the clock CLY *, an inverter 337, and a NOR gate 338. Configured.

  The pixel matrix 303 includes thin film transistors 312 and 312 ′ connected to the source lines 308 and 308 ′ and gate lines 311 and 311 ′ and liquid crystal cells 313 and 313 ′.

Next, an example of a method for driving the liquid crystal display device shown in the equivalent circuit diagram of FIG. 2 will be described with reference to FIGS. FIG. 3 shows the voltages at points P ₁ , P ₂ , Q ₁ , Q ₂ , R ₁ , R ₂ , and V ₁ in FIG. 2 in time series. CLX represents the clock of the X-side shift register, and has a phase relationship opposite to that of CLX *. Similarly, CLY represents the clock of the Y-side shift register, and has a reverse phase relationship with CLY *. Here, CLX * and CLY * are not shown.

The driving method will be described in order. First, the Y-side shift register 309 outputs a pulse having a width of ½ of the cycle of the clocks CLY and CLY * to the buffer 310 in accordance with the timing of the clocks CLY and CLY *. To do. The buffer 310 amplifies and waves the pulse and outputs a gate selection pulse 401 to the gate line 311 (P ₁ ). While the gate selection pulse 401 is at the selection level, the plurality of thin film transistors 312 and 312 ′ connected to the gate line 311 are in a conductive state and connected to the plurality of thin film transistors 312 and 312 ′ connected to the gate line 311. The source line 303 and the liquid crystal cell 313, and the gate line 303 ′ and the liquid crystal cell 313 ′ are electrically connected. At this time, the X-side shift register 304 outputs a pulse having the same width as the clock cycle to the buffer 305 in accordance with the timing of the clocks CLX and CLX *. The pulse is amplified and harmonized, and a sample and hold signal 403 is output to the analog switch 307 (Q ₁ ). The analog switch 307 outputs the video signal 405 of the video signal line 306 (V ₁ ) according to the pulse. Sample and hold the source line 308 (R ₁ ). At this time, as described above, since the plurality of thin film transistors 312 connected to the gate line 311 are in a conductive state, a signal held in the source line 308 is written in the liquid crystal cell 313. Similarly, the analog switch 307 ′ samples and holds the video signal 405 on the source line 308 ′. As a result, a sampled and held signal is written to the source line 308 ′ in the liquid crystal cell 313 ′. By repeating this on the source line driver circuit 301 side, the video signal 405 can be written into the liquid crystal cells of a plurality of pixels connected to the gate line 311.

  Next, after the gate selection pulse 401 becomes a non-selection level, the gate selection pulse 402 is output from the gate line driving circuit 302. When the source line driving circuit 301 is driven in the same manner as described above while the gate selection pulse 402 is at the selection level, the video signal 405 is supplied to the liquid crystal cells of a plurality of pixels connected to the gate line 311 ′. Can write.

  By repeating the above operations, it becomes possible to write a video signal in units of liquid crystal cells of each pixel, and an image can be obtained by changing the polarization state of each liquid crystal cell according to the signal written to the liquid crystal cell. Can do.

  As described above, in the active matrix liquid crystal display device having the above-described configuration, the cause of flickering on the display screen is that the punch-through voltage cannot be made constant in the plane. In a liquid crystal display device in which flicker is visually recognized, the penetration voltage is the highest in the liquid crystal cell of the pixel closest to the gate line driving circuit, and the penetration voltage is the lowest in the liquid crystal cell of the pixel farthest from the gate line driving circuit. Yes. If the difference in the penetration voltage is recognized as flicker when it is large enough to be recognized as a difference in transmittance of the liquid crystal cell, the difference in the penetration voltage may be reduced to such an extent that the flicker cannot be visually recognized. It will be. That is, it is possible to make the punch-through voltage constant by increasing the punch-through voltage in a pixel with a low punch-through voltage, or by reducing the punch-out voltage in a pixel with a high punch-through voltage.

  In the first embodiment, a method of obtaining a flicker-free liquid crystal display device by limiting the resistance of an inverter that directly drives the gate line of the gate line driving circuit when the gate line is shifted from the selected state to the non-selected state. Will be described.

  FIG. 6 is an equivalent circuit diagram in which the gate line driving circuit and the pixel matrix of the liquid crystal display device using the first embodiment are extracted for a single gate line.

Here, the operation of the gate line driving circuit will be described by focusing on the operation of the inverter that directly drives the gate line. Here, it is assumed that the gate line 704 is currently in a non-selected state and immediately before shifting to the selected state. First, the inverter 703 outputs a signal for selecting the gate line 704 by the latch signal 702 output from the shift register portion of the gate line driver circuit 701. Hereinafter, the selected state refers to a state in which the gate line 704 is applied to a voltage that makes the thin film transistors 706 and 706 ′ connected to the gate line 704 conductive. At this time, if the resistance of the P-type thin film transistor of the inverter 703 is R _P , and the resistance of the N-type thin film transistor is R _N , the relationship of R _N >> R _P is established, and the inverter 703 receives the P-type thin film transistor from the power supply wiring V _dd. Thus, a current I _P that charges the gate line 704 flows. Next, in response to the latch signal 702, the inverter 703 outputs a signal for making the gate line non-selected. Hereinafter, the non-selected state refers to a state in which the gate line 704 is applied to a voltage that turns off the thin film transistors 706 and 706 ′ connected to the gate line 704. In this case, the thin film transistor of the resistance of the inverter 703 R _P >> R _N relationship holds is, current in inverter 703 to release the charge stored in the gate line 704 to the ground line GND via the N-type thin film transistor I _N flows. The gate line 704 in the non-selected state in this way receives the latch signal 702 output from the shift register portion of the gate line driver circuit 701 and holds the non-selected state until it is again selected.

In the first embodiment, the gate line driving circuit for the above operation, by limiting the resistance R _N of the N-type thin film transistor in a non-selected state in conditions described below, a penetration voltage previously described by each pixel Can be constant.

First, when there is a first pixel 705 closest to the gate line driving circuit 701 and a second pixel 705 ′ farthest from the gate line driving circuit 701, a gate existing in a distributed constant type between the first pixel 705 and the second pixel 705 ′. It is assumed that the resistance of the line 704 and the capacitance parasitic on the gate line 704 are equivalently represented as a low-pass filter 707 having a cutoff frequency f _L2 . Further, the inverter 703 in the non-selected state, and the resistance R _N of the capacitor C _INV and N-type thin film transistor parasitic on the inverter 703, and shall be expressed as a low-pass filter equivalently cutoff frequency f _L1 . Further, the first pixel 705 is equivalently equivalent to a high-pass filter 148 having a cutoff frequency f _H composed of the resistance of the thin film transistor 706 and the capacitance between the drain electrode connected to the pixel electrode of the thin film transistor 706 and the gate electrode. Similarly, it is assumed that the second pixel 705 ′ can be equivalently represented as a high-pass filter 148 ′ having a cutoff frequency f _H.

If the equivalent circuit diagram of FIG. 6 is further simplified using these filters, the equivalent circuit diagram shown in FIG. 7 can be substituted. In FIG. 7, a low-pass filter 801 having a cutoff frequency f _L1 represents the inverter 703 equivalently, and a high-pass filter 803 having a cutoff frequency f _H equivalently represents the first pixel 705, and similarly the cutoff frequency f _{The H} high-pass filter 804 equivalently represents the second pixel 705 '. The low-pass filter 802 having the cutoff frequency f _L2 is the distributed constant type low-pass filter 707 between the first pixel 705 and the second pixel 705 ′ described above. An output signal of the inverter 703 input to the circuit represented by each of these filters is represented as a signal source 804.

In the first embodiment, when the relationship of f _L1> f _H and f _L2> f _H is made up in this equivalent circuit, the cutoff frequency f _L2 of the cut-off frequency f _L1 of the low-pass filter 801 low-pass filter 802 the f _L1 ≒ f _L2 becomes so relationship is established or f _L1 <way relationship f _L2 is established, or at least f _L1 >> low pass filter 801 of the inverter 703 so as not to f _L2,, between the design.

Hereinafter, the meaning of f _L1 ≈f _L2 > f _H will be described with reference to FIG. FIG. 8A shows the frequency characteristics of the filters when the conventional relationship of f _L1 > f _L2 > f _H is established, and FIG. 8B shows f _L1 ≈f _L2 > f _{H of the} first embodiment. Represents the frequency characteristics of each filter when the above relationship holds. FIG. 8C shows frequency characteristics at points P ₃₁ and P ₃₂ in FIG. 7 when the conventional relationship of f _L1 > f _L2 > f _H is established, and FIG. 8D shows the first embodiment. 7 represents frequency characteristics at points P ₃₁ and P ₃₂ in FIG. 7 when the relationship of f _L1 ≈f _L2 > f _H is established. In FIGS. 8A to 8D, the vertical axis represents the amplification factor as a dB value, and the horizontal axis represents the frequency. Further, FIG. 8E shows voltage waveforms and punch-through voltages ΔV ₁ and ΔV ₂ at points P ₃₁ and P ₃₂ in FIG. 7 when the conventional relationship of f _L1 > f _L2 > f _H is established. FIG. 8F shows voltage waveforms at the points P ₃₁ and P ₃₂ in FIG. 7 and punch-through voltages ΔV ₁ ′ and ΔV ₂ ′ when the relationship of f _L1 ≈f _L2 > f _{H in} the first embodiment is satisfied. Represents. 8 (e) and 8 (f), the vertical axis represents voltage and the horizontal axis represents time. As shown in FIG. 8A, when the conventional relationship of f _L1 > f _L2 > f _H is established between the filters, the point P ₃₁ that has passed through the low-pass filter 801 and the high-pass filter 803. If, when comparing the frequency characteristics in the low-pass filter 801 and the low-pass filter 802 and the high-pass filter 803 'and P ₃₂ that has passed through, at P _31, as shown in FIG. 8 (c) The pass frequency band of P ₃₂ becomes narrower than the pass frequency band, so that the punch-through voltage ΔV ₁ at P ₃₁ is larger than the punch-through voltage ΔV ₂ at P ₃₂ as shown in FIG. When the difference between ΔV ₁ and ΔV ₂ is visually recognized as a difference in liquid crystal transmittance of the pixel portion, flicker is visually recognized on the screen of the liquid crystal display device. On the other hand, when the relationship of f _L1 ≈f _L2 > f _H is established between the filters as shown in FIG. 8B, the frequency characteristics at P ₂₁ and P ₂₂ are compared with each other in FIG. As shown in FIG. 8C, the difference between the pass frequency bands is smaller than that in FIG. 8C. Therefore, as shown in FIG. 8F, the difference between the penetration voltages ΔV ₁ ′ and ΔV ₂ ′ is reduced. . When the difference between ΔV ₁ ′ and ΔV ₂ ′ is such that it cannot be visually recognized as a difference in liquid crystal transmittance of the pixel portion, flicker is not visually recognized on the screen of the liquid crystal display device.

Furthermore, when the relationship f _L1 <f _L2 holds, the low-pass filter 801 blocks the frequency component higher than the cutoff frequency f _L1 before the signal is input to the low-pass filter 802, so the low-pass filter f _L2 hardly functions as a high-frequency cutoff filter. Therefore, the penetration voltages at P ₃₁ and P ₃₂ are inevitably almost equal, and a liquid crystal display device without flicker can be realized.

As described above, it has been described that the low-pass filters 801 and 802 can realize a liquid crystal display device without flicker when a relationship of f _L1 ≈f _L2 or f _L1 <f _L2 is established. At least f _L1 >> f _L2 If the inverter 703 constituting the low-pass filter 801 is designed so that the relationship does not hold, the flicker level itself can be lowered, so that the yield at the time of display inspection can be substantially improved.

As described above, the low-pass filter 801 is composed of the resistor R _N of the N-type thin film transistor of the inverter 703 and the capacitor C _INV parasitic to the inverter in the non-selected state. In the design, it may be considered that the cutoff frequency f _L1 of the low-pass filter 801 equivalently representing the inverter 703 is equal to 1 / (2π × R _N × C _INV ). From these, the cutoff frequency f _{L2 of the} distributed constant type low-pass filter 802 formed on the gate line between the pixel closest to the gate line driving circuit and the pixel farthest from the gate line driving circuit, and R _N , R between the _{C inv N ≒ 1 / (2π} × C inv × f L2) so as relationship holds, or _{R N> 1 / (2π ×} C inv × f L2) becomes such that the relationship is established R _N By designing this, a liquid crystal display device free from flicker can be realized. _{Alternatively} , a low flicker level liquid crystal display device can be realized by designing R _N so that at least the relationship of R _N << 1 / (2π × C _inv × f _L2 ) is not established. Although previously added here, the resistor R _N instead should be infinite value, the inverse of the cutoff frequency f _L1, i.e. one period of the frequency _{f L1 (2π × R N ×} C INV) is, there In order to keep a pixel group connected to one gate line in a selected state, it is necessary to be sufficiently shorter than a given period.

As described above, in order to realize a liquid crystal display device free from flicker from the design it is necessary to increase the resistance R _N of the N-type thin film transistor of the inverter 703 in a non-selected state. On the other hand, the resistance R _P of the P-type thin film transistor in the selected state influences the delay when the gate line is changed from the non-selected state to the selected state, so it is obvious that it should be as low as possible. Therefore, more specifically, it is necessary to intentionally unbalance the design sizes of the N-type thin film transistor and the P-type thin film transistor of the inverter that directly drives the gate line of the gate line driving circuit. Normally, when designing an inverter using complementary transistors, the manufacturing process and design size are optimized so that the resistance value in the linear region of the N-type transistor is the same as the resistance value in the linear region of the P-type transistor. Turn into. By doing so, the performance of the transistor can be fully utilized. In Example 1 In contrast, in only an inverter for driving a gate line of the gate line driving circuit directly, the resistance R _N in the linear region of the N-type thin film transistor to the resistance R _P in the linear region of the P-type thin film transistor Design to be large. Specifically, a flicker-free liquid crystal display device can be realized by a very simple design change such as increasing the channel length of the N-type thin film transistor of the inverter or decreasing the channel width.

  As described above, in the first embodiment, the inverter using the complementary transistor as the inverter for directly driving the gate line of the gate line driving circuit has been described. However, the same applies to the gate line driving circuit using a push-pull type inverter or the like. Applicable. In the first embodiment, a thin film transistor is used as the drive circuit element and the switching element of the pixel. For example, a MOS field effect transistor and an SOI field effect transistor can be used as long as they perform the same operation. Etc. may be used.

  In Embodiment 2, a method for realizing a liquid crystal display device without flicker by providing a low-pass filter between a gate line driving circuit and a pixel will be described.

FIG. 9 is an equivalent circuit diagram in which the gate line driving circuit and the pixel matrix of the liquid crystal display device according to the second embodiment are extracted with respect to a certain gate line. Here, a low-pass filter 123 having a cutoff frequency f _L3 is provided between the inverter 122 that directly drives the gate line of the gate line driving circuit 121 and the first pixel 124 that is closest to the gate line driving circuit 121. At this time, between the first pixel 124 closest to the gate line driving circuit 121 and the second pixel 124 ′ farthest from the gate line driving circuit 121, a distributed constant type low-pass signal having a cutoff frequency f _L2 is obtained. The resistance of the gate line 125 and the capacitance parasitic on the gate line 125 that can be equivalently expressed as a filter exist in a distributed constant manner.

When the liquid crystal display device having the configuration shown in FIG. 9 is simplified using the above-described filters in the same manner as in the first embodiment, the equivalent circuit diagram shown in FIG. 10 can be substituted. Here, the inverter 122, a resistor R _N in a non-selected state of the N-type thin film transistors forming the inverter, the low-pass filter 141 of the capacitor C cutoff composed of a _INV frequency f _L1 parasitic on the inverter Also, the first pixel and the second pixel were replaced as high-pass filters 144 and 144 ′ having a cutoff frequency f _H , respectively.

  At this time, if the low-pass filter 141 and the low-pass filter 142 are collectively expressed as a synthesis filter 143, this is equivalent to FIG. 7 used in the description of the first embodiment. Therefore, by providing a low-pass filter 142 between the gate line driving circuit and the first pixel without changing the design of the inverter that directly drives the gate line of the gate line driving circuit from the conventional design. It can be said that the same effects as those of the first embodiment can be obtained.

Hereinafter, the second embodiment will be described in more detail. In the second embodiment, the range of the cutoff frequency f _L3 of the low-pass filter 142 is defined as follows. First, between the cutoff frequency f _L1 of the low-pass filter 141 configured equivalently to the inverter 122 in the non-selected state and the cutoff frequency f _L3 of the low-pass filter 142 newly provided in the second embodiment. _Has a relationship of f _L1 > f _L3 or at least a relationship of f _L1 ≈f _L3, and the cutoff frequency of the synthesis filter 143 equivalently representing the two low-pass filters 141 and 142 is the cutoff frequency f _L3. It is necessary to depend heavily on This is because the cutoff frequency f _L3 of the low-pass filter 142 newly provided in the second embodiment is arbitrarily designed so that the output signal 146 is input to the pixel closest to the gate line until the output signal 146 is input. This is because it is necessary to control. Further, the cutoff frequency f _{L2 of the} distributed constant type low-pass filter 145 configured equivalently by parasitically forming a gate line across a plurality of pixels, and the low-pass filter 142 newly provided in the second embodiment are used. f _L2> f _L3 the relationship between the cutoff frequency f _L3 of, or it is necessary that at least f _L2 becomes ≒ f _L3 relation holds. This relationship can be explained in the same manner as in the first embodiment described above.

That is, in order to minimize the frequency component cut off by the distributed constant type low-pass filter 145, before outputting the signal to the distributed constant type low-pass filter 145, that is, to the gate line driving circuit most. This means that it is necessary to cut off a frequency component lower than the cut-off frequency f _L2 of the distributed constant type low-pass filter before outputting the signal to a nearby pixel.

Now, in a conventional liquid crystal display device with flicker, that is, a liquid crystal display device with a difference in punch-through voltage, a low-pass filter that is equivalent to an inverter that directly drives the gate line of the gate line driving circuit. The cutoff frequency of the distributed constant type low-pass filter that is equivalently formed by parasitically forming a gate line across a plurality of pixels is lower than the cutoff frequency of the gate line driving circuit. As described above, the absolute value of the punch-through voltage becomes smaller as the pixel becomes smaller, and as a result, the difference in the punch-through voltage is visually recognized as flicker. When this is applied to the second embodiment, the cutoff frequency f _L1 of the low-pass filter 141 configured equivalently to the inverter 122 and the gate line extending between the plurality of pixels are equivalently configured. A relationship of f _L1 > f _L2 is established between the cutoff frequencies f _L2 of the distributed constant type low-pass filter 145. Furthermore, in the liquid crystal display device in which this punch-through voltage is generated in the first place, the cutoff frequency of the high-pass filter equivalently representing each pixel is lower than the cutoff frequency of each low-pass filter parasitic on the gate line, or at least It is necessary to be close to the cutoff frequency of each low-pass filter.

To summarize the above conditions, in order to obtain a flicker-free liquid crystal display device, in the second embodiment, a relationship of f _L1 > f _L2 > f _L3 > f _H is established between the cutoff frequencies of the filters. Although it is ideal to design the cutoff frequency f _L3 of the low-pass filter 142 newly provided, if it is possible to satisfy at least all of the plurality of conditions, the flicker level of the liquid crystal display device can be surely lowered. Therefore, it is possible to reduce the occurrence of display defects related to flicker.

  Now, how this low-pass filter is specifically configured will be described below with reference to FIG. FIG. 11 schematically shows a liquid crystal display device using the second embodiment with respect to one gate line.

  First, in FIG. 11A, a low-pass filter 164 including a resistor and a capacitor is provided between the gate line driving circuit 161 and the pixel group 167. In this case, the cutoff frequency of the low-pass filter 164 can be determined by designing the resistance and the capacitance. Here, the low-pass filter 164 is configured as a distributed constant type, but may be a lumped-constant type low-pass filter.

  Next, FIG. 2B shows a low-pass filter 165 using a P-type thin film transistor in which a voltage is applied to the ground potential of the gate electrode between the gate line driving circuit 162 and the pixel group 168. . Equivalently, it can be seen that the low-pass filter 165 is composed of the resistance of the P-type thin film transistor and the parasitic capacitance of the P-type thin film transistor. In this case, the resistance and the parasitic capacitance are arbitrarily set by a method of changing the channel width, channel length, gate oxide film thickness, etc. of the P-type thin film transistor, or a method of connecting a plurality of P-type thin film transistors in parallel. It becomes possible to design, and thus the cutoff frequency of the low-pass filter 165 can be determined. Here, a P-type thin film transistor is used, but this may be a transistor or a diode capable of realizing the same function as an N-type thin film transistor, and a plurality of transistors such as a transmission gate are combined. It does n’t matter. However, when an N-type transistor is used as the switching element of the pixel group, a P-type transistor is used. When a P-type transistor is used as the switching element of the pixel group, an N-type transistor is used as the low-pass filter. It will be described below that the effect can be obtained more by using the above. Here, description will be made assuming that a P-type transistor is used as the low-pass filter as shown in FIG. The P-type thin film transistor is always in a conductive state because its gate electrode is applied with a voltage to the ground potential. However, even though they are in the same conduction state, the resistance between the drain electrode and the source electrode varies depending on the voltage of the signal passing therethrough, and the closer the voltage of the signal approaches the ground potential, the more the resistance between the drain electrode and the source electrode becomes. The resistance will increase. That is, the resistance of the P-type thin film transistor in the non-selected state is higher than the resistance of the P-type thin film transistor in the selected state, so that the signal delay when shifting from the non-selected state to the selected state is The delay in shifting from the selected state to the non-selected state can be reduced. Thereby, without increasing the delay time of the gate line selection signal when starting the selection of the gate line, the difference in the penetration voltage at the end of the selection period of the gate line is reduced, and a liquid crystal display device without flicker is obtained. Can do. The same applies to the case where a P-type transistor is used for the pixel group and an N-type transistor is used as the low-pass filter.

  In FIG. 11C, a low-pass filter 166 including an operational amplifier, a resistor, and a capacitor is provided between the gate line driving circuit 163 and the pixel group 169. In this case, the cutoff frequency of the low-pass filter 166 can be determined mainly by designing the resistance and the capacitance. In addition, the cutoff frequency of the low-pass filter 166 can be determined by designing various characteristics such as input / output impedance and frequency characteristics of the operational amplifier itself. Here, an active filter using an operational amplifier is shown as an example, but an operational amplifier is not necessary if the circuit has a similar function.

  In the third embodiment, a method of obtaining a liquid crystal display device free from flicker by providing a resistance modulation circuit between a gate line driving circuit and a pixel group and a driving method thereof will be described. FIG. 12 is a diagram illustrating an example of the third embodiment, in which a liquid crystal display device is replaced as an equivalent circuit along the gate line 183. In the third embodiment, a resistance modulation circuit 185 including an N-type thin film transistor is provided between the gate line driving circuit 181 and the pixel group 184. The resistance modulation circuit 185 has its resistance value controlled by a resistance modulation signal output from a voltage source 186. In this figure, the resistance modulation circuit 185 has its resistance controlled by inputting the resistance modulation signal to the gate electrode of the N-type thin film transistor. Modulated.

Next, a driving method of the liquid crystal display device of FIG. 12 will be described in correspondence with the time chart of FIG. FIG. 13 shows voltage waveforms at the points P ₃₁ , P ₃₂ , P ₃₃ and P ₃₄ in FIG. Here, the signal appearing at the point P ₃₁ is a latch signal for driving the final inverter that directly drives the gate line in the gate line driving circuit 181, and the signal appearing at the point P ₃₂ is an output signal from the final inverter. The signal appearing at the point P ₃₃ is the resistance modulation signal for controlling the resistance modulation circuit 185, which is between the high two voltage states than the threshold voltage of the N-type thin film transistor used in the resistance modulation circuit 185 It has changed. Furthermore, represent the final voltage applied to the gate electrode of the pixel groups is the signal appearing at the point P _34. First, in order to start writing to the pixel group, a signal at a voltage level for turning on a thin film transistor used for a switching element of the pixel group connected to the gate line 183 is output from the gate line driver circuit 181. . At this time, the voltage at the point P ₃₂ rises to the power supply voltage almost at the same time when the voltage at the point P ₃₁ falls to the ground potential, and the gate line 183 (P ₃₄ ) is charged to bring the pixel group into a conductive state. . At this time, since the resistance modulation signal appearing at the point P ₃₃ is in the lower voltage state of the two voltage states, the resistance modulation circuit 185 is in a conductive state having a relatively high resistance. The voltage (P ₃₄ ) finally applied to the gate electrode of the pixel group is accompanied by a delay. Thereafter, until the video signal is input to the signal line 187, that is, until the video signal input period 226 starts, the resistance modulation signal (P ₃₃ ) takes the higher voltage state of the two voltage states. By doing so, the resistance of the N-type thin film transistor of the resistance modulation circuit 185 is sufficiently reduced, the voltage applied to the gate line is saturated to the power supply voltage, and the thin film transistor used for the switching element of the pixel group is in a completely conductive state. To. Now, after writing the video signal input from the signal line 187 in the video signal input period 226 to the liquid crystal cell of each pixel, the resistance modulation signal (P ₃₃ ) is again applied to the voltage of the two voltage states. Wait for the selection period 226 to end with the lower voltage state. At the same time as the selection period 226 ends, the gate line driver circuit 181 outputs a voltage level signal (P ₃₂ ) that insulates the thin film transistors used for the switching elements of the pixel group 184 connected to the gate line 183. To do. However, since the resistance modulation element 186 is in a conductive state having a relatively high resistance at this time, the signal is delayed here, and the voltage (P ₃₄ ) finally applied to the gate line gradually decreases. When this is viewed in terms of frequency, high-frequency components that cause penetration voltage are cut off. In addition, the same conditions as in the first and second embodiments are applied to the resistance modulation circuit of this embodiment. By doing so, a liquid crystal display device free from flicker can be obtained.

  In the liquid crystal display device of the third embodiment described above, the total capacitance parasitic on the power supply of the gate line driving circuit when the conventional method of lowering the power supply voltage of the gate line driving circuit is used only at the end of selection of the gate line. Compared with the current consumption required for charging / discharging, it is sufficient to charge / discharge only the same number of thin film transistors as the number of gate lines, so that the same effect can be obtained with much less current consumption.

  In the fourth embodiment, the output of the shift register of the gate line driving circuit, the output of the delay circuit that delays the output of the shift register for a certain time, and the output of the shift register of the next stage if necessary are provided for each stage. A method for realizing a flicker-free liquid crystal display device by applying the three-state voltage exclusively to the gate line after the input to the logical operation circuit will be described in detail.

FIG. 14 is a block diagram for comprehensively explaining the fourth embodiment. This figure is roughly divided into a gate line driving circuit 241, a pixel group 248, and three power supply lines 249, 250, and 251. The gate line driving circuit 241 includes a shift register 242, a delay circuit 243, a logic operation circuit 244, and power switches 245, 246, and 247 that exclusively select three power lines. At this time, the power supply line 249 is applied to the voltage V _dd that makes the pixel group conductive by the positive power supply 252, and the power supply line 250 is applied to the voltage V _ss that makes the pixel group insulated by the negative power supply 253. , is applied to the V _rr by the voltage source 254 of the high voltage V _rr than further power supply line 251 is lower V _ss than V _dd. The power switch 245 is provided to control the conduction state between the power line 249 and the gate line, the power switch 246 is provided to control the conduction state between the power line 250 and the gate line, and the power source The switch 247 is provided so as to control a conduction state between the power supply line 251 and the gate line.

The flow of this block diagram is shown below in order of the operation of the gate line driving circuit. First, it is assumed that a selection signal for selecting a gate line is output from the shift register 242 as in the conventional case. At this time, the logic operation circuit 244 receives the selection signal, the selection signal that has been delayed for a predetermined time through the delay circuit 243, and the output of the next stage of the shift register 242. At this time, since the next-stage gate line is not yet selected, the next-stage output of the shift register 242 is in a non-selected state. In this state, the logic operation circuit 244 makes only the switch 245 connected to the power supply line 249 conductive. Thus, the gate line is applied to the voltage V _dd , and the pixel group connected to the gate line becomes conductive. By sending a video signal to a signal line connected to the pixel group in this state, a signal can be written in the liquid crystal cell of the pixel group connected to the gate line. Next, after the writing to the pixel is completed, a non-selection signal is output from the shift register 242 to deselect the gate line. At this time, the logical operation circuit 244 receives the non-selection signal, the selection signal that has been delayed for a predetermined time through the delay circuit 243, and the output of the next stage of the shift register 242. At this time, a selection signal for selecting the next-stage gate line is output to the next-stage output of the shift register 242. Considering this state in more detail, first, although the non-selection signal from the shift register 242 is input to the delay circuit 243, the output of the delay circuit 243 is delayed. It turns out that it will be in the state where it remains. Hereinafter, the period in this state is referred to as a waiting period. At this time, the logic operation circuit 244 receives from the shift register a non-selection signal for deselecting the gate line, a selection signal for selecting the next-stage gate line, and a delay circuit 243 during the waiting period. A selection signal that is still in a selected state is input from. As a result of the logical operation, the logical operation circuit 244 turns on only the power switch 247 and keeps applying the gate line to the voltage _Vrr during the waiting period. Next, when this waiting period has passed and the output of the delay circuit 243 is also in a non-selected state, the logic operation circuit 244 keeps only the power switch 246 in a conductive state and continues to apply the gate line to the voltage V _ss . By repeating the above for each gate line, all the gate lines can be selected.

Now, let us organize the time series change of the voltage applied to the gate line. First, the gate line is selected and applied to the voltage _Vdd . Next, simultaneously with the end of the selection period, the waiting period is applied to the voltage _Vrr . Finally, simultaneously with the end of the waiting period, the gate line is deselected and applied to the voltage V _ss .
In this way, the difference from the conventional driving method is that the voltage V _ss is not immediately generated when the selection period is completed, but the voltage V _rr is lower than the voltage V _{dd and} higher than the voltage V _ss once. _ss . By performing such driving, the falling signal applied to the gate line from the gate line driving circuit when the gate line is changed from the selected state to the non-selected state can be moderated. If attention is paid to the frequency component of the signal as in the above-described embodiment, the high-frequency component of the falling signal is reduced, and the absolute value of the above-described punch-through voltage can be reduced. That is, the flicker of the liquid crystal display device can be eliminated.

  A liquid crystal display device that realizes the fourth embodiment and its operation will be specifically described below. FIG. 15 is an equivalent circuit diagram illustrating an example of the fourth embodiment. The gate line driving circuit 261 includes a shift register 268, a delay circuit 263, a 2-input EXOR gate 264, a 2-input NAND gate 265, an N-type thin film transistor 266, a P-type thin film transistor 267, and a power supply line 269. The First, the delay circuit 263 is connected to the signal output terminal of the shift register 268, and the input terminal and output terminal of the delay circuit 263 are connected to the two input terminals of the EXOR gate 264, respectively. On the other hand, the output terminal of the delay circuit 263 is connected to one drain electrode of the N-type thin film transistor so as to control the conduction state through the N-type thin film transistor 266 with the gate line 270. Further, the output terminal of the EXOR gate 264 and the output terminal of the next-stage EXOR gate 264 ′ are connected to the two input terminals of the NAND gate 265, respectively. Further, the output terminal of the NAND gate 265 is connected to the gate electrode of the N-type thin film transistor 266, and the conduction state between the gate line 270 and the delay circuit 263 is controlled by the output of the NAND gate 265. The output terminal of the NAND gate 265 is also connected to a gate electrode of a P-type thin film transistor 267 provided so as to control a conduction state between the power supply line 269 and the gate line 270. When this is repeated for each stage of the gate line driving circuit, the gate line driving circuit 261 of FIG. 15 is obtained.

Next, the operation of this gate line driving circuit will be briefly described with reference to FIG. 15 and the time chart shown in FIG. The time chart of FIG. 16 shows time-series changes in voltage at points P _{41 to} P ₄₈ indicated by black circles in FIG. Here, as can be seen from the voltage waveforms at P ₄₁ and P ₄₂ , it is assumed that the selection signal output to each stage by the shift register is separated in time series for each stage.

To explain step by step, in the initial state, the output from the shift register 268 is at a low level, and since the equipotential is maintained before and after the delay circuit 263 (P ₄₁ , P ₄₃ ), the output from the EXOR gate 264 ( P ₄₅₎ also has a low level. Similarly, the output (P ₄₆ ) from the EXOR gate 264 ′ at the next stage is also at a low level. Therefore, the output of the NAND gate 265 that receives the outputs from the two EXOR gates is at a high level, the P-type thin film transistor 267 is in an insulated state, the N-type thin film transistor 266 is in a conductive state, and the delay circuit 263 The low level output (P ₄₃ ) is applied to the gate line 270 (P ₄₈ ).

Assume that this selection is broken and a selection pulse is output from the shift register 268 to the point P ₄₁ . First, the input terminal (P ₄₁ ) of the delay circuit 263 is at a high level, but the output terminal (P ₄₃ ) is still at a low level because of the delay of the signal by the delay circuit 263. Therefore, the EXOR gate 264 having the input / output signal of the delay circuit 263 as an input signal outputs a high level signal (P ₄₅ ). At this time, the EXOR gate of the next stage continues to output the low level signal (P ₄₆ ) because there is no change in its two input terminals. Therefore, the NAND gate 265 that receives the output signals of the two EXOR gates continues to output a high level signal, keeps the N-type thin film transistor 266 in a conductive state, and outputs (P ₄₃₎ from the delay circuit 263. ) Continue to pass through the gate line ( _P48 ). Thereafter, even after the waiting period determined by the delay time of the delay circuit 263 has ended, the potential of the input / output terminal of the delay circuit 263 becomes equal and the output of the EXOR gate (P ₄₅ ) outputs a low level signal again. Except for this, the output signal (P ₄₃ ) from the delay circuit 263 continues to be applied to the gate line 270, and the gate line 270 is applied to a high level voltage. The pixel group connected thereto is brought into a conductive state.

Thereafter, after a video signal is written to the pixel group, a low level signal (P ₄₁ ) for ending the selection period of the gate line 271 is output from the shift register 268. At the same time, the output (P ₄₂ ) of the next stage of the shift register 268 goes high to select the next stage gate line. This moment, to enter the waiting period of the delay circuit 263, EXOR gates 264 and the next stage of the EXOR gate 264 'both outputs a high level (P _45, P _46). In response to this, the NAND gate 265 whose input signals are both at the high level outputs a low level signal (P ₄₇ ), and the gate line 270 and the delay circuit 263 have been kept conductive until now. The N-type thin film transistor 266 is brought into an insulating state. Further, conversely, the P-type thin film transistor 267 that has been in an insulated state is turned on, and the potential applied to the power supply line 269 is applied to the gate line 270 during the waiting period of the delay circuit 263 ( _P48 ). Almost simultaneously with the end of this waiting period and the input / output signals of the delay circuit 263 becoming equipotential, the outputs (P ₄₅ , P ₄₆ ) of the two EXOR gates 264, 264 ′ are again at the low level, The output (P ₄₇ ) of the NAND gate 265 using these as input signals returns to the high level again. This means that this is the same as returning to the initial state again, and the low level signal from the delay circuit 263 is applied to the gate line 270. That is, the delay circuit 263 returns to the initial state again at the end of the waiting period. On the other hand, as for the next-stage gate line, a high level signal is applied simultaneously with the end of the waiting period of the delay circuit, and it can be seen that selection of the gate line is repeated. By repeating this further in the previous stage of the gate line driving circuit, the gate line driving circuit of the fourth embodiment can be operated.

  Now consider the correspondence between the equivalent circuit diagram of FIG. 15 and the block diagram of FIG. Although there are three power lines 252, 253, 254 in the block diagram of FIG. 14, it will first be noticed that only one power line 269 is found in the equivalent circuit diagram of FIG. Here, it is obvious that the power supply line 251 corresponds to the power supply line 269, but the other two power supply lines are not lost. The fact that there are two positive and negative voltage sources for driving the shift register 268, NAND gate, EXOR gate, etc., which are omitted in FIG. 15, is apparent from the existence of voltages corresponding to the high level and low level described above. Will. That is, the positive voltage source and the power supply line that output a voltage corresponding to the high level are the voltage source 252 and the power supply line 249 shown in FIG. 14, and outputs a voltage corresponding to the low level. The negative voltage source corresponds to the voltage source 253 and the power line 250 shown in FIG.

  As described above, in the fourth embodiment, the circuit of the fourth embodiment is incorporated in the gate line driving circuit 241. However, if the circuit has the same configuration, it is provided, for example, immediately before the pixel group 243. It doesn't matter. As for the delay circuit, for example, a delay circuit in which a plurality of inverters are connected to cause a delay in the input and output may be used, or a delay circuit using the discharge time of the charge stored in the capacitor may be constant. Any delay circuit can be used as long as the delay time can be secured. Furthermore, a wiring for sending a signal for controlling the delay time from the outside to the delay circuit may be newly provided.

It is a figure explaining the structure of the conventional liquid crystal display device. It is an equivalent circuit diagram explaining the conventional liquid crystal display device. 8A and 8B illustrate an example of a conventional liquid crystal display device driving method. It is a figure explaining the conventional liquid crystal display device by extracting equivalently about one gate line. It is a figure explaining the transient response of the voltage applied to the liquid crystal of the conventional liquid crystal display device. It is a figure explaining an example of Example 1 of this invention. FIG. 7 is a diagram illustrating a simplified equivalent circuit of the first embodiment of the present invention in FIG. 6. It is a figure explaining the satisfaction conditions of Example 1 of this invention. FIG. 8A is a diagram illustrating the relationship between the frequency characteristics of the conventional frequency filters. FIG. 8B is a diagram illustrating the relationship between the frequency characteristics of the frequency filters in the first embodiment. FIG. 8C is a diagram showing the relationship between the frequency characteristics at the points P ₁ and P ₂ after passing through each frequency filter when the condition of FIG. 8A is satisfied. FIG. 8D is a diagram showing the relationship between the frequency characteristics at the points P ₁ and P ₂ after passing through each frequency filter when the condition of FIG. 8B is satisfied. FIG. 8E is a diagram showing voltage waveforms at points P ₁ and P ₂ after passing through each frequency filter when the condition of FIG. 8A is satisfied. FIG. 8F is a diagram showing voltage waveforms at points P ₁ and P ₂ after passing through each frequency filter when the condition of FIG. 8B is satisfied. It is a figure explaining an example of Example 2 of this invention. FIG. 10 is a diagram illustrating the second embodiment of the present invention in FIG. 9 as a simplified equivalent circuit. It is a figure explaining the specific example of Example 2 of this invention. FIG. 11A is a diagram illustrating a specific example using a low-pass filter composed of a resistor and a capacitor. FIG. 11B illustrates a specific example using a low-pass filter made of a thin film transistor. FIG. 11C illustrates a specific example using a low-pass filter including an operational amplifier, a capacitor, and a resistor. It is a figure explaining an example of Example 3 of the present invention. It is a figure explaining an example of the drive method of Example 3 of FIG. It is a figure explaining an example of Example 4 of this invention. It is a figure explaining an example of Example 4 of this invention. It is a figure explaining an example of the drive method of Example 4 of this invention.

Explanation of symbols

201 ... Source line drive circuit 202 ... Gate line drive circuit 203 ... Pixel matrix 204 ... Transparent insulating substrate 205 ... Thin film transistor 206 ... Liquid crystal cell X ₁ , X ₂ , X ₃ Source lines Y ₁ , Y ₂ , Y ₃ ... Gate line 301... Source line drive circuit 302... Gate line drive circuit 303... Pixel matrix 304. X-side buffer 306 ... Video signal lines 307, 307 '... Analog switches 308, 308' ... Source line 309 ... Y-side shift register 310 ... Y-side buffers 311 and 311 '・ Gate lines 312, 312 ′... Thin film transistor 313, 313 ′... Liquid crystal cell 331... Specified by clock CLX Clocked inverter 332... Clocked inverter defined by clock CLX * 333... Inverter 334... Basic cell of X side shift register 335... Clocked inverter 336 defined by clock CLY. Clocked inverter defined by clock CLY * 337... Inverter 338... NOR logic gate 339... Basic cell of Y shift register 341... Start pulse input terminal 342 of X shift register 342. Start pulse input terminal of Y side shift register 344 ... Video signal input terminal CLX, CLX * ... Clock CLX and clock CLX *
CLY, CLY * ... Clock CLY and Clock CLY *
P _1, P ₂ ... view P ₁ and point P ₂ Q ₁ point 2 of the equivalent circuit, Q ₂ points of an equivalent circuit of ... Figure 2 Q ₁ and the point Q ₂ R _1, R ₂ ... Point R of the equivalent circuit of FIG.
₁ and point R ₂ V ₁ ... Point V _{1 in} the equivalent circuit of FIG.
P _1, P ₂ ... view P ₁ and point P ₂ Q ₁ point 2 of the equivalent circuit, Q ₂ points of an equivalent circuit of ... Figure 2 Q ₁ and the point Q ₂ R _1, R ₂ ... 2 is a voltage waveform at a point P1 in FIG. 2 402 is a voltage waveform at a point P2 in FIG. 2 403 is a voltage waveform at a point Q1 in FIG. Voltage waveform at point Q2 in FIG. 2 405 ... Voltage waveform at point V1 in FIG. 2 406 ... Voltage waveform at point R1 in FIG. 2 407 ... Voltage waveform at point R2 in FIG.・ ・ ・ Video center 411 ・ ・ ・ Voltage waveform of clock CLY in FIG. 2 412 ・ ・ ・ Voltage waveform of clock CLX in FIG. 2 501, 501 ′ ・ ・ ・ Pixel transistor 502 ・ ・ ・ Gate selection pulse 503 ・ ・ ・ Gate Line 504, 504 '... Liquid crystal cell 505, 505' ... Gate line 5 03 and the coupling capacitance between the liquid crystal cells 504 and 504 ′ 508... First low-pass filter 509... Second low-pass filter 510... First delay pulse 511. 2 delay pulses C ₁ , C ₂ , G ₁ , G ₂ ... Point C ₁ , C ₂ , G ₁ , G ₂ 601... Time axis 602. Voltage 603 ... Liquid crystal applied voltage 611 ... Ideally no delay gate selection pulse 612 ... Gate selection pulse at point G ₁ in Fig. 4 613 ... Gate selection pulse at point G ₂ in Fig. 4 621 ... Waveform of liquid crystal applied voltage when a gate selection pulse without an ideal delay is input 622 ... Liquid crystal applied voltage waveform at point C ₁ in FIG. 4 623 ... At point C ₂ in FIG. Liquid crystal applied voltage waveform 701 .. Gate line driving circuit 702... Latch signal for driving final inverter 703 of gate line driving circuit 701... Final inverter for directly driving gate line 704 of gate line driving circuit 701. ... Pixel 705 'closest to gate line drive circuit 701 ... Pixels 706, 706' farthest from gate line drive circuit 701 ... Pixel transistor 707 ... Gate line between pixel 705 and pixel 705 ' Capacitance and resistance parasitic in the form of distributed constant V _dd ... Positive power supply voltage R _N , R _P ... Resistance of N-type and P-type thin film transistors constituting final inverter 703 I _P , I _N ... Final inverter Current flowing in N-type and P-type thin film transistors constituting 703 GND... Ground power source 801 and 802. Motor 803,803 '... high-pass filter 804 output signal of the last inverter ... gate line driving circuit 901 ... frequency axis 902 ... Axis 903 ... point P which represents the gain of each frequency filter ₁ , Axis representing signal gain at point P ₂ 904... Time axis 905... Voltage waveform at points P ₁ and P ₂ 906... Frequency characteristics of low-pass filter 801 in FIG. ... Frequency characteristics of the low-pass filter 802 in Fig. 7 908 ... Frequency characteristics of the high-pass filters 803 and 803 'in Fig. 7 909 ... Frequency characteristics at the point P ₁ 910 ... Point P ₂ Frequency characteristics at 911 ・ ・ ・ Voltage waveform at point P ₁ 912 ・ ・ ・ Voltage waveform at point P ₂ 121 ・ ・ ・ Gate line drive circuit 122 ・ ・ ・ Gate line 125 in the gate line drive circuit 122 directly Final inverter to be driven 123 ... newly provided low-pass filters 124, 124 '... first pixel, second pixel 125 ... gate lines 141, 142 ... low-pass filters 143 ... Synthetic filters 144 and 144 'that are composed of the low-pass filter 141 and the low-pass filter 142 are represented. High-pass filter 145 ... Low-pass filter 146 ... Output signal 161 of the final inverter 162, 163... Gate line drive circuit 164... Low-pass filter composed of capacitance and resistance 165... Low-pass filter composed of P-type thin film transistor 166. Low-pass filters 167, 168, 169,..., Pixel matrix 181,. Circuit 182 ... final inverter of the output signal 183 ... gate lines 184 ... pixel matrix 185, ... N-type thin film transistor using resistance modulation circuit 186 ... resistor modulation source 187 ... signal line P _31, at _{P 32, P 33, P 34} ··· point _{P 31, P 32, P 33} , P 34 221 point P ₃₂ of the voltage waveform 222 ... 12 at a point P ₃₁ of ... 12 Voltage waveform 223 ... Voltage waveform at point P ₃₃ in Fig. 12 224 ... Voltage waveform at point P ₃₄ in Fig. 12 225 ... Gate line selection period 226 ... Video signal input period 241 ... Gate line drive circuit 242 ... Shift register 243 ... Delay circuit 244 ... Logic operation circuit 245 ... Switch 246 for controlling the conduction state between the power supply line 249 and the gate line 246 ... Power supply 250 and the power supply line of the switch 248 ... pixel matrix 249 ... voltage V _dd of controlling electrical continuity between the switch 247 ... power supply line 251 and the gate line for controlling the conduction state between the gate line 250 ... Power source line of voltage V _ss 251 ... Power source line of voltage V _rr 252 ... Voltage source of voltage V _dd 253 ... Voltage source of voltage V _ss 254 ... Voltage source of voltage V _rr 261 ... Gate line driving circuit 262 ... Pixel matrix 263 ... Delay circuit 264, 264 '... EXOR gate 265 ... NAND gate 266 ... N-type thin film transistor 267 ... P-type thin film transistor 268 ... shift registers 269 ... power supply line 270 ... gate lines _{P 41, P 42, P 43} , P 44, P 45, P 46, P 47, P 48 · · Equivalent points of the circuit, the point P _41, the point P _42, the point P _43, the point P _44, the point P _45, the point P _46, the point P _47, at a point P ₄₁ of the point P ₄₈ 281 · · · 15 Voltage waveform 282... Voltage waveform at point P ₄₂ in FIG. 15 283... Voltage waveform at point P ₄₃ in FIG. 15 284... Voltage waveform at point P ₄₄ in FIG. Voltage waveform at point P ₄₅ of 286... Voltage waveform at point P ₄₆ in FIG. 15 287... Voltage waveform at point P ₄₇ in FIG.

Claims (1)

Multiple gate lines,
Multiple source lines,
A plurality of pixels formed corresponding to the intersections of the gate lines and the source lines;
An active matrix liquid crystal display device having a selection signal for selecting each gate line or a non-selection signal for supplying a non-selection signal for deselecting each gate line;
The gate line driving circuit includes:
A shift register for generating the selection signal or the non-selection signal;
A transistor provided between the shift register and each gate line,
The transistor has a resistance value between the shift register and each gate line when the gate line is changed from a selected state to a non-selected state by inputting a resistance modulation signal to the gate electrode of the transistor. The liquid crystal display device is controlled so as to be higher than a resistance value in a state where each of the gate lines is selected.

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