JP2004253584A

JP2004253584A - Method for manufacturing semiconductor device

Info

Publication number: JP2004253584A
Application number: JP2003042008A
Authority: JP
Inventors: Takeshi Seihikari; 毅正光; Yasuhisa Fujii; 藤井　　靖久; Hiromoto Takewaka; 博基竹若
Original assignee: Renesas Technology Corp
Current assignee: Renesas Technology Corp
Priority date: 2003-02-20
Filing date: 2003-02-20
Publication date: 2004-09-09

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device of multilayer interconnection, which effectively prevents short circuit between interconnections when embedded, prevents polish remnants of a conductive material from remaining in forming the embedded interconnections, and prevents deterioration in the dimensional accuracy of an interconnection width, or the like. <P>SOLUTION: In forming a contact plug 3 through chemical mechanical polishing of a first interlayer insulating film 4 and the conductive material, the method comprises steps of performing chemical mechanical polishing wherein polishing of the conductive material has a priority, performing chemical mechanical polishing wherein polishing of the first interlayer insulating film has a priority, and performing chemical mechanical polishing wherein polishing of the conductive material has a priority. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、多層配線構造を有する半導体装置の製造方法に関し、特には化学機械研磨法により埋込配線を形成する場合の配線間の短絡や、配線幅のばらつきなどの発生を防止するための技術に関する。
【０００２】
【従来の技術】
一般に、半導体装置は、集積度が向上するのに伴い、配線の多層化、微細化が必要となっている。また、半導体装置の低消費電力化、動作速度の高速化等の要求に応えるためには、配線間容量や配線抵抗を低減することが必要になっている。
【０００３】
従来、上記の多層配線の要求に応えるための技術として、化学機械研磨（ＣＭＰ）により埋込配線（ダマシン）を形成する方法が提案されている（たとえば、特許文献１参照）。特に、半導体基板に近接した深層側においては、層間接続用としてＷからなるコンタクトプラグを形成する技術が提案されている（たとえば、特許文献１，２，３参照）。また、動作速度の高速化の要求に応えるための技術として、たとえばＳｉＯＦ等の低誘電率を有する層間絶縁膜（ＦＳＧ）を用いて配線間容量を低減する方法が提案されている（たとえば、特許文献４参照）。
【０００４】
ところで、従来は、上記のような各種の技術を利用することにより、たとえば、次のようにして多層配線構造を有する半導体装置が製造される。
【０００５】
図９は多層配線構造を有する半導体装置の一例を示す断面図である。同図において、符号１はＳｉ等からなる半導体基板、２はゲート電極、３はＷ等の導電材料からなるコンタクトプラグ、４はＳｉＯ_２，ＳｉＯＮ等からなる第１層間絶縁膜、５はＣｕ等の導電材料からなる第１埋込配線、６はＳｉＯＦ等の低誘電率を有する第２層間絶縁膜である。また、７はＣｕ等の導電材料からなる第２埋込配線、８はＳｉＯＦ等の低誘電率を有する第３層間絶縁膜、９は最上層のアルミ配線、１０はパッシベーション膜である。
【０００６】
上記構成の半導体装置の従来の製造方法について、図１０を参照して説明する。
【０００７】
まず、半導体基板１上に設けられた第１層間絶縁膜４にビアホール等の接続孔１２を形成し、この接続孔１２を埋めるように導電材料（ここではＷ）をＣＶＤ法や等により成長形成する。この状態では、第１層間絶縁膜４の全面が導電材料で覆われた状態になっている。
【０００８】
そこで、図１０（ａ）に示すように、第１層間絶縁膜４の上面と接続孔１２内の導電材料の上面とが面一となるまで両者を化学機械研磨してコンタクトプラグ３を形成する。この場合の化学機械研磨は、第１層間絶縁膜４の上を覆っている導電材料を除く必要があるため、導電材料が優先的に研磨されるように、研磨パッドの加圧力、スラリー成分などが調整される。
【０００９】
この導電材料研磨優先の化学機械研磨では、単位面積当たりのコンタクトプラグ３の占有率が大きい程、第１層間絶縁膜４およびコンタクトプラグ３の研磨量が略比例的に大きくなる。したがって、図１０（ａ）において、左側の位置では単位面積当たりのコンタクトプラグ３の占有率が大きいので研磨量が多く、図中右側の位置ではコンタクトプラグ３の占有率が小さいので研磨量が少なくなる。その結果として、第１層間絶縁膜４に段差Δ（Δ＝５０ｎｍ〜１００ｎｍ）を生じる。この段差Δは、コンタクトプラグ３の単位面積当たりの占有率の差が大きいほど、大きな値になる。
【００１０】
そこで、このような単位面積当たりのコンタクトプラグ３の占有率の違いによって生じる段差Δを低減するために、引き続いて、第１層間絶縁膜研磨優先の化学機械研磨を行う。この化学機械研磨を行うと、図１０（ｂ）に示すように、段差が無くなり、また、コンタクトプラグ３の高さも揃うが、コンタクトプラグ３と第１層間絶縁膜４の研磨特性の違い、つまり研摩レートの差によって第１層間絶縁膜４の上面からコンタクトプラグ３の上部が２０ｎｍ〜４０ｎｍ程度突き出した状態になる。
【００１１】
この状態で、次に、図１０（ｃ）に示すように、第１層間絶縁膜４およびコンタクトプラグ３の全面を覆うようにＳｉＯＦ等の低誘電率を有する第２層間絶縁膜６を高密度プラズマＣＶＤ法やＣＶＤ法などによって形成する。この場合、第２層間絶縁膜６は、下地の凹凸面を比較的忠実に反映して形成される。したがって、この第２層間絶縁膜６の表面は、コンタクトプラグ３の突き出し形状を反映した凹凸形状になっている。
【００１２】
続いて、図１０（ｄ）に示すように、第２層間絶縁膜６の上記コンタクトプラグ３の対応位置に接続孔１３をフォトリソグラフィやドライエッチング等を組み合わせて形成する。この場合、接続孔１３の形成箇所以外の第２層間絶縁膜６には、図１０（ｃ）に示した表面の凹凸形状を反映した窪み１４がそのまま残されることになる。
【００１３】
次に、図１０（ｅ）に示すように、上記の接続孔１３を埋めるようにＣｕ等の導電材料１５をスパッタ法、ＣＶＤ法、メッキ法などにより成長形成する。この状態では、第２層間絶縁膜６および接続孔１３の全面が導電材料１５で覆われた状態になっているので、次に、図１０（ｆ）に示すように、第２層間絶縁膜６の上面と接続孔１３内の導電材料１５の上面とが面一となるまで両者を化学機械研磨して第１埋込配線５を形成する。この場合の化学機械研磨は、第２層間絶縁膜６の上を覆っている導電材料１５を除く必要があるため、導電材料１５が優先的に研磨されるように、研磨パッドの加圧力、スラリー成分などが調整される。
【００１４】
その後は、フォトリソグラフィやドライエッチング、スパッタ法、ＣＶＤ法、化学機械研磨等を組み合わせて、上述の場合と同様に、第１埋込配線５の直上に第２埋込配線７を形成し、この第２埋込配線７の直上にさらに図示しない第３埋込配線を形成するなどして、多層配線構造を形成する。最後は、最上層の上面にアルミ配線９を形成し、その上を覆ってパッシベーション膜１０を形成する。これにより、図９に示したような多層配線構造を有する半導体装置が得られる。
【００１５】
【特許文献１】
特開平９−２６０４９０号公報（第３−５頁、図１）
【特許文献２】
特開平３−２４４１３０号公報（第１−５頁、図１）
【特許文献３】
特開平８−２６４５３４号公報（第２−６頁、図４）
【特許文献４】
特開平１１−３５４４６４号公報（第２−４頁、図１−図２）
【００１６】
【発明が解決しようとする課題】
ところで、図１０（ｆ）に示したように、第１埋込配線５を形成する場合、第２層間絶縁膜６およびコンタクトプラグ６の上を覆っている導電材料１５を除くために導電材料研摩優先の化学機械研磨が行われるが、その際、接続孔１３の形成箇所を除いた第２層間絶縁膜６には、この第２層間絶縁膜６形成の際に生じた表面の凹凸形状を反映した窪み１４がそのまま残されている。
【００１７】
このため、導電材料研摩優先の化学機械研磨を行うと、研摩目的である導電材料（ここではＣｕ）１５は容易に研摩されるが、ＳｉＯＦ等の低誘電率を有する第２層間絶縁膜６は殆ど研摩されない。その結果、図１１に示すように、第２層間絶縁膜６に存在する窪み１４に導電材料１５が残滓１６として存在するようになる。そして、この残滓１６によって互いに隣接する第１埋込配線５間が電気的に短絡されてしまい、その結果、半導体装置が正常に動作しなくなるなどの不都合を生じる。
【００１８】
上記のような不都合が生じないようにするには、たとえば、図１０（ｃ）に示した第２層間絶縁膜６の形成工程が終了した後に、第２層間絶縁膜６を化学機械研磨して表面の凹凸の除いて平坦化することが考えられる。しかし、ＳｉＯＦ等の低誘電率を有する第２層間絶縁膜６を均一に研摩することは難しいため、実用性に欠ける。
【００１９】
また、第２層間絶縁膜６の窪み１４に残滓１６が存在して第１埋込配線５間の短絡が生じる原因は、図１０（ｂ）に示したように、第１層間絶縁膜研磨優先の化学機械研磨を行って段差Δを低減する工程を設けた結果、コンタクトプラグ３が第１層間絶縁膜４の上面から突き出していることにある。
【００２０】
そこで、図１０（ｂ）に示した工程を省略し、その前の図１０（ａ）に示した工程が終了した段階で、次に、図１２（ａ）に示すように、第１層間絶縁膜４およびコンタクトプラグ３の上を覆って第２層間絶縁膜６を形成する。このようにすると、第１層間絶縁膜４の段差Δは残るが、第１層間絶縁膜４からのコンタクトプラグ３の上部突き出しが殆ど無いため、第２層間絶縁膜６は比較的平坦な表面になる。
【００２１】
しかしながら、第１層間絶縁膜４の上に第２層間絶縁膜６を形成した後、図１０（ｄ），（ｅ），（ｆ）の各工程と同様に、フォトリソグラフィで接続孔１３を形成し、次に、ＣＶＤ法等で導電材料１５を成長形成し、引き続いて、化学機械研磨を行なって第１埋込配線５を形成した場合には、図１２（ｂ）に示すように、初期の段差Δの影響を受けて、コンタクトプラグ３の単位面積当たりの占有率が大きい領域（図中左の領域）に導電材料１５を十分に取り除けない研摩残部１７が生じる。このため、依然として、この研摩残部１７によって互いに隣接する第１埋込配線５間が電気的に短絡されてしまうという不都合を生じる。
【００２２】
また、図１２（ａ）に示したように、第１層間絶縁膜４の上に第２層間絶縁膜６を形成した後、フォトリソグラフィで第１埋込配線５形成用の接続孔１３を形成する際には、初期の段差Δの影響を受けてデフォーカスが生じ易くなり、第１埋込配線５の配線幅がばらつくなどの不都合も生じる。
【００２３】
本発明は、上記の課題を解決するためになされたもので、埋込配線を形成する場合の配線間の短絡や、導電材料の研磨残りを生じたり、配線幅の寸法精度の劣化等を有効に防止した多層配線構造の半導体装置の製造方法を提供することを目的とする。
【００２４】
【課題を解決するための手段】
本発明は、上記の目的を達成するために、半導体基板上に設けられた第１層間絶縁膜に接続孔を形成し、この接続孔を埋めるように導電材料を成長形成する工程と、上記第１層間絶縁膜および導電材料を化学機械研磨してコンタクトプラグを形成する工程と、上記第１層間絶縁膜およびコンタクトプラグを覆って第２層間絶縁膜を形成する工程と、この第２層間絶縁膜の上記コンタクトプラグの対応位置に接続孔を形成し、この接続孔を埋めるように導電材料を成長形成する工程と、上記第２層間絶縁膜および導電材料を化学機械研磨して埋込配線を形成する工程と、を含む半導体装置の製造方法を前提として、次のようにしている。
【００２５】
すなわち、請求項１記載に係る半導体装置の製造方法は、上記第１層間絶縁膜および導電材料を化学機械研磨してコンタクトプラグを形成する工程が、導電材料研磨優先の化学機械研磨を行う工程と、第１層間絶縁膜研磨優先の化学機械研磨を行う工程と、導電材料研磨優先の化学機械研磨を行う工程と、を順次組み合わせたものであることを特徴としている。これにより、コンタクトプラグを形成する場合にコンタクトプラグが第１層間絶縁膜から突き出すことに起因して第１埋込配線間が短絡するのを有効に防止することができる。
【００２６】
請求項２記載の発明に係る半導体装置の製造方法は、上記第１層間絶縁膜および導電材料を化学機械研磨してコンタクトプラグを形成する工程が、導電材料研磨優先の化学機械研磨を行う工程と、第１層間絶縁膜研磨優先の化学機械研磨を行う工程と、を順次組み合わせてなり、また、上記第１層間絶縁膜およびコンタクトプラグを覆って第２層間絶縁膜を形成する工程は、第１層間絶縁膜およびコンタクトプラグを覆って化学機械研磨による均一性のとれた平坦化が第１層間絶縁膜よりも容易な層間絶縁膜を形成する工程と、この層間絶縁膜を化学機械研磨して表面平坦化する工程と、この平坦化された層間絶縁膜の上にさらに層間絶縁膜を形成する工程と、を順次組み合わせたものであることを特徴としている。これにより、コンタクトプラグを形成する場合にコンタクトプラグが第１層間絶縁膜から突き出すことに起因して第１埋込配線間が短絡するのを有効に防止することができる。
【００２７】
請求項３記載の発明に係る半導体装置の製造方法は、上記第１層間絶縁膜に接続孔を形成し、この接続孔を埋めるように導電材料を成長形成する工程において、上記コンタクトプラグの単位面積当たりの占有率が均一になるように上記接続孔とともにダミー用接続溝を予め形成しておくことを特徴としている。これにより、コンタクトプラグを形成する場合にコンタクトプラグが第１層間絶縁膜から突き出すことに起因して第１埋込配線間が短絡するのを有効に防止することができる。しかも、段差解消のための第１層間絶縁膜研磨優先の化学機械研磨を省略することができるため、工程の省略化が図れる。
【００２８】
請求項４記載の発明に係る半導体装置の製造方法は、上記第１層間絶縁膜および導電材料を化学機械研磨してコンタクトプラグを形成する工程は、導電材料研磨優先の化学機械研磨を行う工程であり、また、上記第１層間絶縁膜およびコンタクトプラグを覆って第２層間絶縁膜を形成する工程は、第１層間絶縁膜およびコンタクトプラグを覆って化学機械研磨による均一性のとれた平坦化が第１層間絶縁膜よりも容易な層間絶縁膜を形成する工程と、この層間絶縁膜を化学機械研磨して表面平坦化する工程と、この平坦化された層間絶縁膜の上にさらに層間絶縁膜を形成する工程と、を順次組み合わせたものであることを特徴としている。これにより、コンタクトプラグを形成する場合に、導電材料研磨優先の化学機械研磨を行うことにより生じる段差に起因して、その後、フォトリソグラフィで接続孔を形成する際にデフォーカスが生じて第１埋込配線４の配線幅がばらついたり、第１埋込配線形成時に導電材料の研磨残部が生じて第１埋込配線間での短絡が生じるなどの不都合が回避される。
【００２９】
【発明の実施の形態】
実施の形態１．
図１は本発明の実施の形態１に係る半導体装置の断面図、図２は図１の半導体装置の製造方法の一部を工程順に示す断面図であり、図９および図１０に示した従来技術と対応する構成部分には同一の符号を付す。
【００３０】
この実施の形態１の半導体装置は、第１層間絶縁膜４からコンタクトプラグ３が上方に突き出しておらず、第１層間絶縁膜４の上面とコンタクトプラグ３の上面とが面一になっている。このため、第２層間絶縁膜６の上面も平坦で従来のような窪みは生じていない。
その他の構成については、図９に示した従来のものと同様であるからここでは詳しい説明を省略する。
【００３１】
次に、この実施の形態１における半導体装置の製造方法の特徴について、図２を参照して具体的に説明する。
【００３２】
この実施の形態１においても、従来の図１０（ａ），（ｂ）に示した場合と同様に、コンタクトプラグ３の形成にあたって、第１層間絶縁膜４の全面を覆うＷ等の導電材料を優先的に研磨する化学機械研磨を行ない、次に、コンタクトプラグ３の占有率の違いによって生じる段差Δを無くすために、第１層間絶縁膜４の研磨優先の化学機械研磨を行う。
【００３３】
この工程が終了すると、段差が無くなり、また、コンタクトプラグ３の高さも揃うが、コンタクトプラグ３と第１層間絶縁膜４の研磨レート差によって第１層間絶縁膜４の上面からコンタクトプラグ３の上部が突き出した状態になる。ここに、図２（ａ）は図１０（ｂ）と同じ状態を示している。
【００３４】
この状態から、この実施の形態１では、コンタクトプラグ３の上部の突き出し部分を除くために、コンタクトプラグ３を構成する導電材料（ここではＷ）の研磨優先の化学機械研磨を行う。この化学機械研磨は、たとえば、研磨パッドの加圧力を小さくしたり、研磨パッドを硬質のものにしたり、あるいは第１層間絶縁膜４とコンタクトプラグ３に対する研磨レートが同じになるようにスラリー成分を調整するなどして実施される。これにより、図２（ｂ）に示すように、第１層間絶縁膜４の上面とコンタクトプラグ３の上面とが面一となって平坦面になる。
【００３５】
続いて、第１層間絶縁膜４およびコンタクトプラグ３の全面を覆うようにＳｉＯＦ等の低誘電率を有する第２層間絶縁膜６を高密度プラズマＣＶＤ法やＣＶＤ法などによって形成する。この場合、図２（ｂ）に示した工程で既に第１層間絶縁膜４およびコンタクトプラグ３の上面は平坦面となっているので、図２（ｃ）に示すように、第２層間絶縁膜６も凹凸のない平坦面となる。
【００３６】
以降は、従来の図１０（ｄ），（ｅ），（ｆ）に示した各工程と同様に、フォトリソグラフィで第２層間絶縁膜６に接続孔１３を形成し、次に、ＣＶＤ法等でＣｕなどの導電材料１５を成長形成し、引き続いて、化学機械研磨を行なって第１埋込配線５を形成することになるが、図２（ｃ）に示したように、第２層間絶縁膜６の上面は平坦で従来のような窪みがないため、第１埋込配線５の相互間が導電材料１５の残滓によって短絡するといった不具合を有効に防止することができる。また、コンタクトプラグ３や第１埋込配線５は、いずれの箇所においても略同じ高さになるため、配線抵抗のばらつきを生じることもない。
その他の工程については、従来と同様であるので、ここでは詳しい説明は省略する。
【００３７】
このように、この実施の形態１では、コンタクトプラグ３を形成する場合に、コンタクトプラグ３の上面が第１層間絶縁膜４の上面と面一になるように化学機械研磨を行うので、従来ように、コンタクトプラグ３が第１層間絶縁膜４から突き出すことに起因して第１埋込配線５の相互間が短絡するのを有効に防止することができる。
【００３８】
実施の形態２．
図３は本発明の実施の形態２に係る半導体装置の断面図、図４は図３の半導体装置の製造方法の一部を工程順に示す断面図であり、図９および図１０に示した従来技術と対応する構成部分には同一の符号を付す。
【００３９】
この実施の形態２の半導体装置は、第１層間絶縁膜４からコンタクトプラグ３が上方に突き出しているが、第１層間絶縁膜４の上に化学機械研磨による均一性のとれた平坦化が第１層間絶縁膜４よりも容易な層間絶縁膜２０が形成され、さらに、この層間絶縁膜２０の上にＳｉＯＦ等の低誘電率を有する層間絶縁膜２１が形成されており、両者２０，２１によって第２層間絶縁膜６が構成されている。そして、この第２層間絶縁膜６の上面は平坦で従来のような窪みは生じていない。
その他の構成については、図９に示した従来構成の場合と同様であるからここでは詳しい説明を省略する。
【００４０】
次に、この実施の形態２における半導体装置の製造方法の特徴について、図４を参照して具体的に説明する。
【００４１】
この実施の形態２においても、従来の図１０（ａ），（ｂ）に示した場合と同様に、コンタクトプラグ３の形成にあたって、第１層間絶縁膜４の全面を覆う導電材料を優先的に研磨する化学機械研磨を行ない、次に、コンタクトプラグ３の占有率の違いによって生じる段差Δを無くすために、第１層間絶縁膜４の研磨優先の化学機械研磨を行う。
【００４２】
この工程が終了すると、段差Δが無くなり、また、コンタクトプラグ３の高さも揃うが、コンタクトプラグ３と第１層間絶縁膜４の研磨レート差によって第１層間絶縁膜４の上面からコンタクトプラグ３の上部が突き出した状態になる。ここに、図４（ａ）は図１０（ｂ）と同じ状態を示している。
【００４３】
この状態から、この実施の形態２では、図４（ｂ）に示すように、たとえば高密度プラズマＣＶＤ法やＣＶＤ法などを用いて、第１層間絶縁膜４およびコンタクトプラグ３の上を覆って化学機械研磨による均一性のとれた平坦化が第１層間絶縁膜４よりも容易な層間絶縁膜２０を形成する。この場合の層間絶縁膜２０としては、たとえば原料ガスとしてＴＥＯＳ系（テトラエチルオルソシリケート）を用いて１００ｎｍ〜３００ｎｍ程度の厚さになるように形成される。その際、既にコンタクトプラグ３の上部が第１層間絶縁膜４の上面から突き出しているため、層間絶縁膜２０の表面は、コンタクトプラグ３の突き出し形状を反映した凹凸形状になる。
【００４４】
そこで、図４（ｃ）に示すように、層間絶縁膜２０をコンタクトプラグ３が露出することなく全面に残る程度に化学機械研磨して表面を平坦化する。この場合、層間絶縁膜２０は比較的容易に化学機械研磨により均一性のとれた平坦化が成される。
【００４５】
続いて、図４（ｄ）に示すように、上記のようにして表面が平坦化された層間絶縁膜２０の上にＳｉＯＦ等の低誘電率を有する層間絶縁膜２１を形成する。この場合、図４（ｃ）に示した先の工程で研磨容易な層間絶縁膜２０の上面は平坦面となっているので、低誘電率の層間絶縁膜２１の上面も凹凸のない平坦面となる。
【００４６】
以降は、従来の図１０（ｄ），（ｅ），（ｆ）に示した各工程と同様に、フォトリソグラフィで第２層間絶縁膜６に接続孔１３を形成し、次に、ＣＶＤ法等でＣｕなどの導電材料１５を成長形成し、引き続いて、化学機械研磨を行なって第１埋込配線５を形成することになるが、図４（ｄ）に示したように、第２層間絶縁膜６の上面は平坦で従来のような窪みがないため、第１埋込配線５の相互間が導電材料１５の残滓によって短絡するといった不具合を有効に防止することができる。また、コンタクトプラグ３や第１埋込配線５は、いずれの箇所においても略同じ高さになるため、配線抵抗のばらつきを生じることもない。
その他の工程については、従来と同様であるので、ここでは詳しい説明は省略する。
【００４７】
実施の形態３．
図５は本発明の実施の形態３に係る半導体装置の断面図、図６は図５の半導体装置の製造方法の一部を工程順に示す断面図であり、図９および図１０に示した従来技術と対応する構成部分には同一の符号を付す。
【００４８】
この実施の形態３の半導体装置は、単位面積当たりのコンタクトプラグ３の占有率がいずれの箇所においても等しくなるように、コンタクトプラグ３の占有率の小さい領域にダミー用埋込配線２２が設けられている。また、第１層間絶縁膜４から各コンタクトプラグ３が上方に突き出しておらず、第１層間絶縁膜４の上面とコンタクトプラグ３の上面とが面一になっている。そのため、第２層間絶縁膜６の上面も平坦で従来のような窪みは生じていない。
その他の構成については、図９に示した従来構成の場合と同様であるからここでは詳しい説明を省略する。
【００４９】
次に、この実施の形態３における半導体装置の製造方法の特徴について、図６を参照して具体的に説明する。
【００５０】
この実施の形態３においては、コンタクトプラグ３の形成にあたって、まず最初に半導体基板１上に形成された第１層間絶縁膜４にコンタクトプラグ３の形成用の接続孔１２だけでなく、コンタクトプラグ３の占有率の小さい領域に予めダミー用接続溝２３が予め形成されている。
【００５１】
続いて、上記の接続孔１２およびダミー用接続溝２３を埋めるように導電材料（ここではＷ）をＣＶＤ法等により成長形成する。この状態では、第１層間絶縁膜４の全面が導電材料で覆われた状態になっている。
【００５２】
そこで、第１層間絶縁膜４と導電材料とが面一になるように導電材料を優先的に研磨する化学機械研磨を行う。この導電材料研磨優先の化学機械研磨を行った場合、コンタクトプラグ３の占有率はいずれの箇所においても略等しいので、従来のようなコンタクトプラグ３の占有率の違いに起因した段差Δは生じず、図６（ａ）に示すように、第１層間絶縁膜４の上面は平坦になる。
【００５３】
続いて、図６（ｂ）に示すように、第１層間絶縁膜４の上にＳｉＯＦ等の低誘電率を有する第２層間絶縁膜６を形成する。この場合、図６（ａ）に示したように、既に第１層間絶縁膜４の上面は平坦面となっているので、低誘電率の第２層間絶縁膜６の上面も凹凸のない平坦面となる。
【００５４】
以降は、従来の図１０（ｄ），（ｅ），（ｆ）に示した各工程と同様に、フォトリソグラフィで第２層間絶縁膜６に接続孔１３を形成し、次に、ＣＶＤ法等でＣｕなどの導電材料１５を成長形成し、引き続いて、化学機械研磨を行なって第１埋込配線５を形成することになるが、図６（ｂ）に示したように、第２層間絶縁膜６の上面は平坦で従来のような窪みがないため、第１埋込配線５の相互間が導電材料１５の残滓によって短絡するといった不具合を有効に防止することができる。
【００５５】
また、コンタクトプラグ３はいずれの箇所においても略同じ高さになるため、配線抵抗のばらつきを生じることもない。さらに、この実施の形態３では、段差Δ解消のための第１層間絶縁膜４研磨優先の化学機械研磨を省略することができるため、工程の省略化が図れる。
【００５６】
実施の形態４．
図７は本発明の実施の形態４に係る半導体装置の断面図、図８は図７の半導体装置の製造方法の一部を工程順に示す断面図であり、図９および図１０に示した従来技術と対応する構成部分には同一の符号を付す。
【００５７】
この実施の形態４の半導体装置は、第１層間絶縁膜４に段差Δが生じているが、この第１層間絶縁膜４の上に化学機械研磨による均一性のとれた平坦化が第１層間絶縁膜４よりも容易な層間絶縁膜２０が形成され、さらに、この層間絶縁膜の上にＳｉＯＦ等の低誘電率を有する層間絶縁膜２１が形成されており、両者２０，２１によって第２層間絶縁膜６が構成されている。このため、第２層間絶縁膜６の上面は平坦で従来のような窪みは生じていない。
その他の構成については、図９に示した従来構成の場合と同様であるからここでは詳しい説明を省略する。
【００５８】
次に、この実施の形態４における半導体装置の製造方法の特徴について、図８を参照して具体的に説明する。
【００５９】
この実施の形態４においても、コンタクトプラグ３の形成にあたって、従来の図１０（ａ）に示した場合と同様に、第１層間絶縁膜４の全面を覆う導電材料を優先的に研磨する化学機械研磨を行なう。その場合、コンタクトプラグ３の占有率の違いによって段差Δが生じる。ここに、図８（ａ）は図１０（ａ）と同じ状態を示している。
【００６０】
次の工程では、図１０（ｂ）に示したような段差Δを無くすための第１層間絶縁膜４の研磨優先の化学機械研磨を行わず、その代わりに、この実施の形態４では、図８（ｂ）に示すように、たとえば高密度プラズマＣＶＤ法やＣＶＤ法などを用いて、第１層間絶縁膜４およびコンタクトプラグ３を覆って化学機械研磨による均一性のとれた平坦化が第１層間絶縁膜４よりも容易な層間絶縁膜２０を形成する。
【００６１】
この場合の層間絶縁膜２０としては、実施の形態２の場合と同様に、たとえば原料ガスとしてＴＥＯＳ系（テトラエチルオルソシリケート）を用いて１００ｎｍ〜３００ｎｍ程度の厚さになるように形成される。この層間絶縁膜２０を形成するとその表面に依然として段差Δが発生する。そこで、図８（ｃ）に示すように、層間絶縁膜２０をコンタクトプラグ３が露出することなく全面に残る程度に化学機械研磨して表面を平坦化する。
【００６２】
続いて、図８（ｄ）に示すように、既に表面が平坦化された層間絶縁膜２０の上にＳｉＯＦ等の低誘電率を有する層間絶縁膜２１を形成する。この場合、図８（ｃ）に示した先の工程で研磨容易な層間絶縁膜２０の上面は平坦面となっているので、低誘電率の層間絶縁膜２１の上面も凹凸のない平坦面となる。
【００６３】
以降は、従来の図１０（ｄ），（ｅ），（ｆ）に示した各工程と同様に、フォトリソグラフィで第２層間絶縁膜６に接続孔１３を形成し、次に、ＣＶＤ法等でＣｕなどの導電材料１５を成長形成し、引き続いて、化学機械研磨を行なって第１埋込配線５を形成することになるが、図４（ｄ）に示したように、第２層間絶縁膜６の上面は平坦で従来のような窪みがないため、第１埋込配線５の相互間が導電材料１５の残滓によって短絡するといった不具合を有効に防止することができる。ただし、コンタクトプラグ３の高さは、その単位面積当たりの占有率の違いによって生じる段差Δのために変化し、したがって、配線抵抗に若干のばらつきが生じる。
その他の工程については、従来と同様であるので、ここでは詳しい説明は省略する。
【００６４】
なお、本発明は、上記の実施の形態１〜４で説明した内容に限定されるものではなく、本発明の趣旨を逸脱しない範囲で適宜に変更して実施することができる。
【００６５】
【発明の効果】
請求項１記載ないし請求項３記載の発明に係る半導体装置の製造方法によれば、コンタクトプラグを形成する際にコンタクトプラグが第１層間絶縁膜から突き出すことに起因して第１埋込配線間が短絡するのを有効に防止することができる。また、コンタクトプラグや第１埋込配線はいずれの箇所においても略同じ高さになるため、配線抵抗のばらつきを生じることもない。また、特に、請求項３記載の発明によれば、段差解消のための第１層間絶縁膜研磨優先の化学機械研磨を省略することができるため、工程の省略化が図れる。
【００６６】
請求項４記載の発明に係る半導体装置の製造方法によれば、コンタクトプラグ形成のための導電材料研磨優先の化学機械研磨により生じる段差に起因して、その後にフォトリソグラフィで接続孔を形成する際にデフォーカスが生じて第１埋込配線４の配線幅がばらついたり、第１埋込配線形成時に導電材料の研磨残部が生じて第１埋込配線間での短絡が生じるなどの不都合を回避することができる。
【図面の簡単な説明】
【図１】本発明の実施の形態１に係る製造方法で得られる半導体装置の断面図である。
【図２】図１に示した半導体装置の製造方法の一部を工程順に示す断面図である。
【図３】本発明の実施の形態２に係る製造方法で得られる半導体装置の断面図である。
【図４】図３に示した半導体装置の製造方法の一部を工程順に示す断面図である。
【図５】本発明の実施の形態３に係る製造方法で得られる半導体装置の断面図である。
【図６】図５に示した半導体装置の製造方法の一部を工程順に示す断面図である。
【図７】本発明の実施の形態４に係る製造方法で得られる半導体装置の断面図である。
【図８】図７に示した半導体装置の製造方法の一部を工程順に示す断面図である。
【図９】従来の製造方法で得られる半導体装置の断面図である。
【図１０】図９に示した半導体装置の製造方法の一部を工程順に示す断面図である。
【図１１】従来の製造方法で得られる半導体装置の一部を拡大して示す断面図である。
【図１２】従来の他の半導体装置の製造方法の一部を工程順に示す断面図である。
【符号の説明】
１半導体基板、３コンタクトプラグ、４第１層間絶縁膜、５第１埋込配線、６第２層間絶縁膜、７第２埋込配線、８第３層間絶縁膜、１２接続孔、１５導電材料、２０研磨による均一性のとれた平坦化が容易な層間絶縁膜、２３ダミー用接続孔、Δ 段差。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having a multilayer wiring structure, and more particularly to a technique for preventing the occurrence of short-circuiting between wirings and variations in wiring width when forming embedded wiring by chemical mechanical polishing. About.
[0002]
[Prior art]
In general, as the degree of integration of a semiconductor device increases, it is necessary to increase the number of wiring layers and miniaturization. Further, in order to meet demands for lower power consumption and higher operation speed of semiconductor devices, it is necessary to reduce the capacitance between wirings and the wiring resistance.
[0003]
Conventionally, as a technique for responding to the demand for the above-described multilayer wiring, a method of forming a buried wiring (damascene) by chemical mechanical polishing (CMP) has been proposed (for example, see Patent Document 1). In particular, on the deep layer side close to a semiconductor substrate, a technique of forming a contact plug made of W for interlayer connection has been proposed (for example, see Patent Documents 1, 2, and 3). Further, as a technique for responding to a demand for a higher operation speed, a method of reducing an inter-wiring capacitance using an interlayer insulating film (FSG) having a low dielectric constant such as SiOF has been proposed (for example, see Patent Reference 4).
[0004]
By the way, conventionally, a semiconductor device having a multilayer wiring structure is manufactured by using the above-described various technologies, for example, as follows.
[0005]
FIG. 9 is a sectional view showing an example of a semiconductor device having a multilayer wiring structure. In the figure, reference numeral 1 denotes a semiconductor substrate made of Si or the like, 2 denotes a gate electrode, 3 denotes a contact plug made of a conductive material such as W, ₂ , A first interlayer insulating film made of SiON or the like, 5 a first buried wiring made of a conductive material such as Cu, and 6 a second interlayer insulating film having a low dielectric constant such as SiOF. Reference numeral 7 denotes a second buried wiring made of a conductive material such as Cu, 8 denotes a third interlayer insulating film having a low dielectric constant such as SiOF, 9 denotes an uppermost aluminum wiring, and 10 denotes a passivation film.
[0006]
A conventional method for manufacturing a semiconductor device having the above configuration will be described with reference to FIG.
[0007]
First, a connection hole 12 such as a via hole is formed in the first interlayer insulating film 4 provided on the semiconductor substrate 1, and a conductive material (here, W) is grown and formed by a CVD method or the like so as to fill the connection hole 12. I do. In this state, the entire surface of the first interlayer insulating film 4 is covered with a conductive material.
[0008]
Therefore, as shown in FIG. 10A, the contact plug 3 is formed by chemically and mechanically polishing the upper surface of the first interlayer insulating film 4 and the upper surface of the conductive material in the connection hole 12 until they are flush with each other. . In the chemical mechanical polishing in this case, since it is necessary to remove the conductive material covering the first interlayer insulating film 4, the pressing force of the polishing pad, the slurry component, etc., so that the conductive material is polished preferentially. Is adjusted.
[0009]
In the chemical mechanical polishing in which the polishing of the conductive material is prioritized, as the occupation ratio of the contact plug 3 per unit area increases, the polishing amount of the first interlayer insulating film 4 and the contact plug 3 increases substantially proportionally. Therefore, in FIG. 10A, the polishing amount is large because the occupancy rate of the contact plug 3 per unit area is large at the left side position, and the polishing amount is small because the occupation rate of the contact plug 3 is small at the right side position in FIG. Become. As a result, a step Δ (Δ = 50 nm to 100 nm) occurs in the first interlayer insulating film 4. This step Δ has a larger value as the difference in occupancy per unit area of the contact plug 3 is larger.
[0010]
Then, in order to reduce the step Δ caused by such a difference in the occupation ratio of the contact plug 3 per unit area, chemical mechanical polishing is performed successively with priority given to polishing the first interlayer insulating film. When this chemical mechanical polishing is performed, as shown in FIG. 10 (b), the steps are eliminated and the heights of the contact plugs 3 are uniform, but the difference in the polishing characteristics between the contact plugs 3 and the first interlayer insulating film 4, that is, Due to the difference in the polishing rate, the upper portion of the contact plug 3 projects from the upper surface of the first interlayer insulating film 4 by about 20 nm to 40 nm.
[0011]
In this state, as shown in FIG. 10C, the second interlayer insulating film 6 having a low dielectric constant such as SiOF is formed to a high density so as to cover the entire surface of the first interlayer insulating film 4 and the contact plug 3. It is formed by a plasma CVD method, a CVD method, or the like. In this case, the second interlayer insulating film 6 is formed to relatively faithfully reflect the uneven surface of the base. Therefore, the surface of the second interlayer insulating film 6 has an uneven shape reflecting the protruding shape of the contact plug 3.
[0012]
Subsequently, as shown in FIG. 10D, connection holes 13 are formed in the second interlayer insulating film 6 at positions corresponding to the contact plugs 3 by a combination of photolithography and dry etching. In this case, in the second interlayer insulating film 6 other than where the connection holes 13 are formed, the dents 14 reflecting the surface irregularities shown in FIG. 10C are left as they are.
[0013]
Next, as shown in FIG. 10E, a conductive material 15 such as Cu is grown and formed by a sputtering method, a CVD method, a plating method, or the like so as to fill the connection hole 13. In this state, the entire surface of the second interlayer insulating film 6 and the connection hole 13 is covered with the conductive material 15. Next, as shown in FIG. Of the conductive material 15 in the connection hole 13 are flush with each other until the upper surface thereof is flush with the upper surface of the conductive material 15 to form the first embedded wiring 5. In the chemical mechanical polishing in this case, since it is necessary to remove the conductive material 15 covering the second interlayer insulating film 6, the pressing force of the polishing pad, the slurry, and the like are applied so that the conductive material 15 is preferentially polished. The components are adjusted.
[0014]
After that, the second buried wiring 7 is formed immediately above the first buried wiring 5 by a combination of photolithography, dry etching, sputtering, CVD, chemical mechanical polishing, and the like. A third wiring (not shown) is formed directly above the second wiring 7 to form a multilayer wiring structure. Finally, an aluminum wiring 9 is formed on the upper surface of the uppermost layer, and a passivation film 10 is formed to cover the aluminum wiring 9. Thereby, a semiconductor device having a multilayer wiring structure as shown in FIG. 9 is obtained.
[0015]
[Patent Document 1]
JP-A-9-260490 (page 3-5, FIG. 1)
[Patent Document 2]
JP-A-3-244130 (pages 1-5, FIG. 1)
[Patent Document 3]
JP-A-8-264534 (page 2-6, FIG. 4)
[Patent Document 4]
Japanese Patent Application Laid-Open No. 11-354664 (pages 2-4, FIGS. 1-2)
[0016]
[Problems to be solved by the invention]
By the way, as shown in FIG. 10F, when the first embedded wiring 5 is formed, the conductive material is polished to remove the conductive material 15 covering the second interlayer insulating film 6 and the contact plug 6. The preferential chemical mechanical polishing is performed. At this time, the unevenness of the surface generated when the second interlayer insulating film 6 is formed is reflected on the second interlayer insulating film 6 excluding the portion where the connection hole 13 is formed. The hollow 14 is left as it is.
[0017]
Therefore, if chemical mechanical polishing is performed with priority on polishing of the conductive material, the conductive material (here, Cu) 15 to be polished is easily polished, but the second interlayer insulating film 6 having a low dielectric constant such as SiOF is formed. Hardly polished. As a result, as shown in FIG. 11, the conductive material 15 exists as the residue 16 in the depression 14 existing in the second interlayer insulating film 6. Then, the first buried wirings 5 adjacent to each other are electrically short-circuited by the residue 16, and as a result, inconveniences such as a malfunction of the semiconductor device occur.
[0018]
In order to prevent the above inconvenience, for example, after the step of forming the second interlayer insulating film 6 shown in FIG. 10C is completed, the second interlayer insulating film 6 is subjected to chemical mechanical polishing. It is conceivable that the surface is flattened except for irregularities on the surface. However, since it is difficult to uniformly polish the second interlayer insulating film 6 having a low dielectric constant such as SiOF, it is not practical.
[0019]
Further, as shown in FIG. 10B, the cause of the short-circuit between the first buried interconnects 5 due to the presence of the residue 16 in the recess 14 of the second interlayer insulating film 6 is that the first interlayer insulating film has a higher polishing priority. As a result of the step of reducing the step Δ by performing the chemical mechanical polishing described above, the contact plug 3 protrudes from the upper surface of the first interlayer insulating film 4.
[0020]
Therefore, the step shown in FIG. 10B is omitted, and after the step shown in FIG. 10A is completed, the first interlayer insulating film is then formed as shown in FIG. A second interlayer insulating film 6 is formed to cover the film 4 and the contact plug 3. By doing so, the step Δ of the first interlayer insulating film 4 remains, but since the upper portion of the contact plug 3 does not substantially protrude from the first interlayer insulating film 4, the second interlayer insulating film 6 has a relatively flat surface. Become.
[0021]
However, after forming the second interlayer insulating film 6 on the first interlayer insulating film 4, the connection holes 13 are formed by photolithography in the same manner as in the steps of FIGS. 10 (d), (e) and (f). Next, when the conductive material 15 is grown and formed by the CVD method or the like, and subsequently, the first buried wiring 5 is formed by chemical mechanical polishing, as shown in FIG. Of the contact plug 3 per unit area (region on the left side in the figure), the polishing residue 17 in which the conductive material 15 cannot be sufficiently removed occurs. Therefore, there is still a disadvantage that the first buried wirings 5 adjacent to each other are electrically short-circuited by the remaining polishing portion 17.
[0022]
Further, as shown in FIG. 12A, after forming the second interlayer insulating film 6 on the first interlayer insulating film 4, a connection hole 13 for forming the first embedded wiring 5 is formed by photolithography. In such a case, defocus is likely to occur due to the influence of the initial step Δ, and disadvantages such as a variation in the wiring width of the first embedded wiring 5 also occur.
[0023]
The present invention has been made in order to solve the above-mentioned problems, and is effective in preventing a short circuit between wirings when forming an embedded wiring, remaining polishing of a conductive material, deterioration of dimensional accuracy of a wiring width, and the like. It is an object of the present invention to provide a method of manufacturing a semiconductor device having a multi-layer wiring structure which has been prevented.
[0024]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a step of forming a connection hole in a first interlayer insulating film provided on a semiconductor substrate, and growing and forming a conductive material so as to fill the connection hole. A step of forming a contact plug by chemically and mechanically polishing the first interlayer insulating film and the conductive material, a step of forming a second interlayer insulating film covering the first interlayer insulating film and the contact plug, and a step of forming the second interlayer insulating film Forming a contact hole at a position corresponding to the contact plug, growing a conductive material so as to fill the contact hole, and forming a buried wiring by chemical mechanical polishing the second interlayer insulating film and the conductive material. And a method of manufacturing a semiconductor device including the following steps.
[0025]
That is, in the method of manufacturing a semiconductor device according to claim 1, the step of forming a contact plug by chemically mechanically polishing the first interlayer insulating film and the conductive material includes the step of performing chemical mechanical polishing with priority on polishing of a conductive material. The method is characterized by sequentially combining a step of performing chemical mechanical polishing with priority on polishing of the first interlayer insulating film and a step of performing chemical mechanical polishing with priority on polishing of conductive material. Thereby, when forming the contact plug, it is possible to effectively prevent a short circuit between the first embedded wirings due to the contact plug protruding from the first interlayer insulating film.
[0026]
According to a second aspect of the present invention, in the method of manufacturing a semiconductor device, the step of chemically mechanically polishing the first interlayer insulating film and the conductive material to form a contact plug includes the step of performing chemical mechanical polishing with priority on conductive material polishing. And a step of performing chemical mechanical polishing with priority on polishing of the first interlayer insulating film. The step of forming the second interlayer insulating film covering the first interlayer insulating film and the contact plug includes the first step. A step of forming an interlayer insulating film that covers the interlayer insulating film and the contact plugs and that is more easily planarized by chemical mechanical polishing than the first interlayer insulating film; It is characterized in that a step of flattening and a step of further forming an interlayer insulating film on the flattened interlayer insulating film are sequentially combined. Thereby, when forming the contact plug, it is possible to effectively prevent a short circuit between the first embedded wirings due to the contact plug protruding from the first interlayer insulating film.
[0027]
4. The method of manufacturing a semiconductor device according to claim 3, wherein the step of forming a connection hole in the first interlayer insulating film and growing and forming a conductive material so as to fill the connection hole includes: It is characterized in that dummy connection grooves are formed in advance together with the connection holes so that the occupation ratio per contact becomes uniform. Thereby, when forming the contact plug, it is possible to effectively prevent a short circuit between the first embedded wirings due to the contact plug protruding from the first interlayer insulating film. In addition, chemical mechanical polishing, which gives priority to polishing of the first interlayer insulating film for eliminating a step, can be omitted, so that steps can be omitted.
[0028]
According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device, the step of forming a contact plug by chemically mechanically polishing the first interlayer insulating film and the conductive material is a step of performing chemical mechanical polishing with priority on conductive material polishing. The step of forming the second interlayer insulating film over the first interlayer insulating film and the contact plug includes the step of covering the first interlayer insulating film and the contact plug with uniform planarization by chemical mechanical polishing. A step of forming an interlayer insulating film easier than the first interlayer insulating film, a step of flattening the surface of the interlayer insulating film by chemical mechanical polishing, and a step of further forming an interlayer insulating film on the flattened interlayer insulating film. And the step of forming is sequentially combined. As a result, when forming a contact plug, a defocus occurs when a connection hole is formed by photolithography due to a step caused by performing chemical mechanical polishing with priority on polishing of a conductive material. Inconveniences such as a variation in the wiring width of the embedded wiring 4 and the occurrence of a short circuit between the first embedded wirings due to the generation of the polishing residue of the conductive material during the formation of the first embedded wiring are avoided.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a part of a method of manufacturing the semiconductor device of FIG. The same reference numerals are given to the components corresponding to the technology.
[0030]
In the semiconductor device of the first embodiment, the contact plug 3 does not protrude upward from the first interlayer insulating film 4, and the upper surface of the first interlayer insulating film 4 and the upper surface of the contact plug 3 are flush. . For this reason, the upper surface of the second interlayer insulating film 6 is also flat and does not have a depression as in the related art.
Other configurations are the same as those of the conventional configuration shown in FIG. 9, and therefore detailed description is omitted here.
[0031]
Next, features of the method for manufacturing a semiconductor device according to the first embodiment will be specifically described with reference to FIG.
[0032]
Also in the first embodiment, a conductive material such as W covering the entire surface of the first interlayer insulating film 4 is used for forming the contact plug 3 as in the case shown in FIGS. 10A and 10B. Chemical mechanical polishing is performed for preferential polishing, and then chemical mechanical polishing for polishing the first interlayer insulating film 4 is performed in order to eliminate the step Δ caused by the difference in the occupation ratio of the contact plug 3.
[0033]
When this step is completed, the steps are eliminated and the heights of the contact plugs 3 are made uniform, but the polishing rate difference between the contact plugs 3 and the first interlayer insulating film 4 causes the upper portion of the contact plug 3 Is protruding. Here, FIG. 2A shows the same state as FIG. 10B.
[0034]
From this state, in the first embodiment, in order to remove the protruding portion at the upper portion of the contact plug 3, chemical-mechanical polishing is performed with priority on polishing of the conductive material (here, W) forming the contact plug 3. In this chemical mechanical polishing, for example, the pressing force of the polishing pad is reduced, the polishing pad is hardened, or the slurry component is adjusted so that the polishing rates for the first interlayer insulating film 4 and the contact plug 3 become the same. The adjustment is performed. Thereby, as shown in FIG. 2B, the upper surface of the first interlayer insulating film 4 and the upper surface of the contact plug 3 are flush with each other and become a flat surface.
[0035]
Subsequently, a second interlayer insulating film 6 having a low dielectric constant such as SiOF is formed by high-density plasma CVD or CVD so as to cover the entire surface of the first interlayer insulating film 4 and the contact plug 3. In this case, since the upper surfaces of the first interlayer insulating film 4 and the contact plug 3 are already flat in the step shown in FIG. 2B, as shown in FIG. 6 also becomes a flat surface without unevenness.
[0036]
Thereafter, as in the respective steps shown in FIGS. 10D, 10E, and 10F, the connection holes 13 are formed in the second interlayer insulating film 6 by photolithography, and then the CVD method or the like is performed. Then, a conductive material 15 such as Cu is grown and formed, and subsequently, the first embedded wiring 5 is formed by performing chemical mechanical polishing. However, as shown in FIG. Since the upper surface of the film 6 is flat and does not have a depression as in the related art, it is possible to effectively prevent a short circuit between the first embedded wirings 5 due to residues of the conductive material 15. Further, since the contact plug 3 and the first buried wiring 5 have substantially the same height at any position, the wiring resistance does not vary.
The other steps are the same as in the related art, and thus detailed description is omitted here.
[0037]
As described above, in the first embodiment, when the contact plug 3 is formed, the chemical mechanical polishing is performed so that the upper surface of the contact plug 3 is flush with the upper surface of the first interlayer insulating film 4. In addition, it is possible to effectively prevent a short circuit between the first embedded wirings 5 due to the contact plug 3 protruding from the first interlayer insulating film 4.
[0038]
Embodiment 2 FIG.
FIG. 3 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention, and FIG. 4 is a cross-sectional view showing a part of a method of manufacturing the semiconductor device of FIG. The same reference numerals are given to the components corresponding to the technology.
[0039]
In the semiconductor device according to the second embodiment, the contact plug 3 protrudes upward from the first interlayer insulating film 4, but the first interlayer insulating film 4 is flattened with uniformity by chemical mechanical polishing. An interlayer insulating film 20 that is easier than one interlayer insulating film 4 is formed, and an interlayer insulating film 21 having a low dielectric constant such as SiOF is formed on the interlayer insulating film 20. A second interlayer insulating film 6 is formed. The upper surface of the second interlayer insulating film 6 is flat and does not have a depression as in the related art.
The other configuration is the same as that of the conventional configuration shown in FIG. 9, so that the detailed description is omitted here.
[0040]
Next, features of the method of manufacturing a semiconductor device according to the second embodiment will be specifically described with reference to FIG.
[0041]
Also in the second embodiment, the conductive material covering the entire surface of the first interlayer insulating film 4 is preferentially formed in forming the contact plug 3 as in the case shown in FIGS. 10A and 10B. Polishing is performed by chemical mechanical polishing, and then chemical mechanical polishing of the first interlayer insulating film 4 is performed in order to eliminate the step Δ caused by the difference in the occupation ratio of the contact plug 3.
[0042]
When this step is completed, the step Δ disappears, and the height of the contact plug 3 becomes uniform. However, the difference in the polishing rate between the contact plug 3 and the first interlayer insulating film 4 causes the contact plug 3 The upper part protrudes. Here, FIG. 4A shows the same state as FIG. 10B.
[0043]
From this state, in the second embodiment, as shown in FIG. 4B, the first interlayer insulating film 4 and the contact plug 3 are covered by using, for example, a high-density plasma CVD method or a CVD method. An interlayer insulating film 20 is formed, which is more easily planarized by chemical mechanical polishing than the first interlayer insulating film 4. In this case, the interlayer insulating film 20 is formed to have a thickness of about 100 nm to 300 nm using, for example, a TEOS-based (tetraethyl orthosilicate) as a source gas. At this time, since the upper portion of the contact plug 3 has already protruded from the upper surface of the first interlayer insulating film 4, the surface of the interlayer insulating film 20 has an uneven shape reflecting the protruding shape of the contact plug 3.
[0044]
Therefore, as shown in FIG. 4C, the surface of the interlayer insulating film 20 is flattened by chemical mechanical polishing so that the contact plug 3 remains on the entire surface without being exposed. In this case, the interlayer insulating film 20 can be relatively easily planarized by chemical mechanical polishing relatively easily.
[0045]
Subsequently, as shown in FIG. 4D, an interlayer insulating film 21 having a low dielectric constant such as SiOF is formed on the interlayer insulating film 20 whose surface is flattened as described above. In this case, since the upper surface of the interlayer insulating film 20 which is easy to be polished in the previous step shown in FIG. 4C is a flat surface, the upper surface of the low dielectric constant interlayer insulating film 21 also has a flat surface with no unevenness. Become.
[0046]
Thereafter, as in the respective steps shown in FIGS. 10D, 10E, and 10F, the connection holes 13 are formed in the second interlayer insulating film 6 by photolithography, and then the CVD method or the like is performed. Then, a conductive material 15 such as Cu is grown and formed, and subsequently, the first embedded wiring 5 is formed by chemical mechanical polishing. As shown in FIG. Since the upper surface of the film 6 is flat and does not have a depression as in the related art, it is possible to effectively prevent a short circuit between the first embedded wirings 5 due to residues of the conductive material 15. Further, since the contact plug 3 and the first buried wiring 5 have substantially the same height at any position, the wiring resistance does not vary.
The other steps are the same as in the related art, and thus detailed description is omitted here.
[0047]
Embodiment 3 FIG.
FIG. 5 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention. FIG. 6 is a cross-sectional view showing a part of a method of manufacturing the semiconductor device of FIG. The same reference numerals are given to the components corresponding to the technology.
[0048]
In the semiconductor device according to the third embodiment, the dummy buried wiring 22 is provided in a region where the occupancy of the contact plug 3 is small so that the occupancy of the contact plug 3 per unit area is equal at any position. ing. Further, each contact plug 3 does not protrude upward from the first interlayer insulating film 4, and the upper surface of the first interlayer insulating film 4 and the upper surface of the contact plug 3 are flush. For this reason, the upper surface of the second interlayer insulating film 6 is also flat and does not have a depression as in the related art.
The other configuration is the same as that of the conventional configuration shown in FIG. 9, so that the detailed description is omitted here.
[0049]
Next, the features of the method for manufacturing a semiconductor device according to the third embodiment will be specifically described with reference to FIG.
[0050]
In the third embodiment, in forming the contact plug 3, first, not only the connection hole 12 for forming the contact plug 3 but also the contact plug 3 is formed in the first interlayer insulating film 4 formed on the semiconductor substrate 1. The dummy connection groove 23 is previously formed in a region where the occupancy is small.
[0051]
Subsequently, a conductive material (here, W) is grown and formed by a CVD method or the like so as to fill the connection holes 12 and the dummy connection grooves 23. In this state, the entire surface of the first interlayer insulating film 4 is covered with a conductive material.
[0052]
Therefore, chemical mechanical polishing is performed to preferentially polish the conductive material so that the first interlayer insulating film 4 and the conductive material are flush with each other. When the chemical mechanical polishing is performed with priority on the polishing of the conductive material, the occupancy of the contact plugs 3 is substantially equal at any position, so that the step Δ due to the difference in the occupancy of the contact plugs 3 does not occur. As shown in FIG. 6A, the upper surface of the first interlayer insulating film 4 becomes flat.
[0053]
Subsequently, as shown in FIG. 6B, a second interlayer insulating film 6 having a low dielectric constant such as SiOF is formed on the first interlayer insulating film 4. In this case, as shown in FIG. 6A, since the upper surface of the first interlayer insulating film 4 is already flat, the upper surface of the second interlayer insulating film 6 having a low dielectric constant is also flat without irregularities. It becomes.
[0054]
Thereafter, as in the respective steps shown in FIGS. 10D, 10E, and 10F, the connection holes 13 are formed in the second interlayer insulating film 6 by photolithography, and then the CVD method or the like is performed. Then, a conductive material 15 such as Cu is grown and formed, followed by chemical mechanical polishing to form the first buried wiring 5, but as shown in FIG. Since the upper surface of the film 6 is flat and does not have a depression as in the related art, it is possible to effectively prevent a short circuit between the first embedded wirings 5 due to residues of the conductive material 15.
[0055]
In addition, since the contact plugs 3 have substantially the same height at any position, there is no variation in wiring resistance. Further, in the third embodiment, the chemical mechanical polishing which gives priority to the polishing of the first interlayer insulating film 4 for eliminating the step Δ can be omitted, so that the process can be omitted.
[0056]
Embodiment 4 FIG.
7 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention, and FIG. 8 is a cross-sectional view showing a part of a method of manufacturing the semiconductor device of FIG. The same reference numerals are given to the components corresponding to the technology.
[0057]
In the semiconductor device according to the fourth embodiment, a step Δ is formed in the first interlayer insulating film 4. An interlayer insulating film 20 which is easier than the insulating film 4 is formed, and an interlayer insulating film 21 having a low dielectric constant such as SiOF is formed on the interlayer insulating film. An insulating film 6 is formed. For this reason, the upper surface of the second interlayer insulating film 6 is flat and does not have a depression as in the related art.
The other configuration is the same as that of the conventional configuration shown in FIG. 9, so that the detailed description is omitted here.
[0058]
Next, the features of the semiconductor device manufacturing method according to the fourth embodiment will be specifically described with reference to FIG.
[0059]
Also in the fourth embodiment, in forming the contact plug 3, similarly to the conventional case shown in FIG. 10A, a chemical mechanical device for preferentially polishing a conductive material covering the entire surface of the first interlayer insulating film 4. Polishing is performed. In this case, a step Δ occurs due to a difference in the occupancy of the contact plug 3. Here, FIG. 8A shows the same state as FIG. 10A.
[0060]
In the next step, the first interlayer insulating film 4 is not subjected to chemical-mechanical polishing in order to eliminate the step Δ as shown in FIG. 10 (b). As shown in FIG. 8B, the first interlayer insulating film 4 and the contact plugs 3 are covered with the uniformity by chemical mechanical polishing using the high-density plasma CVD method or the CVD method. An interlayer insulating film 20 which is easier than the interlayer insulating film 4 is formed.
[0061]
As in the case of the second embodiment, the interlayer insulating film 20 in this case is formed to have a thickness of about 100 nm to 300 nm by using, for example, a TEOS-based (tetraethyl orthosilicate) as a source gas. When this interlayer insulating film 20 is formed, a step Δ still occurs on its surface. Therefore, as shown in FIG. 8C, the interlayer insulating film 20 is subjected to chemical mechanical polishing so as to remain on the entire surface without exposing the contact plug 3 to flatten the surface.
[0062]
Subsequently, as shown in FIG. 8D, an interlayer insulating film 21 having a low dielectric constant such as SiOF is formed on the interlayer insulating film 20 whose surface is already flattened. In this case, since the upper surface of the interlayer insulating film 20 which is easy to be polished in the previous step shown in FIG. 8C is a flat surface, the upper surface of the interlayer insulating film 21 having a low dielectric constant also has a flat surface without unevenness. Become.
[0063]
Thereafter, as in the respective steps shown in FIGS. 10D, 10E, and 10F, the connection holes 13 are formed in the second interlayer insulating film 6 by photolithography, and then the CVD method or the like is performed. Then, a conductive material 15 such as Cu is grown and formed, and subsequently, the first embedded wiring 5 is formed by chemical mechanical polishing. As shown in FIG. Since the upper surface of the film 6 is flat and does not have a depression as in the related art, it is possible to effectively prevent a short circuit between the first embedded wirings 5 due to residues of the conductive material 15. However, the height of the contact plug 3 changes due to the step Δ caused by the difference in the occupation ratio per unit area, and therefore, the wiring resistance slightly varies.
The other steps are the same as in the related art, and thus detailed description is omitted here.
[0064]
It should be noted that the present invention is not limited to the contents described in the above-described first to fourth embodiments, and can be implemented with appropriate modifications without departing from the spirit of the present invention.
[0065]
【The invention's effect】
According to the method of manufacturing a semiconductor device according to the first to third aspects of the present invention, when the contact plug protrudes from the first interlayer insulating film when the contact plug is formed, the first buried wiring is formed. Can be effectively prevented from being short-circuited. Further, since the contact plug and the first buried wiring have almost the same height at any position, there is no variation in wiring resistance. In particular, according to the third aspect of the present invention, the chemical mechanical polishing which gives priority to the polishing of the first interlayer insulating film for eliminating the step can be omitted, so that the process can be omitted.
[0066]
According to the method of manufacturing a semiconductor device according to the fourth aspect of the present invention, when a connection hole is subsequently formed by photolithography due to a step caused by chemical mechanical polishing giving priority to polishing of a conductive material for forming a contact plug. Inconveniences such as defocusing and variation in the wiring width of the first buried wiring 4 and the occurrence of a short circuit between the first buried wirings due to the formation of the first buried wirings due to the remaining polishing of the conductive material during the formation of the first buried wirings are avoided. can do.
[Brief description of the drawings]
FIG. 1 is a sectional view of a semiconductor device obtained by a manufacturing method according to a first embodiment of the present invention;
2 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device shown in FIG. 1 in the order of steps;
FIG. 3 is a sectional view of a semiconductor device obtained by a manufacturing method according to a second embodiment of the present invention;
FIG. 4 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device shown in FIG. 3 in the order of steps;
FIG. 5 is a sectional view of a semiconductor device obtained by a manufacturing method according to a third embodiment of the present invention;
6 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device shown in FIG. 5 in the order of steps.
FIG. 7 is a sectional view of a semiconductor device obtained by a manufacturing method according to a fourth embodiment of the present invention;
FIG. 8 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device shown in FIG. 7 in the order of steps.
FIG. 9 is a cross-sectional view of a semiconductor device obtained by a conventional manufacturing method.
10 is a cross-sectional view showing a part of the method of manufacturing the semiconductor device shown in FIG. 9 in the order of steps.
FIG. 11 is an enlarged sectional view showing a part of a semiconductor device obtained by a conventional manufacturing method.
FIG. 12 is a cross-sectional view showing a part of another conventional method for manufacturing a semiconductor device in the order of steps.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 semiconductor substrate, 3 contact plug, 4 first interlayer insulating film, 5 first buried wiring, 6 second interlayer insulating film, 7 second buried wiring, 8 third interlayer insulating film, 12 connection hole, 15 conductive material 20, an interlayer insulating film having uniformity by polishing and easy to planarize, 23 connection holes for dummy, and Δ step.

Claims

Forming a connection hole in a first interlayer insulating film provided on a semiconductor substrate, growing a conductive material so as to fill the connection hole, and performing chemical mechanical polishing on the first interlayer insulating film and the conductive material. Forming a contact plug, forming a second interlayer insulating film covering the first interlayer insulating film and the contact plug, and forming a connection hole in the second interlayer insulating film at a position corresponding to the contact plug. A method of growing a conductive material so as to fill the connection hole, and a step of chemically and mechanically polishing the second interlayer insulating film and the conductive material to form a buried wiring.
The step of forming a contact plug by chemically mechanically polishing the first interlayer insulating film and the conductive material includes the step of performing chemical mechanical polishing with priority on polishing of the conductive material and the step of performing chemical mechanical polishing with priority on polishing of the first interlayer insulating film And a step of performing chemical-mechanical polishing prioritizing polishing of a conductive material.

Forming a connection hole in a first interlayer insulating film provided on a semiconductor substrate, growing a conductive material so as to fill the connection hole, and performing chemical mechanical polishing on the first interlayer insulating film and the conductive material. Forming a contact plug, forming a second interlayer insulating film covering the first interlayer insulating film and the contact plug, and forming a connection hole in the second interlayer insulating film at a position corresponding to the contact plug. A method of growing a conductive material so as to fill the connection hole, and a step of chemically and mechanically polishing the second interlayer insulating film and the conductive material to form a buried wiring.
The step of forming a contact plug by chemically mechanically polishing the first interlayer insulating film and the conductive material includes the step of performing chemical mechanical polishing with priority on polishing of the conductive material and the step of performing chemical mechanical polishing with priority on polishing of the first interlayer insulating film And are sequentially combined,
In the step of forming the second interlayer insulating film covering the first interlayer insulating film and the contact plug, the first interlayer insulating film and the contact plug may be formed by chemical mechanical polishing. A step of forming an interlayer insulating film easier than an interlayer insulating film, a step of flattening the surface of the interlayer insulating film by chemical mechanical polishing, and further forming an interlayer insulating film on the flattened interlayer insulating film And a step of sequentially combining the steps.

Forming a connection hole in a first interlayer insulating film provided on a semiconductor substrate, growing a conductive material so as to fill the connection hole, and performing chemical mechanical polishing on the first interlayer insulating film and the conductive material. Forming a contact plug, forming a second interlayer insulating film covering the first interlayer insulating film and the contact plug, and forming a connection hole in the second interlayer insulating film at a position corresponding to the contact plug. A method of growing a conductive material so as to fill the connection hole, and a step of chemically and mechanically polishing the second interlayer insulating film and the conductive material to form a buried wiring.
In the step of forming a connection hole in the first interlayer insulating film and growing and forming a conductive material so as to fill the connection hole, a dummy is formed together with the connection hole so that the occupation rate per unit area of the contact plug becomes uniform. A method for manufacturing a semiconductor device, comprising: forming a connection groove for use in advance.

Forming a connection hole in a first interlayer insulating film provided on a semiconductor substrate, growing a conductive material so as to fill the connection hole, and performing chemical mechanical polishing on the first interlayer insulating film and the conductive material. Forming a contact plug, forming a second interlayer insulating film covering the first interlayer insulating film and the contact plug, and forming a connection hole in the second interlayer insulating film at a position corresponding to the contact plug. A method of growing a conductive material so as to fill the connection hole, and a step of chemically and mechanically polishing the second interlayer insulating film and the conductive material to form a buried wiring.
The step of forming a contact plug by chemically mechanically polishing the first interlayer insulating film and the conductive material is a step of performing chemical mechanical polishing with priority on conductive material polishing,
In the step of forming the second interlayer insulating film covering the first interlayer insulating film and the contact plug, the first interlayer insulating film and the contact plug may be formed by chemical mechanical polishing. A step of forming an interlayer insulating film easier than an interlayer insulating film, a step of flattening the surface of the interlayer insulating film by chemical mechanical polishing, and further forming an interlayer insulating film on the flattened interlayer insulating film And a step of sequentially combining the steps.