JP2004241406A - Semiconductor device, its wiring method, microcomputer and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an enhancing power supply from bending in the vicinity of a macro ring power supply when enhancing power supply wiring is performed from a basic cell to power supply wiring provided in a macro using an automatic placement and routing tool. <P>SOLUTION: This semiconductor integrated device 10 includes a basic cell region 30 and a macro region 20 and has three or more wiring layers. The semiconductor integrated device 10 comprises ring power supplies 40 and 42 of a first wiring layer, a VSS60 and a VDD62 connected electrically with the first power supplies in a second wiring layer different from the first wiring layer, third auxiliary power supply wiring 80 arranged in the overlapping area of the ring power supplies 40 and 42 and the VSS60 or the VDD62 in a third wiring layer different from the first and second wiring layers and connected electrically with the first ring power supplies 40 and 42, and enhancing power supply wiring 50-1 and 50-2 connected electrically with the third auxiliary power supply wiring 80 in the third wiring layer. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a wiring method therefor, and more particularly to a technique effective when wiring is performed using an automatic placement and routing tool.
[0002]
[Background Art]
Due to demands for higher integration and shorter development time of semiconductor devices, there are many cases where ICs are manufactured by combining a prepared macro having a specific function and a basic cell.
[0003]
In addition, after the wiring is performed using the automatic placement and routing tool, the automatic wiring is automatically corrected using the design rule check function of the automatic placement and routing tool and manually corrected.
[0004]
[Patent Document 1]
JP-A-5-326843
[Problems to be solved by the invention]
Conventionally, using the automatic placement and routing tool, wiring of the enhanced power supply from the basic cell to the power supply wiring provided inside the macro of the semiconductor device including such a basic cell area and the macro area, near the macro ring power supply Avoidance (bent) of the reinforced power supply had occurred.
[0006]
Normally, when a reinforced power supply is bent, a design rule check error is detected, so manual correction was performed. However, if the design rule check error did not occur even if the reinforced power supply was bent, no particular correction was made.
[0007]
However, if the length of one side of the ring power supply is long, many bendings of the enhanced power supply occur. In this case, design rule check errors frequently occur, and thus the amount of manual correction increases.
[0008]
If the occurrence of the bent of the enhanced power supply is not detected by the design rule check error, the correction is not performed, but the channel width used increases due to the bent, and the wiring efficiency is deteriorated.
[0009]
The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a semiconductor device including a basic cell region and a macro region, provided inside a macro by using an automatic placement and routing tool. A semiconductor device and a wiring method thereof capable of preventing occurrence (bending) of an enhanced power supply in the vicinity of a macro ring power supply when an enhanced power supply wiring is performed from a basic cell to a given power supply wiring. is there.
[0010]
[Means for Solving the Problems]
(1) The present invention is a semiconductor integrated device including three or more wiring layers including a basic cell region and a macro region,
A first power supply wiring arranged in a ring shape around the macro region in the first wiring layer;
In a second wiring layer different from the first wiring layer, a second power supply wiring arranged inside the macro and electrically connected to the first power supply;
A third wiring layer different from the first wiring layer and the second wiring layer, the first power wiring being arranged in an overlapping area of the first power wiring and the second power wiring; A third power supply wiring electrically connected to
It is characterized by including.
[0011]
The first power supply wiring arranged annularly around the macro region in the first wiring layer is, for example, a ring power supply connected to the macro cell and supplying a power supply potential (VDD) and a ground potential (VSS) to the macro cell. .
[0012]
In a second wiring layer different from the first wiring layer, the second power supply wiring disposed inside the macro and electrically connected to the first power supply wiring is, for example, connected to a macro cell and connected to the macro cell. It is a macro internal power supply for supplying any of a power supply potential (VDD) and a ground potential (VSS).
[0013]
The arrangement of the third power supply line in the overlapping area of the first power supply line and the second power supply line may be the same as the overlapping area of the third power supply line or a part of the third power supply line. Alternatively, the entirety may be included in the overlapping area, or the third power supply wiring may include part or all of the overlapping area.
[0014]
According to the present invention, in a third wiring layer different from the first wiring layer and the second wiring layer, the first power wiring and the second power wiring are arranged in an overlapping area, and Since the third power supply wiring electrically connected to the first power supply wiring is provided, no bending occurs when wiring the enhanced power supply of the basic cell to the third wiring layer using the automatic placement and routing tool. Then, it extends straight and is connected to the third power supply wiring.
[0015]
(2) The semiconductor device of the present invention comprises:
The third wiring layer includes a strengthened power supply line electrically connected to the third power supply line and extending in a direction perpendicular to the third power supply line to supply a potential to a basic cell. .
[0016]
(3) The semiconductor device of the present invention comprises:
A plurality of power supply wirings for supplying a power supply potential and power supply wirings for supplying a ground potential are alternately arranged as the second power supply wiring, and correspond to the plurality of power supply wirings for supplying the power supply potential and the power supply wiring for supplying the reference potential. A plurality of the third power supply wiring provided as
The length of the given third power supply line in the longitudinal direction of the first power supply line is equal to or greater than the width of the second power supply line, and is electrically short-circuited with another adjacent third power supply line. The length is set to be equal to or less than a length that does not cause the occurrence.
[0017]
(4) The microcomputer of the present invention comprises:
A semiconductor device is formed using any of the above-described semiconductor devices.
[0018]
(5) The electronic device of the present invention includes:
The microcomputer described above,
Input means for data to be processed by the microcomputer,
Output means for outputting data processed by the microcomputer.
[0019]
(6) The wiring method for a semiconductor device according to the present invention includes:
A wiring method for a semiconductor integrated device including a basic cell region and a macro region, and having three or more wiring layers,
In the first wiring layer, wiring of the first power supply wiring arranged annularly around the macro region is performed,
In a second wiring layer different from the first wiring layer, wiring of a second power supply wiring arranged inside the macro and electrically connected to the first power supply wiring is performed;
In a third wiring layer different from the first wiring layer and the second wiring layer, the first power wiring and the electric power are connected to an overlapping area of the first power wiring and the second power wiring. Wiring of a third power supply wiring that is electrically connected.
[0020]
(7) The wiring method for a semiconductor device according to the present invention includes:
In the third wiring layer, wiring of an enhanced power supply electrically connected to the third power supply wiring and supplying a potential to a basic cell is performed by using an automatic placement and routing tool.
[0021]
(8) The wiring method for a semiconductor device according to the present invention includes:
A plurality of power supply wirings for supplying a power supply potential and power supply wirings for supplying a ground potential are alternately arranged as the second power supply wiring, and correspond to the plurality of power supply wirings for supplying the power supply potential and the power supply wiring for supplying the reference potential. A plurality of the third power supply wiring provided as
The length of the given third power supply line in the longitudinal direction of the first power supply line is equal to or greater than the width of the second power supply line, and is electrically short-circuited with another adjacent third power supply line. The length is set to be equal to or less than the length that does not cause the occurrence.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
1. Semiconductor Device Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the drawings.
[0023]
FIG. 1 is a diagram for describing a semiconductor device (IC chip) of the present embodiment.
[0024]
The semiconductor device 10 of the present embodiment has three or more wiring layers including the basic cell region 30 and the macro region 20.
[0025]
Here, 32 is a basic cell, 70 and 72 are peripheral power lines, and 74 and 76 are power lines connected to the peripheral power line and the basic cell. Reference numerals 40 and 42 denote a ring power supply 1 (VSS) (first power supply wiring) and a ring power supply 2 (VDD) (first power supply wiring) connected to cells inside the macro at the outer periphery of the macro area. Reference numerals 60 and 62 denote a macro internal power supply 1 (VSS) (second power supply wiring) and a macro internal power supply 2 (VDD) (second power supply wiring) connected to cells inside the macro. Reference numerals 50 and 52 denote reinforced power supply lines for supplying a power supply potential (VDD) and a ground potential (VSS) to the basic cell, respectively.
[0026]
FIGS. 2 to 5 are diagrams for explaining an enhanced power supply of the basic cell 32 which is drawn by an automatic placement and routing tool in a conventional semiconductor device.
[0027]
FIG. 2 is a plan view showing a state near a connection portion between the enhanced power supplies 50 ′-1 and 50 ′-2, the ring power supply 40, and the macro internal power supply 1 (VSS) 60.
[0028]
3 is a cross-sectional view of a main part taken along line aa of FIG. 2, FIG. 4 is a cross-sectional view of a main part taken along line bb of FIG. 2, and FIG. It is sectional drawing.
[0029]
3 to 5, reference numeral 110 denotes a macro area, 120 denotes a basic cell area, 130 denotes an insulating layer, and M1, M2, and M3 denote metal 1 layers (second wiring layers) and metal 2 layers (first wiring layers), respectively. , Three metal layers (third wiring layer), and B indicates a via.
[0030]
The ring power supplies 40 and 42 are wired to the metal 2 layer (first wiring layer) M2, and the macro internal power supply (VSS) 60 is wired to the metal 1 layer (second wiring layer) M1 (FIG. 3).
[0031]
When wiring the enhanced power supplies 50'-1 and 50'-2 to the metal 1 layer (second wiring layer) M1 and the metal 3 layer (third wiring layer) M3 using the automatic placement and routing tool, The reinforced power supply 50'-1 extends straight in the horizontal direction in the metal 1 layer (second wiring layer) M1 and is connected to the macro internal power supply 1 (VSS) 60 (see FIGS. 2 and 4).
[0032]
However, when the reinforced power supply 50'-2 is wired in the third metal layer (third wiring layer) M3, bending occurs (see 70 in FIG. 2). This is because when the wiring of the enhanced power supply 50'-2 is performed by using the automatic placement and routing tool, the metal layers are electrically connected via the vias B over three layers. This is because wiring is performed to avoid this.
[0033]
Therefore, in the third metal layer (third wiring layer) M3, the reinforced power supply 50′-2 is wired so as to be connected to the ring power supply 40 while avoiding the overlapping area of the ring power supply 40 and the macro internal power supply 60. The above-mentioned bending occurs.
[0034]
FIGS. 6 to 8 are diagrams for explaining the enhanced power supply of the basic cell drawn by the automatic placement and routing tool in the semiconductor device of the present embodiment.
[0035]
FIG. 6 is a plan view showing a state near a connection between the enhanced power supplies 50-1 and 50-2, the ring power supply 40, and the macro internal power supply 1 (VSS) 60.
[0036]
7 is a cross-sectional view of a main part taken along line dd of FIG. 6, and FIG. 8 is a cross-sectional view of a main part taken along line ee of FIG.
[0037]
7 and 8, reference numeral 110 denotes a macro area, 120 denotes a basic cell area, 130 denotes an insulating layer, and M1, M2, and M3 denote a metal 1 layer (second wiring layer) and a metal 2 layer (first wiring layer), respectively. , Three metal layers (third wiring layer), and B indicates a via.
[0038]
The ring power supplies 40 and 42 in FIG. 6 are wired to the metal 2 layer (first wiring layer) M2, and the macro internal power supply (VSS) 60 is wired to the metal 1 layer (second wiring layer) M1. (See FIG. 7).
[0039]
A characteristic configuration of the present embodiment is that a metal three layer (third wiring layer) M3 different from the metal two layer (first wiring layer) M2 and the metal one layer (second wiring layer) M1 includes: The ring power supply (first power supply wiring) 40 and the macro internal power supply wiring (second power supply wiring) 60 are arranged in an overlapping area, and are electrically connected to the ring power supply (first power supply wiring) 40 and vias 90. In that it has an auxiliary power supply wiring (third power supply wiring) 80 connected to the power supply.
[0040]
If the auxiliary power supply wiring 80 is present when wiring the enhanced power supplies 50-1 and 50-2 of the basic cell 32 using the automatic placement and routing tool, the enhanced power supply 50-2 is connected to the third metal layer (third wiring layer). When wiring is performed at M3, no bending occurs.
[0041]
Therefore, in the semiconductor device of the present embodiment, in the third metal layer (third wiring layer) M3, the enhanced power supply 50-2 extends in the horizontal direction and is connected to the auxiliary power supply wiring 80 (70 in FIG. 6, FIG. 8). reference).
[0042]
The enhanced power supply 50-1 extends straight in the horizontal direction in the metal 1 layer (second wiring layer) M1 and is connected to the macro internal power supply 1 (VSS) 60 (see FIGS. 6 and 8).
[0043]
As described above, according to the present invention, even when an automatic placement and routing tool is used, a design rule check error is less likely to occur because the enhanced power supply is drawn in a straight line. Therefore, it is not necessary to perform manual correction, and the work efficiency of wiring can be improved.
[0044]
In addition, it is possible to automatically prevent an increase in channel width used due to bending.
[0045]
FIG. 9 is a diagram for describing the length of the auxiliary power supply in the present embodiment in the vertical direction (the same direction as the longitudinal direction of the ring power supply).
[0046]
Reference numeral 310 denotes a macro internal power supply 1 (second power supply wiring) for supplying a power supply potential (VDD), and reference numeral 320 denotes a macro internal power supply 2 (second power supply wiring) for supplying a ground (reference) potential (VSS). . In the present embodiment, a plurality of 310s and 320s are alternately arranged. Reference numerals 340 and 350 denote a plurality of auxiliary power supply wires (third power supply wires) provided corresponding to the macro internal power supply 1 (second power supply wiring) 310 and the macro internal power supply 2 (second power supply wiring) 320, respectively. is there.
[0047]
Here, the length of the auxiliary power supply wiring (third power supply wiring) 340 is equal to or more than the width (lmin) of the macro internal power supply 1 (second power supply wiring) 310 and is adjacent to another auxiliary power supply wiring (third power supply wiring). The length is set to a length (lmax) or less that does not cause an electrical short circuit with the wiring (350).
[0048]
Similarly, the length of the auxiliary power supply line (third power supply line) 350 is equal to or more than the width (lmin) of the macro internal power supply 2 (second power supply line) 320 and is adjacent to another auxiliary power supply line (third power supply line). The length is set to a length (lmax) or less that does not cause an electrical short circuit with the wiring 340.
[0049]
When it is difficult to secure the power supply width of the macro internal power supply 1 (first power supply wiring) 310 or the macro internal power supply 2 (second power supply wiring) 320, even if the automatic placement and routing tool avoids the problem. The macro internal power supply 1 (first power supply wiring) 310 or the macro internal power supply 2 (second power supply wiring) 320 may be created so that a design check error does not occur.
[0050]
FIGS. 10 and 11 are diagrams for explaining the length of the auxiliary power supply in the present embodiment in the lateral direction (the direction perpendicular to the longitudinal direction of the ring power supply).
[0051]
FIG. 10 is a plan view showing a state in the vicinity of a connection portion between the enhanced power supplies 50-1 and 50-2, the ring power supply 40, and the macro internal power supply 1 (VSS) 60. FIG. It is principal part sectional drawing.
[0052]
As shown in FIGS. 10 and 11, the lateral direction (direction perpendicular to the longitudinal direction of the ring power supply) 442 of the auxiliary power supply wiring (third power supply wiring) 440 may extend in the macro internal direction.
[0053]
2. Microcomputer FIG. 12 is an example of a hardware block diagram of the microcomputer of the present embodiment.
[0054]
The microcomputer 700 includes a CPU 510, a cache memory 520, a memory management unit (MMU) 730, an LCD controller 530, a reset circuit 540, a programmable timer 550, a real-time clock (RTC) 560, a DMA controller F570, an interrupt controller 580, and a communication control circuit. 590, a bus controller 600, an A / D converter 610, a D / A converter 620, an input port 630, an output port 640, an I / O port 650, a clock generator 560, a prescaler 570, and various buses 680 connecting them. , Various pins 690 and the like.
[0055]
Here, the microcomputer 700 is formed using, for example, a semiconductor device having the configuration described with reference to FIGS.
[0056]
3. Electronic Device FIG. 13 shows an example of a block diagram of an electronic device of the present embodiment. The electronic device 800 includes a microcomputer (or ASIC) 810, an input unit 820, a memory 830, a power generation unit 840, an LCD 850, and a sound output unit 860.
[0057]
Here, the input unit 820 is for inputting various data. The microcomputer 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power supply generation unit 840 is for generating various power supplies used in the electronic device 800. The LCD 850 is for outputting various images (characters, icons, graphics, and the like) displayed by the electronic device. The sound output unit 860 is for outputting various sounds (sounds, game sounds, etc.) output from the electronic device 800, and its function can be realized by hardware such as a speaker.
[0058]
Here, the microcomputer (or ASIC) 810 has a configuration as described with reference to FIG. 12, for example.
[0059]
FIG. 14A illustrates an example of an external view of a mobile phone 950 which is one of electronic devices. The mobile phone 950 includes a dial button 952 functioning as an input unit, an LCD 954 displaying a telephone number, a name, an icon, and the like, and a speaker 956 functioning as a sound output unit and outputting sound.
[0060]
FIG. 14B illustrates an example of an external view of a portable game device 960 which is one of the electronic devices. The portable game device 960 includes an operation button 962 functioning as an input unit, a cross key 964, an LCD 966 displaying a game image, and a speaker 968 functioning as a sound output unit and outputting game sounds.
[0061]
FIG. 14C illustrates an example of an external view of a personal computer 970 which is one of electronic devices. The personal computer 970 includes a keyboard 972 functioning as an input unit, an LCD 974 for displaying characters, numbers, graphics, and the like, and a sound output unit 976.
[0062]
14A, 14B, and 14C, a portable information terminal, a pager, an electronic desk calculator, a device including a touch panel, and the like. Various electronic devices using an LCD, such as a projector, a word processor, a viewfinder type or a monitor direct-view type video tape recorder, and a car navigation device can be considered.
[0063]
The present invention is not limited to the present embodiment, and various modifications can be made within the scope of the present invention.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a semiconductor device (IC chip) according to an embodiment.
FIG. 2 is a plan view showing a state in the vicinity of a connection portion between a conventional enhanced power supply, a ring power supply, and a macro internal power supply 1 (VSS).
FIG. 3 is a sectional view of a principal part taken along line aa of FIG. 2;
FIG. 4 is a sectional view of an essential part taken along line bb of FIG. 2;
FIG. 5 is a sectional view of a principal part taken along line cc of FIG. 2;
FIG. 6 is a plan view showing a state near a connection portion between an enhanced power supply, a ring power supply, and a macro internal power supply 1 (VSS) according to the present embodiment.
FIG. 7 is a sectional view of a main part taken along line dd of FIG. 6;
FIG. 8 is a sectional view of a principal part taken along line ee in FIG. 6;
FIG. 9 is a diagram for describing the length of the auxiliary power supply in the present embodiment in the vertical direction (the same direction as the longitudinal direction of the ring power supply).
FIG. 10 is a diagram for describing a lateral length (a direction perpendicular to the longitudinal direction of the ring power supply) of the auxiliary power supply according to the present embodiment;
11 is a sectional view of a main part taken along line ff of FIG. 10; FIG. 12 is an example of a hardware block diagram of a microcomputer according to the present embodiment;
FIG. 13 illustrates an example of a block diagram of an electronic device including a microcomputer.
FIGS. 14A, 14B, and 14C are examples of external views of various electronic devices.
[Explanation of symbols]
10 semiconductor device, 20 macro area, 30 basic cell area,
32 basic cells, 40 ring power supply 1 (VSS)
42 Ring power supply 2 (VDD), 50, 52 Enhanced power supply wiring 60 Macro internal power supply 1 (VSS), 62 Macro internal power supply 2 (VDD)
70, 72 peripheral power wiring, 74, 76 peripheral power wiring 80 auxiliary power wiring (third power wiring), 90 via, 110 macro area 120 basic cell area, 130 insulating layer,
M1 metal 1 layer (second wiring layer), M2 metal 2 layer (first wiring layer),
M3 metal 3 layer (third wiring layer), 500 microprocessor,
510 CPU, 520 cache memory, 530 LCD controller 540 reset circuit, 550 programmable timer,
560 real-time clock (RTC), 570 DMA controller,
580 interrupt controller, 590 communication control circuit,
600 bus controller, 610 A / D converter, 620 D / A converter 630 input port, 640 output port, 650 I / O port,
660 clock generator (PLL), 670 prescaler,
680 various buses, 690 various pins, 700 microcomputers,
710 ROM, 720 RAM, 730 MMU, 800 Electronic equipment

Claims (8)

A semiconductor integrated device including a basic cell region and a macro region, and having three or more wiring layers,
A first power supply wiring arranged in a ring shape around the macro region in the first wiring layer;
In a second wiring layer different from the first wiring layer, a second power supply wiring arranged inside the macro and electrically connected to the first power supply;
A third wiring layer different from the first wiring layer and the second wiring layer, the first power wiring being arranged in an overlapping area of the first power wiring and the second power wiring; A third power supply wiring electrically connected to
A semiconductor device comprising: In claim 1,
The third wiring layer includes a strengthened power supply line electrically connected to the third power supply line and extending in a direction perpendicular to the third power supply line to supply a potential to a basic cell. Semiconductor device. In any one of claims 1 and 2,
A plurality of power supply wirings for supplying a power supply potential and power supply wirings for supplying a ground potential are alternately arranged as the second power supply wiring, and correspond to the plurality of power supply wirings for supplying the power supply potential and the power supply wiring for supplying the reference potential. A plurality of the third power supply wiring provided as
The length of the given third power supply line in the longitudinal direction of the first power supply line is equal to or greater than the width of the second power supply line, and is electrically short-circuited with another adjacent third power supply line. Wherein the length is set to be equal to or less than a length that does not cause the problem. A microcomputer formed using the semiconductor device according to claim 1. A microcomputer according to claim 4,
Input means for data to be processed by the microcomputer,
Output means for outputting data processed by the microcomputer. A wiring method for a semiconductor integrated device including a basic cell region and a macro region, and having three or more wiring layers,
In the first wiring layer, wiring of the first power supply wiring arranged annularly around the macro region is performed,
In a second wiring layer different from the first wiring layer, wiring of a second power supply wiring arranged inside the macro and electrically connected to the first power supply wiring is performed;
In a third wiring layer different from the first wiring layer and the second wiring layer, the first power wiring and the electric power are connected to an overlapping area of the first power wiring and the second power wiring. A wiring method for a semiconductor device, wherein wiring of a third power supply wiring, which is electrically connected, is performed. In claim 6,
A wiring method for a semiconductor device, wherein wiring of an enhanced power supply electrically connected to the third power supply wiring and supplying a potential to a basic cell in the third wiring layer is performed using an automatic placement and routing tool. . In any one of claims 6 and 7,
A plurality of power supply wirings for supplying a power supply potential and power supply wirings for supplying a ground potential are alternately arranged as the second power supply wiring, and correspond to the plurality of power supply wirings for supplying the power supply potential and the power supply wiring for supplying the reference potential. A plurality of the third power supply wiring provided as
The length of the given third power supply line in the longitudinal direction of the first power supply line is equal to or greater than the width of the second power supply line, and is electrically short-circuited with another adjacent third power supply line. A wiring method for a semiconductor device, wherein the length is set to be equal to or less than a length that does not cause a problem.

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