JP2001345384A - Semiconductor integrated circuit device and its layout method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a layout method for laying out memories of a desirable capacity in a memory layout desirable area when a usable gate region is restricted in a semiconductor integrated circuit device in which a hard macro and a usable gate are mixedly present; and the semiconductor integrated circuit device laid out by the layout method. SOLUTION: This is a layout method of a semiconductor integrated circuit device in which a hard macro and a usable gate are mixedly present. When the shape of a memory layout desirable area in a usable gate area does not agree with the shape of a memory of a desirable capacity to be laid out in the memory layout desirable area, the memory of the desirable capacity is divided into a plurality of memories of a smaller shape which can be laid out in the memory layout desirable area, and the plurality of divided memories are laid out in the memory layout desirable area. Incidentally, the layout may be carried out by dividing into (n) equal divisions (n: a natural number).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a layout method thereof, and more particularly, to a semiconductor integrated circuit device in which a memory to be integrated is divided and arranged, and a layout method thereof.

[0002]

2. Description of the Related Art In recent years, the demand for ICs capable of realizing high functions with one chip has increased due to high integration. Here, from the demand for high-speed equipment, AS
There is a high need for custom ICs called ICs. However, since custom ICs have a high development load such as a period required for development, cost, and personnel, semi-custom ICs that are easy to design and have a short development period have been rapidly gaining importance in recent years in order to reduce the development load.

[0003] The embedded cell array is one of the recently developed methods of developing a semi-custom IC, and has features of a gate array and a standard cell. Basic cells are arranged in the logic gate region in advance, but a hard macro at a functional block level can be arranged in advance.

Therefore, when the logic design has progressed to a certain extent, a hard macro cell at the gate scale or a functional block level to be specified is predicted, a master layout is performed, and after the master layout is completed, a master process is performed in parallel with the circuit design. Can proceed.

The applicant of the present application has mounted a CPU core and the like as a large hard macro by using an embedded cell array technique, and further integrated a controller and a memory corresponding to various functions of an electronic device to be mounted in a usable gate area. We are developing functional one-chip ICs.

FIGS. 1A and 1B are diagrams for explaining an example of a layout of a memory arrangement on an embedded cell array.

When a large hard macro 30 such as a CPU core is arranged on the IC 10 as shown in FIG. 1A, the usable gate region 20 becomes a narrow L-shaped region.

Here, for example, when a predetermined memory use module 40 is arranged in the usable gate area 20, it is necessary to arrange a memory accessed by the memory use module 40 in a nearby empty area 50 from the viewpoint of wiring efficiency. Is also preferred.

However, in the case shown in FIG. 1A, the memory 60 having a desired capacity used by the memory use module 40 cannot be arranged in the memory arrangement desired area 50 as it is.

As described above, in a semiconductor integrated circuit device (one-chip IC) in which a hard macro and a usable gate are mixed, as the area occupied by the hard macro becomes larger, the usable gate region 20 becomes relatively narrower, and the memory arrangement desired area 50 becomes larger. May not be able to arrange the memory 60 having the desired capacity.

In such a case, as shown in FIG. 1B, the memory arrangement position must be changed to another area having a free area in which the memory can be arranged (see 60 ').

Generally, the desired area for memory arrangement is determined to be an optimum position based on the position of the memory use module and the terminal.

Therefore, if the memory arrangement position is changed from the memory arrangement desired area to another area, it is necessary to route the wiring and the like, and there are many disadvantages in wiring efficiency, man-hours and the like.

The present invention has been made in view of the above technical problems, and an object of the present invention is to limit a usable integrated gate region in a semiconductor integrated circuit device in which a hard macro and a usable gate are mixed. It is an object of the present invention to provide a layout method for arranging a memory of a desired capacity in a memory arrangement desired area in a case where there is, and a semiconductor integrated circuit device arranged by the layout method.

[0015]

SUMMARY OF THE INVENTION The present invention relates to a layout method for a semiconductor integrated circuit device in which a hard macro and a usable gate are mixed. When the shape of the memory having the desired capacity to be arranged does not match, the memory having the desired capacity is divided into a plurality of memories having a smaller shape which can be arranged in the memory arrangement desired area, and the divided plurality of memories are divided. Is arranged in the memory arrangement desired area.

A semiconductor integrated circuit device in which a hard macro and a usable gate are mixed includes, for example, a semi-custom IC such as an embedded cell array.

The useable gate is an area that can be freely designed by the user according to his or her own specifications. For example, an area where basic cells or the like are arranged in advance and the user can wire with a desired library. is there.

Here, division refers to a case where signals necessary for memory access are commonly used, and refers to, for example, a case where it can be physically handled as a single memory when viewed from a memory using module.

The divided memory may be, for example, a RAM or a ROM.

The memory may be divided so that the divided memories have the same capacity, or may be divided so that the divided memories have different capacities.

The memory may be divided into a plurality of regions either in the region divided in the width direction of one data line or in the address direction.

The optimum area for the memory arrangement is determined by the position of the memory using module that uses the memory, the position of the terminal to which the memory is connected, and the like.

The case where the memory arrangement of the usable gate area does not match the shape of the memory having the desired capacity to be arranged in the memory arrangement desired area means that the shape of the memory arrangement area differs from the shape of the memory having the desired capacity. In some cases, even if the shapes are the same, the memory cannot be arranged due to the directional restrictions on the memory arrangement.

However, according to the present invention, even if there is no free area of an appropriate shape and orientation in the desired area for memory arrangement,
The memory can be divided into a plurality of smaller-sized memories that can be arranged in the desired memory arrangement area, and the divided memories can be arranged in the desired memory arrangement area.

Therefore, it is not necessary to route the wiring as in the case where the arrangement position of the memory is changed, and it is possible to avoid disadvantages such as a decrease in wiring efficiency and an increase in man-hours.

Further, since wiring and the like are not required, there is a merit that a usable area increases.

Further, in the layout method of the present invention, the memory having the desired capacity is divided into n equal parts (n is a natural number) so that the capacity of each memory after division becomes equal, and It is characterized by being arranged.

According to the present invention, since the capacity of each divided memory is equal, the design and arrangement are facilitated.

Further, in the layout method of the present invention, the memory divided into two equal parts are arranged adjacent to each other in line symmetry, and the signal lines common to the two divided memories among the signal lines necessary for memory access are adjacent to each other. Wiring is provided as a common signal line between two memories, and a signal line is drawn into each memory from a common signal line between two adjacent memories.

The line-symmetric arrangement means, for example, a case where two memories are laid out in a mirror shape in a library.

The common signal line is a signal line commonly used by the two memories, such as an address line, a data line, and other control signal lines necessary for memory access.

For example, when dividing in the width direction of one data line, a signal line in which an address line and a control signal line are shared by each divided memory is used. In the case of dividing in the address direction, each divided memory is used. , The data line, the lower address line and the control signal line become a common signal line.

As in the present invention, the memory divided into two equal parts are arranged side by side in a line-symmetric manner, and two signal lines common to the two divided memories out of the signal lines necessary for memory access are adjacent to each other. By wiring as a common signal line between the memories and drawing the signal line from the common signal line between the two adjacent memories to each memory, the section where the common portion of the signal line can be shared by the two memories becomes longer. Wiring efficiency is improved.

In the layout method of the present invention, the divided memories are arranged side by side in a predetermined direction, and the signal lines used for memory access are arranged so as to be adjacent to one side of each of the divided memories. The common signal lines are wired in parallel to the direction, and the signal lines for drawing signals from the common signal lines to the respective memories are wired so as to be substantially perpendicular to the common signal lines.

Here, a signal line for drawing a signal from the common signal line to each memory is arranged so as to be substantially perpendicular to the common signal line. Includes any case where wiring is performed by

According to the present invention, the wiring efficiency of the memory divided into two or more can be improved.

According to the present invention, there is also provided a semiconductor integrated circuit device in which a hard macro and a usable gate are mixed, wherein a memory having a desired capacity which does not conform to the shape of the desired memory arrangement area of the usable gate region is provided. The memory is divided into a plurality of smaller-sized memories that can be arranged in a desired area and arranged in the memory arrangement desired area.

Further, the semiconductor integrated circuit device of the present invention is divided into n equal parts (n is a natural number) such that the memory having the desired capacity becomes a plurality of memories of a smaller shape which can be arranged in the memory arrangement desired area. In the memory arrangement desired area.

In the semiconductor integrated circuit device according to the present invention, halved memories are arranged adjacent to each other in line symmetry, and two of the signal lines necessary for memory access are divided.
A signal line common to two memories is wired as a common signal line between two adjacent memories, and a signal line is drawn into each memory from a common signal line between two adjacent memories. .

Further, in the semiconductor integrated circuit device of the present invention, the divided memories are arranged side by side in a predetermined direction, and the signal lines used for memory access are arranged adjacent to one side of each divided memory. And a signal line for drawing a signal from the common signal line to each memory is arranged so as to be substantially perpendicular to the common signal line.

According to the present invention, there is provided a microcomputer formed using any one of the above semiconductor integrated circuit devices, wherein a CPU core is formed as the hard macro.

Further, an electronic apparatus according to the present invention includes the microcomputer, input means for data to be processed by the microcomputer, and output means for outputting data processed by the microcomputer. Features.

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION Semiconductor Integrated Circuit Device Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIGS. 2A and 2B are diagrams for explaining an example of the layout method according to the present embodiment.

Reference numeral 110 denotes an IC (semiconductor integrated circuit device) in which the hard macro 120 and the usable gate 160 are mixed. Here, for example, the memory use module 130
140 near the memory allocation area is the area where
Is a memory having a desired capacity to be arranged in the memory arrangement desired area.

However, since the shape of the memory 150 having the desired capacity to be arranged in the memory arrangement desired area 140 does not conform to the shape of the memory arrangement desired area 140, the memory 150 having the desired capacity is directly stored in the memory arrangement desired area. 140 (see FIG. 2A).

In this case, in this embodiment, the memory 150 having a desired capacity is replaced with a plurality of smaller memories 150-.
1, 150-2, and the memory arrangement desired area 140
(See FIG. 2B).

By dividing the memory 150 having a desired capacity into a plurality of smaller-sized memories 150-1 and 150-2, it is possible to arrange the memory 150 having a desired capacity to be accessed by the memory using module. It can be located in area 140. The division is not limited to the case of dividing into two, but may be the case of dividing into n (n is a natural number of 2 or more). Further, it may be divided into equal parts or divided into different capacities.

When a memory having a desired capacity is divided and arranged, the divided memories do not necessarily have to be arranged next to each other.

FIGS. 3A and 3B are diagrams for explaining another example of the layout method of the present embodiment.

As shown in FIG. 3A, a number of hard macros 220-1 to 220-
When 5 is arranged, the shape and size of the usable gate are limited, so that a desired memory arrangement area 240 of a large space may not be secured. In such a case, a plurality of divided memories 250-1 and 250-2 may be arranged at remote positions as shown in FIG.

FIGS. 4A and 4B are diagrams for explaining the division mode.

FIG. 4A shows a state where the memory is inserted in the data width direction 310.
This is a case where data is divided into data (a case where data is divided). For example, a 16-bit width RAM 320 is replaced with an 8-bit width RAM-
A (330) and RAM-B (340). As shown in the figure, the 0th to 7th bits of the first data line are allocated to the RAM-B (320),
The fifth bit is allocated to the RAM-A (330).

In this case, RAM-A (330) and R
Each corresponding line of AM-B (340) will have the same address.

FIG. 4 (B) shows the memory in the address width direction 36.
This is a case where the data is divided into 0 (when divided by an address).
For example, from address 00000 to address 11111 R
AM 370 is changed from address 00000 to address 011.
The data is divided into 11 RAM-A (380) and RAM-B (370) at address 11111 from address 10000.

FIGS. 5 and 6 are diagrams for explaining the input / output relationship of data before and after division when the RAM is divided by data.

As shown in FIG. 5, in the RAM 320 before division, a chip select signal 321, a read control 322, a read address 32
3, write control 324, write address 325, and input data 326 are input, and output data 327 is output.

RAM-A (330) and RAM-B
After division into (340), as shown in FIG. 6, the chip select signal 321, the read control 322, and the read address 3
23, the write control 324, and the write address 325 are signals common to the two RAMs.

The RAM-A (330) and the RAM-A
Since B (340) is divided into data, 8 to 15 bits of the input data are input to RAM-A (326-
1), and 8 to 15 bits are input to the RAM-B (see 326-2).

The output data of 8 to 15 bits is stored in RAM.
-A (see 327-1) and 8 to 15 bits are output from RAM-B (see 327-2).

As described above, the case where the memory is divided in the present embodiment refers to the case where a part of signals necessary for memory access is commonly used, and when viewed from a memory using module, a physically single memory is used. Means that it can be handled as

Next, a layout method concerning the arrangement and wiring of the divided memories will be described.

FIG. 7 is a diagram for explaining a layout method relating to the arrangement and wiring of a memory divided into two equal parts by data.

RAM-A (330) and RAM-B
(340) is obtained by dividing a RAM (320) having a desired capacity into two equal parts by data.

In the present embodiment, as shown in FIG.
-A (330) and RAM-B (340) are arranged side-by-side and symmetrically. In this case, since the data is divided by the data, the address 41 out of the signals necessary for the memory access is used.
0, R / W control signal 420, chip select signal 430
Are common to the RAM-A (330) and the RAM-B (340).

Therefore, the address line 410, the R / W control signal line 420, and the chip select signal line 430 are connected to the RAM-A
(330) and the RAM-B (340) are wired as a common signal line, and as shown in FIG.
0, 420, 430 to RAM-A (330) and R
A signal line is drawn into AM-B (340).

In this way, for the common signal, 2
Since the section that can be shared by two memories becomes longer, the wiring efficiency is improved.

FIG. 8 is a diagram for explaining a layout method relating to the arrangement and wiring of a memory divided into two equal parts by addresses.

RAM-A (380) and RAM-B
(390) is obtained by dividing a RAM (370) having a desired capacity into two equal parts by data.

In the present embodiment, as shown in FIG.
-A (380) and RAM-B (390) are placed side-by-side and symmetrically. In this case, since the data is divided by the address, the lower address 412, the R / W control signal 420, and the data 440 among the signals required for memory access are RA.
It is common to MA (380) and RAM-B (390).

Therefore, the lower address 412, the R / W control signal 420, and the data 440 are wired as common signal lines between the RAM-A (380) and the RAM-B (390).
As shown in FIG. 6, the common signal lines 412, 420, 44
0 to RAM-A (380) and RAM-B (39)
0) lead the signal line.

In this way, for the common signal, 2
Since the section that can be shared by two memories becomes longer, the wiring efficiency is improved.

The RAM-A (380) and the RAM-A
Since B (390) is divided into two equal parts by the address, the value of the upper address determines which RAM is selected. Therefore, the upper address 414 is used as a chip select signal.

FIGS. 9A and 9B are diagrams for explaining a layout method for arrangement and wiring when a memory is divided into two or more.

As shown in FIG. 9A, the RAM 500 is moved in the data width direction by the RAM-A (510) and the RAM-B (5).
20), RAM-C (530), RAM-D (540)
An example of arrangement and wiring in the case of dividing into four (in the case of dividing by data) will be described.

As shown in FIG. 9B, the RAM-A (51
0), RAM-B (520), RAM-C (530),
The RAM-D (540) is arranged in a predetermined direction. A chip select signal line 610, R, which is a signal used for memory access with the RAM using module 600.
/ W control signal line 620, address signal 630, and data signal 640 are transferred to RAM-A (510) and RAM-B (52).
0), a common signal line is wired in parallel with the memory arrangement direction 550 so as to be adjacent to one side of the RAM-C (530) and the RAM-D (540), and a signal is sent from the common signal line to each memory. The signal lines to be drawn in are arranged so as to be substantially perpendicular to the common signal lines.

In this case, the section sharing the common part of the signal lines becomes longer, so that the wiring efficiency is improved.

2. FIG. 10 shows a CP of the microcomputer according to the present embodiment.
It is an example of a hardware block diagram of a U core.

The microcomputer 1700 has a CP
U1510, reset circuit 1540, programmable timer 1550, real-time clock (RTC) 156
0, DMA 1570, interrupt controller 1580,
Serial interface 1590, bus controller 1600, A / D converter 1610, D / A converter 162
0, input port 1630, output port 1640, I / O
It includes a port 1650, a clock generator 1560, a prescaler 1570, a RAM 1720, various buses 1680 connecting them, and various pins 1690.

Here, these circuits are configured as a hard macro on the IC (semiconductor integrated circuit device) of the present embodiment.

3. Electronic Device FIG. 11 illustrates an example of a block diagram of an electronic device of this embodiment. The electronic device 800 includes a character display control unit 8
10, input unit 820, memory 830, power generation unit 84
0, an image output unit 850 and a sound output unit 860.

Here, the input section 820 is for inputting various data. The character display control unit 810 uses the character display control device of the present embodiment, and performs various processes based on data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like.
The power supply generation unit 840 is for generating various power supplies used in the electronic device 800. Image output unit 850
Indicates various images (characters, icons,
Graphics, etc.).

The sound output section 860 is for outputting various sounds (voices, game sounds, etc.) output from the electronic device 800, and its function can be realized by hardware such as a speaker.

FIG. 12A shows an example of an external view of a mobile phone 950 which is one of electronic devices. This mobile phone 950
Is a dial button 952 that functions as an input unit, and an LCD 954 that displays telephone numbers, names, icons, and the like.
And a speaker 95 that functions as a sound output unit and outputs sound.
6 is provided.

FIG. 12B shows an example of an external view of a portable game device 960 which is one of the electronic devices. The portable game device 960 includes an operation button 962 functioning as an input unit, a cross key 964, an image output unit 966 displaying a game image, and a speaker 968 functioning as a sound output unit and outputting game sounds.

FIG. 12C shows an example of an external view of a portable information device (PDA) 970 which is one of the electronic devices. The portable information device (PDA) 970 includes a keyboard 972 functioning as an input unit, an image output unit 974 for displaying characters, numbers, graphics, and the like, and a sound output unit 976.

The electronic apparatus to which the present embodiment can be applied is, in addition to those shown in FIGS. 12A, 12B and 12C, an apparatus having a personal computer, a pager, an electronic desk calculator, and a touch panel. , A projector, a word processor, a viewfinder type or a monitor direct-view type video tape recorder, and an electronic device such as a car navigation device.

Note that the present invention is not limited to this embodiment,
Various modifications can be made within the scope of the present invention.

In this embodiment, an example has been described in which the memory is divided into n equal parts so that the divided memories have the same capacity. However, the present invention is not limited to this. For example, it may be a case of dividing into a plurality of memories of different capacities.

Further, in the present embodiment, the case where the RAM is divided has been described as an example, but the present invention is not limited to this. For example, RO
M may be divided into a plurality.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams for explaining an example of a layout of a memory arrangement on an embedded cell array; FIGS.

FIGS. 2A and 2B are diagrams for explaining an example of a layout method according to the embodiment; FIGS.

FIGS. 3A and 3B are diagrams for explaining another example of the layout method according to the embodiment; FIGS.

FIGS. 4A and 4B are diagrams for explaining a mode of division.

FIG. 5 is a diagram illustrating an input / output relationship of data before and after division when a RAM is divided by data.

FIG. 6 is a diagram for explaining an input / output relationship of data before and after division when a RAM is divided by data.

FIG. 7 is a diagram for explaining a layout method regarding the arrangement and wiring of a memory divided into two equal parts by data;

FIG. 8 is a diagram for explaining a layout method for arrangement and wiring of a memory divided into two equal parts by an address;

FIGS. 9A and 9B are diagrams for explaining a layout method regarding arrangement and wiring when a memory is divided into two or more.

FIG. 10 is an example of a hardware block diagram of a microcomputer of the present embodiment.

FIG. 11 illustrates an example of a block diagram of an electronic device of this embodiment.

FIGS. 12A, 12B, and 12C are examples of external views of various electronic devices.

[Explanation of symbols]

 110 IC 120 Hard macro 130 Memory use module 140 Memory arrangement desired area 150 Memory of desired capacity 150-1 and 150-2 Divided memory 310 Data width direction 320 RAM 321 Chip select signal 322 Read control 323 Read address 324 Write control 325 Write address 326, 326-1, 326-2 Input data 327, 327-1, 327-2 Output data 330 RAM-A 340 RAM-B 360 Address direction 370 RAM 380 RAM-A 390 RAM-B 410 Address line 412 Lower address line 414 Upper address line 420 R / W control signal 430 Chip select signal 500 RAM 510 RAM-A 520 RAM-B 530 RAM-C 540 RAM-D 600 AM use module 610 Chip select signal 620 R / W control signal 630 Address 640 Data 800 Electronic device 810 Character display control unit 820 Input unit 830 Memory 840 Power generation unit 850 Image output unit 860 Sound output unit 1500 Microprocessor 1510 CPU 1520 Cache device 1540 Reset circuit 1550 Programmable timer 1560 Real-time clock (RTC) 1570 DMA 1580 Interrupt controller 1590 Serial interface 1600 Bus controller 1610 A / D converter 1620 D / A converter 1630 Input port 1640 Output port 1650 I / O port 1560 Clock generator (PLL) 1670 Prescaler 1680 Various buses 1690 Various pins 1700 microcomputer 1710 ROM 1720 RAM

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/822 H01L 27/04 U

Claims (10)

[Claims] 1. A layout method for a semiconductor integrated circuit device in which a hard macro and a usable gate are mixed, wherein a shape of a memory arrangement desired area of a usable gate area and a desired capacity to be arranged in the memory arrangement desired area are provided. If the shape of the memory does not match, the memory having the desired capacity is divided into a plurality of smaller-sized memories that can be arranged in the memory arrangement desired area, and the divided memories are divided into the memory arrangement desired. A layout method characterized by being arranged in an area. 2. The memory according to claim 1, wherein the memory having the desired capacity is divided into n equal parts (n is a natural number) so that the respective memories after division become equal in size, and are arranged in the desired memory arrangement area. And a layout method. 3. The memory device according to claim 1, wherein the divided memories are arranged symmetrically adjacent to each other, and two of the signal lines necessary for memory access are divided.
A layout method characterized in that a signal line common to two memories is wired as a common signal line between two adjacent memories, and a signal line is drawn into each memory from a common signal line between two adjacent memories. 4. The memory according to claim 1, wherein the divided memories are arranged side by side in a predetermined direction, and a signal line used for memory access is adjacent to one side of each of the divided memories. A common signal line parallel to a memory arrangement direction, and a signal line for drawing a signal from the common signal line to each memory is arranged so as to be substantially perpendicular to the common signal line. Method. 5. A semiconductor integrated circuit device in which a hard macro and a usable gate are mixed, wherein a memory having a desired capacity which does not conform to the shape of the desired memory arrangement area of the usable gate area is provided in the desired memory arrangement area. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is divided into a plurality of smaller-sized memories that can be arranged and arranged in the desired memory arrangement area. 6. The memory according to claim 5, wherein the memory having the desired capacity is divided into n equal parts (n is a natural number) and arranged in the desired memory arrangement area so that the capacities of the divided memories become equal. And a semiconductor integrated circuit device. 7. The memory according to claim 5, wherein the equally divided memories are arranged adjacently and symmetrically with respect to each other, and are common to two divided memories among signal lines required for memory access. A semiconductor integrated circuit device, wherein a signal line is wired as a common signal line between two adjacent memories, and a signal line is drawn into each memory from the common signal line between the two adjacent memories. 8. The memory according to claim 5, wherein the divided memories are arranged in a predetermined direction, and a signal line used for memory access is adjacent to one side of each of the divided memories. Are arranged as common signal lines parallel to the arrangement direction of the memories, and signal lines for drawing signals from the common signal lines to the respective memories are arranged so as to be substantially perpendicular to the common signal lines. Semiconductor integrated circuit device. 9. A microcomputer formed using the semiconductor integrated circuit device according to claim 5, wherein a CPU core is formed as the hard macro. 10. A microcomputer according to claim 9, further comprising: input means for inputting data to be processed by said microcomputer; and output means for outputting data processed by said microcomputer. And electronic equipment.