JP3071617B2 - Semiconductor design method and semiconductor design device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device (LS)
I)), and a semiconductor design method for designing a semiconductor device in which logic circuits (cells) operating at different voltage levels are mixed.

2. Description of the Related Art Semiconductor devices such as LSIs mainly operate on a single power supply, and each logic circuit (cell) in the device is operated.
Operate at the same voltage level. However, in recent years, with the spread of portable personal computers and the like, the number of devices that use a battery as a power source has increased. For example, circuits that require constant power supply, such as a timer circuit, are operated at a low voltage in order to save power consumption. It is desirable. In addition, it is desirable that a circuit requiring a high-speed processing operation, such as an arithmetic circuit, be operated at a high voltage in terms of processing speed. Therefore, 1
There is a demand for a semiconductor device that realizes power saving and high-speed processing operation by mixing circuits having different operation voltage levels in one semiconductor device. In order to meet this demand, for example, a converter is incorporated in an I / O cell arranged at an I / O port to enable an interface with an external device having a different voltage level, and each circuit in the device has a plurality of circuits. It had to operate at different voltage levels.

[0003]

2. Description of the Related Art In general, a semiconductor device is designed by a CAD apparatus having various libraries for storing pattern data obtained by converting various design information into macros. In designing a semiconductor device in which a plurality of circuits (cells) having different operating voltage levels are mixed, a subdivision pattern for subdividing an internal cell region into a plurality of small regions is registered in a library, and based on the subdivision pattern. The internal cell area is subdivided into a plurality of small areas for each voltage level. Then, a layout method is adopted in which the arrangement position of the internal cell is freely selected on each set small area in a range where the operating voltage level of the internal cell and the voltage level of the small area correspond. For example, a chip pattern as shown in FIG. 7 is displayed on the display screen of the CAD device by the subdivision pattern function stored in the library. That is, the I /
The internal cell area 43 set inside the O cell area 42 is subdivided into a plurality of small areas 44 and 45 for each different type (two types in the figure) of voltage levels designated as shown in FIG. In the figure, the hatched small area 44 is set as a high voltage level area, and the unhatched small area 45 is set as a low voltage level area. Then, the internal cells of the high voltage level are freely arranged and set at appropriate positions on the small region 44, and the internal cells of the low voltage level are freely arranged and set at appropriate positions on the small region 45, thereby forming the internal cells. The layout is going on.

[0004]

According to this method, small areas 44 and 45 subdivided into a predetermined size and shape.
It was necessary to accommodate all of the internal cells inside and to lay out the layout efficiently. However, the small areas 44 and 45 are uniquely determined by the subdivision patterns registered in the library, and are not based on the size and shape of each internal cell. Small area 4
It was not always possible to efficiently lay out the layout within 4,45. In some cases, the internal cells to be accommodated cannot be accommodated in each of the small areas 44 and 45 in the middle of the layout work of the internal cells, so that the master and the package have to be changed. If you want to use a slightly larger master with room to prevent such master or package changes,
There is a problem that a large amount of useless space in which no internal cell is arranged is likely to be generated. In some cases, the position of the internal cell must be set at a position distant from the I / O cell to be connected. In this case, there is a possibility that the length of the wiring drawn from the internal cell becomes long and the circuit characteristics cannot be guaranteed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to design an internal cell in designing a semiconductor device in which a plurality of circuits operating at different voltage levels are mixedly mounted on one chip. It is an object of the present invention to provide a semiconductor design method and a semiconductor design apparatus which can efficiently lay out a semiconductor device.

[0006]

In order to achieve the above object, according to the first aspect of the present invention, a plurality of internal circuit sections operating at different voltage levels are mixedly mounted in an internal cell area of a chip, and the internal cell area is mounted on the chip. In a semiconductor design method for designing a semiconductor device in which a plurality of power supply wirings corresponding to the operating voltage levels of the internal circuit portions are provided on the periphery of the semiconductor device, a plurality of internal circuit portions operating at different voltage levels are logically designed in advance. First, the internal circuit units are classified for each voltage level, and further divided into groups each including an internal circuit unit having the same voltage level, and the cells constituting the internal circuit unit for each internal circuit unit of each group. If the cell arrangement area that can be accommodated is set in the internal cell area, and then a blank area where the basic cell is not arranged is set at the position corresponding to the boundary position of each cell arrangement area set next Moni power draw subjected to wire leads from the space portion to the power supply line to each cell layout region, and the internal circuit unit further advance logic designed to place set in the corresponding cell placement area.

According to a second aspect of the present invention, in the semiconductor design method according to the first aspect, the converter circuit section and the internal circuit section are logically designed in advance for each operating voltage level. To be placed in the internal cell area near the external terminal to be placed, and then place each cell placement area in the internal cell area where the converter circuit section was not placed.
The section is set near the converter circuit section having a relatively high connection density with the cells arranged in the cell arrangement area.

According to the third aspect of the present invention, a plurality of internal circuit sections operating at different voltage levels are mixedly mounted in the internal cell area of the chip, and the operating voltage level of each internal circuit section is set at the periphery of the internal cell area. 2. Description of the Related Art In a semiconductor design apparatus for designing a semiconductor device provided with a plurality of power supply wirings corresponding thereto, a size and an operating voltage level of an internal circuit portion which is logically designed in advance and arranged and set in an internal cell region are stored as cell data. A library and cells constituting the internal circuit unit are grouped into groups based on the cell data stored in the library, and a plurality of groups capable of accommodating the cells constituting the internal circuit unit for each internal circuit unit of each group. Cell placement area determining means for partitioning a cell placement area, and a base for deleting a basic cell existing at a position corresponding to a boundary position of the cell placement area. Cell deletion means, lead-in wiring setting means for applying power supply wiring from the power supply wiring to each cell placement area so as to correspond to the voltage level through a blank portion formed as a basic cell trace by the basic cell deletion means, and lead-in wiring setting And a cell arranging means for arranging and setting the cells of the internal circuit section in which the cell arranging area is set within a cell arranging area in which a predetermined voltage can be supplied via the power supply wiring provided by the means.

According to a fourth aspect of the present invention, in the semiconductor design apparatus according to the third aspect, the size and the operating voltage level of the converter circuit section are stored as converter cell data together with the cell data in the library. And a converter arrangement information storage unit for storing the position information of the external terminal corresponding to the external terminal position information as the external terminal position information, and arranging and setting the converter circuit unit in the internal cell area at a nearby position corresponding to each external terminal based on the external terminal position information. And a converter arranging means, wherein the cell arranging area determining means causes the cell arranging area to be set in the internal cell area other than the setting area of the converter circuit section arranged and set in the internal cell area by the converter arranging means. .

According to a fifth aspect of the present invention, in the semiconductor design apparatus of the third aspect, there is provided a converter layout position storage unit for storing layout position information for each operating voltage level of each converter circuit corresponding to the internal cell. The cell placement area determining means may partition the cell placement area in the vicinity of a converter circuit section having a relatively high connection density with cells to be placed in the cell placement area based on the placement position information stored in the converter placement position storage section. Set it.

[0011]

According to the first and third aspects of the present invention,
First, the internal circuit units operating at a plurality of different voltage levels are logically designed in advance. For each internal circuit section classified for each operating voltage level, a cell arrangement area is set in the internal cell area based on the size shape and number of cells constituting the internal circuit section. Power is supplied to each cell arrangement region via a power supply wiring from a power supply line provided in a blank portion set at a position corresponding to a boundary position of each cell arrangement region. Then, each of the internal logic circuit parts logically designed in advance is arranged and set in the corresponding cell arrangement area. Therefore, by dividing each cell arrangement area into a freely selected area in the internal cell area and arranging and setting each internal circuit section corresponding to each cell arrangement area, each cell of the internal circuit section can be efficiently used. It is possible to layout well. In addition, since the cell placement area is set in consideration of the size, the number, and the like of each internal circuit portion arranged and set in the area, the master and the package may be changed during the design stage. Disappears.

According to the second and fourth aspects of the present invention, the converter circuit section to be arranged in the internal cell region is logically designed in advance together with the internal circuit section. Then, first, each converter circuit section is arranged and set in an internal cell region located near a corresponding external terminal. Next, the cell arrangement region is set in the internal cell region where the converter circuit unit is not arranged. Therefore, even if the converter circuit section is arranged and set in the internal cell region, the cells of the internal circuit section can be efficiently laid out.

According to the second and fifth aspects of the present invention, each cell arrangement region is partitioned and set near a converter circuit portion having a relatively high connection density with cells arranged in the cell arrangement region. . Accordingly, the length of the wiring provided between the converter circuit section and the internal circuit section can be made relatively short, and the circuit characteristics can be almost guaranteed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will now be described with reference to FIGS.
Explanation will be given based on FIG. FIG. 2 shows a CA to which the present invention is applied.
It is a system configuration | structure figure of D apparatus. As shown in FIG. 2, a central processing unit (hereinafter, referred to as a CPU) 1, a memory 2, a keyboard (including a mouse or the like) 3, a printer 4, and a display 5 such as a CRT are connected to each other by a system bus 6. The CPU 1 operates based on predetermined program data stored in the memory 2. Memory 2
The program data to be executed by the CPU 1 and various data necessary for the execution of the program data are stored in advance, and processing results of the CPU 1 based on the program data are temporarily stored. Keyboard 3 is memory 2
Is used for selecting and inputting necessary data from a library or the like described later stored in the printer 4 or inputting an output command such as a processing result to the printer 4 or the display 5.

In the memory 2, a library 7, a layout database 8, a converter cell storage unit 9, an internal cell storage unit 10, and an area data storage unit 11 are set as shown in FIG. The library 7, the layout database 8, and the storages 9 to 11 are read from an external storage medium such as an optical disk into the memory 2 and stored therein.
The CPU 1 executes the processing flow shown in FIG. 1 based on the program data stored in the memory 2. That is, the CPU 1 executes the respective processing steps of the input units 12a and 12b, the cell classifying unit 13, the converter area determining unit 14, the internal circuit area determining unit 15, the deleted BC cell arranging unit 16, and the power supply wiring lead-in unit 17 based on the program data. They are executed sequentially.

In the CAD apparatus of this embodiment, as shown in the circuit diagram of FIG. 6, a logic circuit (cell) operating at two different voltage levels (for example, low voltage 3.3 V and high voltage 5 V) is provided on one chip. An LSI (large-scale integrated circuit) to be mixed is designed. Before the layout processing of each cell is performed by the CAD device, a logic design is performed in advance, and a low-voltage converter circuit section A1, a high-voltage converter circuit section A2, a low-voltage internal circuit section B1, Internal circuit section B2 for high voltage, I / O cell C1 for low voltage and I for high voltage
/ O cell C2 (all shown in FIG. 6) is set.

The library 7 includes converter circuit sections A1,
A2, each cell of the internal circuit units B1, B2, I / O
The size shape and cell type of the cells C1 and C2 are stored as cell data for each operating voltage level. The layout database 8 stores logic circuit data and external terminal position information. Converter cell storage 9
Stores only the converter cells A1 and A2 classified from the cell group stored in the library 7 by the cell classification unit 13. In the internal cell storage unit 10, the internal circuit units B1,
Only each cell constituting B2 is stored. The area data storage unit 11 includes a converter area determination unit 1
4 and the respective arrangement positions of the converter circuit units A1 and A2 and the internal circuit units B1 and B2 determined by the internal circuit region determination unit 15 are stored as region setting information. It should be noted that the layout database 8 contains FIG.
The layout information of the logic circuit designed by executing the processing flow shown in FIG.

Next, the functions of the CAD apparatus in the main processing steps of the processing steps 12 to 17 constituting the processing flow shown in FIG. 1 will be described. When the CAD apparatus executes the processing flow of FIG. 1, a chip pattern 18 (see FIGS. 3 and 4) serving as a base (base) for laying out cells and the like is displayed on the display unit 5.
Etc.) are displayed. The chip pattern 18 has I /
An O cell area 19 and an internal cell area 20 are set. The I / O cell area 19 is set along the periphery of the chip pattern 18, and the internal cell area 20 is set inside the I / O cell area.

In the I / O cell area 19, I / O cells C1,
C2 is arranged, and converter circuit sections A1, A2 and internal circuit sections B1, B2 are arranged in the internal cell region 20. In the internal cell region 20, a plurality of gate array portions 21 in which a number of basic cells BC (shown in FIG. 5) are arranged in a row are set. The internal cell area 2
A plurality of power supply wirings 22 and 23 and a grounding wiring 24 as shown in FIG. 5 for supplying a predetermined voltage corresponding to the operating voltage of the internal circuit units B1 and B2 are set along the periphery of 0. Further, a power supply wiring and a ground wiring (not shown) are similarly set in the I / O cell area 19.

The converter circuit sections A1 and A2 are gate arrays located near the corresponding I / O cells C1 and C2 arranged and set in the I / O cell area 19 based on the external terminal position information stored in the layout database 8. The layout is automatically set in the unit 21. The arrangement setting of the converter circuit units A1 and A2 by manual operation is also possible. In addition, cell arrangement regions 25 and 26 (shown in FIGS. 4 and 5), which will be described later,
1, the low-voltage cell arrangement area 25 is located near an area relatively connected to the low-voltage converter circuit section A1 based on the connection density of each of the operating voltage levels with the converter circuit sections A1 and A2 set to 1. The high-voltage cell arrangement area 26 is arranged and set near an area which is arranged and relatively connected to the high-voltage converter circuit part A2 in a relatively large number. It is also possible to set the arrangement of the cell arrangement areas 25 and 26 by manual operation. Further, a deleted BC cell is set in the library 7, and by setting the deleted BC cell, the basic cell BC in the gate array unit 21 at a position corresponding to the boundary between the cell arrangement areas 25 and 26 is deleted. It has become so.

A circuit designed by the CAD device is shown in a circuit diagram as shown in FIG.
In the O cells C1 and C2, converter circuit portions A1 and A2 and internal circuit portions B1 and B2 are arranged in the internal cell region 20, respectively. The external terminal 27a to which the low voltage level is input is connected to the low voltage I / O cell C1, and the I / O cell C1 is connected to the low voltage internal circuit B1 or the low voltage internal circuit B1 via the low voltage converter circuit A1. It is designed to be connected to the high-voltage internal circuit section B2. or,
The external terminal 27b to which the high voltage level is input is connected to the high voltage I
The I / O cell C2 is connected to the I / O cell C2. The I / O cell C2 is connected to the low-voltage internal circuit B1 or the high-voltage internal circuit B2 via the high-voltage converter circuit A2. Even if the input voltages at the corresponding external terminals 27a and 27b are different, the internal circuit sections B1 and B2 operate at the same voltage level by level conversion by the converter circuits A1 and A2 on the input side, so that signals can be exchanged with each other. The output voltages from the internal circuit units B1 and B2 are level-converted by the converter circuits A1 and A2 on the output side and output from the external terminals 28a and 28b via the I / O cells C1 and C2, respectively. Has become.

Next, the operation of the semiconductor design apparatus configured as described above will be described. Low voltage (for example, 3.
3V) and a high-voltage (for example, 5V) multi-power CM including internal circuits (cells) operating at two different voltage levels.
The case of designing an OS gate array will be described as an example.

First, when the logic circuit is determined by the logic design, the number of pins is uniquely determined, a package corresponding to the number of pins is selected, and the external terminal information and the chip pattern 18 relating to the selected package are displayed on the screen of the display 5. Displayed above. An I / O cell region 19 and an internal cell region 20 are set in the chip pattern 18 as shown in FIGS. The internal cell region 20 includes a plurality of columns of gate array units 2.
1 is displayed in an initial state where the basic cell BC is filled. As shown in FIG. 5, two power supply wirings 22 and 23 and one ground wiring 24 are set in the internal cell region 20 along the periphery thereof in a loop shape. Similar power supply wiring and ground wiring (both not shown) are also set on the I / O cell area 19. The number of the power supply wirings 22 and 23 is determined based on the cell data stored in the library 7 according to the operating voltages of the internal circuit units B1 and B2.
The library 7 has I / Os corresponding to the respective voltage levels.
Cells C1 and C2 are also stored in advance.

First, I / O cells C1 and C
2, the I / O cells C1 and C2 corresponding to the respective voltage levels are arranged and set at appropriate positions on the I / O cell area 19 as shown in FIG. Next, the converter circuit portions A1, A2 and the internal circuit portions B1,
The layout process of B2 is performed. Hereinafter, description will be given according to the processing flow shown in FIG.

First, the input units 12a and 12b read cell data from the library 7 and read logic circuit data and external terminal position information from the layout database 8. The cell classification unit 13 extracts all cells constituting the converter circuit units A1 and A2 and all cells constituting the internal circuit units B1 and B2 from the cell group registered in the library 7 based on the read cell data. Each of the converter circuit units A1 and A2 and the internal circuit units B1 and B2 are classified.

The converter area determining section 14 firstly converts each cell of the converter circuit sections A1 and A2 into a cell of the low voltage converter circuit section A1 and a cell of the high voltage converter circuit section A2 based on the cell data read from the library 7. Classify into. Therefore, at this time, the size occupied by each low-voltage converter circuit portion A1 and each high-voltage converter circuit portion A2 can be determined from the number and size of the cells. Then, each of the converter circuit units A1 and A2 performs the operation shown in FIG.
As shown in (1), the layout is automatically set in the gate array section 21 in the internal cell region 20 located near the corresponding I / O cells C1 and C2. That is, the low-voltage converter circuit section A
1 is arranged and set in the gate array unit 21 located near the low-voltage I / O cell C1, and the high-voltage converter circuit unit A2 is located in the gate array unit 21 located near the high-voltage I / O cell C2. The layout is set. Then, the converter circuit sections A1 and A2, which are arranged and set, respectively, have the same circuit section A.
Cells constituting A1, A2 are arranged. The converter circuit units A1 and A2 can be arranged and set by manual operation as needed, or the converter circuit units A1 and A
2 is changed. Converter circuit units A1, A2
Is completed, the converter circuit units A1, A2
The position information for each operating voltage level of the
And the process proceeds to the internal circuit area determination unit 15.

In the internal circuit area determining section 15, first, based on the cell data read from the library 7, the internal circuit section B
1 and B2 are classified according to their operating voltage levels. That is, all the cells constituting the internal circuit sections B1 and B2 are classified into cells of the low-voltage internal circuit section B1 and cells of the high-voltage internal circuit section B2. Then, based on the logic circuit data and the cell data, the internal circuit sections B1 and B2 having the same operating voltage level to be laid out at positions close to each other are extracted as a group, and the size and shape of each cell of the internal circuit sections B1 and B2 belonging to the group are extracted. From the number, the internal circuit units B1,
The size and shape of the cell placement areas 25 and 26 in which B2 is placed are determined. This is performed for each extracted group. In this way, the size and shape of the low-voltage cell arrangement area 25 and the high-voltage cell arrangement area 26 to be arranged and set in the internal cell area 20 are determined, and all of these cell arrangement areas 25 and 26 are arranged with the converter circuit units A1 and A2. It is checked whether it can be arranged in the remaining internal cell area 20. As a result of the check, the cell placement areas 25 and 26 are
If all of the cell arrangement areas 25 and 26 cannot be arranged in the internal cell area 20, the setting of the cell arrangement areas 25 and 26 is repeated until all the cell arrangement areas 25 and 26 can be arranged in the internal cell area 20. When the cell arrangement regions 25 and 26 are determined for each operation voltage level in this manner, the region data storage unit 11 stores the converter circuit units A1 and A1.
The position information of A2 is read, and the connection density between the cells arranged in the cell arrangement regions 25 and 26 and the converter circuit units A1 and A2 is checked for each voltage level based on the position information. Then, as shown in FIG.
6 are arranged and set in the vicinity of converter circuit portions A1 and A2, respectively, having a relatively high connection density with cells arranged in the cell arrangement regions 25 and 26. That is, as shown in FIG. 4, the low-voltage cell arrangement region 25 is arranged and set so that a relatively large number of low-voltage converter circuit portions A1 are present near the low-voltage cell arrangement region 25, and the high-voltage cell arrangement region 26 is relatively large in the vicinity Are arranged and set so that the high-voltage converter circuit section A2 exists. When the placement of the cell placement areas 25 and 26 is completed in this way, the placement information of the cell placement areas 25 and 26 is stored in the area data storage unit 11 and the deleted BC cell placement unit 16 is deleted.
Move to

In the deleted BC cell arranging section 16, each cell arranging area 2 set and arranged by the internal circuit area deciding section 15 is set.
The deleted BC cell 29 (see FIG. 4) is added to the basic cell BC in the gate array unit 21 at a position corresponding to the boundary line between the cells 5 and 26.
Are indicated by bold lines and are filled in FIG. 5). That is, the basic cell BC in the gate array unit 21 at a position corresponding to the boundary between the cell arrangement regions 25 and 26 is deleted from the chip pattern 18. As a result, each of the cell arrangement regions 25 and 26 is electrically disconnected from the other regions. Basic cell B
Due to the deletion of C, a blank portion where the basic cell BC is not formed is set at a position corresponding to the boundary between the cell arrangement regions 25 and 26. Thereafter, the process proceeds to the power supply wiring lead-in section 17.

In the power supply wiring lead-in section 17, the power supply wirings 22, 2 are placed in the blank portions set at positions corresponding to the boundaries of the cell arrangement areas 25, 26 due to the arrangement of the deleted BC cells 29.
Two lead-in wirings 30 and 31 extending from 3 are set. The lead-in wirings 30 and 31 set orthogonal to the longitudinal direction of the gate array unit 21 are connected to a low-voltage power supply wiring 22 and a high-voltage power supply wiring 23, respectively.
When the arrangement setting of the cell arrangement areas 25 and 26 and the setting of the lead-in wirings 30 and 31 are completed in this way, the setting data thus far is stored in the layout database 8. Thus, the processing flow illustrated in FIG. 1 ends.

Thereafter, the arrangement information of the cell arrangement areas 25 and 26 is read from the area data storage unit 11, and each of the internal circuits belonging to the group whose area size is determined in each of the cell arrangement areas 25 and 26 based on the arrangement information. Part B1,
Each cell constituting B2 is automatically arranged and set.
Since the area size of each of the cell arrangement areas 25 and 26 is determined from the size and shape of each cell of each of the internal circuit sections B1 and B2 arranged and set in the area, each of the internal circuit sections B1 and B2 is configured. Each of the cells is reliably located in the corresponding cell placement area 25, 26. Also, each cell arrangement area 2
5 and 26 are set in areas relatively close to the converter circuit sections A1 and A2 that are strongly connected to the cells arranged in the area, so that the converter circuit sections A1 and A2 and the internal circuit section B
On the other hand, the length of the wiring connecting the first and B2 becomes short on average. As a result, various inconveniences such as a loss in voltage level caused by an increase in the wiring length are prevented, and desired circuit characteristics are almost guaranteed.

Then, vias for electrically connecting the internal circuit portions B1 and B2 to the lead wirings 30 and 31 are arranged and set in the cell arrangement regions 25 and 26. Also, various wirings are set between the internal circuit units B1 and B2 and between the cells of the converter circuit units A1 and A2 and the cells of the internal circuit units B1 and B2. Thus, a logic circuit is created on the chip pattern 18.

As described above in detail, according to the present embodiment, the internal circuit sections B1, B2 arranged and set in the internal cell area 20 are provided.
Are determined in advance based on the size shape and the number of all the cells constituting the cell, and the cell arrangement areas 25 and 26 are arranged and set at appropriate positions in the internal cell area 20. Then, the basic cell BC in the gate array unit 21 at a position corresponding to the boundary between the cell arrangement regions 25 and 26 is deleted by arranging the deleted BC cell 29 to set a blank portion, and each cell is placed in the blank portion. Placement area 25,
The lead-in wirings 30 and 31 to 26 are provided.

As a result, the cell arrangement regions 25 and 26 for arranging the internal circuit portions B1 and B2 can be freely arranged at desired positions in the internal cell region 20 without being restricted by the subdivision pattern unlike the conventional device. Can be set. Then, the cell placement areas 25, 26 are located in the respective cell placement areas 25, 26.
By arranging and setting the internal circuit units B1 and B2 for which the 26 area sizes have been determined, the cells of the internal circuit units B1 and B2 can be efficiently laid out in the internal cell region 20. In addition, the size and shape of the cell placement regions 25 and 26 are determined based on the size and shape of all the cells constituting each of the internal circuit portions B1 and B2, and are set so that all of the cells can be arranged in the internal cell region 20. Has been
All the cells of all the internal circuit sections B1 and B2 can be reliably arranged and set in the internal cell area 20. As a result, it is possible to prevent the master and the package from being changed during the design.

The converter circuit sections A1 and A2 are connected to I / O
Since the arrangement is made in the internal cell area 20 instead of the cell area 19, the I / O cell C1,
Only C2 is arranged, and the number of pins of the I / O port can be increased. Further, since the respective cell arrangement regions 25 and 26 are arranged and set so that the converter circuit sections A1 and A2 having the same voltage level as the voltage levels thereof are located relatively close to each other, the converter circuit sections A1 and A2 are connected to the internal sections. Circuit part B
1 and B2 can be relatively short. As a result, various inconveniences such as instability of the voltage level due to an increase in the wiring length can be prevented, and desired circuit characteristics can be almost guaranteed. Further, in the logic design stage, it is not necessary to consider the size and shape and the layout of the internal circuit units B1 and B2.

The present invention is not limited to the above embodiment, but can be modified as follows, for example, without departing from the spirit of the invention. (1) In the above embodiment, a semiconductor device is designed in which logic circuits (cells) operating at two different voltage levels are mixedly mounted on one chip. However, an internal circuit operating at three or more different voltage levels is designed as one chip. A semiconductor device to be mounted above may be designed.

(2) In the above embodiment, the present invention is applied to the layout of a logic circuit in a gate array integrated circuit. However, the present invention is applied to the design of an integrated circuit other than a gate array integrated circuit such as an embedded array integrated circuit. You may.

(3) The present invention is applied to converter circuit sections A1, A
2 may be applied to a semiconductor device arranged and set in the I / O cell region 19.

[0038]

As described above in detail, according to the present invention, 1
In designing a semiconductor device in which a plurality of circuits operating at different voltage levels are mixedly mounted on one chip, an excellent effect that cells constituting an internal circuit portion can be efficiently laid out is provided.

[Brief description of the drawings]

FIG. 1 is a flowchart of a process performed by a CAD apparatus according to an embodiment;

FIG. 2 is a schematic diagram illustrating a system configuration of a CAD apparatus.

FIG. 3 is a plan view showing a chip.

FIG. 4 is a plan view showing a chip.

FIG. 5 is a plan view showing a chip.

FIG. 6 is a circuit diagram illustrating a logic circuit.

FIG. 7 is a plan view showing a conventional chip.

[Explanation of symbols]

1 cell arrangement area determining means, basic cell deleting means,
Central processing unit (CPU) as lead-in wiring setting means, cell placement means and converter placement means 7 Library 8 Converter placement information storage section 11 Converter placement position storage section 18 Chip pattern as chip 20 Internal cell area 22, 23 Power supply wiring 25 , 26 Cell arrangement area 29 Deleted BC cell as a blank part 30, 31, Power supply wiring A1, A2 Converter circuit part B1, B2 Internal circuit part BC Basic cell

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/82 H01L 27/118

Claims (5)

(57) [Claims] An internal cell area (20) of a chip (18)
Internal circuit units (B) operating at different voltage levels
1, B2) and the internal cell area (2
0) in a semiconductor design method for designing a semiconductor device in which a plurality of power supply wirings (22, 23) corresponding to the operating voltage levels of the respective internal circuit sections (B1, B2) are provided on the periphery. Internal circuit (B1,
B2) is logically designed in advance, and the internal circuit units (B1, B2) are first classified for each voltage level, and further divided into a group including the internal circuit units (B1, B2) having the same voltage level. , Each internal circuit part of each group (B
(B1, B2), a cell arrangement area (25, 26) capable of accommodating the cells constituting the internal circuit portion (B1, B2) is set in the internal cell area (20), and then each of the set cells is set. A blank portion (2) where a basic cell (BC) is not arranged at a position corresponding to the boundary position of the cell arrangement region (25, 26)
9) and setting the cell arrangement areas (25, 2) from the power supply wirings (22, 23) in the blank portions (29).
Power supply wiring (30, 31) leading to 6) is given,
Further, the internal circuit units (B1, B2) which have been logically designed in advance
In the corresponding cell placement area (25, 26). 2. The semiconductor design method according to claim 1, wherein said internal circuit units (B1, B2) and said converter circuit units (A1, A2) are logically designed in advance for each operating voltage level. A circuit section (A1, A2) is arranged and set in an internal cell area (20) near a corresponding external terminal, and then the respective cell arrangement areas (25, 26) are arranged by the converter circuit section (A1, A2). The cell arrangement area (25, 2)
6) A method of designing a semiconductor device, comprising setting a section near the converter circuit section (A1, A2) having a relatively high connection density with a cell arranged therein. 3. An internal cell area (20) of a chip (18).
Internal circuit units (B) operating at different voltage levels
1, B2) and the internal cell area (2
In a semiconductor design apparatus for designing a semiconductor device in which a plurality of power supply wirings (22, 23) corresponding to the operating voltage levels of the internal circuit portions (B1, B2) are provided on the peripheral portion of (0), a logic design is performed in advance. A library (7) for storing the size shape and operating voltage level of the internal circuit units (B1, B2) arranged and set in the internal cell area (20) as cell data; and a library (7) stored in the library (7). Cells constituting the internal circuit units (B1, B2) are divided into groups based on the cell data, and each internal circuit unit (B
A plurality of cell arrangement areas (25, 26) capable of accommodating the cells constituting the internal circuit section (B1, B2) for each of (1, B2)
Cell placement area determining means (1) for setting a partition, and basic cell deleting means (1) for removing a basic cell (BC) existing at a position corresponding to a boundary position of the cell placement areas (25, 26). Through the blank portion (29) formed as a trace of the basic cell by the basic cell deletion means (1), the power supply wiring (22, 23) is connected to each of the cell arrangement regions (25, 26) so that the voltage level corresponds. A predetermined voltage can be supplied through a lead-in wiring setting means (1) for providing a power lead-in wiring (30, 31) and the power lead-in wiring (30, 31) provided by the lead-in wiring setting means (1). A cell arrangement for arranging and setting the cells of the internal circuit section (B1, B2) in which the cell arrangement areas (25, 26) are set in the cell arrangement areas (25, 26). Semiconductor design device being characterized in that a means (1). 4. The semiconductor design apparatus according to claim 3, wherein the library (7) stores the size shape and operating voltage level of the converter circuit section (A1, A2) together with the cell data as converter cell data. A converter arrangement information storage unit (8) for storing position information of an external terminal corresponding to each converter circuit unit (A1, A2) as external terminal position information; and a converter arrangement unit (A1, A2) based on the external terminal position information. ) In the internal cell area (20) at a position corresponding to each of the external terminals. The converter arranging means (1) includes: 1) The internal cells other than the setting area of the converter circuit section (A1, A2) arranged and set in the internal cell area (20). Semiconductor design device being characterized in that the region (20) the cell layout region in (25, 26) so as to partition set. 5. The converter layout according to claim 3, wherein layout position information for each operating voltage level of each converter circuit section (A1, A2) corresponding to said internal cell (B1, B2) is stored. A position storage unit (11), wherein the cell arrangement region determining means (1) stores the cell arrangement regions (25, 26) based on the arrangement position information stored in the converter arrangement position storage unit (11). A semiconductor design apparatus characterized in that a partition is set near a converter circuit section (A1, A2) having a relatively high connection density with a cell arranged in a cell arrangement area (25, 26).