JP2004236141A

JP2004236141A - Phase locked loop circuit and noise component eliminating method

Info

Publication number: JP2004236141A
Application number: JP2003024128A
Authority: JP
Inventors: Kazuhide Asada; 和秀浅田
Original assignee: Icom Inc
Current assignee: Icom Inc
Priority date: 2003-01-31
Filing date: 2003-01-31
Publication date: 2004-08-19

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase locked loop circuit for suppressing spurious radiation and providing high signal purity and to provide a noise component eliminating method. <P>SOLUTION: The phase locked loop circuit is provided with a reference signal output circuit 11 for frequency-dividing an output of an oscillator and outputting a reference signal; a phase comparator 12 for outputting a phase difference signal between the reference signal and a frequency division signal; a loop filter 13; and a voltage-controlled oscillator 14 oscillating according to a phase difference signal passing through the loop filter 13; a frequency divider 15 for applying frequency division to an output of the voltage-controlled oscillator 14 and outputting the result to the phase comparator 12 as a frequency division signal; a setting circuit 17 for obtaining a frequency division ratio N1 of the reference signal output circuit 11 and a fractional frequency division ratio N2 of the frequency divider 15 to obtain an instructed output frequency; and a frequency division ratio switching control circuit 16 for switching a plurality of integer frequency division ratios and setting the selected frequency division ratio to the frequency divider 15 to obtain an average fractional frequency division ratio N2. The setting circuit 17 selects the frequency division ratios N1, N2 so as to locate the spurious frequency caused by the switching of the frequency division ratio to an attenuation frequency band of the loop filter 13. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、位相同期ループ回路及び雑音成分除去方法に関する。
【０００２】
【従来の技術】
基準周波数以下のステップで出力周波数を設定できる位相同期ループ（ＰＬＬ：ＰｈａｓｅＬｏｃｋｅｄＬｏｏｐ）回路として、フラクショナルＮ型のものがある（例えば、特許文献１）。フラクショナルＮ型のＰＬＬ回路は、プログラマブル分周器の分周比を高速で切り換えて、その平均的な分周比によってロックさせるようにしたことで、整数以外の分周比を設定することができるようにしたものである。例えば、分周値Ｎ＝１００．１を実現するには、１０回の位相比較の期間中に、９回はＮ＝１００で行い、１回をＮ＝１０１で行う。それによって、Ｎ＝１００．１（＝（１００×９＋１０１×１）／１０）を得る。
【０００３】
【特許文献１】
特開平１０−１５４９３５号公報
【０００４】
【発明が解決しようとする課題】
フラクショナルＮ型ＰＬＬ回路にあっては、分周比を周期的に切り換えることに起因して、特有のスプリアスが発生する（特許文献１参照）。
具体的に説明すると、平均的な分周値として、１００．１が得られても、位相比較を行う瞬時瞬時は、分周比Ｎ＝１００或いはＮ＝１０１であり、位相比較器からは位相ずれによるエラー信号が周期的に発生し、これがスプリアスとして現れる。例えば、次のような設定がなされた場合を想定する。
分周比：ｉ＋ｆ（ｉは分周比の整数部分、ｆは分周比の小数部分）、分周比を切り換えるクロック周波数：Ｃ
【０００５】
この場合、平均的な分周比としてして（ｉ＋ｆ）を得るためには、分周比ｉと（ｉ＋１）とを（１−ｆ）：ｆの割合で切り換える必要がある。このため、Ｃ×ｆ若しくはＣ×（１−ｆ）の周波数で周期的な分周比の切り換えが行われて位相エラーが発生し、出力周波数がこの周波数によってＦＭ変調された状態となり、これがスプリアスとなる。このスプリアスがループフィルタの通過帯域内にある場合には、出力信号にスプリアスとして現れてしまい、信号純度が低下する。
【０００６】
本発明は、このような従来の問題点に鑑みてなされたもので、高い信号純度を有する位相同期ループ回路及び雑音成分除去方法を提供することを目的とする。
【０００７】
【課題を解決するための手段】
上記目的を達成するため、この発明の第１の観点にかかる位相同期ループ回路は、
第１の発振器と該第１の発振器の発振信号を分周して基準周波数を有する基準信号を出力する第１の分周器とを有する基準信号出力回路と、
前記基準信号の位相と所定の分周信号との位相とを比較し、両信号の位相差に対応する信号レベルを有する信号を出力する位相比較器と、
通過周波数帯域と減衰周波数帯域とを有し、前記位相比較器の出力信号をフィルタリングするフィルタと、
前記フィルタを通過した前記位相比較器からの信号の信号レベルに従った周波数で発振する第２の発振器と、
前記第２の発振器の出力信号を所定の分周比で分周して、前記所定の分周信号として前記位相比較器に出力する第２の分周器と、
出力周波数指示信号が指示する出力周波数を得るために、第１の分周器に設定する整数表現の第１の分周比を求めて前記第１の分周器に設定し、前記第２の分周器に設定する小数表現の第２の分周比とを求めて出力する設定回路と、
前記設定回路から出力された第２の分周比を平均値で得るために、少なくとも２つの整数の分周比を切り換えて前記第２の分周器に設定する分周比切換制御回路と、
を備え、
前記設定回路は、第１の分周器に設定する第１の分周比と前記第２の分周器に設定する小数表現の第２の分周比とを、前記分周比切換制御回路による分周比の切り換えにより発生するノイズの周波数が前記フィルタの減衰周波数帯域に位置するように設定する、
ことを特徴とする。
【０００８】
前記設定回路は、例えば、出力周波数と第１の分周器に設定する整数表現の第１の分周比と前記第２の分周器に設定する小数表現の第２の分周比とが予め対応付けて設定されているテーブルを備え、前記出力周波数指示信号が指示する出力周波数に対応する第１と第２の分周比を前記テーブルから読み出して出力する。
【０００９】
前記分周比切換制御回路は、例えば、クロック信号の供給を受け、指示された小数表現の第２の分周比を得るために、小数表現の第２の分周比の整数部で表される第３の分周比と第３の分周比と１だけ差がある第４の分周比とを前記クロック信号に応じて前記第２の分周器に設定する。
【００１０】
前記設定回路は、例えば、前記クロック信号の周波数と小数表現の第２の分周比の小数部との積及び／又は前記クロック信号の周波数と小数表現の第２の分周比の小数部と１との差との積で表される周波数が前記フィルタの減衰周波数帯域に位置するように、前記第１の分周比を設定する。
【００１１】
本発明の第２の観点に係る雑音成分除去方法は、
所定信号を第１の分周比で分周して基準信号を出力するステップと、
基準信号の位相と所定の分周信号との位相とを比較し、両信号の位相差に対応する位相差信号を出力するステップと、
前記位相差信号に含まれる周波数成分のうち所定の減衰周波数帯域の信号成分を減衰して出力する減衰ステップと、
前記減衰周波数帯域の信号成分が減衰された位相差信号の信号レベルに従った周波数の発振信号を出力するステップと、
該発振信号を小数表現の第２の分周比で分周して、前記所定の分周信号として出力する分周ステップと、
出力周波数指示信号が指示する出力周波数を得るために前記第１と第２の分周比を設定する設定ステップと、
を備え、
前記分周ステップでは、第２の小数表現の分周比を平均値で得るために、少なくとも２つの整数の分周比を切り換えて分周を実行し、
前記設定ステップでは、前記分周ステップにおける分周比の切り換えにより発生するノイズの周波数が前記減衰ステップにおける減衰周波数帯域に位置するように、前記第１と第２の分周比を設定する、
ことを特徴とする。
【００１２】
【発明の実施の形態】
以下、本発明の実施の形態に係る位相同期ループ回路を図面を参照して説明する。
本実施の形態に係る位相同期ループ回路の構成を図１に示す。
本実施の形態に係る位相同期ループ回路は、発振器１１１と第１の分周器１１２とから構成される基準周波数信号出力部１１と、位相比較器１２と、ループフィルタ１３と、電圧制御発振器１４と、第２の分周器１５と、分周比切換制御回路１６と、設定回路１７と、から構成される。
【００１３】
発振器１１１は、水晶発振器などから構成され、所定周波数で発振する。第１の分周器１１２は、プログラマブルカウンタ等から構成され、設定回路１７から指示される第１の分周比Ｎ１で、発振器１１１の出力信号を分周して基準周波数信号を出力する。
【００１４】
位相比較器１２は、基準周波数信号出力部１１から出力された周波数信号の位相と第２の分周器１５から出力された信号の位相とを比較し、比較結果として位相差に応じたパルス幅を有する位相差信号を出力する。
【００１５】
ループフィルタ１３は、ローパスフィルタ、即ち、積分器より構成され、位相比較器１２から出力された位相差信号を構成するパルス信号の高周波成分を減衰することにより、平滑化して出力する、
【００１６】
電圧制御発振器（ＶＣＯ）１４は、ループフィルタ１３を介して位相比較器１２から出力された位相差信号の電圧レベルに対応した発振周波数の発振信号を出力するものである。尚、電圧制御発振器１４は、例えば、印加される制御電圧に従って容量が変化する可変容量ダイオード、発振器等（図示せず）を備え、この可変容量ダイオードの容量の変化に応じた周波数で発振する。
【００１７】
第２の分周器１５は、プログラマブルカウンタ等から構成され、分周比切換制御回路１６から供給される分周比で電圧制御発振器１４の出力する発振信号を分周し、位相比較器１２に出力する。
【００１８】
設定回路１７は、マイクロプロセッサ（ＭＰＵ）等から構成され、外部回路から出力周波数指示信号を受信し、この出力周波数指示信号が指示する周波数を得る（電圧制御発振器１４の出力とする）ために、第１と第２の分周器１１２と１５の分周比（第１と第２の分周比）を求め、求めた分周比を指示する信号を第１の分周器１１２と分周比切換制御回路１６とに出力する。
【００１９】
具体的に説明すると、設定回路１７は、外部より出力周波数ｆｏｕｔを指示する出力周波数指示信号が供給されると、出力周波数ｆｏｕｔを得るために、第１の分周器１１２と第２の分周器１５にセットすべき分周比Ｎ１とＮ２とを求める。
【００２０】
出力信号ｆｏｕｔは次式で定義される。
【数１】

ここで、Ｎ２は第２の分周器１５が行う分周の平均的な小数表現の分周比（第２の分周比）であり（ｉ＋ｆ）で表される。ｉは整数部、ｆは小数部である。また、Ｎ１は第１の分周器１１２が実行する分周の整数表現の分周比である。ｆｒは、発振器１１１の発振周波数である。
【００２１】
設定回路１７は、この式より、出力周波数ｆｏｕｔを得るために、第１と第２の分周器１１２と１５にセット可能な分周比Ｎ１，Ｎ２の組を誤差（指示された出力周波数とＮ１とＮ２により得られる出力周波数との差）の小さい順に複数組求める。
【００２２】
次に、設定回路１７は、誤差の小さい組から順番に、小数部ｆ×Ｃ（Ｃ：後述するクロックＣの周波数）と（１−ｆ）×Ｃとが共にループフィルタ１３の減衰特性の減衰周波数帯域（カットオフ周波数ｆｃ以上）に位置するか否かを判別する。設定回路１７は、位置すると判断された分周比Ｎ１とＮ２の組を、第１の分周器１１２と分周比切換制御回路１６とに出力する。このようにして、設定回路１７は、ｆ×Ｃと（１−ｆ）×Ｃとが共に減衰周波数範囲に位置するという条件を満足する範囲で、最も目的周波数ｆｏｕｔに近い出力周波数が得られる分周比Ｎ１とＮ２とを求めて出力する。
【００２３】
分周比切換制御回路１６は、クロックＣを受け、設定回路１７から指示された分周比Ｎ２を平均値で得るために、個々のタイミングで第２の分周器１５に整数の分周比を設定する。例えば、分周比Ｎ１として１００．１が設定されている場合には、９クロックの間、Ｎ１＝１００を設定し、１クロックの間、Ｎ１＝１０１を設定する。これにより、平均的な分周比はＮ１＝（１００×９＋１０１×１）／１０＝１００．１となる。なお、クロックＣとしては、第１の分周器１１２の出力する基準周波数信号を使用できる。
【００２４】
次に本実施の形態に係る位相同期ループ回路の動作を説明する。
設定回路１７に、この位相同期ループ回路の出力信号の周波数（出力周波数：目的周波数）が外部回路より指示されると、設定回路１７は、その周波数を得るために適した第１の分周器１１２の分周比Ｎ１（整数表現）と、第２の分周器１５の分周比Ｎ２（ｉ＋ｆ：ｉは整数部、ｆは小数部）と、を求める。この際、設定回路１７は、分周比Ｎ１（整数表現）と分周比Ｎ２（小数表現）とを、分周比Ｎ１とＮ２とで定まる出力周波数と指定された周波数との誤差が許容誤差範囲内で且つ誤差ができるだけ小さく、さらに、周波数Ｃ・ｆとＣ・（１−ｆ）で表されるスプリアスの周波数がループフィルタ１３の通過帯域の外に位置するように選択する。
設定回路１７は、このような条件を充足するように選択した第１の分周比Ｎ１を第１の分周器１１２に出力し、第２の分周比Ｎ２を分周比切換制御回路１６に出力する。
【００２５】
分周比切換制御回路１６は、通知された平均的な分周比Ｎ２を実現するために、第２の分周器１５にその時点での分周比ｉとｉ＋１の一方を指定する。即ち、ｆが小数点ｎ桁の数字であるとすれば、クロックＣの１０^ｎ回について、ｆ’クロック期間（ｆ’はｆの小数点を無視した整数値）、分周比ｉ＋１を選択して第２の分周器１５に出力し、（１０^ｎ−ｆ’）クロック期間、分周比ｉを選択して第２の分周器１５に出力する。
【００２６】
例えば、分周比Ｎ２＝１００．１が指定された場合、ｉ＝１００であり、ｆ＝０．１であり、ｆ’＝１，ｎ＝１である。そこで、クロックＣの１０（＝１０^１）クロック期間中の、９（＝１０^１−ｆ’）クロック期間はｉ＝１００を指定し、ｆ’＝１クロック期間中はｉ＝１０１を指定する。それによって、平均値として、Ｎ２＝１００．１（＝（１００×９＋１０１×１）／１０）を得る。
【００２７】
基準周波数信号出力部１１の発振器１１１は所定周波数ｆｒの信号を出力する。第１の分周器１１２は、発振器１１１の出力信号を、設定回路１７から指示された分周比Ｎ１で分周して、基準周波数信号を生成して位相比較器１２に出力する。
【００２８】
位相比較器１２は、第２の分周器１５からの分周信号と基準周波数信号出力部１１から出力された基準周波数信号との位相を比較して、両信号の位相差に対応するパルス幅の位相差信号としてループフィルタ１３に出力する。
【００２９】
ループフィルタ１３は、位相差信号に含まれている周波数成分のうち、カットオフ周波数ｆｃより高い周波数成分とを除去（減衰）して、これを実質的に積分し、平滑化された位相差信号を電圧制御発振器１４に出力する。
【００３０】
電圧制御発振器１４は、位相差信号の制御電圧に対応した発振周波数の発振信号を生成し、生成した発振信号を出力する。この発振信号は、基準周波数信号出力部１１の出力する基準周波数信号に同期したものとなる。
【００３１】
第２の分周器１５は、その時点で、分周比切換制御回路１６から指示されている分周比ｉ又はｉ＋１で電圧制御発振器１４の出力信号を分周して、位相比較器１２に出力する。
【００３２】
このような構成によれば、第１の分周器１１２の分周比Ｎ１（整数表現）と第２の分周器１５の分周比Ｎ２（ｉ＋ｆ：ｉは整数部、ｆは小数部）とが、分周比Ｎ１とＮ２とで定まる出力周波数と指定された周波数との誤差が許容誤差範囲内で且つ誤差ができるだけ小さく、さらに、周波数Ｃ・ｆとＣ・（１−ｆ）で表されるスプリアスがループフィルタ１３の通過帯域の外に位置するように選択されているので、スプリアスが減衰され、誤差が小さく且つノイズの少ない出力信号を得ることができる。
【００３３】
次に、設定回路１７を図２及び図３を参照してより詳細に説明する。
設定回路１７は、図２に示すように、プロセッサ１７１と、ＲＯＭ１７２と、ＲＡＭ１７３と、入出力部（Ｉ／Ｏ）１７４とを備える。
ＲＯＭ１７２は、ループフィルタ１３のカットオフ周波数ｆｃと、クロックＣの周波数と、発振器１１１の発振周波数ｆｒと、プロセッサ１７１の動作プログラムを記憶する。
ＲＡＭ１７３は、プロセッサ１７１のワークエリアとして機能する。
Ｉ／Ｏ１７４は、外部より出力周波数（電圧制御発振器１４の発振周波数）を指示する出力周波数指示信号を受信して、プロセッサ１７１に通知する。また、プロセッサ１７１が計算した、分周比Ｎ１とＮ２とを第１と第２の分周器１１２と１５とにそれぞれ出力する。
プロセッサ１７１は、マイクロプロセッサなどから構成され、ＲＯＭ１７２に格納された動作プログラムに従って動作し、出力周波数指示信号で指定される周波数を出力するために設定すべき分周比Ｎ１とＮ２とを後述する図３のフローチャートに沿って求めて出力する。
【００３４】
次に、このような構成の設定回路１７の動作を図３のフローチャートを参照して説明する。
Ｉ／Ｏ１７４は、外部より新たな出力周波数指示信号が供給されると、それをプロセッサ１７１に提供する。
プロセッサ１７１は、この信号に応答して、ＲＯＭ１７２に格納された動作プログラムに従って図３に示す処理を開始する。
【００３５】
まず、プロセッサ１７１は、指示された周波数ｆｏｕｔを得ることができる分周比Ｎ１とＮ２との組合せを求める（ステップＳ１１）。
この処理の手法自体は、任意であるが、例えば、分周比Ｎ１を可変範囲内でスキャンし、各分周比Ｎ１について、目的周波数ｆｏｕｔ近傍の周波数を得ることができる分周比Ｎ２を求め、この組合せで得られる周波数と目的周波数ｆｏｕｔとの誤差を求め、誤差が許容範囲内の組合せについて、Ｎ１、Ｎ２、誤差をＲＡＭ１７３に登録する。換言すれば、選択可能なＮ１とＮ２との全組合せについて、その組合せにより得られる周波数と目的周波数ｆｏｕｔとの差を求め、その誤差が許容誤差内のものをピックアップして、ＲＡＭ１７３に登録する。
【００３６】
次に、プロセッサ１７１は、ＲＡＭ１７３に登録されたＮ１：Ｎ２：誤差の組合せデータを、誤差の小さい順にソートする（ステップＳ１２）。
【００３７】
次に、誤差の小さい順を示すポインタｊに１をセットする（ステップＳ１３）。
次に、誤差がｊ番目に小さい分周比の組合せを選択し（ステップＳ１４）、周波数Ｃ・ｆとＣ・（１−ｆ）を求める（ステップＳ１５）。
次に、ステップＳ１５で求めた周波数Ｃ・ｆとＣ・（１−ｆ）（スプリアスの周波数）が、ループフィルタ１３のカットオフ周波数ｆｃよりも高域（減衰周波数帯域）にあるか否かを判別する（ステップＳ１６）。
【００３８】
次に、スプリアスの位置が共に通過帯域の外であると判別された場合（ステップＳ１６；Ｙｅｓ）、ｊ番目のＮ１とＮ２（ｉ＋ｆ）とをＩ／Ｏ１７４を介して出力し（ステップＳ１７）、処理を終了する。
一方、ステップＳ１６で、少なくとも一方が通過帯域（ｆｃ以下）内に位置すると判別した場合（ステップＳ１６；Ｎｏ）には、ＲＡＭ１７３に登録されている分周比Ｎ１とＮ２の全ての組合せについて処理を終了したか否かを判別する（ステップＳ１８）。処理を終了していない（残りの分周比の組が存在する）と判別した場合（ステップＳ１８；Ｎｏ）には、ｊを＋１して（ステップＳ１９）、ステップＳ１４からの処理を繰り返す。
【００３９】
一方、ステップＳ１８で、処理を終了した（残りの分周比の組が存在しない）と判別した場合（ステップＳ１８；Ｙｅｓ）には、所定のエラー処理（例えば、誤差の最も小さい分周比Ｎ１とＮ２を選択して出力する）を実行して（ステップＳ２０）、処理を終了する。
【００４０】
この方法によれば、指示された出力周波数ｆｏｕｔとの誤差が予め設定されている許容誤差の範囲内で、且つ、スプリアスノイズをループフィルタ１３の減衰域に位置させる分周比Ｎ１とＮ２とを求めることができる。
【００４１】
なお、この例では、出力周波数の指示があるたびに、分周比Ｎ１とＮ２とを計算する例を示したが、選択可能な全ての出力周波数について、予め最適な分周比Ｎ１とＮ２とを事前に計算して、図４に例示するように、テーブル１７５に登録して用意しておき、出力周波数ｆｏｕｔの指示があると、このテーブル１７５をアクセスして、指示された出力周波数ｆｏｕｔに対応する分周比Ｎ１とＮ２とを読み出して、出力するようにしてもよい。このような構成によれば、実験などにより、誤差以外の要素をも考慮して最適な分周比Ｎ１とＮ２を求めて登録することができる。
【００４２】
尚、本発明を実施するにあたっては、種々の形態が考えられ、上記実施の形態に限られるものではない。
例えば、図１、図２，図４に示すＰＬＬ回路の回路構成は任意に変更可能である。同様に、図３に示すフローチャートも同様の機能を実現できるならば、任意に変更可能である。
また、上記実施の形態では、第２の分周器１５に設定する分周比として、ｉとｉ＋１の２つの分周比を設定する例を示したが、３つ以上の分周比を設定するようにしてもよい。例えば、分周比切換制御回路１６で分周比（ｉ＋ｆ）のΔΣ変調を行って、３つ以上で変化する整数の分周比を得て、これを第２の分周器１５に設定するようにしてもよい。
上記実施の形態では、基準周波数信号出力回路１１として、発振器１１１と第１の分周器１１２とから構成される回路を使用したが、設定回路１７からの指示で周波数を変更でき且つ安定した周波数で発振できる任意の回路を使用可能である。
【００４３】
【発明の効果】
以上説明したように、本発明によれば、スプリアスを抑えて信号純度を向上させることができる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態に係る位相同期ループ回路の構成を示すブロック図である。
【図２】図１に示す設定回路１７の構成例を示す説明図である。
【図３】図２に示すプロセッサの動作例を示すフローチャートである。
【図４】図１に示す設定回路の他の構成例を示すブロック図である。
【符号の説明】
１１基準周波数信号出力部
１２位相比較器
１３ループフィルタ
１４電圧制御発振器
１５第２の分周器
１６分周比切換制御回路
１７設定回路
１１１発振器
１１２第１の分周器[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a phase locked loop circuit and a noise component removing method.
[0002]
[Prior art]
As a phase locked loop (PLL) circuit capable of setting an output frequency in steps equal to or lower than a reference frequency, there is a fractional N type circuit (for example, Patent Document 1). The fractional N-type PLL circuit can set a non-integer frequency division ratio by switching the frequency division ratio of the programmable frequency divider at a high speed and locking the frequency with the average frequency division ratio. It is like that. For example, in order to realize the frequency division value N = 100.1, during the period of ten phase comparisons, nine times are performed with N = 100, and one time is performed with N = 101. Thereby, N = 100.1 (= (100 × 9 + 101 × 1) / 10) is obtained.
[0003]
[Patent Document 1]
JP-A-10-154935
[Problems to be solved by the invention]
In a fractional N-type PLL circuit, a spurious characteristic occurs due to periodic switching of the frequency division ratio (see Patent Document 1).
More specifically, even if 100.1 is obtained as an average frequency division value, the instantaneous moment at which the phase comparison is performed is the frequency division ratio N = 100 or N = 101. An error signal due to the shift is periodically generated and appears as spurious. For example, it is assumed that the following settings are made.
Frequency division ratio: i + f (i is an integer part of the frequency division ratio, f is a decimal part of the frequency division ratio), clock frequency for switching the frequency division ratio: C
[0005]
In this case, in order to obtain (i + f) as an average frequency division ratio, it is necessary to switch the frequency division ratios i and (i + 1) at a ratio of (1-f): f. For this reason, the frequency division ratio is periodically switched at the frequency of C × f or C × (1-f) to generate a phase error, and the output frequency is FM-modulated by this frequency, which is a spurious response. It becomes. If the spurious is within the pass band of the loop filter, it appears as spurious in the output signal, and the signal purity is reduced.
[0006]
The present invention has been made in view of such conventional problems, and has as its object to provide a phase locked loop circuit having high signal purity and a noise component removing method.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a phase locked loop circuit according to a first aspect of the present invention comprises:
A reference signal output circuit comprising: a first oscillator; and a first frequency divider for dividing an oscillation signal of the first oscillator to output a reference signal having a reference frequency;
A phase comparator that compares the phase of the reference signal and the phase of the predetermined frequency-divided signal, and outputs a signal having a signal level corresponding to the phase difference between the two signals;
A filter having a pass frequency band and an attenuation frequency band, and filtering an output signal of the phase comparator;
A second oscillator that oscillates at a frequency according to the signal level of the signal from the phase comparator that has passed through the filter;
A second frequency divider that divides an output signal of the second oscillator by a predetermined frequency division ratio and outputs the frequency-divided signal to the phase comparator as the predetermined frequency-divided signal;
In order to obtain an output frequency indicated by the output frequency instruction signal, a first frequency division ratio in an integer expression to be set in the first frequency divider is obtained and set in the first frequency divider, and the second frequency is set in the second frequency divider. A setting circuit for obtaining and outputting a second division ratio in decimal representation to be set in the frequency divider;
A frequency division ratio switching control circuit for switching at least two integer frequency division ratios and setting the second frequency divider in order to obtain a second frequency division ratio output from the setting circuit as an average value;
With
The setting circuit converts a first frequency division ratio set in a first frequency divider and a second frequency division ratio expressed in a decimal number to be set in the second frequency divider into a frequency division ratio switching control circuit. Set so that the frequency of the noise generated by the switching of the frequency division ratio is located in the attenuation frequency band of the filter,
It is characterized by the following.
[0008]
The setting circuit may be configured, for example, such that an output frequency and a first division ratio in an integer representation set in the first divider and a second division ratio in a decimal representation set in the second divider are set. There is provided a table which is set in advance in association with the table, and reads and outputs first and second frequency division ratios corresponding to the output frequency indicated by the output frequency instruction signal from the table.
[0009]
The frequency division ratio switching control circuit is, for example, supplied with a clock signal and is represented by an integer part of a second frequency division ratio of a decimal number in order to obtain a second frequency division ratio of a designated decimal number. A third frequency division ratio and a fourth frequency division ratio having a difference of 1 from the third frequency division ratio are set in the second frequency divider in accordance with the clock signal.
[0010]
The setting circuit may include, for example, a product of a frequency of the clock signal and a fractional part of a second division ratio expressed in decimals and / or a fractional part of a frequency of the clock signal and a second division ratio expressed in decimals. The first frequency division ratio is set so that the frequency represented by the product of the difference from 1 is located in the attenuation frequency band of the filter.
[0011]
The noise component removing method according to the second aspect of the present invention includes:
Outputting a reference signal by dividing the predetermined signal by a first division ratio;
Comparing the phase of the reference signal with the phase of the predetermined frequency-divided signal, and outputting a phase difference signal corresponding to the phase difference between the two signals;
An attenuation step of attenuating and outputting a signal component of a predetermined attenuation frequency band among frequency components included in the phase difference signal,
Outputting an oscillation signal having a frequency according to the signal level of the phase difference signal in which the signal component of the attenuation frequency band has been attenuated,
A frequency dividing step of dividing the oscillation signal by a second frequency dividing ratio expressed as a decimal and outputting as the predetermined frequency divided signal;
A setting step of setting the first and second frequency division ratios to obtain an output frequency indicated by an output frequency instruction signal;
With
In the frequency dividing step, frequency division is performed by switching a frequency dividing ratio of at least two integers in order to obtain a frequency dividing ratio of a second decimal representation as an average value.
In the setting step, the first and second frequency division ratios are set so that the frequency of noise generated by switching the frequency division ratio in the frequency division step is located in the attenuation frequency band in the attenuation step.
It is characterized by the following.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a phase locked loop circuit according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows the configuration of the phase locked loop circuit according to the present embodiment.
The phase locked loop circuit according to the present embodiment includes a reference frequency signal output unit 11 including an oscillator 111 and a first frequency divider 112, a phase comparator 12, a loop filter 13, a voltage controlled oscillator 14, , A second frequency divider 15, a frequency division ratio switching control circuit 16, and a setting circuit 17.
[0013]
The oscillator 111 includes a crystal oscillator or the like, and oscillates at a predetermined frequency. The first frequency divider 112 includes a programmable counter or the like, and divides the output signal of the oscillator 111 at a first frequency division ratio N1 specified by the setting circuit 17, and outputs a reference frequency signal.
[0014]
The phase comparator 12 compares the phase of the frequency signal output from the reference frequency signal output unit 11 with the phase of the signal output from the second frequency divider 15, and as a comparison result, a pulse width corresponding to the phase difference Is output.
[0015]
The loop filter 13 is composed of a low-pass filter, that is, an integrator, and attenuates a high-frequency component of a pulse signal constituting the phase difference signal output from the phase comparator 12, thereby smoothing and outputting the pulse signal.
[0016]
The voltage control oscillator (VCO) 14 outputs an oscillation signal having an oscillation frequency corresponding to the voltage level of the phase difference signal output from the phase comparator 12 via the loop filter 13. Note that the voltage controlled oscillator 14 includes, for example, a variable capacitance diode, an oscillator, etc. (not shown) whose capacitance changes according to an applied control voltage, and oscillates at a frequency corresponding to a change in the capacitance of this variable capacitance diode.
[0017]
The second frequency divider 15 is configured by a programmable counter or the like, divides the frequency of the oscillation signal output from the voltage controlled oscillator 14 by the frequency division ratio supplied from the frequency division ratio switching control circuit 16, Output.
[0018]
The setting circuit 17 is composed of a microprocessor (MPU) or the like, receives an output frequency instruction signal from an external circuit, and obtains the frequency indicated by the output frequency instruction signal (the output of the voltage controlled oscillator 14). The frequency division ratios (first and second frequency division ratios) of the first and

second frequency dividers

112 and 15 are obtained, and a signal indicating the obtained frequency division ratio is divided by the first frequency divider 112 and the first frequency divider 112. Output to the ratio switching control circuit 16.
[0019]
More specifically, when an output frequency instruction signal indicating the output frequency fout is supplied from the outside, the setting circuit 17 outputs the first frequency divider 112 and the second frequency divider to obtain the output frequency fout. The frequency division ratios N1 and N2 to be set in the detector 15 are obtained.
[0020]
The output signal fout is defined by the following equation.
(Equation 1)

Here, N2 is a frequency division ratio (second frequency division ratio) in an average decimal representation of frequency division performed by the second frequency divider 15, and is represented by (i + f). i is an integer part and f is a decimal part. N1 is a division ratio of the division performed by the first frequency divider 112 in an integer expression. fr is the oscillation frequency of the oscillator 111.
[0021]
From this equation, the setting circuit 17 determines the set of frequency division ratios N1 and N2 that can be set in the first and

second frequency dividers

112 and 15 by an error (in order to obtain the output frequency fout). A plurality of sets are determined in ascending order of the difference between the output frequencies obtained by N1 and N2).
[0022]
Next, the setting circuit 17 determines that both the decimal part f × C (C: frequency of a clock C to be described later) and (1-f) × C are the attenuation of the attenuation characteristic of the loop filter 13 in order from the set with the smallest error. It is determined whether or not it is located in the frequency band (not less than the cutoff frequency fc). The setting circuit 17 outputs the set of the dividing ratios N1 and N2 determined to be located to the first divider 112 and the dividing ratio switching control circuit 16. In this way, the setting circuit 17 obtains an output frequency closest to the target frequency fout within a range that satisfies the condition that both f × C and (1−f) × C are located in the attenuation frequency range. The ratios N1 and N2 are obtained and output.
[0023]
The division ratio switching control circuit 16 receives the clock C, and obtains the division ratio N2 instructed by the setting circuit 17 as an average value. Set. For example, if 1001 is set as the frequency division ratio N1, N1 = 100 is set for nine clocks, and N1 = 101 is set for one clock. Thus, the average frequency division ratio is N1 = (100 × 9 + 101 × 1) /10=100.1. Note that the reference frequency signal output from the first frequency divider 112 can be used as the clock C.
[0024]
Next, the operation of the phase locked loop circuit according to the present embodiment will be described.
When the frequency of the output signal of the phase locked loop circuit (output frequency: target frequency) is instructed to the setting circuit 17 from an external circuit, the setting circuit 17 sets a first frequency divider suitable for obtaining the frequency. A frequency division ratio N1 (expressed as an integer) of 112 and a frequency division ratio N2 (i + f: i is an integer part and f is a decimal part) of the second frequency divider 15 are obtained. At this time, the setting circuit 17 sets the frequency division ratio N1 (expressed as an integer) and the frequency division ratio N2 (expressed as a decimal number) as an allowable error between the output frequency determined by the frequency division ratios N1 and N2 and the designated frequency. The selection is made so that the error is as small as possible within the range and the spurious frequencies represented by the frequencies C · f and C · (1−f) are outside the pass band of the loop filter 13.
The setting circuit 17 outputs the first frequency dividing ratio N1 selected so as to satisfy such a condition to the first frequency divider 112, and outputs the second frequency dividing ratio N2 to the frequency dividing ratio switching control circuit 16 Output to
[0025]
The frequency division ratio switching control circuit 16 specifies one of the current frequency division ratios i and i + 1 to the second frequency divider 15 in order to realize the notified average frequency division ratio N2. That is, assuming that f is a number with n decimal places, for 10 ⁿ times of the clock C, the f ′ clock period (f ′ is an integer value ignoring the decimal point of f) and the frequency division ratio i + 1 are selected. The second frequency divider 15 selects the frequency ^dividing ratio i for (10 ⁿ −f ′) clock periods and outputs the selected frequency ^dividing ratio i to the second frequency divider 15.
[0026]
For example, when the frequency division ratio N2 = 100.1, it is i = 100, f = 0.1, f ′ = 1, and n = 1. Therefore, i = 100 is specified during 9 (= 10 ¹ −f ′) clock periods in 10 (= 10 ¹ ) clock periods of the clock C, and i = 101 is specified during f ′ = 1 clock period. Thereby, N2 = 100.1 (= (100 × 9 + 101 × 1) / 10) is obtained as an average value.
[0027]
The oscillator 111 of the reference frequency signal output section 11 outputs a signal having a predetermined frequency fr. The first frequency divider 112 divides the frequency of the output signal of the oscillator 111 by the frequency division ratio N1 specified by the setting circuit 17, generates a reference frequency signal, and outputs the reference frequency signal to the phase comparator 12.
[0028]
The phase comparator 12 compares the phase of the frequency-divided signal from the second frequency divider 15 with the phase of the reference frequency signal output from the reference frequency signal output unit 11, and determines the pulse width corresponding to the phase difference between the two signals. Is output to the loop filter 13 as a phase difference signal.
[0029]
The loop filter 13 removes (attenuates) a frequency component higher than the cutoff frequency fc among the frequency components included in the phase difference signal, substantially integrates the same, and smoothes the phase difference signal. Is output to the voltage controlled oscillator 14.
[0030]
The voltage controlled oscillator 14 generates an oscillation signal having an oscillation frequency corresponding to the control voltage of the phase difference signal, and outputs the generated oscillation signal. This oscillation signal is synchronized with the reference frequency signal output from the reference frequency signal output unit 11.
[0031]
The second frequency divider 15 divides the output signal of the voltage controlled oscillator 14 by the frequency division ratio i or i + 1 instructed by the frequency division ratio switching control circuit 16 at that time, and supplies the divided signal to the phase comparator 12. Output.
[0032]
According to such a configuration, the frequency division ratio N1 of the first frequency divider 112 (expressed as an integer) and the frequency division ratio N2 of the second frequency divider 15 (i + f: i is an integer part, f is a decimal part) Is such that the error between the output frequency determined by the dividing ratios N1 and N2 and the specified frequency is within an allowable error range and the error is as small as possible, and is expressed by the frequencies C · f and C · (1-f). Since the selected spurious is selected to be located outside the pass band of the loop filter 13, the spurious is attenuated, and an output signal with a small error and a small noise can be obtained.
[0033]
Next, the setting circuit 17 will be described in more detail with reference to FIGS.
The setting circuit 17 includes a processor 171, a ROM 172, a RAM 173, and an input / output unit (I / O) 174, as shown in FIG.
The ROM 172 stores a cutoff frequency fc of the loop filter 13, a frequency of the clock C, an oscillation frequency fr of the oscillator 111, and an operation program of the processor 171.
The RAM 173 functions as a work area for the processor 171.
The I / O 174 receives an output frequency instruction signal indicating the output frequency (the oscillation frequency of the voltage controlled oscillator 14) from the outside, and notifies the processor 171 of the output frequency instruction signal. Further, the frequency division ratios N1 and N2 calculated by the processor 171 are output to the first and

second frequency dividers

112 and 15, respectively.
The processor 171 is constituted by a microprocessor or the like, operates according to an operation program stored in the ROM 172, and sets the frequency division ratios N1 and N2 to be set to output the frequency specified by the output frequency instruction signal. 3 and is output in accordance with the flowchart of FIG.
[0034]
Next, the operation of the setting circuit 17 having such a configuration will be described with reference to the flowchart of FIG.
When a new output frequency indication signal is supplied from outside, the I / O 174 provides it to the processor 171.
In response to this signal, processor 171 starts the processing shown in FIG. 3 according to the operation program stored in ROM 172.
[0035]
First, the processor 171 obtains a combination of the frequency division ratios N1 and N2 that can obtain the specified frequency fout (step S11).
The method of this processing itself is arbitrary. For example, the frequency division ratio N1 is scanned within a variable range, and a frequency division ratio N2 that can obtain a frequency near the target frequency fout is obtained for each frequency division ratio N1. Then, the error between the frequency obtained by this combination and the target frequency fout is obtained, and N1, N2, and the error are registered in the RAM 173 for the combination in which the error is within the allowable range. In other words, with respect to all selectable combinations of N1 and N2, the difference between the frequency obtained by the combination and the target frequency fout is obtained, and the error within the allowable error is picked up and registered in the RAM 173.
[0036]
Next, the processor 171 sorts the N1: N2: error combination data registered in the RAM 173 in ascending order of the error (step S12).
[0037]
Next, 1 is set to a pointer j indicating the order of the smallest error (step S13).
Next, a combination of frequency division ratios having the j-th smallest error is selected (step S14), and frequencies C · f and C · (1-f) are obtained (step S15).
Next, it is determined whether or not the frequencies C · f and C · (1−f) (spurious frequencies) obtained in step S15 are in a higher band (attenuation frequency band) than the cutoff frequency fc of the loop filter 13. It is determined (step S16).
[0038]
Next, when it is determined that both spurious positions are outside the passband (step S16; Yes), the j-th N1 and N2 (i + f) are output via the I / O 174 (step S17). The process ends.
On the other hand, if it is determined in step S16 that at least one is located within the pass band (fc or lower) (step S16; No), the processing is performed for all combinations of the dividing ratios N1 and N2 registered in the RAM 173. It is determined whether the process has been completed (step S18). If it is determined that the processing has not been completed (there is a set of remaining frequency division ratios) (Step S18; No), j is incremented by 1 (Step S19), and the processing from Step S14 is repeated.
[0039]
On the other hand, if it is determined in step S18 that the process has been completed (there is no remaining set of frequency division ratios) (step S18; Yes), predetermined error processing (for example, frequency division ratio N1 with the smallest error) is performed. And N2 are selected and output) (step S20), and the process ends.
[0040]
According to this method, the frequency division ratios N1 and N2 that make the error with the specified output frequency fout within the range of a preset allowable error and locate the spurious noise in the attenuation region of the loop filter 13 are determined. You can ask.
[0041]
In this example, the division ratios N1 and N2 are calculated each time the output frequency is instructed. However, the optimum division ratios N1 and N2 are set in advance for all selectable output frequencies. Is calculated in advance and registered and prepared in a table 175 as shown in FIG. 4, and when there is an instruction of the output frequency fout, the table 175 is accessed and the specified output frequency fout is The corresponding frequency division ratios N1 and N2 may be read and output. According to such a configuration, it is possible to obtain and register the optimum frequency division ratios N1 and N2 in consideration of factors other than the error by an experiment or the like.
[0042]
In carrying out the present invention, various modes are conceivable, and the present invention is not limited to the above embodiments.
For example, the circuit configurations of the PLL circuits shown in FIGS. 1, 2, and 4 can be arbitrarily changed. Similarly, the flowchart shown in FIG. 3 can be arbitrarily changed as long as the same function can be realized.
In the above-described embodiment, an example has been described in which two division ratios i and i + 1 are set as the division ratios set in the second divider 15, but three or more division ratios are set. You may make it. For example, the frequency division ratio switching control circuit 16 performs ΔΣ modulation of the frequency division ratio (i + f) to obtain an integer frequency division ratio that changes by three or more, and sets this to the second frequency divider 15. You may do so.
In the above embodiment, a circuit composed of the oscillator 111 and the first frequency divider 112 is used as the reference frequency signal output circuit 11, but the frequency can be changed by the instruction from the setting circuit 17 and the stable frequency can be changed. Any circuit that can oscillate in the circuit can be used.
[0043]
【The invention's effect】
As described above, according to the present invention, it is possible to suppress spurious and improve signal purity.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a phase locked loop circuit according to a first embodiment of the present invention.
FIG. 2 is an explanatory diagram showing a configuration example of a setting circuit 17 shown in FIG.
FIG. 3 is a flowchart illustrating an operation example of the processor illustrated in FIG. 2;
FIG. 4 is a block diagram showing another configuration example of the setting circuit shown in FIG. 1;
[Explanation of symbols]
11 Reference Frequency Signal Output Unit 12 Phase Comparator 13 Loop Filter 14 Voltage Controlled Oscillator 15 Second Divider 16 Dividing Ratio Switching Control Circuit 17 Setting Circuit 111 Oscillator 112 First Divider

Claims

A reference signal output circuit comprising: a first oscillator; and a first frequency divider for dividing an oscillation signal of the first oscillator to output a reference signal having a reference frequency;
A phase comparator that compares the phase of the reference signal and the phase of the predetermined frequency-divided signal, and outputs a signal having a signal level corresponding to the phase difference between the two signals;
A filter having a pass frequency band and an attenuation frequency band, and filtering an output signal of the phase comparator;
A second oscillator that oscillates at a frequency according to the signal level of the signal from the phase comparator that has passed through the filter;
A second frequency divider that divides an output signal of the second oscillator by a predetermined frequency division ratio and outputs the frequency-divided signal to the phase comparator as the predetermined frequency-divided signal;
In order to obtain an output frequency indicated by the output frequency instruction signal, a first frequency division ratio in an integer expression to be set in the first frequency divider is obtained and set in the first frequency divider, and the second frequency is set in the second frequency divider. A setting circuit for obtaining and outputting a second frequency division ratio in decimal representation to be set in the frequency divider;
A frequency division ratio switching control circuit for switching at least two integer frequency division ratios and setting the second frequency divider in order to obtain a second frequency division ratio output from the setting circuit as an average value;
With
The setting circuit converts a first frequency division ratio set in a first frequency divider and a second frequency division ratio expressed in a decimal number to be set in the second frequency divider into a frequency division ratio switching control circuit. Set so that the frequency of the noise generated by the switching of the frequency division ratio is located in the attenuation frequency band of the filter,
A phase locked loop circuit characterized by the above.

In the setting circuit, an output frequency, a first division ratio in an integer representation set in the first divider, and a second division ratio in a decimal representation set in the second divider correspond in advance. A table which is attached and set, and reads and outputs first and second frequency division ratios corresponding to the output frequency indicated by the output frequency instruction signal from the table,
The phase-locked loop circuit according to claim 1, wherein:

The frequency division ratio switching control circuit receives the clock signal, and obtains the designated second frequency division ratio in the decimal representation in order to obtain the second frequency division ratio in the decimal representation. Setting a frequency division ratio of 3 and a fourth frequency division ratio having a difference of 1 from the third frequency division ratio in the second frequency divider according to the clock signal;
The phase-locked loop circuit according to claim 1 or 2, wherein:

The setting circuit may be a product of a frequency of the clock signal and a decimal part of a second division ratio expressed in a decimal number and / or a frequency part of the clock signal and a decimal part of a second division ratio expressed in a decimal number, and 1 Setting the first frequency division ratio so that a frequency represented by a product of the first and second differences is located in an attenuation frequency band of the filter.
The phase-locked loop circuit according to claim 3, wherein:

Outputting a reference signal by dividing the predetermined signal by a first division ratio;
Comparing the phase of the reference signal with the phase of the predetermined frequency-divided signal, and outputting a phase difference signal corresponding to the phase difference between the two signals;
An attenuation step of attenuating and outputting a signal component of a predetermined attenuation frequency band among frequency components included in the phase difference signal,
Outputting an oscillation signal having a frequency according to the signal level of the phase difference signal in which the signal component of the attenuation frequency band has been attenuated,
A frequency dividing step of dividing the oscillation signal by a second frequency dividing ratio expressed as a decimal and outputting as the predetermined frequency divided signal;
A setting step of setting the first and second frequency division ratios to obtain an output frequency indicated by an output frequency instruction signal;
With
In the frequency dividing step, frequency division is performed by switching a frequency dividing ratio of at least two integers in order to obtain a frequency dividing ratio of a second decimal representation as an average value.
In the setting step, the first and second frequency division ratios are set so that the frequency of noise generated by switching the frequency division ratio in the frequency division step is located in the attenuation frequency band in the attenuation step.
A noise component removing method characterized by the above-mentioned.