JP2004235499A5 - - Google Patents
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- Publication number
- JP2004235499A5 JP2004235499A5 JP2003023324A JP2003023324A JP2004235499A5 JP 2004235499 A5 JP2004235499 A5 JP 2004235499A5 JP 2003023324 A JP2003023324 A JP 2003023324A JP 2003023324 A JP2003023324 A JP 2003023324A JP 2004235499 A5 JP2004235499 A5 JP 2004235499A5
- Authority
- JP
- Japan
- Prior art keywords
- potential
- power supply
- transistor
- supplied
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 15
- 230000003321 amplification Effects 0.000 claims 2
- 238000003199 nucleic acid amplification method Methods 0.000 claims 2
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003023324A JP2004235499A (ja) | 2003-01-31 | 2003-01-31 | 半導体装置 |
| US10/768,394 US6985023B2 (en) | 2003-01-31 | 2004-01-30 | Selective switching of a transistor's back gate potential |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003023324A JP2004235499A (ja) | 2003-01-31 | 2003-01-31 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2004235499A JP2004235499A (ja) | 2004-08-19 |
| JP2004235499A5 true JP2004235499A5 (https=) | 2005-04-21 |
Family
ID=32952154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003023324A Pending JP2004235499A (ja) | 2003-01-31 | 2003-01-31 | 半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6985023B2 (https=) |
| JP (1) | JP2004235499A (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5143483B2 (ja) * | 2007-07-03 | 2013-02-13 | ルネサスエレクトロニクス株式会社 | 昇圧回路、およびその昇圧回路を備える集積回路 |
| US20100321094A1 (en) * | 2010-08-29 | 2010-12-23 | Hao Luo | Method and circuit implementation for reducing the parameter fluctuations in integrated circuits |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2585450B2 (ja) | 1990-04-18 | 1997-02-26 | 東芝マイクロエレクトロニクス株式会社 | 半導体回路装置 |
| JPH07131332A (ja) | 1993-11-04 | 1995-05-19 | Pfu Ltd | Cmos回路 |
| JP3379050B2 (ja) | 1993-11-15 | 2003-02-17 | 富士通株式会社 | 半導体装置 |
| US5606287A (en) | 1994-06-17 | 1997-02-25 | Fujitsu Limited | Operational amplifier having stable operations for a wide range of source voltage, and current detector circuit employing a small number of elements |
| JP3180662B2 (ja) * | 1996-03-29 | 2001-06-25 | 日本電気株式会社 | 電源切り替え回路 |
| JP3814385B2 (ja) * | 1997-10-14 | 2006-08-30 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
| DE69823982D1 (de) * | 1998-05-29 | 2004-06-24 | St Microelectronics Srl | Monolithisch integrierter Umschalter für elektrisch programmierbare Speicherzellenvorrichtungen |
| JP2001186007A (ja) * | 1999-12-24 | 2001-07-06 | Sharp Corp | 金属酸化膜半導体トランジスタ回路およびそれを用いた半導体集積回路 |
-
2003
- 2003-01-31 JP JP2003023324A patent/JP2004235499A/ja active Pending
-
2004
- 2004-01-30 US US10/768,394 patent/US6985023B2/en not_active Expired - Fee Related
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