JP2004228308A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent side faces of conductive films from being exposed in contact holes, in a semiconductor device wherein the contact holes are formed among the plurality of conductive films formed at spaces. <P>SOLUTION: On top of a semiconductor substrate 11, gate electrodes 15 are formed at spaces via a silicon oxide film 12. The gate electrodes 15 are coated with an etching stopper film 19 and an interlayer insulation film 20. The contact holes 21 are formed in the interlayer insulation film 20, and a metal film 22 which constitutes a contact is formed inside the contact holes 21. The contact holes 21 are arranged so that the centers thereof may fall on the centers between each two adjacent gate electrodes 15. A dimension b of an upper opening of the contact holes 21 should satisfy b>a+2d<SB>max</SB>, where d<SB>max</SB>is the maximum value for overlay displacement when patterning the contact holes 21 and the reference (a) is a distance between the gate electrodes 15. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a contact and a method of manufacturing the same, and more particularly, to a semiconductor device having a self-aligned contact that can be formed in a self-aligned manner with a conductive film such as a gate wiring and a method of manufacturing the same.
[0002]
[Prior art]
In a semiconductor device such as a semiconductor integrated circuit device using a MIS transistor or a semiconductor memory device using a DRAM cell, a wiring pitch of a gate wiring, a bit wiring and the like tends to be reduced with miniaturization of the semiconductor device.
[0003]
However, when the wiring pitch is reduced, in the process of patterning the contact holes between the wirings, if the overlapping displacement between the patterns is large, the contact hole formation position is shifted from between the wirings. However, there is a problem that the semiconductor device does not operate due to a short circuit with the gate wiring or the bit wiring.
[0004]
Therefore, in recent years, a silicon nitride film is formed so as to cover the upper surface and side surfaces of a conductive film constituting a wiring such as a gate wiring, and the silicon nitride film is used as an etching stopper film to form a conductive film such as a gate wiring. On the other hand, a self-aligned contact that forms a contact hole in a self-aligned manner has been proposed.
[0005]
Hereinafter, a conventional method for manufacturing a semiconductor device having a self-aligned contact will be described with reference to the drawings.
[0006]
16 (a) to 16 (c) and FIGS. 17 (a) to 17 (c) show a method of manufacturing a semiconductor device having a conventional MOS transistor. Here, FIGS. 16 (a), 16 (b), and 17 (a) to 17 (c) show cross-sectional structures in the order of steps, and FIG. 16 (c) shows the steps shown in FIG. 16 (b). 2 shows a planar configuration.
[0007]
First, as shown in FIG. 16A, a silicon oxide film 102, a polysilicon film 103, a tungsten film 104, and a first silicon nitride film 105 are formed on a semiconductor substrate 101 by a chemical vapor deposition (CVD) method. Are sequentially deposited, a first resist pattern 106 covering the gate electrode formation region is formed by a photolithography method using a photomask (not shown) having a gate pattern.
[0008]
Subsequently, the first silicon nitride film 105, the tungsten film 104, the polysilicon film 103, and the silicon oxide film 102 are sequentially and selectively etched by a dry etching method using the first resist pattern 106 as a mask. Thus, the gate electrode 107 of the MOS transistor is formed from the polysilicon film 103 and the tungsten film 104.
[0009]
Next, as shown in FIG. 16B, after removing the first resist pattern 106, impurities are diffused into the semiconductor substrate using the gate electrodes 107 adjacent to each other as a mask, so that the source electrode of the MOS transistor is removed. An impurity diffusion region to be a drain electrode is formed. Subsequently, the second silicon nitride film 109 is formed on the entire surface of the semiconductor substrate 101 so as to include the first silicon nitride film 105 and the wall surface of the gate electrode 107 and the first silicon nitride film 105. Is deposited. Here, the first silicon nitride film 105 and the second silicon nitride film 109 become an etching stopper film 110 covering the gate electrode.
[0010]
Subsequently, after an interlayer insulating film 111 made of silicon oxide is deposited on the second silicon nitride film 109, a contact hole forming region is formed by a photolithography method using a photomask (not shown) having a hole pattern. Then, a second resist pattern 112 having an opening 112a having a plane circular shape is formed.
[0011]
The planar arrangement of the openings 112a of the second resist pattern 112 will be described with reference to FIG. As shown in FIG. 16C, the openings 112a of the second resist pattern 112 are arranged such that the centers are located at the centers of the gate electrodes 107 adjacent to each other. Here, the gate electrode 107 is patterned so that the width dimension is about 180 nm and the interval between the gate electrodes 107 is about 320 nm (that is, the pitch between gate wirings is about 500 nm). With respect to the gate electrode 107, the opening 112a, which is a hole pattern, is designed such that the opening diameter is about 200 nm, the pitch in the direction perpendicular to the gate is about 500 nm, and the pitch in the direction parallel to the gate is about 500 nm. . At this time, the distance between the gate electrode 107 and the opening 112a is about 60 nm on both sides.
[0012]
Next, as shown in FIG. 17A, a contact hole 113 is formed in the interlayer insulating film 111 by a dry etching method using the second resist pattern 112. The etching gas for etching the interlayer insulating film 111 is C ₄ F ₆ Or C ₅ F ₈ Is used.
[0013]
Next, as shown in FIG. 17B, the second silicon nitride film 109 located below the contact hole 113 is removed to expose the impurity diffusion region 108 of the semiconductor substrate 101. CF as the etching gas for the second silicon nitride film 109 ₄ Or CHF ₃ Is used.
[0014]
Next, as shown in FIG. 17C, by forming a metal film 114 so as to fill the inside of the contact hole 113, a contact and a wiring layer electrically connected to the impurity diffusion region 108 are formed.
[0015]
However, in the photolithography process for forming the second resist pattern 112, if a misalignment occurs in the superposition of the hole pattern with respect to the gate pattern, the designed position (that is, the opening 112a) is positioned with respect to the gate electrode 107. (A position substantially deviated from the center of the adjacent gate electrodes 107) is formed in the opening 112a.
[0016]
Hereinafter, a case where a misalignment occurs in a conventional method of manufacturing a semiconductor device will be specifically described with reference to FIGS.
[0017]
FIG. 18A shows a planar configuration in the case where misalignment between patterns occurs in the photolithography step shown in FIG. 16B, and FIGS. 18B and 18C respectively show FIGS. FIG. 18A shows a cross-sectional configuration of a step corresponding to the step shown in FIG. 17A and FIG.
[0018]
As shown in FIG. 18A, the center of the contact hole 113 is displaced from the center of the adjacent gate electrodes 107 due to misalignment of the exposure apparatus. FIG. 18A shows a case where the overlay displacement is about 80 nm. The amount of misalignment is measured as the distance d between the center line between the gate electrodes 107 adjacent to each other and the center of the contact hole 113.
[0019]
Here, the amount of misalignment is a value determined by the accuracy of an exposure apparatus (stepper) used for pattern exposure when forming the second resist pattern 112, and its maximum value can be measured in advance.
[0020]
Next, as shown in FIG. 18B, when the interlayer insulating film 111 is etched using the second resist pattern 112 as a mask, the etching stopper film 110 located above the gate electrode 107 is formed at the end of the contact hole 113. Is exposed. At this time, the upper portion of the etching stopper film 110 is etched, but the gate electrode 107 is not exposed because the etching rate of the etching gas with respect to the silicon nitride film is small.
[0021]
Next, as shown in FIG. 18C, in the step of removing the second silicon nitride film 109 exposed at the bottom of the contact hole 113, the upper portion of the etching stopper film 110 is further etched. Since the first silicon nitride film 105 is formed sufficiently thicker than the silicon nitride film 109, the gate electrode 107 is not exposed.
[0022]
As described above, in the conventional method of manufacturing a semiconductor device, by forming the etching stopper film 110, it is possible to secure a margin for overlapping the hole pattern with the gate pattern, and the contact hole 113 is self-aligned with the gate electrode 107. Is formed.
[0023]
[Patent Document 1]
JP-A-10-12868
[0024]
[Problems to be solved by the invention]
However, in the conventional method of manufacturing a semiconductor device, when the wall surface of the contact hole 113 is disposed so as to be substantially in contact with the side surface of the gate electrode 107 due to misalignment of the hole pattern, a metal film serving as a contact is formed. There is a problem that a short circuit occurs between 114 and the gate electrode 107.
[0025]
In the following, the effect of the overlay shift amount during the formation of the contact hole will be specifically described.
[0026]
FIG. 19 is a graph showing the relationship between the amount of misalignment of the hole pattern with respect to the gate pattern and the leakage current between the contact and the gate. 19, the horizontal axis represents the center of the gate electrodes 107 and the opening when the formation position is shifted from a predetermined position in the step of forming the second resist pattern 112 shown in FIG. 16C. It represents the distance from the center of 112a. The vertical axis indicates a leak current flowing between the metal film 114 and the gate electrode 107 when the second resist pattern 112 is formed shifted.
[0027]
As shown in FIG. 19, when the overlay displacement amount is smaller than 40 nm, no current flows between the metal film 114 and the gate electrode 107, and no short circuit occurs between the contact and the gate. Similarly, even when the overlay displacement amount is larger than 80 nm, no short circuit occurs between the contact and the gate. On the other hand, when the overlay displacement is in the range of about 40 to 80 nm, a leak current is generated between the metal film 114 and the gate electrode 107. In particular, when the overlay displacement is about 60 nm, the leakage current between the metal film 114 and the gate electrode 107 is large, and it is apparent that a short circuit occurs between the contact and the gate.
[0028]
FIG. 20 is a graph showing the relationship between the amount of misalignment of the hole pattern with respect to the gate pattern and the etching depth of the etching stopper film. Here, the etching depth of the etching stopper film refers to the etching depth on the same plane as the side surface of the gate electrode 107 of the etching stopper film 110 when the etching of the interlayer insulating film 111 is completed.
[0029]
As shown in FIG. 20, when the overlay displacement amount is 20 nm or less, the etching stopper film 110 is hardly etched. This is because, like the second resist pattern 112 in FIGS. 16B and 16C, the opening 112a does not overlap the upper side of the etching stopper film 110.
[0030]
When the amount of misalignment increases, the opening 112a of the second resist pattern 112 is disposed so as to overlap the upper side of the gate electrode 107, so that the etching stopper film 110 is etched from the upper surface side. The etching depth becomes maximum when the amount of misalignment is about 60 nm.
[0031]
As described above, when the amount of misalignment is about 60 nm, the portion of the etching stopper film 110 formed on the same plane as the side surface of the gate electrode 107 is deeply etched. Are short-circuited.
[0032]
Here, in the conventional semiconductor device, the diameter of the contact hole 113 is about 200 nm, and the distance between the gate electrodes 107 is about 320 nm. The horizontal distance from the electrode 107 is about 60 nm. In other words, the case where the overlay displacement amount is about 60 nm is the case where the wall surface of the contact hole 113 is formed at a position in contact with the gate electrode 107. Therefore, the wall surface of the opening 112a of the second resist pattern 112 is It can be said that a short circuit occurs between the gate electrode 107 and the contact when the contact is arranged so as to be substantially in contact with the side surface of the contact 107.
[0033]
Hereinafter, in the conventional method for manufacturing a semiconductor device, the order of steps in the case where misalignment occurs such that the wall surface of the opening 112a is arranged above the side surface of the gate electrode 107 will be described with reference to FIGS. This will be described with reference to FIG. Here, FIG. 21A shows a plan configuration of the same process as the process shown in FIG. 16B, and FIGS. 21B and 21C show FIGS. 17A and 17B, respectively. 3) shows a cross-sectional configuration of a process corresponding to the process shown in FIG.
[0034]
As shown in FIG. 21A, when the overlay displacement amount is shifted from the predetermined position by about 60 nm, the side surface of the opening 112a of the second resist pattern 112 is flush with the side surface of the gate electrode 107. It is arranged so that it may contact. At this time, the edge of the etching stopper film 110 is slightly exposed below the opening 112a.
[0035]
Next, as shown in FIG. 21B, by etching the interlayer insulating film 111 using the second resist pattern 112 as a mask, the end of the etching stopper film 110 is etched. At this time, the etching depth of the etching stopper film 110 on the same plane as the side surface of the gate electrode 107 is larger than when the opening 112a is arranged above the gate electrode 107.
[0036]
Next, as shown in FIG. 21C, in the step of removing the second silicon nitride film exposed on the bottom surface of the opening 112a, even the second silicon nitride film 109 in contact with the side surface of the gate electrode 107 is removed. The gate electrode 107 is partially removed and the gate electrode 107 is exposed. Therefore, when the metal film 114 is buried in the contact hole 113 in the same manner as in the step shown in FIG. 17C, the side surface of the gate electrode 107 and the metal film 114 are short-circuited.
[0037]
Hereinafter, the manner of etching the etching stopper film 110 in the step of etching the interlayer insulating film 111 based on the difference in the amount of misalignment will be specifically described with reference to FIGS. 22A and 22B. Here, FIG. 22A shows a case where the opening 112a is arranged so as to overlap the upper side of the gate electrode 107, similarly to FIG. 18A, and FIG. 22B shows FIG. FIG. 4 is a partially enlarged view of a cross-sectional configuration showing a case where a wall surface of an opening 112a is arranged on substantially the same plane as a side surface of a gate electrode 107, similarly to FIG.
[0038]
As shown in FIGS. 22A and 22B, in the step of etching the interlayer insulating film 111, a reaction product of an etching gas and the interlayer insulating film 111 is deposited on a surface to be etched, and a polymer deposition film is formed. The step of forming 115 and the step of etching the surface to be etched by the etching gas (that is, the surfaces of the interlayer insulating film 111, the etching stopper film 110, and the polymer deposition film 115) are in a state of competition.
[0039]
Here, as shown in FIG. 22A, when the opening 112a is arranged so as to overlap the upper part of the gate electrode 107, the surface to be etched is gentle because the area of the upper surface of the etching stopper film 110 is large. It becomes a slope. At this time, the polymer deposition film 115 is more likely to be deposited on a horizontal surface or a gentle slope than a vertical surface or a steep slope with respect to the etching direction. As a result, the etching does not easily proceed, so that the etching depth of the etching stopper film 110 is reduced.
[0040]
On the other hand, as shown in FIG. 22B, when the opening 112a is arranged so as to substantially coincide with the upper side of the side surface of the gate electrode 107, the side surface of the etching stopper film is etched. At this time, since the exposed area on the upper surface of the etching stopper film 110 is small, the surface to be etched of the etching stopper film has a steep slope. Accordingly, since the thickness of the polymer deposition film 115 on the upper surface of the etching stopper film 110 becomes smaller, the etching proceeds more easily, and the etching depth of the etching stopper film 110 becomes larger.
[0041]
As described above, when the wall surface of the opening 112a is disposed in contact with the substantially same surface as the side surface of the gate electrode 107, the etching stopper film 110 is etched deeply.
[0042]
As described above, in the conventional method of manufacturing a semiconductor device, in the photolithography step of forming a hole pattern, the etching stopper film 110 may be deeply etched depending on the amount of misalignment between patterns. In this case, there is a problem that the gate electrode 107 is exposed inside the contact hole 113 and short-circuits with the contact.
[0043]
The present invention solves the above-mentioned conventional problems, and in a semiconductor device in which a contact hole is formed between a plurality of conductive films formed at intervals from each other, a side surface of the conductive film is not exposed from the contact hole. The purpose is to do.
[0044]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is to prevent the wall surface of the through hole from being in contact with the side surface of the first conductive film even when an overlay error occurs in the step of forming the through hole. The size of the opening of the through hole may be increased, or a protective film covering the wall surface of the through hole may be formed after forming the through hole.
[0045]
Specifically, the semiconductor device of the present invention includes a plurality of conductive films formed on a semiconductor substrate and extending in parallel at an interval from each other; an etching stopper film covering each side surface and an upper surface of the plurality of conductive films; An interlayer insulating film formed on a semiconductor substrate including an etching stopper film, wherein the interlayer insulating film has a maximum value of the amount of misalignment between adjacent conductive films in a plurality of conductive films. An opening dimension in a direction intersecting with a direction in which the plurality of conductive films extends in the through hole has a through hole patterned using an exposure apparatus being measured, and is larger than an interval between conductive films adjacent to each other. The difference between the dimension and the interval between the adjacent conductive films is larger than twice the maximum value of the overlay shift amount.
[0046]
According to the semiconductor device of the present invention, since the difference between the opening size of the through hole and the distance between the conductive films is larger than twice the maximum value of the amount of misalignment, misalignment occurs in the process of forming the through hole. Even in this case, since the wall surface above the through hole is disposed above the conductive film, the wall surface above the through hole is not formed so as to be substantially in contact with the side surface of the conductive film. Therefore, in the through hole forming step, the side surface portion of the etching stopper film is not sharply etched, so that the through hole is formed so as not to expose the side surface of the conductive film.
[0047]
In the semiconductor device of the present invention, the planar shape of the through-hole is preferably an elliptical shape or an elliptical shape having a major axis in a direction intersecting with a direction in which the plurality of conductive films extend.
[0048]
With this configuration, in the direction intersecting with the direction in which the conductive film extends, the opening size is ensured such that the wall surface above the through hole is arranged above the conductive film, but the opening size is maintained in the direction in which the conductive film extends. Therefore, through holes can be formed with high density in the direction in which the conductive film extends. Thereby, the density of the semiconductor element can be increased.
[0049]
In the semiconductor device of the present invention, the etching stopper film is preferably made of silicon nitride.
[0050]
This makes it possible to reduce the etching rate of the etching stopper film at the time of forming the through hole, so that a self-aligned contact using the etching stopper film as a mask is reliably formed.
[0051]
In the semiconductor device of the present invention, the interlayer insulating film is preferably made of silicon oxide.
[0052]
By doing so, the etching selectivity of the interlayer insulating film with respect to the etching stopper film can be improved when the through hole is formed, and a self-aligned contact is reliably formed.
[0053]
In the semiconductor device of the present invention, the plurality of conductive films are preferably made of at least one conductive material of polysilicon, tungsten, and an alloy containing tungsten.
[0054]
A first method for manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of conductive films extending in parallel at intervals on a semiconductor substrate, and an etching method for covering the respective side surfaces and upper surfaces of the plurality of conductive films. A step of forming a stopper film, a step of forming an interlayer insulating film over the entire surface including an etching stopper film on a semiconductor substrate, and a step of forming a resist film on the interlayer insulating film, and then setting a maximum value of the amount of misalignment. Patterning an opening in which both ends of the resist film overlap the upper sides of adjacent conductive films in the plurality of conductive films using an exposure apparatus in which the resist film is measured in advance; and a patterned resist film and an etching stopper. By performing etching on the interlayer insulating film using the film as a mask, a through hole is formed between adjacent conductive films. A degree, the overlapping part with the upper conductive film in the opening is greater than the displacement amount overlapped width in the direction orthogonal to the direction in which the plurality of conductive films extend is.
[0055]
According to the first method for manufacturing a semiconductor device of the present invention, the width of the portion of the opening of the resist film that overlaps with the upper side of the conductive film in the direction intersecting with the direction in which the plurality of conductive films extends is smaller than the amount of misalignment. Because of the large size, the edge of the opening of the resist film is arranged so as to overlap with the upper side of the first conductive film even if the misalignment occurs. Therefore, since the wall surface of the opening of the resist film is not disposed so as to be in contact with the same surface as the side surface of the conductive film, the side surface portion of the etching stopper film is not sharply etched, and A through hole can be formed so as not to be exposed.
[0056]
In the first method for manufacturing a semiconductor device of the present invention, it is preferable that the planar shape of the opening of the resist film is an elliptical shape or an elliptical shape having a major axis in a direction intersecting a direction in which the plurality of conductive films extend.
[0057]
With this configuration, in the direction intersecting with the direction in which the conductive film extends, the opening size is ensured so that the end of the opening overlaps the upper side of the conductive film, but the opening size is reduced in the direction in which the conductive film extends. Therefore, the through holes can be formed with high density in the direction in which the conductive film extends. Thereby, the density of the semiconductor element can be increased.
[0058]
A second method for manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of conductive films extending in parallel at intervals from each other on a semiconductor substrate, and an etching method for covering the respective side surfaces and upper surfaces of the plurality of conductive films. A step of forming a stopper film, a step of forming an interlayer insulating film over the entire surface including the etching stopper film on the semiconductor substrate, and a step of forming a plurality of conductive films between adjacent conductive films on the interlayer insulating film. Forming a resist film having an opening in the opening, forming a through hole between adjacent conductive films by etching the interlayer insulating film using the resist film having the opening as a mask, Forming a protective film covering the wall surface of the hole.
[0059]
According to the second method of manufacturing a semiconductor device of the present invention, since the method includes the step of forming the protective film covering the wall surface of the through hole, when the side surface of the gate electrode is exposed inside the through hole during the formation of the through hole, Also, the exposed portion of the gate electrode can be protected by the protective film.
[0060]
In the second method for manufacturing a semiconductor device of the present invention, in the step of forming the protective film, it is preferable that the protective film is formed on the interlayer insulating film over the entire surface including the wall surface and the bottom surface of the through hole.
[0061]
In the second method for manufacturing a semiconductor device according to the present invention, in the step of forming the etching stopper film, the etching stopper film is formed over the semiconductor substrate over the entire surface including the upper surfaces and the wall surfaces of the plurality of conductive films. Is preferred.
[0062]
In the second method of manufacturing a semiconductor device according to the present invention, after the step of forming the through hole and before the step of forming the protective film, a step of removing a bottom portion of the through hole in the etching stopper film; It is preferable that the method further includes a step of removing a bottom surface portion of the through hole in the protective film after the step of forming the film.
[0063]
With this configuration, the semiconductor substrate located on the bottom surface of the through hole is exposed, so that a contact connected to the semiconductor substrate can be reliably formed in the through hole.
[0064]
The method for manufacturing a semiconductor device according to the second aspect of the present invention preferably further includes a step of sequentially removing the protective film and the etching stopper film located on the bottom surface of the through hole after the step of forming the protective film.
[0065]
With this configuration, when the semiconductor substrate located on the bottom surface of the through hole is exposed, damage to the semiconductor substrate due to etching can be reduced.
[0066]
In the second method for manufacturing a semiconductor device according to the present invention, the protective film is preferably made of silicon oxide.
[0067]
In the first method for manufacturing a semiconductor device or the second method for manufacturing a semiconductor device according to the present invention, the etching stopper film is preferably made of silicon nitride.
[0068]
With this configuration, in the step of forming a through hole in the interlayer insulating film, the etching is reliably stopped by the etching stopper film, so that a self-aligned contact can be reliably formed.
[0069]
In the first method for manufacturing a semiconductor device or the second method for manufacturing a semiconductor device according to the present invention, the interlayer insulating film is preferably made of silicon oxide.
[0070]
This makes it possible to improve the etching selectivity with respect to the etching stopper film in the step of forming a through hole in the interlayer insulating film, so that a self-aligned contact can be reliably formed.
[0071]
In the first method for manufacturing a semiconductor device or the second method for manufacturing a semiconductor device according to the present invention, the plurality of conductive films are preferably made of at least one conductive material of polysilicon, tungsten, and an alloy containing tungsten. .
[0072]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
A first embodiment of the present invention will be described with reference to the drawings.
[0073]
FIG. 1A shows a plan configuration of the semiconductor device according to the first embodiment, and FIG. 1B shows a cross-sectional configuration taken along line Ib-Ib in FIG. 1A. In FIG. 1A, the illustration of the wiring layer and the contacts is omitted so that the contact holes are exposed.
[0074]
As shown in FIGS. 1A and 1B, for example, a polycrystalline silicon film having a thickness of about 80 nm is formed on a semiconductor substrate 11 made of silicon via a silicon oxide film 12 having a thickness of about 2 nm. A silicon film 13 and a tungsten film 14 having a thickness of about 60 nm are stacked so as to extend in parallel at intervals. Here, the polysilicon film 13 and the tungsten film 14 constitute a gate electrode 15 of the MIS transistor, and the silicon oxide film 12 becomes a gate insulating film. On the semiconductor substrate 11 on the side of the gate electrode 15, an impurity diffusion region 16 serving as a source electrode or a drain electrode of the MIS transistor is formed.
[0075]
A first silicon nitride film 17 having a thickness of about 200 nm is formed on the upper surface of the gate electrode 15 (that is, the upper surface of the tungsten film 14), and includes the first silicon nitride film 17. On the semiconductor substrate 11, a second silicon nitride film 18 having a thickness of about 30 nm is formed so as to cover the side surface of the gate electrode 15.
[0076]
Here, the first silicon nitride film 17 and the second silicon nitride film 18 serve as an etching stopper film 19 for protecting the gate electrode 15 when forming the contact hole.
[0077]
An interlayer insulating film 20 made of silicon oxide having a thickness of about 800 nm is formed on the etching stopper film 19, and a portion of the interlayer insulating film 20 located between the gate electrodes 15 has a diameter b. A contact hole 21 having a plane circular shape of about 500 nm is provided. A metal film 22 made of, for example, tungsten is formed in the interlayer insulating film 20 so as to fill the inside of the contact hole 21. The metal film 22 becomes a contact and a wiring layer electrically connected to the impurity diffusion region 16.
[0078]
Hereinafter, the planar arrangement of the gate electrode 15 and the contact hole 21 will be specifically described with reference to FIG.
[0079]
The gate electrodes 15 are arranged in parallel at intervals of about 500 nm. Here, the width dimension of the gate electrode 15 is about 180 nm, and the distance a between the adjacent gate electrodes 15 is about 320 nm. In the following description, the direction in which the gate electrode 15 extends is referred to as a gate parallel direction, and the direction orthogonal to the direction in which the gate electrode 15 extends is referred to as a gate orthogonal direction.
[0080]
The pattern of the contact holes 21 (hereinafter referred to as a hole pattern) is arranged such that the pitch in the gate vertical direction is about 500 nm and the pitch in the gate parallel direction is 800 nm. In the step of forming the hole pattern, the gate electrode is formed. In the case where the position of the hole pattern is not shifted with respect to the fifteenth pattern (hereinafter referred to as a gate pattern), that is, when the contact hole 21 is shifted from the designed position, the contact hole 21 Are arranged such that their centers in the direction orthogonal to the gates are located on a center line connecting the gate electrodes 15 adjacent to each other.
[0081]
Since the diameter b of the contact hole 21 is larger than the distance a between the gate electrodes 15, the end in the gate orthogonal direction becomes an overlap region 21 a where the planar arrangement overlaps with the adjacent gate electrodes 15 on both sides. The width c in the direction orthogonal to the gate in the overlap region 21a is about 90 nm.
[0082]
Here, in the step of superimposing the hole pattern on the gate pattern, a deviation may occur in the superposition between the patterns due to the accuracy of the exposure apparatus. In the first embodiment, in the hole pattern forming step, the hole pattern is formed using an exposure apparatus in which the maximum value of the overlay displacement amount is about 80 nm.
[0083]
In the semiconductor device according to the first embodiment, when the semiconductor device is formed without an overlay shift, the width c in the gate parallel direction in the overlap region 21a is larger than the maximum value of the overlay shift amount. Features. That is, the maximum value of the overlay displacement amount is d _max Then, the diameter b of the contact hole on the upper surface of the interlayer insulating film 20 is b> a + 2d _max It is formed so as to satisfy.
[0084]
As a result, the difference between the diameter b of the contact hole 21 and the distance a between the gate electrodes 107 is larger than twice the maximum value of the overlay shift amount, and the hole pattern is shifted from a predetermined position with respect to the gate pattern. Even when the contact hole 21 is formed, a width dimension larger than the maximum value of the amount of misalignment is secured as an overlap margin such that the wall surface of the contact hole 21 does not contact the same surface as the side surface of the gate electrode 15. be able to. Therefore, the end of the contact hole 21 in the direction perpendicular to the gate is not formed in contact with the same surface as the side surface of the gate electrode 15, and a short circuit between the gate electrode 15 and the contact can be prevented.
[0085]
Hereinafter, a method of manufacturing the semiconductor device according to the first embodiment configured as described above will be described with reference to the drawings.
[0086]
2A to 2C and 3A to 3C show a method for manufacturing a semiconductor device according to the first embodiment.
[0087]
First, as shown in FIG. 2A, for example, after a silicon oxide film 12 is formed on a semiconductor substrate 11 by a thermal oxidation method, a polysilicon film having a thickness of about 80 nm is formed by a chemical vapor deposition (CVD) method. A silicon film 13, a tungsten film 14 having a thickness of about 60 nm, and a first silicon nitride film 17 having a thickness of about 200 nm are sequentially formed.
[0088]
Thereafter, a photosensitive resist material is applied on the first silicon nitride film 17 to form a resist film. Subsequently, the resist film is subjected to pattern exposure by a photolithography method using a photomask having a gate pattern, and then the exposed resist film is developed, so that the first resist covering the gate electrode formation region is formed. The pattern 23 is formed.
[0089]
Next, as shown in FIG. 2B, the first silicon nitride film 17, the tungsten film 14, the polysilicon film 13 and the silicon oxide film 12 are formed by a dry etching method using the first resist pattern 23 as a mask. Selectively remove sequentially. Thereby, the gate electrode 15 is patterned from the polysilicon film 13 and the tungsten film 14.
[0090]
Subsequently, after removing the first resist pattern 23, an impurity is implanted into the semiconductor substrate 11 between the gate electrodes 15 to form an impurity diffusion region 16 serving as a source region or a drain region.
[0091]
Next, as shown in FIG. 2C, a second silicon nitride film 18 having a thickness of about 30 nm and a thickness of about 800 nm are formed on the entire surface of the semiconductor substrate 11 so as to cover the side surfaces of the gate electrode 15. Are sequentially formed, and the upper surface of the interlayer insulating film 20 is flattened by a chemical mechanical polishing (CMP) method.
[0092]
Here, the first silicon nitride film 17 and the second silicon nitride film 18 become an etching stopper film 19 in the contact hole forming step.
[0093]
Next, as shown in FIG. 3A, a photosensitive resist material is applied on the interlayer insulating film 20 to form a resist film. Subsequently, after performing a pattern exposure using an exposure apparatus in which the maximum value of the overlay shift amount is measured in advance by photolithography using a photomask having a hole pattern, By developing the exposed resist film, a second resist pattern 24 having an opening 24a in a contact hole forming region is formed.
[0094]
Here, the opening 24a of the second resist pattern 24 is formed such that the diameter b is about 500 nm and the center is located at the center of the gate electrodes 15 adjacent to each other. At this time, since the diameter b of the opening 24a is larger than the distance a between the gate electrodes 15, the end of the opening 24a in the gate vertical direction becomes an overlap region 21a overlapping the upper side of the gate electrode 15. Since the distance a between the gate electrodes 15 is about 320 nm, and the diameter b of the opening 24a is about 500 nm, when the opening 24a is formed at a predetermined position, the width dimension c of the overlap region 21a is 90 nm.
[0095]
Subsequently, for example, C is used as an etching gas. ₄ F ₆ Or C ₅ F ₈ The contact hole 21 penetrating through the interlayer insulating film 20 is formed by removing the interlayer insulating film 20 exposed in the opening 24a of the second resist pattern 24 by a dry etching method using.
[0096]
In the step of forming the contact hole 21, since the etching rate of the etching gas with respect to silicon oxide is relatively high, the interlayer insulating film 20 can be removed while protecting the gate electrode 15 with the etching stopper film 19. In this etching step, the upper portion of the etching stopper film 19 is etched. However, since the opening 24a is formed so as to overlap the upper side of the gate electrode 15, the portion of the etching stopper film 19 that contacts the side surface of the gate electrode 15 is sharp. Is not etched.
[0097]
Next, as shown in FIG. 3B, after removing the second resist pattern 24, for example, CHF is used as an etching gas. ₃ Or CF ₄ The semiconductor substrate 11 is exposed on the bottom surface of the contact hole 21 by etching and removing the second silicon nitride film 18 exposed on the bottom surface of the contact hole 21 by a dry etching method using a fluorocarbon gas composed of, for example.
[0098]
Next, as shown in FIG. 3C, a contact and wiring layer are formed by depositing a metal film 22 made of, for example, copper so as to fill the inside of the contact hole 21 by the CVD method. The semiconductor device of the first embodiment shown in FIG. 1A and FIG. 1B is completed.
[0099]
According to the method for manufacturing a semiconductor device of the first embodiment, the opening 24 a of the second resist pattern 24 is formed so as to overlap the upper side of the gate electrode 15, and the portion of the opening overlapping the upper side of the gate electrode 15 is formed. Since the width dimension in the direction perpendicular to the gate is larger than the maximum value of the amount of misalignment, even if misalignment occurs in the process of forming the second resist pattern 24, the second resist pattern 24 is positioned above the gate electrode 15. They are arranged to overlap.
[0100]
Therefore, the side surface of the gate electrode 15 in the etching stopper film 19 is not sharply etched unlike the conventional method of manufacturing a semiconductor device, and the side surface of the gate electrode 15 is not exposed.
[0101]
Hereinafter, a case where the position of the hole pattern is shifted will be described with reference to FIGS. FIG. 4A is a plan view in the case where misalignment occurs in the steps shown in FIGS. 2B and 2C, and FIGS. 4B and 4C respectively show FIGS. FIG. 4A is a cross-sectional configuration view of a step corresponding to FIG. 3A and FIG.
[0102]
As shown in the plan view of FIG. 4A, when the overlay shift occurs, the overlay shift amount can be measured as a distance d between the center of the adjacent gate electrodes 15 and the center of the contact hole 21. Here, the width dimension c of the overlap area 21a when no overlay shift occurs is the maximum value d of the overlay shift amount. _max In the case where overlay misalignment occurs, the position of the wall surface of the opening 24a does not shift to almost the same plane as the side surface of the gate electrode 15, and the opening 24a is It is arranged so as to overlap with the upper side of the gate electrode 15.
[0103]
Therefore, as shown in the cross-sectional view of FIG. 4B, in the step of etching the interlayer insulating film 20 using the second resist pattern 24, the upper portion of the gate electrode 15 on both sides of the opening 24a overlapping with each other is etched. The stopper film 19 is etched on a gentle slope.
[0104]
Thereafter, as shown in the cross-sectional view of FIG. 4C, in the step of removing the second silicon nitride film exposed on the bottom surface of the contact hole 21, the gate side surface portion of the etching stopper film 19 is not sharply etched. Therefore, the side surface of the gate electrode is not exposed.
[0105]
Hereinafter, the characteristics of the semiconductor device in the case where the overlay deviation amount is changed in the method of manufacturing the semiconductor device of the first embodiment described above will be described.
[0106]
FIG. 5 shows the amount of misalignment when the gate electrodes 15 are shifted from the center in the step of forming the second resist pattern 24 and the etching of the etching stopper film 19 on the surface along the side surface of the gate electrode 15. This shows the relationship with the depth.
[0107]
Here, the vertical axis represents the measured value of the etching depth of the etching stopper film 19 on the same plane as the side surface of the gate electrode 15, and the horizontal axis represents the amount of misalignment of the hole pattern with respect to the gate pattern. The distance between the center between the gate electrodes 15 and the center of the contact hole 21.
[0108]
As shown in FIG. 5, the etching depth of the etching stopper film 19 is substantially constant irrespective of the amount of misalignment. That is, it is shown that the etching stopper film 19 is not sharply etched at a specific displacement amount as in the conventional method of manufacturing a semiconductor device.
[0109]
FIG. 6 shows the relationship between the amount of superposition deviation when the gate electrodes 15 are formed offset from the center in the step of forming the second resist pattern 24 and the amount of current flowing between the gate electrodes 15 and the contacts. Is shown.
[0110]
As shown in FIG. 6, it can be confirmed that no short circuit has occurred regardless of the amount of displacement of the hole pattern.
[0111]
In the first embodiment, the opening 24a of the second resist pattern 24 and the opening 24a are not limited to a plane circular shape, and the distance between the opening dimension in the direction perpendicular to the gate and the interval between the gate electrodes 15 adjacent to each other. The planar shape may be an elliptical shape, an elliptical shape, or a polygonal shape, as long as the difference is formed so as to be larger than twice the overlay displacement amount.
[0112]
Of course, the shape of the contact hole 21 having the same shape as the opening 24a is not limited to a plane circular shape, and the opening dimension in the direction perpendicular to the gate on the upper surface side of the interlayer insulating film 20 is different from the interval between the adjacent gate electrodes 15. May be formed so as to be larger than twice the amount of misalignment, and the planar shape may be an elliptical shape, an elliptical shape, or a polygonal shape.
[0113]
In the first embodiment, the etching stopper film 19 is not limited to the structure using the silicon nitride film, but may be made of an insulating material having a lower etching rate than the material forming the interlayer insulating film 20. . This allows the gate electrode 15 to be protected by the etching stopper film 19 in the step of forming the contact hole 21 in the interlayer insulating film 20.
[0114]
In the first embodiment, the material forming the interlayer insulating film 20 is not limited to silicon oxide, but may be any insulating material having an etching rate higher than that of the etching stopper film 19.
[0115]
(Modification of First Embodiment)
Hereinafter, a modified example of the first embodiment will be described with reference to the drawings.
[0116]
7A and 7B show a plan configuration of a semiconductor device according to a modification of the first embodiment, and FIG. 7B is a cross section taken along line VII-VII of FIG. The configuration is shown. 7A and 7B, the same members as those shown in FIGS. 1A and 1B are denoted by the same reference numerals, and description thereof will be omitted.
[0117]
As shown in FIGS. 7A and 7B, the semiconductor device of the present modification includes an oval contact hole 21 having a major axis in a direction perpendicular to the gate. Here, the contact hole 21 has a dimension b in the direction perpendicular to the gate. ₁ Is about 500 nm, and the opening dimension b in the gate parallel direction is ₂ Is about 200 nm. The pitch in the direction parallel to the gate is about 500 nm, and the pitch in the direction perpendicular to the gate is about 500 nm.
[0118]
The contact holes 21 are arranged such that the centers in the gate vertical direction coincide with the centers of the gate electrodes 15 adjacent to each other. Here, the distance between the gate electrodes 15 is about 320 nm, and the opening dimension of the contact hole 21 in the direction perpendicular to the gate is about 500 nm. Therefore, the overlap region 21 a overlapping the upper side of the gate electrode 15 in the contact hole 21 is The dimension in the orthogonal direction is about 90 nm.
[0119]
Also in the semiconductor device of this modification, the end of the contact hole 21 in the gate vertical direction is formed so as to overlap the upper side of the gate electrode 15. The size of the overlap region 21a overlapping the upper side of the gate electrode 15 is about 90 nm, and even if the overlay of the second resist pattern 24 is displaced in the process of forming the contact hole 21, the opening 24a is Is not formed in contact with the same surface as that of the side surface.
[0120]
Hereinafter, a method for manufacturing a semiconductor device according to the present modification will be described with reference to FIGS. 2 (a) to 2 (c) and FIGS. 3 (a) to 3 (c).
[0121]
First, a gate electrode 15 is formed on a semiconductor substrate 11 via a silicon oxide film 12 in the same manner as in the steps shown in FIGS. Impurities are implanted to form impurity diffusion regions 16. Further, an etching stopper film 19 and an interlayer insulating film 20 are formed so as to cover the side surface and the upper surface of the gate electrode 15.
[0122]
Next, a second resist pattern 24 having an opening 24a serving as a hole pattern is formed in the same manner as in the step shown in FIG. Here, the opening 24a has a dimension in the direction perpendicular to the gate of about 500 nm and an opening in the direction parallel to the gate of about 200 nm. Subsequently, by removing the interlayer insulating film 20 exposed between the openings 24a by dry etching, the contact holes 21 having the same planar shape as the openings 24a are formed.
[0123]
Here, also in the present modified example, as in the first embodiment, the opening 24a of the second resist pattern 24 has a difference between the opening dimension b in the gate orthogonal direction and the distance a between the adjacent gate electrodes 15. Is formed so as to be larger than twice the amount of misalignment, so that even if misalignment occurs, the wall surface of the opening 24a is formed in contact with the substantially same surface as the side surface of the gate electrode 15. There is no.
[0124]
Next, in the same manner as the steps shown in FIGS. 3B and 3C, the second silicon nitride film 18 exposed below the contact hole 21 is removed, and then the inside of the contact hole 21 is filled. The contact and the wiring layer are formed by forming the metal film 22 as described above.
[0125]
As described above, according to the semiconductor device of the modified example of the first embodiment, the hole pitch in the gate parallel direction is smaller than in the case where the contact hole 21 is formed in a circular shape. Can be formed.
[0126]
In the present modification, the shape of the contact hole 21 is not limited to an elliptical shape, and may be formed so that the width dimension in the gate parallel direction is smaller than the gate orthogonal direction. It may be shaped.
[0127]
(Second embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
[0128]
FIG. 8A shows a plan configuration of the semiconductor device according to the second embodiment, and FIG. 8B shows a cross-sectional configuration taken along line VIIIb-VIIIb of FIG. 8A. 8A and 8B, the same components as those shown in FIGS. 1A and 1B are denoted by the same reference numerals, and description thereof will be omitted.
[0129]
As shown in FIGS. 8A and 8B, the semiconductor device according to the second embodiment includes a polycrystalline silicon film 13 and a tungsten film 14 on a semiconductor substrate 11 with a silicon oxide film 12 interposed therebetween. A gate electrode 15 having a structure is formed. Further, an impurity diffusion region 16 serving as a source region or a drain region is formed in the semiconductor substrate 11 located between the gate electrodes 15.
[0130]
The gate electrodes 15 have a wiring pitch of about 500 nm and are arranged in parallel at intervals. Here, the width dimension of each gate electrode 15 is about 180 nm, and the distance a between adjacent gate electrodes 15 is about 320 nm.
[0131]
A first silicon nitride film 17 is formed above the gate electrode 15, and a second silicon nitride film 17 is formed on the semiconductor substrate 11 including the first silicon nitride film 17 so as to cover the side surface of the gate electrode 15. Of silicon nitride film 18 is formed.
[0132]
On the second silicon nitride film 18, an interlayer insulating film 20 made of silicon oxide having a thickness of about 800 nm is formed. A contact hole 21 having a diameter b of about 200 nm is provided in a portion of the interlayer insulating film 20 located between the gate electrodes 15.
[0133]
As a feature of the second embodiment, an NSG film 31 having a thickness of about 30 nm is formed inside the contact hole 21 so as to cover at least the wall surface thereof. Here, the NSG film is a silicon oxide film (None-doped Silicate Glass) not doped with an impurity, and particularly refers to a deposited film of silicon oxide to which boron and phosphorus are not added.
[0134]
By embedding a metal film made of copper in the contact hole 21, a contact and a wiring layer electrically connected to the impurity diffusion region 16 are formed.
[0135]
Hereinafter, a method of manufacturing the semiconductor device according to the second embodiment configured as described above will be described with reference to the drawings.
[0136]
9A to 9C show a method of manufacturing the semiconductor device according to the second embodiment, and show a cross-sectional configuration in a process order at a position corresponding to the line VIIIb-VIIIb in FIG. 8A. I have.
[0137]
First, as shown in FIG. 9A, a silicon oxide film 12, a polysilicon film 13, and a tungsten film 14 are formed on a semiconductor substrate 11 in the same manner as in the steps shown in FIGS. 2A and 2B. After sequentially laminating the first silicon nitride film 17 and the first silicon nitride film 17, the silicon oxide film 12 and the gate electrode 15 are formed by dry etching using the first resist pattern 23. Subsequently, after removing the first resist pattern 23, an impurity diffusion region 16 is formed in the semiconductor substrate 11 between the gate electrodes 15.
[0138]
Next, as shown in FIG. 9B, a second silicon nitride film is formed on the entire surface of the semiconductor substrate 11 so as to cover the side surfaces of the gate electrode 15 in the same manner as the step shown in FIG. 18 and an interlayer insulating film 20 are sequentially formed. Subsequently, the upper surface of the interlayer insulating film 20 is planarized by the CMP method.
[0139]
Next, as shown in FIG. 9C, in the same manner as in the step shown in FIG. 3A, a photolithography method is used to form an opening 24 a having an opening 24 a in the contact hole formation region on the interlayer insulating film 20. The second resist pattern 24 is formed, and the interlayer insulating film 20 exposed in the opening 24a of the second resist pattern 24 is removed by a dry etching method, thereby forming a contact hole 21 penetrating the interlayer insulating film 20. .
[0140]
Here, the opening 24a of the second resist pattern 24 is formed so as to have a diameter of about 200 nm and a center located between the gate electrodes 15.
[0141]
Next, as shown in FIG. 10A, in the same manner as in the step shown in FIG. 3B, the second resist pattern 24 located below the opening 24a is formed by dry etching. The exposed portion of the silicon nitride film 18 is removed by etching to expose the semiconductor substrate 11 on the bottom of the contact hole 21.
[0142]
Next, as shown in FIG. 10B, an NSG film 31 is deposited on the entire surface of the interlayer insulating film including the wall surface and the bottom surface of the contact hole 21 by, for example, a CVD method.
[0143]
Next, as shown in FIG. ₄ F ₆ Or C ₅ F ₈ The entire surface of the NSG film 31 is etched back by an anisotropic dry etching method using an etching gas composed of As a result, portions of the NSG film located on the upper surface of the interlayer insulating film 20 and the bottom surface of the contact hole 21 are etched, and the semiconductor substrate 11 is exposed on the bottom surface of the contact hole 21.
[0144]
Thereafter, although not shown, a metal film is deposited to fill the inside of the contact hole 21 to form a contact and a wiring layer in the same manner as in the step shown in FIG. The semiconductor device of the second embodiment shown in FIG. 8A and FIG. 8B is completed.
[0145]
According to the method of manufacturing the semiconductor device of the second embodiment, since the NSG film 31 is formed as a protective film covering the inside of the contact hole 21, the etching stopper film 19 located on the side surface of the gate electrode 15 when the contact hole is formed. Is exposed, the side surface of the gate electrode 15 is not exposed in the step of exposing the bottom surface of the contact hole 21.
[0146]
Hereinafter, a description will be given of a case where misalignment occurs in the step of forming a second resist pattern for patterning the contact hole 21.
[0147]
FIGS. 11A to 11C and FIGS. 12A to 12C show the opening 24a of the second resist pattern 24 in the step shown in FIG. 3 shows the state of the process order when the contact holes are formed in contact with the same surface.
[0148]
As shown in the plan view of FIG. 11A, in the step of forming the second resist pattern 24 on the interlayer insulating film 20, if the amount of misalignment is about 60 nm, The opening 24a is arranged so as to be in contact with the same surface.
[0149]
Next, as shown in FIG. 11B, a contact hole 21 is formed by etching using the second resist pattern 24. Here, since the wall surface of the opening 24a is arranged in contact with the same surface as the side surface of the gate electrode 15, when etching is performed on the interlayer insulating film 20, the side surface portion of the etching stopper film 19 becomes steeply sloped. And the etching depth increases.
[0150]
Next, as shown in FIG. 11C, in the step of removing the second silicon nitride film 18 exposed on the bottom surface of the contact hole 21, the side surface of the etching stopper film 19 is further etched. 15 sides are exposed.
[0151]
Next, as shown in FIG. 12A, an NSG film 31 is deposited on the interlayer insulating film 20 including the wall surface and the bottom surface of the contact hole 21. Thus, the exposed portion of the side surface of the gate electrode 15 is protected by the NSG film 31.
[0152]
Next, as shown in FIG. 12B, the semiconductor substrate 11 is exposed on the bottom of the contact hole 21 by performing dry etching on the NSG film 31.
[0153]
Next, as shown in FIG. 12C, by depositing a metal film 22 so as to fill the inside of the contact hole 21, a contact and a wiring layer are formed, and FIG. 8A and FIG. The semiconductor device according to the second embodiment shown in FIG.
[0154]
In the method of manufacturing the semiconductor device according to the second embodiment, since the NSG film 31 covering the wall surface of the contact hole 21 is formed, the NSG film 31 protects the gate electrode 15 even when the gate electrode 15 is exposed in the etching step for the interlayer insulating film 20. Therefore, the contact hole 21 can be formed without exposing the gate electrode 15.
[0155]
(Modification of Second Embodiment)
Hereinafter, a modification of the manufacturing method according to the second embodiment of the present invention will be described with reference to the drawings.
[0156]
FIGS. 13A to 13C and FIGS. 14A to 14C show a method of manufacturing a semiconductor device according to the present modification, and show a position corresponding to the line VIIIb-VIIIb in FIG. 3 shows a cross-sectional configuration in the order of steps.
[0157]
First, as shown in FIG. 13A, a silicon oxide film 12, a polysilicon film 13 and a tungsten film are formed on a semiconductor substrate 11 in the same manner as in the steps shown in FIGS. 9A to 9C. A gate electrode 15 made of the film 14, an etching stopper film 19 made of the first silicon nitride film 17 and the second silicon nitride film 18, and an interlayer insulating film 20 are formed.
[0158]
Subsequently, a second resist pattern 24 having an opening 24a in a contact hole forming region is formed on the interlayer insulating film 20 by a photolithography method, and the opening of the second resist pattern 24 is formed by a dry etching method. By removing the interlayer insulating film 20 exposed at 24a, a contact hole 21 penetrating through the interlayer insulating film 20 is formed.
[0159]
Next, as shown in FIG. 13B, an NSG film 31 is deposited on the entire surface of the interlayer insulating film including the wall surface and the bottom surface of the contact hole 21 by, for example, a CVD method.
[0160]
Next, as shown in FIG. ₄ F ₆ Or C ₅ F ₈ The entire surface of the NSG film 31 is etched back by an anisotropic dry etching method using an etching gas composed of As a result, the portion of the NSG film 31 located on the upper surface of the interlayer insulating film 20 and the portion located on the bottom surface of the contact hole 21 are etched, and the second silicon nitride film 18 is exposed on the bottom surface of the contact hole 21.
[0161]
Next, as shown in FIG. 14A, the exposed portion of the second silicon nitride film 18 located below the opening 24a of the second resist pattern 24 is removed by dry etching to form a contact. The semiconductor substrate 11 is exposed at the bottom of the hole 21.
[0162]
Next, as shown in FIG. 14B, a metal film 22 is deposited so as to fill the inside of the contact hole 21 to form a contact and a wiring layer. The semiconductor device according to the second embodiment shown in FIG.
[0163]
Hereinafter, a case where a misalignment occurs in the step of forming a second resist pattern for patterning the contact hole 21 will be described.
[0164]
FIGS. 15A to 15C show a case where the opening 24a of the second resist pattern 24 is formed in contact with the same surface as the side surface of the gate electrode 15 in the step shown in FIG. 9C. Are shown in the order of steps.
[0165]
As shown in FIG. 15A, etching is performed on the interlayer insulating film 20 using the second resist pattern 24 in a state where the opening 24a is disposed so as to be in contact with the same surface as the side surface of the gate electrode 15. Then, a contact hole 21 is formed. Thereby, the side surface portion of the etching stopper film 19 is etched into a steep slope, and the etching depth is increased.
[0166]
Next, as shown in FIG. 15B, an NSG film 31 is deposited on the interlayer insulating film 20 including the wall surface and the bottom surface of the contact hole 21. Thus, the sharply etched portion of the etching stopper film 19 is protected by the NSG film 31.
[0167]
Next, as shown in FIG. 15C, the bottom portion of the contact hole 21 in the NSG film 31 is removed by an anisotropic dry etching method. Subsequently, the bottom portion of the contact hole 21 in the second silicon nitride film 18 is removed by an anisotropic dry etching method. In the step of removing the second silicon nitride film 18, since the wall surface of the gate electrode 15 is covered with the NSG film 31, the gate electrode 15 is not exposed inside the contact hole.
[0168]
In the present modification, an NSG film 31 is formed before removing the second silicon nitride film exposed below the contact hole 21, and the second silicon nitride film 18 located on the bottom surface of the contact hole 21 and the NSG film 31 are formed. Since the film 31 and the film 31 can be removed by one etching, the etching damage to the impurity diffusion region 16 can be made smaller than in the second embodiment.
[0169]
In the first and second embodiments, the gate electrode 15 is described as a polymetal gate in which the polysilicon film 13 and the tungsten film 14 are stacked. However, the present invention is not limited to this. It may be a layer film, for example, and may be formed of a conductive film made of an alloy such as polysilicon, tungsten, or tungsten nitride. Of course, the gate electrode 15 may be formed as a polymetal gate made of a polysilicon film and a tungsten alloy.
[0170]
Further, in the method of manufacturing the semiconductor device according to the first embodiment, the second embodiment, and the modified example thereof, the contact structure used for the MIS transistor has been described as an example. It can be applied to a method of manufacturing a semiconductor device in which a self-aligned contact is formed between a plurality of conductive films formed in the above. For example, the present invention can be similarly applied to a contact that passes between bit lines of a dynamic RAM device and is connected to an electrode of a charge storage capacitor.
[0171]
【The invention's effect】
According to the first method for manufacturing a semiconductor device of the present invention, even when misalignment occurs during the formation of a hole pattern, a contact hole is not formed so as to be substantially in contact with the side surface of the conductive film. The conductive film is not exposed inside the contact hole.
[0172]
Further, according to the second method for manufacturing a semiconductor device of the present invention, even when the contact hole is formed so as to be substantially in contact with the side surface of the conductive film due to misalignment at the time of forming the hole pattern, Since the protective film is formed on the wall surface of the contact hole, the conductive film is not exposed inside the contact hole.
[Brief description of the drawings]
FIG. 1A is a plan view showing a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a sectional view taken along line Ib-Ib of FIG.
FIGS. 2A to 2C show a method of manufacturing a semiconductor device according to a first embodiment of the present invention, and are sectional views in the order of steps at positions corresponding to the Ib-Ib line in FIG. FIG.
3 (a) to 3 (c) show a method for manufacturing a semiconductor device according to the first embodiment of the present invention, and are sectional views in the order of steps at positions corresponding to the Ib-Ib line in FIG. 1 (a). FIG.
FIG. 4A shows a case where a positional shift occurs in the superposition of a mask pattern for forming a contact hole in a second resist pattern forming step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention; (B) and (c) are cross-sectional views showing a state of a process sequence at a position corresponding to the line IVb-IVb in (a).
FIG. 5 is a graph showing the relationship between the amount of misalignment of a hole pattern with respect to a gate pattern and the etching depth of an etching stopper film in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
FIG. 6 is a graph showing the relationship between the amount of misalignment of a hole pattern with respect to a gate pattern and the amount of leakage current flowing between a gate electrode and a contact in the method for manufacturing a semiconductor device according to the first embodiment of the present invention. .
FIG. 7A is a plan view illustrating a semiconductor device according to a modification of the first embodiment of the present invention, and FIG. 7B is a cross-sectional view taken along line VIIb-VIIb of FIG.
8A is a diagram illustrating a semiconductor device according to a second embodiment of the present invention, and FIG. 8B is a cross-sectional view taken along line VIIIb-VIIIb of FIG.
FIGS. 9A to 9C show a method of manufacturing a semiconductor device according to a second embodiment of the present invention, and show cross-sectional configurations in the order of steps at positions corresponding to lines VIIIb-VIIIb in FIG. FIG.
FIGS. 10A to 10C show a method of manufacturing a semiconductor device according to a second embodiment of the present invention, and show a cross-sectional configuration in a process order at a position corresponding to the line VIIIb-VIIIb in FIG. FIG.
FIG. 11 shows a case in which a mask pattern for forming a contact hole is misaligned in the method for manufacturing a semiconductor device according to the second embodiment of the present invention, and the wall surface of an opening serving as a contact formation region has 4A and 4B show a state of a process order when arranged in contact with the same side surface as a side surface of a gate electrode, wherein FIG. 4A is a plan view, and FIGS. 4B and 4C are lines XIb-XIb of FIG. It is a structure sectional view in a corresponding position.
FIGS. 12 (a) to 12 (c) show a case where misalignment occurs in a mask pattern for forming a contact hole in the method of manufacturing a semiconductor device according to the second embodiment of the present invention; FIG. 12 is a configuration sectional view in a process order at a position corresponding to a line XIb-XIb in FIG. 11A when a wall surface of an opening serving as a region is arranged in contact with the same surface as a side surface of a gate electrode.
FIGS. 13A to 13C show a method of manufacturing a semiconductor device according to a modification of the second embodiment of the present invention, and show a process at a position corresponding to the line VIIIb-VIIIb in FIG. FIG.
FIGS. 14A and 14B show a method for manufacturing a semiconductor device according to a modification of the second embodiment of the present invention, and show a process at a position corresponding to the line VIIIb-VIIIb in FIG. FIG.
FIGS. 15A to 15C illustrate a method of manufacturing a semiconductor device according to a modified example of the second embodiment of the present invention, in which a mask pattern for forming a contact hole is overlapped in a second resist pattern forming step; FIG. 11B shows a case where the side surface of the opening of the mask pattern is arranged in contact with the same surface as the side surface of the gate electrode due to an alignment error, and the configuration in the process order at a position corresponding to line XIb-XIb in FIG. It is sectional drawing.
FIGS. 16A and 16B are cross-sectional views in the order of steps showing a conventional method for manufacturing a semiconductor device, and FIG. 16C is a plan view of the step shown in FIG.
17 (a) to 17 (c) are cross-sectional views in the order of steps showing a conventional method for manufacturing a semiconductor device.
FIGS. 18A and 18B show a sequence of steps in a case where a mask pattern for forming a contact hole is misaligned in a conventional method of manufacturing a semiconductor device, wherein FIG. 18A is a plan view, FIG. (C) is a cross-sectional view of a configuration of a contact hole formation region.
FIG. 19 is a graph showing the relationship between the amount of misalignment of a hole pattern with respect to a gate pattern and the amount of leakage current flowing between a gate electrode and a contact in a conventional method of manufacturing a semiconductor device.
FIG. 20 is a graph showing the relationship between the amount of misalignment of a hole pattern with respect to a gate pattern and the etching depth of an etching stopper film in a conventional method for manufacturing a semiconductor device.
FIG. 21 shows a case in which a mask pattern for forming a contact hole is misaligned in a conventional method of manufacturing a semiconductor device, and a wall surface of an opening serving as a contact formation region is the same as a side surface of a gate electrode. FIGS. 4A and 4B show a state of a process order when they are arranged in contact with. FIG. 4A is a plan view, and FIGS.
FIG. 22 shows a state in which a polymer deposition film is formed on an etching stopper film during etching of an interlayer insulating film in a conventional method of manufacturing a semiconductor device, and FIG. FIG. 4B is a cross-sectional view illustrating a configuration in which a wall surface is disposed above a gate electrode; FIG. 4B illustrates a case where a wall surface of an opening serving as a contact formation region is disposed in contact with the same surface as a side surface of the gate electrode; FIG.
[Explanation of symbols]
11 Semiconductor substrate
12 Silicon oxide film
13 Polysilicon film
14 Tungsten film
15 First silicon nitride film
16 Gate electrode
17 Impurity diffusion region
18 Second silicon nitride film
19 Etching stopper film
20 interlayer insulating film
21 Contact hole
21a Overlap area
22 Metal film
23 First resist pattern
24 Second resist pattern
24a opening
31 NSG film

Claims (16)

A plurality of conductive films formed on the semiconductor substrate and extending in parallel at intervals from each other;
An etching stopper film covering each side surface and top surface of the plurality of conductive films,
An interlayer insulating film formed on the semiconductor substrate including on the etching stopper film,
The interlayer insulating film, between the conductive films adjacent to each other in the plurality of conductive films, has a through-hole patterned using an exposure apparatus in which the maximum value of the overlay shift amount is measured in advance,
An opening dimension of the through hole in a direction intersecting with a direction in which the plurality of conductive films extends is larger than an interval between the adjacent conductive films, and a difference between the opening dimension and the interval between the adjacent conductive films. Is larger than twice the maximum value of the overlay displacement amount. 2. The semiconductor device according to claim 1, wherein the planar shape of the through hole is an elliptical shape or an elliptical shape having a major axis in a direction intersecting with a direction in which the plurality of conductive films extends. 3. 3. The method according to claim 1, wherein the etching stopper film is made of silicon nitride. The semiconductor device according to claim 1, wherein the interlayer insulating film is made of silicon oxide. The semiconductor device according to claim 1, wherein the plurality of conductive films are made of at least one conductive material of polysilicon, tungsten, and an alloy containing tungsten. Forming a plurality of conductive films extending in parallel at intervals on the semiconductor substrate;
Forming an etching stopper film covering each side and top surface of the plurality of conductive films;
Forming an interlayer insulating film over the entire surface including the etching stopper film on the semiconductor substrate;
After a resist film is formed on the interlayer insulating film, both ends of the resist film are adjacent to each other in the plurality of conductive films using an exposure apparatus in which the maximum value of the overlay shift amount is measured in advance. Patterning an opening overlapping with the upper side of the conductive film to be formed;
Forming a through hole between the adjacent conductive films by performing etching on the interlayer insulating film using the patterned resist film and the etching stopper film as a mask,
A method of manufacturing a semiconductor device, wherein a portion of the opening that overlaps with the upper side of the conductive film has a width dimension in a direction intersecting with a direction in which the plurality of conductive films extends is larger than the overlay displacement amount. 7. The semiconductor device according to claim 6, wherein the planar shape of the opening of the resist film is an elliptical shape or an elliptical shape having a major axis in a direction intersecting a direction in which the plurality of conductive films extends. Method. Forming a plurality of conductive films extending in parallel at intervals on the semiconductor substrate;
Forming an etching stopper film covering each side and top surface of the plurality of conductive films;
Forming an interlayer insulating film over the entire surface including the etching stopper film on the semiconductor substrate;
Forming a resist film having an opening between adjacent conductive films in the plurality of conductive films on the interlayer insulating film;
Forming a through hole between the adjacent conductive films by etching the interlayer insulating film using the resist film having the opening as a mask;
Forming a protective film covering a wall surface of the through-hole. 9. The semiconductor device according to claim 8, wherein in the step of forming the protective film, the protective film is formed on the entire surface of the interlayer insulating film, including a wall surface and a bottom surface of the through hole. Method. 10. The method according to claim 9, wherein, in the step of forming the etching stopper film, the etching stopper film is formed on the semiconductor substrate over the entire surface including the upper surface and the wall surface of each of the plurality of conductive films. The manufacturing method of the semiconductor device described in the above. After the step of forming the through hole and before the step of forming the protective film, a step of removing a bottom surface portion of the through hole in the etching stopper film;
The method of manufacturing a semiconductor device according to claim 10, further comprising, after the step of forming the protective film, removing a bottom portion of the through hole in the protective film. 11. The semiconductor device according to claim 10, further comprising, after the step of forming the protective film, a step of sequentially removing the protective film and the etching stopper film located on the bottom surface of the through hole. Production method. 13. The method according to claim 10, wherein the protective film is made of silicon oxide. 14. The method according to claim 6, wherein the etching stopper film is made of silicon nitride. The method according to any one of claims 6 to 14, wherein the interlayer insulating film is made of silicon oxide. 16. The semiconductor device according to claim 6, wherein the plurality of conductive films are made of at least one conductive material among polysilicon, tungsten, and an alloy containing tungsten. Method.

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