JP2004227707A - Error signal generator circuit for optical disk - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide circuit constitution in which the dc offset of a 1 chip CMOS integrated circuit generating an analog error signal is eliminated. <P>SOLUTION: This circuit has at least an analog error signal generating part outputting an analog error signal based on the output signal of an optical pickup, a differential operational amplifier for eliminating the offset in which the error signal is inputted to one side of input terminals and the reference voltage is applied to the other input terminal, an A/D converting part converting the output signal of the differential operational amplifier for eliminating the offset into a digital signal and outputting it, and a reference voltage control part varying reference voltage applied to the operation amplifier based on the digital signal to eliminate offset, and the circuit is constituted of 1 chip CMOS type integrated circuit. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an error signal generation circuit for an optical disk.
[0002]
[Prior art]
Generally, in an optical disk reproducing apparatus (hereinafter, referred to as an optical disk apparatus), after amplifying two output signals from an optical pickup, the difference between the two signal intensities is obtained by a differential operational amplifier, thereby obtaining a focus error of the optical disk. A signal and a tracking error signal are obtained. By performing control based on these error signals, the servo control system can accurately irradiate one spot of light beam following the track of the optical disk.
[0003]
Conventionally, as a configuration of an error signal generation circuit for obtaining a focus error signal and a tracking error signal, an IC chip (RF signal processing circuit) that performs an analog processing system in a preceding stage and an IC chip (servo system) that performs a digital processing system in a subsequent stage Processing circuit). That is, in the analog processing IC chip, after amplifying the two output signals from the optical pickup, the difference between the two signal strengths is obtained by the differential operational amplifier, and the focus error signal and the tracking error signal are output to the digital processing IC chip. I do.
[0004]
Then, in the digital processing IC chip, the obtained focus error signal and tracking error signal are converted into digital signals by an A / D converter, and a signal for adjusting an offset by an appropriate control logic in a digital signal processing unit is converted. Generate.
[0005]
The offset adjustment signal is fed back to the preceding analog processing IC chip to obtain a focus error signal and a tracking error signal from which the offset has been canceled (for example, see Patent Document 1).
[0006]
The analog processing IC chip is constituted by bipolar, while the digital processing IC chip is constituted by CMOS. That is, in the analog signal processing, since a bipolar process is used, the generation of an unmanageable DC offset voltage which is a hindrance such as that of a CMOS is small and hardly causes any problem.
[0007]
[Patent Document 1]
JP-A-10-105997 (FIG. 1)
[0008]
[Problems to be solved by the invention]
Such an error signal generation circuit is composed of two chips, an analog processing IC chip and a digital processing IC chip. Therefore, there is a problem that the chip cost and the mounting area are large.
Therefore, it is conceivable to configure the error signal generation circuit with one chip of CMOS. However, when the analog processing system is configured by CMOS, a so-called DC (direct current) offset becomes a problem. That is, the DC offset greatly changes due to manufacturing variations and the like, and quality control becomes difficult. As a result, there is a problem that the yield is reduced.
[0009]
[Means for Solving the Problems]
In the error signal generating circuit for an optical disk according to the present invention, an analog error signal generating unit that outputs an analog error signal based on an output signal of an optical pickup, and the error signal is input to one input terminal and the other input terminal. A differential operational amplifier for offset removal to which a reference voltage is applied to a terminal, an A / D conversion unit for converting an output signal of the differential operational amplifier for offset removal into a digital signal and outputting the digital signal, and an operational amplifier for removing the offset And at least a reference voltage control unit that makes the reference voltage applied to the VCO based on the digital signal, and is configured by a one-chip CMOS integrated circuit.
[0010]
In the present invention, as compared with the conventional case where the analog processing system and the digital processing system are each configured by separate chips, a single chip configuration is adopted, thereby reducing the chip area and cost. Can be achieved.
[0011]
Further, based on the digital signal output from the A / D conversion unit, the reference voltage input to the offset removal differential operational amplifier is controlled. Therefore, it is possible to eliminate a DC offset having a large variation inherent in the CMOS analog circuit with respect to the error signal. Therefore, a so-called digital DC offset becomes possible, and the yield of the optical disk error signal generation circuit composed of a one-chip CMOS integrated circuit can be improved.
[0012]
The reference voltage control unit is connected to the other input terminal of the differential amplifier for offset removal, and generates a resistor group that varies the reference voltage and a resistor group according to an external control signal. A selector for selecting a voltage as the reference voltage.
[0013]
Alternatively, the reference voltage control unit includes: an offset cancel circuit that outputs a reference voltage determination digital signal for determining the reference voltage based on the digital signal output by the A / D conversion unit; And a D / A converter for converting a digital signal for use in analog to output as a reference voltage.
[0014]
Therefore, since a circuit for generating a control signal for controlling the reference voltage is internally provided, and transmission / reception of the control signal to / from the external device is not required, the speed of the reference voltage control process can be increased.
[0015]
Furthermore, the offset cancel circuit of the reference voltage control unit includes:
A comparing unit that compares the digital signal of the A / D conversion unit with a target digital signal corresponding to a predetermined target voltage; and A sequence control unit for transmitting a control command for adding or subtracting a value, and a counter for generating the reference voltage determination digital signal in response to the control command and outputting the digital signal to the D / A converter may be provided.
[0016]
Furthermore, when the reference voltage applied to the operational amplifier by the reference voltage control unit changes and the error signal reaches a predetermined target voltage, the offset of the error signal may be removed.
[0017]
Further, the predetermined target voltage may be an initial value of the reference voltage before being changed by the reference voltage control unit.
[0018]
Furthermore, the error signal can be a focus error signal or a tracking error signal.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
=== Overall overview ===
As shown in FIG. 1, the optical disk error signal generation circuit 100 generates a focus error signal FE ′ and a tracking error signal TE ′ adjusted to remove a DC offset based on a signal group from the optical pickup 200. The optical disk error signal generation circuit 100 is manufactured by a CMOS process as a part of an optical disk reproduction signal processing LSI constituted by a one-chip integrated circuit.
[0020]
The optical disk error signal generation circuit 100 includes an analog error signal generation unit 110, a tracking error signal DC offset adjustment unit 120, a focus error signal DC offset adjustment unit 130, and a servo processing circuit 140.
[0021]
For the tracking error signal TE generated by the analog error signal generation unit 110, the tracking error signal DC offset adjustment unit 120 operates to remove the DC offset. Further, with respect to the focus error signal FE generated by the analog error signal generation unit 110, the focus error signal DC offset adjustment unit 130 operates to remove the DC offset.
[0022]
The focus error signal FE ′ and the tracking error signal TE ′ whose DC offset has been adjusted are supplied to the servo processing circuit 140. The servo processing circuit 140 performs necessary processing based on the focus error signal FE ′ and the tracking error signal TE ′.
[0023]
The focus error signal FE ′ and the tracking error signal TE ′ whose DC offset has been adjusted are supplied to the servo processing circuit 140. The servo processing circuit 140 generates a servo signal based on the focus error signal FE ′ and the tracking error signal TE, and supplies the servo signal to the optical pickup 200.
[0024]
As for the analog error signal generator 110 that generates the tracking error signal TE and the focus error signal FE, a known circuit configuration similar to the related art can be employed. For example, the circuit configuration of the RF signal processing circuit described in the above-mentioned Japanese Patent Application Laid-Open No. 10-105997 (especially, FIG. 1 and the following paragraph number) can be adopted.
[0025]
The tracking error signal DC offset adjustment unit 120 and the focus error signal DC offset adjustment unit 130 can have the same circuit configuration. Therefore, in this embodiment, the error signal DC offset adjustment units 120 and 130 will be described in the following first and second examples using a common circuit diagram for convenience of explanation.
[0026]
=== First Embodiment ===
As shown in FIG. 2, the tracking error signal DC offset adjustment unit 120 and the focus error signal DC offset adjustment unit 130 include a differential operational amplifier 10 for offset removal, an A / D converter (A / D conversion unit) 20, an error signal Register 30, a microcomputer interface 40, a selector control signal register 50, a resistor group (reference voltage control unit) 60, and a selector (reference voltage control unit) 70. Note that the focus error signal and the tracking error signal are collectively referred to as an error signal as appropriate.
[0027]
In the differential operational amplifier 10 for offset removal, the error signals TE and FE are input to the inverting input terminal via the resistor R10, and the reference voltage Vref is applied to the non-inverting input terminal. The output of the offset removing differential operational amplifier 10 returns to the inverting input terminal via the resistor R11. The A / D converter 20 converts an output signal of the differential operational amplifier 10 for offset removal into a digital signal and outputs the digital signal. This digital signal is also output to the servo processing circuit 140 of FIG. The error signal register 30 holds a digital signal output from the A / D converter 20. The microcomputer interface 40 has a function of a communication interface with a control microcomputer external to the optical disc reproduction signal processing LSI. The selector control signal register 50 holds a selector control signal (selector control data) from an external control microcomputer. The resistor group 60 and the selector 70 change the reference voltage Vref applied to the offset removing differential operational amplifier 10 based on the digital signal of the A / D converter 20 to remove the offset.
[0028]
That is, the resistor group 60 is configured by, for example, a series circuit of five resistors R61 to R65. This series circuit is connected between the power supply Vdd and the ground. The resistor group 60 is connected to a non-inverting input terminal of the differential operational amplifier 10 for offset removal via a selector 70, and supplies the reference voltage Vref while appropriately changing the reference voltage Vref. The selector 70 selects a voltage generated in the resistor group 60 as a reference voltage Vref according to a selector control signal from an external microcomputer.
[0029]
A specific operation will be described. The error signals TE and FE are input to the offset removing differential operational amplifier 10 via the resistor R10. The offset-removal differential operational amplifier 10 outputs error signals TE ′ and FE ′ obtained by an arithmetic expression of (Vref−TE, FE) * R11 / R10. The error signals TE ′ and FE ′ are output as digital signals by the A / D converter 20 and are held in the error signal register 30. The held digital data of the error signals TE 'and FE' is read out to an external control microcomputer via the microcomputer interface 40.
[0030]
In this external control microcomputer, a DC offset removal control program is running. By the operation of this control program, the control microcomputer makes a positive or negative judgment with the initial value (target voltage) of the reference voltage Vref as zero with respect to the digital data of the error signals TE ′ and FE ′. A selector control signal is generated to vary the reference voltage Vref so as to be equal to the initial value of the reference voltage Vref. This control logic is expressed, for example, as a control table created in advance. The control table refers to this control table as appropriate. The initial value is a half value (so-called center voltage) of the operating power supply Vdd applied to the resistor group 60, and is stored in the control microcomputer in advance.
[0031]
For example, when it is determined that the error signals TE and FE are higher or lower than the reference voltage Vref, the control microcomputer transmits a selector control signal to the microcomputer interface 40 to change the resistance value of the entire resistor group 60. This selector control signal is temporarily held in the selector control signal register 50 and is read out by the selector 70. The selector 70 switches and changes the connection state of the resistors R60 to R65 based on the selector control signal, and changes the reference voltage Vref. With this change, the error signals TE and FE are controlled so as to approach the initial value of the reference voltage Vref.
[0032]
That is, the control microcomputer monitors changes in the error signals TE and FE, and outputs a selector control signal as needed. When the error signals TE and FE reach the initial value of the reference voltage Vref as a result of the change of the reference voltage Vref, the control microcomputer ends the DC offset adjustment, assuming that the offset of the error signals TE and FE has been removed. .
[0033]
In the first embodiment, when the reference voltage applied to the operational amplifier is controlled to remove the offset, the connection form of the resistor group is changed in accordance with an external control signal. That is, a circuit for generating a control signal for controlling the reference voltage does not need to be provided inside, so that the chip area and cost can be further reduced.
[0034]
=== Second embodiment ===
As shown in FIG. 3, the tracking error signal DC offset adjustment unit 120 and the focus error signal DC offset adjustment unit 130 include a differential operational amplifier 10 for offset removal, an A / D converter (A / D conversion unit) 20, an automatic offset A cancel circuit (reference voltage control unit) 80 and a D / A converter (reference voltage control unit) 90 are provided. Note that the focus error signal and the tracking error signal are collectively referred to as an error signal as appropriate.
[0035]
In the differential operational amplifier 10 for offset removal, the error signals TE and FE are input to the inverting input terminal via the resistor R10, and the reference voltage Vref is applied to the non-inverting input terminal. The output of the offset removing differential operational amplifier 10 returns to the inverting input terminal via the resistor R11. The A / D converter 20 converts an output signal of the differential operational amplifier 10 for offset removal into a digital signal and outputs the digital signal. This digital signal is also output to the servo processing circuit 140 of FIG.
[0036]
The automatic offset cancel circuit 80 outputs a reference voltage determination digital signal for determining the reference voltage Vref based on the digital signal output from the A / D converter 20 to the D / A converter 90. The D / A converter 90 converts the digital signal for reference voltage determination into an analog signal and outputs it as a reference voltage Vref. The automatic offset cancel circuit 80 and the D / A converter 90 change the reference voltage Vref applied to the offset removing differential operational amplifier 10 based on the digital signal of the A / D converter 20 to remove the offset.
[0037]
As shown in FIG. 4, the automatic offset cancel circuit 80 includes a comparator (comparison unit) 81, a sequence control circuit (sequence control unit) 82, and a counter 83 including a register. The comparator 81 compares the digital signal from the A / D converter 20 with a target digital signal corresponding to the initial value (target voltage) of the reference voltage Vref. Based on the comparison result of the comparator 81, the sequence control circuit 82 sends a control command to the counter 83 to increase or decrease the value of the digital signal so that the value of the digital signal from the A / D converter 20 matches the target digital signal. Send out. In response to the control command, the counter 83 adds or subtracts the reference voltage determining digital signal and outputs the signal to the D / A converter 90.
[0038]
A specific operation will be described. As shown in FIG. 3, error signals TE and FE are input to a differential operational amplifier 10 for offset removal via a resistor R10. The offset-removal differential operational amplifier 10 outputs error signals TE ′ and FE ′ obtained by an arithmetic expression of (Vref−TE, FE) * R11 / R10. The error signals TE 'and FE' are output to the automatic offset cancel circuit 80 as digital signals by the A / D converter 20.
[0039]
As shown in FIG. 4, when a start signal is supplied from a microcomputer external to the optical disk reproduction signal processing LSI to the sequence control circuit 82, control of DC offset adjustment is started. The sequence control circuit 82 makes a positive or negative determination with respect to the digital data of the error signals TE ′ and FE ′ by setting the initial value of the reference voltage Vref to zero. Then, the sequence control circuit 82 sends a control command to the counter 83 to vary the reference voltage Vref so that the error signals TE and FE become equal to the initial value of the reference voltage Vref. This counter 83 holds digital data corresponding to the initial value (target voltage) of the reference voltage Vref.
[0040]
The content of the specific control command from the sequence control circuit 82 is increment or decrement for the value of the digital data. That is, if the control command is increment, the counter 83 increases the value of the digital data and outputs the digital data to the D / A converter 90 as a reference voltage determination digital signal. On the other hand, if the control command is decrement, the counter 83 reduces the value of the digital data and outputs the digital data to the D / A converter 90 as a reference voltage determination digital signal. As a result, the error signals TE and FE are controlled so as to approach the initial value of the reference voltage Vref.
[0041]
That is, the automatic offset cancel circuit 80 monitors the changes of the error signals TE and FE, and when the error signals TE and FE reach the initial value of the reference voltage Vref as a result of the change of the reference voltage Vref, the automatic offset cancel circuit 80 outputs the error signals TE and FE. Assuming that the offset has been removed, the sequence control circuit 82 ends the DC offset adjustment.
[0042]
FIG. 5 is a graph showing changes in the reference voltage Vref and the error signals TE and FE in this control. When a start signal is supplied to the sequence control circuit 82 (T0 in the figure), the error signals (solid lines) TE and FE are larger than the reference voltage Vref (dashed line), so that the control command of the sequence control circuit 82 is incremented. I do. As a result, the reference voltage Vref increases from its initial value (a so-called center voltage, which is a half of the operating power supply Vdd), and the error signals TE and FE decrease. When the error signals TE and FE match the initial value of the reference voltage Vref (T1 in the figure), it is determined that the DC offset has been removed, and the DC offset adjustment ends.
[0043]
In the second embodiment, a circuit for generating a control signal for controlling the reference voltage is internally provided, and the transmission and reception of the control signal with the outside need not be performed, so that the speed of the reference voltage control process can be increased. .
[0044]
As described above, the embodiment of the present invention has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist of the invention.
[0045]
In the present embodiment, compared to the conventional case where the analog processing system and the digital processing system are each configured by separate chips, the chip area is reduced to a single chip configuration. Cost reduction can be achieved.
[0046]
Further, based on the digital signal output from the A / D conversion unit, the reference voltage input to the offset removal differential operational amplifier is controlled. Therefore, it is possible to eliminate a DC offset having a large variation inherent in the CMOS analog circuit with respect to the error signal. Therefore, a so-called digital DC offset becomes possible, and the yield of the optical disk error signal generation circuit composed of a one-chip CMOS integrated circuit can be improved.
[0047]
【The invention's effect】
The chip area and cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an optical disk error signal generation circuit according to the present invention.
FIG. 2 is a block diagram illustrating error signal DC offset adjustment units 120 and 130 according to the first embodiment of the present invention.
FIG. 3 is a block diagram illustrating error signal DC offset adjustment units 120 and 130 according to a second embodiment of the present invention.
FIG. 4 is a specific block diagram showing an automatic offset cancel circuit 80 according to a second embodiment of the present invention.
FIG. 5 is a graph showing changes in a reference voltage Vref and error signals TE and FE according to the present invention.
[Explanation of symbols]
10 Offset removal differential operational amplifier 20 A / D converter (A / D converter)
30 error signal register 40 microcomputer interface 50 selector control signal register 60 resistor group (reference voltage control unit)
70 selector (reference voltage control unit)
80 Automatic offset cancel circuit (reference voltage control unit)
90 D / A converter (reference voltage control unit)
Reference Signs List 100 Error signal generation circuit for optical disk 110 Analog error signal generation unit 120 Tracking error signal DC offset adjustment unit 130 Focus error signal DC offset adjustment unit 140 Servo processing circuit 150 Microcomputer 200 Optical pickup FE, FE 'Focus error signal, error signal TE, TE 'tracking error signal, error signal Vref reference voltage

Claims (7)

An analog error signal generation unit that outputs an analog error signal based on an output signal of the optical pickup;
An offset removal differential operational amplifier in which the error signal is input to one input terminal and a reference voltage is applied to the other input terminal;
An A / D converter for converting an output signal of the offset removing differential operational amplifier into a digital signal and outputting the digital signal;
A reference voltage control unit that varies the reference voltage applied to the operational amplifier based on the digital signal, to remove an offset;
Has at least
An error signal generation circuit for an optical disk, comprising a one-chip CMOS integrated circuit. The reference voltage controller,
A resistor group that is connected to the other input terminal of the offset removal differential operational amplifier and that varies the reference voltage;
A selector for selecting a voltage generated in the resistor group as the reference voltage according to an external control signal;
2. The error signal generating circuit for an optical disk according to claim 1, further comprising: The reference voltage controller,
An offset canceling circuit for outputting a reference voltage determining digital signal for determining the reference voltage based on the digital signal output by the A / D converter;
A D / A converter that converts the reference voltage determining digital signal into an analog signal and outputs the analog signal as the reference voltage;
2. The optical disk error signal generating circuit according to claim 1, comprising: The offset cancel circuit of the reference voltage control unit,
A comparator for comparing the digital signal of the A / D converter with a target digital signal corresponding to a predetermined target voltage;
A sequence control unit that sends a control command to increase or decrease the value of the digital signal to match the target digital signal based on a comparison result of the comparison unit;
A counter that generates the reference voltage determination digital signal according to the control command and outputs the digital signal to the D / A converter;
4. The error signal generating circuit for an optical disk according to claim 3, comprising: 2. The offset of the error signal is removed when the error signal reaches a predetermined target voltage as a result of a change in the reference voltage applied to the operational amplifier by the reference voltage control unit. 5. The optical disk error signal generation circuit according to any one of claims 1 to 4. The optical disk error signal generation circuit according to claim 1, wherein the predetermined target voltage is an initial value of the reference voltage before being changed by the reference voltage control unit. 7. The error signal generating circuit for an optical disk according to claim 1, wherein the error signal is a focus error signal or a tracking error signal.

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