JP2004227264A - Lsi for communication - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an LSI for communication capable of reducing the load of a processor. <P>SOLUTION: An LSI 100 for communication is provided with an arithmetic logical arithmetic unit 3 and a product sum arithmetic unit 4 arranged for performing the arithmetic processing of communication data, a processor 5 for supplying a control code for controlling the operations of the arithmetic logical arithmetic unit 3 and the product sum arithmetic unit 4 and an arithmetic control unit 1 for controlling the arithmetic logical arithmetic unit 3 and the product sum arithmetic unit 4 based on a control code supplied by the processor 5. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an LSI integrated circuit, and particularly to a communication LSI.
[0002]
[Prior art]
Devices for realizing high-speed communication modems such as ADSL and wireless LAN require various processes such as FFT (Fourier transform), filter, FEC (forward error correction), complex mapping, CRC, scrambling and interleaving. Is done.
[0003]
As a method of realizing an LSI for high-speed communication in the related art, there is a method of realizing an LSI for communication by preparing one control processor and performing signal processing mainly by dedicated hardware.
[0004]
FIG. 11 is a block diagram showing a configuration of a conventional communication LSI 90. The communication LSI 90 includes one processor 95, an arithmetic logic unit 93 for processing modem data, and a multiply-accumulate unit 94. The arithmetic logic unit 93 includes a Framing CRC 81, a scramble 82, an FEC 83, an interleave 84, a Trellis vitarbi 85, and a Mapping 86. The product-sum operation unit 94 includes an FEQ 87, an FFT 88, and a filter 89.
[0005]
When a communication LSI is to be realized using such dedicated hardware, the processing content is fixedly determined, and thus lacks flexibility. For this reason, it is difficult to change the standard and cope with a problem when connecting to a modem of another company.
[0006]
As another method, there is a method in which a plurality of processors such as a microcomputer and a DSP are mounted and a communication LSI is realized by making full use of a program. In an actual communication LSI, as a method intermediate between the above two methods, there are many methods in which a part is realized by dedicated hardware and the remaining part is realized by a microcomputer and a DSP.
[0007]
FIG. 12 is a block diagram showing the configuration of another conventional communication LSI 80. The communication LSI 80 includes a processor 85, a processor 86 for processing modem data, and a DSP 87.
[0008]
As described above, when a communication LSI is to be realized by a plurality of processors such as a microcomputer and a DSP, the processing capability of each processor is reduced due to competition of memory access between the processors. In this case, the instruction control becomes complicated, so that the instruction memory capacity increases. As a result, the circuit scale increases and the cost increases.
[0009]
In order to avoid these problems even in the prior art, there is a dedicated hardware that has hardware capable of supporting various modes and has a certain degree of flexibility (for example, Patent Reference 1).
[0010]
Alternatively, for a filter having a large amount of calculation, FFT processing, and processing such as FEC having complicated calculations, a hardware accelerator is prepared to reduce the load on the processor.
[0011]
[Patent Document 1]
JP-A-10-243049 (pages 10 to 13, FIG. 1)
[0012]
[Problems to be solved by the invention]
However, in the above-described method of providing the dedicated hardware with various modes, when a function other than a function prepared in advance becomes necessary due to, for example, a standard change or an unexpected factor, such a function is supported. There is a problem that it is difficult to give the communication LSI only flexibility.
[0013]
Further, in the above-described method of preparing a hardware accelerator to reduce the load on the processor, there is a problem that an interrupt from the hardware accelerator to the processor greatly reduces the processing capability of the processor.
[0014]
Further, there is a problem that an interrupt from the hardware accelerator to the processor may be added as a new load to an operation that requires a data transfer period between the hardware accelerator and the processor in advance.
[0015]
An object of the present invention is to provide a communication LSI that can reduce the load on a processor.
[0016]
[Means for Solving the Problems]
A communication LSI according to the present invention includes: an arithmetic unit provided for performing arithmetic processing on communication data; a processor for supplying a control code for controlling an operation of the arithmetic unit; and the control unit provided by the processor. Computing control means for controlling the computing means based on a code, and control code storing means for storing the control code, wherein the computing control means is based on the control code regardless of the operation of the processor. The operation means has a function of reading from the control code storage means, the operation means includes a product-sum operation unit for performing a product-sum operation on the communication data, and an arithmetic operation for performing an arithmetic and logic operation on the communication data. And a logical operation unit.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
In the communication LSI according to the present embodiment, the operation control means controls the product-sum operation unit and the arithmetic and logic operation unit based on the control code supplied by the processor. For this reason, the product-sum operation unit and the arithmetic and logic operation unit for performing arithmetic processing on the communication data are controlled by the operation control means. Therefore, the processor does not need to control the product-sum operation unit and the arithmetic and logic operation unit for performing arithmetic processing on communication data. As a result, the processor can sufficiently exhibit performance in processing other than processing of communication data, so that it is possible to obtain a communication LSI in which the load on the processor is reduced.
[0018]
It is preferable that the product-sum operation unit filters the communication data.
[0019]
It is preferable that the filter processing includes any of FIR filter processing, IIR filter processing, and echo canceller processing.
[0020]
It is preferable that the product-sum operation unit performs FEQ processing on the communication data.
[0021]
It is preferable that the product-sum operation unit performs an FFT process on the communication data.
[0022]
It is preferable that the arithmetic and logic unit performs a bit mapping process on the communication data.
[0023]
The arithmetic and logic unit preferably scrambles the communication data.
[0024]
It is preferable that the arithmetic and logic unit performs a CRC process on the communication data.
[0025]
It is preferable that the arithmetic and logic unit performs a Viterbi process or an interleave process on the communication data.
[0026]
It is preferable that the arithmetic and logic unit has a first arithmetic unit for executing a first type of arithmetic and logic operation and a second arithmetic unit for executing a second type of arithmetic and logic operation. .
[0027]
The arithmetic control means includes: a first arithmetic control instruction for controlling the first arithmetic unit provided in the arithmetic and logic unit; and a second arithmetic control instruction for controlling the second arithmetic unit. A decoder that is generated based on a control code, and a first operation unit controller that controls the first operation unit provided in the arithmetic and logic operation unit based on the first operation control instruction generated by the decoder. And a second operation unit controller that controls the second operation unit provided in the arithmetic and logic operation unit based on the second operation control instruction generated by the decoder.
[0028]
The first type of arithmetic and logic operation performed by the first arithmetic unit provided in the arithmetic and logic unit is a byte arithmetic and logical operation, and is performed by the second arithmetic unit provided in the arithmetic and logic unit. It is preferable that the second type of arithmetic and logic operation to be performed is any of a bit arithmetic and logic operation and a bit division / combination operation.
[0029]
A memory unit provided for storing data related to an arithmetic operation performed by one of the first arithmetic unit and the second arithmetic unit provided in the arithmetic and logic unit; Generating a memory means control instruction for controlling the memory means based on the control code, and further comprising a data path controller for controlling the memory means based on the memory means control instruction generated by the decoder. The memory means reads out data stored in the memory means and supplies the data to one of the first arithmetic unit and the second arithmetic unit under the control of the data path controller. It is preferable that data supplied from any one of the first arithmetic unit and the second arithmetic unit is written to the memory unit.
[0030]
The processor supplies another control code for controlling an operation processing of the communication data by the operation means, and the other control code supplied by the processor and work data related to the processing operation of the processor. And a request from the processor for an access request from the arithmetic control unit to the other control code stored in the work memory and the work data stored in the work memory. An arbiter for arbitrating the access request is preferably further provided.
[0031]
The processor requests the arbiter to access the work memory according to a predetermined priority, and the arithmetic control unit determines a priority higher than the predetermined priority and the predetermined priority according to an operation state of the processor. It is preferable to request the arbiter to access the work memory according to one of the priorities lower than the priority of the arbiter.
[0032]
The processor, after supplying the other control code to the work memory, instructs the operation control unit to access the work memory, and the operation control unit transmits the access code to the work memory in accordance with an instruction from the processor. Preferably, access is requested from the arbiter.
[0033]
A work memory for storing the control code supplied by the processor, wherein the arithmetic control unit performs the arithmetic operation of the arithmetic unit during a training period in preparation for transmitting and receiving the communication data. During the transmission / reception period for transmitting / receiving the communication data, the processing unit stops the processing operation, and based on the control code stored in the work memory, causes the calculation unit to execute the calculation processing operation. It is preferable to control.
[0034]
The arithmetic means is preferably an arithmetic and logic unit for performing an arithmetic and logic operation on the communication data.
[0035]
Preferably, the work memory further stores work data related to a processing operation of the processor, and the processor executes the processing operation based on the work data stored in the work memory.
[0036]
The apparatus further comprises a memory provided for storing data related to the arithmetic processing by the arithmetic means, wherein the control code supplied by the processor controls the arithmetic processing of the communication data by the arithmetic means. A computing unit control code for controlling the computing unit and a data path control code for controlling the operation of the memory means, and for storing the computing unit control code supplied by the processor. Preferably, the apparatus further comprises a storage, and a data path control code storage for storing the data path control code supplied by the processor.
[0037]
The operation control means is responsive to the start command issued by the processor, the operation unit control code stored in the operation unit control code storage unit and the data path stored in the data path control code storage unit. It is preferable to have a control code reader for reading the control code.
[0038]
The arithmetic control unit includes: an arithmetic unit decoder that generates an arithmetic control instruction for controlling an arithmetic processing operation of the arithmetic unit based on the arithmetic unit control code read by the control code read unit; A data path decoder that generates a data path control instruction for controlling the operation of the memory unit based on the data path control code read by the code reader. The communication unit performs arithmetic processing on the communication data according to the arithmetic control instruction generated by the arithmetic unit decoder, and the memory unit stores the data stored in the memory unit according to the data path control instruction generated by the data path decoder. And supplies the read data to the arithmetic means, and the data supplied from the arithmetic means to the memory means. It is preferable to burn them.
[0039]
Memory means provided for storing data related to the arithmetic processing by the arithmetic means, a data queue for storing communication data supplied from the processor, and the communication data stored in the data queue. Preferably, a data path controller for storing the data in the memory means is further provided.
[0040]
It is preferable that the arithmetic means performs arithmetic processing on the communication data stored in the memory means by the data path controller.
[0041]
Preferably, the data queue has a FIFO structure.
[0042]
The communication LSI according to the embodiment includes an arithmetic and logic unit for executing communication data processing, a product-sum operation unit, and a control processor. The arithmetic and logic unit and the product-sum operation unit are based on a control code. It works. The arithmetic logic unit prepares control codes such as bit ALU / byte ALU / bit division / bit combination, and the product sum unit prepares control codes such as product-sum operation, complex multiplication, and product-sum + addition / subtraction. The arithmetic logic unit and the product-sum unit have a storage device for storing control codes, and these control codes are written by a control processor.
[0043]
Each arithmetic unit has an arithmetic control unit that analyzes the control code and controls the operation of the arithmetic unit and input / output data, and the arithmetic control unit receives a communication synchronization signal as a start signal, thereby controlling the control code. The process written in is repeatedly executed.
[0044]
In the communication LSI according to the embodiment, the processing capability of the processor is reduced by automatically repeating the processing programmed by the control code in units of a symbol and a frame synchronization signal which are processing units of communication data. Since communication data can be transmitted and received without any need, and the control code can be freely rewritten from the microcomputer, it is possible to have flexibility in processing. In addition, since the control code generator is integrated in the control processor and code generation in the product-sum operation unit and the arithmetic and logic operation unit is unnecessary, a large-scale on-chip memory such as a general-purpose DSP is not required as the control code generator. .
[0045]
The types of operations required for high-speed communication modem devices such as ADSL and wireless LAN are two types: high-speed product-sum operation such as FFT and filter, and arithmetic logic operation in bit or byte units such as Viterbi decoding, interleaving and mapping. These are roughly classified into types of operations.
[0046]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0047]
(Embodiment 1)
FIG. 1 is a block diagram illustrating a configuration of a communication LSI 100 according to Embodiment 1, FIG. 2 is a block diagram illustrating a configuration of an arithmetic and control unit 1 provided in the communication LSI 100, and FIG. FIG. 2 is a block diagram for explaining a configuration of an arithmetic and control unit 2 provided in the communication LSI 100.
[0048]
The arithmetic and logic unit 3 is controlled by the operation control unit 1, and its control code is stored in the control code storage 6. The product-sum operation unit 4 is controlled by the operation control unit 2, and its control code is stored in the control code storage 7. The control code is written in the control code storage 6 and the control code storage 7 by the processor 5.
[0049]
The detailed configurations of the operation controller 1 and the operation controller 2 shown in FIG. 1 are shown in FIGS. 2 and 3, respectively. Both the arithmetic control 1 and the arithmetic controller 2 can be realized by a similar configuration. Hereinafter, this operation will be described.
[0050]
First, the processor 5 writes respective control codes into the control code storage 6 and the control code storage 7. Next, the processor 5 issues a start command to the operation controller 1 and the operation controller 2. The operation controller 1 and the operation controller 2 are activated by receiving a communication synchronization signal after an activation instruction is first issued from the processor 5.
[0051]
When the operation controller 1 is activated, the control code reader 8 reads out the control code from the control code storage 6 and sends it to the decoder 9. Then, the decoder 9 sends an instruction for controlling the arithmetic processing of the arithmetic and logic unit 3 to the arithmetic unit control unit 11. Next, the arithmetic and logic unit 3 performs an arithmetic process according to an instruction from the arithmetic unit control unit 11.
[0052]
The decoder 9 decodes the control code read from the control code storage 6 and sends an instruction for controlling the position of input / output data and the address mode to the data path controller 10. Then, the memory / register 12 reads and writes data according to an instruction from the data path controller 10.
[0053]
When the reading of the control code is completed, the control code reader 8 returns to the control code start position at the next start-up and stops, and is started by receiving the communication synchronization signal for the second and subsequent times.
[0054]
The operation controller 2 configured similarly to the operation controller 1 also operates in the same manner as the operation controller 1.
[0055]
Since the normal processing required for transmitting and receiving communication data is a repetitive processing for each synchronization signal, such a configuration allows the processor 5 to store the control code in the control code storage 6 and the control code storage 7. After the first start instruction is issued to the operation controller 1 and the operation controller 2 respectively, the operation of the processor 5 is performed by entrusting the operation processing of the communication data to the operation controller 1 and the operation controller 2. Becomes possible. This makes it possible to support various higher-level applications according to the computing capacity of the processor 5.
[0056]
With the above configuration, most of the processing required in the communication data processing can be executed by a small-scale control code.
[0057]
Considering the product-sum multiplier 4, for example, in the case of filter processing, a communication LSI uses an FIR filter, an IIR filter, an echo canceller, or the like. In this case, all the processing contents of the operation can be realized by the product-sum operation function based on the signal data and the coefficient data. Therefore, by writing the number of repetitions of the product-sum operation in the arithmetic unit control unit 11 and appropriately writing the control of the read / write position and the addressing mode in the data path controller 10, it is possible to execute all the filtering processes. is there.
[0058]
The FEQ can be executed by setting a complex multiplication operation in the arithmetic unit control unit 11 and performing processing in the order of input data. In FFT, basically, processing can be performed by repeating a complex multiplication function and an addition / subtraction function.
[0059]
Therefore, a product-sum operation unit 4 having a product-sum operation control function such as a product-sum operation, a complex multiplication, and a product-sum + addition / subtraction operation, and an operation controller 2 having a memory register 26 and a data path controller 10 are illustrated. 1 and the configuration as shown in FIG. 3 and the processor 5 freely writes control codes, so that digital arithmetic processing optimal for communication standards and communication conditions can be performed.
[0060]
As a further effect, there is a bias that the required performance of each arithmetic processing is low in the FEQ and extremely high in the filter and the FFT. However, since all the processing is performed by one product-sum operation unit 4, the circuit scale is small. It is possible to optimize the number of large multipliers.
[0061]
Considering the arithmetic and logic unit 3, for example, in a bit mapping process, it is possible to set the bit division / combination processing function in the arithmetic and logic unit 3 and execute the processing in the order of input data. The scramble processing and the CRC processing can be realized by setting the bit-wise EXOR in the arithmetic and logic unit 3. Although the processing performed by the FEC is slightly complicated, the processing is basically performed by the ALU function in units of bytes. Accordingly, FIG. 2 shows an arithmetic and logic unit 3 having a bit division / combination process, an ALU in a bit unit, and an ALU function in a byte unit, and an operation controller 1 which also supports the memory registers 12 and the rearrangement of data. The connection is made in such a configuration, and the processor 5 freely writes the control code, so that the digital arithmetic processing optimal for the communication standard and the communication state can be performed.
[0062]
By connecting the product-sum operation unit 4 and the arithmetic and logic operation unit 3 to the control processor 5 as shown in FIG. 1, a load is not applied to the control processor 5 while processing communication data. It is possible to provide the flexible communication LSI 100 that can cope with a change in the standard or a trouble when connected to a modem made by another company by changing the control code.
[0063]
(Embodiment 2)
FIG. 4 is a block diagram for explaining the configuration of the arithmetic and control unit 1A provided in the communication LSI according to the second embodiment. In the first embodiment, the same components as those described above with reference to FIG. 2 are denoted by the same reference numerals. Therefore, a detailed description of these components will be omitted.
[0064]
The processing executed by the arithmetic and logic unit 3A requires many types of operations. However, since a multiplier is not required for processing, the circuit scale is small. For this reason, as shown in FIG. 4, the arithmetic and logic unit 3A is divided into a plurality of operation units for each function, and a plurality of operation unit controllers for controlling each operation unit are prepared in the operation unit control unit. Therefore, the circuit scale is not greatly increased.
[0065]
The arithmetic and logic unit 3A includes a byte ALU 13 for performing a byte operation, a bit ALU 14 for performing a bit operation, a bit division / bit combination operation unit 15 for performing a bit division operation and a bit combination operation, and a dedicated instruction. It is divided into a dedicated instruction operation unit 16 for executing an operation.
[0066]
The operation controller 1A includes an operation unit controller 17 for controlling the byte ALU 13, an operation unit controller 18 for controlling the bit ALU 14, and an operation unit for controlling the bit division / bit combination operation unit 15. A controller 19 and an operation unit controller 20 for controlling the dedicated instruction operation unit 16 are provided.
[0067]
By dividing the arithmetic and logic operation unit 3A and the operation unit control unit in this manner, the types of operations to be prepared in the individual operation unit controllers are reduced, so that it is possible to reduce the amount of control codes. In addition, it is possible to improve the processing speed of the calculation by parallelizing the calculation processing. At this time, even if the arithmetic and logic unit 3A is parallelized, the flexibility can be accommodated by changing the control code as in the case where the arithmetic and logic unit 3A is not parallelized by setting one data path controller 10A. It is possible to maintain sex.
[0068]
(Embodiment 3)
FIG. 5 is a block diagram showing a configuration of a communication LSI 100B according to the third embodiment, and FIG. 6 is a block diagram for explaining an operation of an arbiter 22 provided in the communication LSI 100B. The same components as those of the communication LSI 100 described above with reference to FIG. 1 are denoted by the same reference numerals. Therefore, a detailed description of these components will be omitted.
[0069]
In addition to the configuration of Embodiment 1 described above with reference to FIG. 1, a write path is provided from the work memory 21 used by the processor 5B to the control code storage 6B, and control of the processor 5B and operation control It is assumed that an arbiter 22 for arbitrating control of the device 1B is provided.
[0070]
As shown in FIG. 6, the use request of the work memory 21 from the arithmetic controller 1B to the arbiter 22 is a high-priority request having a higher priority than the use request of the work memory 21 from the processor 5B and a low-priority request. Low priority requests with priority.
[0071]
By adopting the above configuration, even when the control code for communication data processing cannot be accommodated by the capacity of the control code storage 6B prepared in advance, the communication data processing can be performed without greatly impeding the processing of the processor 5B. Can be handled. Hereinafter, this operation will be described.
[0072]
When the control code does not fit in the control code storage unit 6B, the processor 5B writes an access instruction to the work memory 21 in the control code, and instructs the operation controller 1B to issue an access request to the arbiter 22. Then, the arithmetic controller 1B sends a read request to the work memory 21 to the arbiter 22 in accordance with the access command at the time when the processing of the control code progresses and the control code can be overwritten in the control code storage 6B.
[0073]
The access request sent by the operation controller 1B to the arbiter 22 is a low-priority request while the arithmetic and logic unit 3 is operable by the control code stored in the control code storage unit 6B. The arbiter 22 releases the access right to the work memory 21 to the operation controller 1B in accordance with a request from the operation controller 1B only during a period in which the memory is being used or the work memory 21 is not being accessed due to the sleep state. I do.
[0074]
If the control code can be rewritten while the processor 5B is not using the work memory 21 as described above, the processing performance of the processor 5B can be maintained even if the operation controller 1B reads the control code from the work memory 21. Is not reduced.
[0075]
If the control code cannot be rewritten while the processor 5B is not using the work memory 21, the arithmetic and logic unit 3 cannot operate with only the control code stored in the control code storage 6B. At this point, the request from the operation controller 1B to the arbiter 22 becomes a high priority request. Then, the arbiter 22 stops the access to the work memory 21 from the processor 5B and releases the right to access the work memory 21 to the operation controller 1B.
[0076]
Although this will hinder the movement of the processor 5B, it is possible to continue the processing without causing a failure in the communication processing. By operating as described above, even when the control code does not fit in the control code storage unit 6B, it is possible to cope with the communication process without significantly hindering the processing of the processor 5B.
[0077]
(Embodiment 4)
FIG. 7 is a block diagram showing a configuration of a communication LSI 100C according to the fourth embodiment, and FIG. 8 is a block diagram for explaining an operation of the communication LSI 100C. The same components as those of the communication LSI 100 described above with reference to FIG. 1 are denoted by the same reference numerals. Therefore, a detailed description of these components will be omitted.
[0078]
In addition to the configuration of the first embodiment described above with reference to FIG. 1, it is assumed that a control code for controlling the arithmetic and logic unit 3 is stored in the work memory 21C used by the processor 5C.
[0079]
According to the standards for modem communication such as ADSL and wireless LAN, a training period for detecting a line state is required for normal transfer between devices. During the training period, the processing performed by the arithmetic and logic unit 3, such as error correction and frequency mapping, is unnecessary, and instead, a complicated processing of detecting the line state is performed. Therefore, the role of the processor 5C increases, and the capacity of the work memory 21C required by the processor 5C increases. Conversely, during the modem transmission / reception processing after the training period ends, the role of the processor 5C is reduced, so that the capacity of the work memory 21C required by the processor 5C is also reduced.
[0080]
For this reason, the control code storage unit for storing the control code for controlling the arithmetic and logic unit 3 can be shared with the work memory 21C used by the processor 5C.
[0081]
During the training period, the processor 5C uses the work memory 21C as shown in FIG. 7, and the operation controller 1C issues a stop instruction to the arithmetic and logic unit 3. During the modem transmission / reception period, as shown in FIG. 8, the operation controller 1C controls the operation of the arithmetic and logic unit 3 based on the control code stored in the work memory 21C.
[0082]
With the above configuration, it is possible to reduce the memory resources required for storing the control codes without impairing the operation of the entire communication LSI 100C.
[0083]
(Embodiment 5)
FIG. 9 is a block diagram for explaining the configuration of the arithmetic and control unit 1D provided in the communication LSI according to the fifth embodiment. In the first embodiment, the same components as those described above with reference to FIG. 2 are denoted by the same reference numerals. Therefore, a detailed description of these components will be omitted.
[0084]
The control code storage 6 in the configuration of the first embodiment described above with reference to FIG. 2 is divided into an arithmetic unit control code storage 27 and a data path control code storage 28. It is assumed that the control code reader 8D simultaneously controls the reading of the arithmetic unit control code and the reading of the data path control code.
[0085]
Various operations required for the communication processing may be different in the readout position of the operation data by the data path controller 10 and the addressing mode even though the control by the operation unit control unit 11 is the same. Conversely, even though the method of reading operation data by the data path controller 10 is constant, there is a process in which the operation type of the operation unit control unit 11 is different. Therefore, as shown in FIG. 9, the arithmetic unit control code storage unit 27 and the data path control code storage unit 28 are independently provided, and various readout positions and addressing modes are combined for one type of arithmetic unit control code. Alternatively, conversely, by combining various types of arithmetic unit control codes with one type of data path control code, it is possible to reduce the amount of necessary control codes.
[0086]
(Embodiment 6)
FIG. 10 is a block diagram showing a configuration of a communication LSI 100E according to the sixth embodiment. In Embodiment 1, the same components as those described with reference to FIGS. 1 and 2 are denoted by the same reference numerals. Therefore, a detailed description of these components will be omitted.
[0087]
In addition to the configuration described with reference to FIGS. 1 and 2 in the first embodiment, a data queue 25 connected as a work register of processor 5E and a memory / register 12 as a modem operation data memory are connected from data queue 25. And a data path controller 10E having the read / write control function. The data queue 25 has a FIFO structure.
[0088]
In a communication standard such as an ADSL modem that requires a long-term connection, it is information data that does not require real-time properties such as communication maintenance and maintenance information. In some cases, information data that is effective to perform processing is transmitted and received by being carried on modem data. When such information data is stored in the memory / register 12 from the processor 5E and loaded on the modem data, the data queue 25 is used.
[0089]
The processor 5E writes a check instruction for checking the data queue 25 in the control code in advance. Then, the processor 5E writes the transmission data to the data queue 25 when it becomes necessary to transmit the data during transmission and reception of the modem data.
[0090]
Next, the data path controller 10E periodically checks whether data is stored in the data queue 25 according to the control code. When there is no data in the data queue 25, the modem operation processing is continued as it is. If there is data in the data queue 25, the data is taken out from the data queue 25 and stored in the memory / register 12, and then the modem arithmetic processing is continued. The reverse operation is performed for reading from the modem data.
[0091]
With the above operation, the processor 5E can transmit / receive data to / from the modem data at an arbitrary timing via the data queue 25. As a result, the transmission / reception processing of the modem data can be continued without receiving the interruption of the arithmetic controller 1E.
[0092]
As described above, in the communication LSI according to the first to sixth embodiments, the versatility can be improved because the communication arithmetic processing is executed based on the control code.
[0093]
Further, since the control code does not have a complicated control mechanism such as conditional branch control, the circuit size of the controller can be reduced.
[0094]
Furthermore, since the function of generating control codes is integrated in the processor, there is no need to generate control codes in the product-sum operation unit / arithmetic logic operation unit. Therefore, a large-scale on-chip memory such as a general-purpose DSP is not required as a control code generator.
[0095]
Further, since the processor is separated from the real-time control of the communication data, the processor can exhibit sufficient performance in addition to the processing of the communication data.
[0096]
Furthermore, the number of multipliers can be optimized by using a multiplier having a large area cost in a plurality of product-sum operations.
[0097]
As a result, the area can be reduced while maintaining flexibility, and a low-cost communication LSI can be provided.
[0098]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a communication LSI that can reduce the load on a processor and maintain flexibility in calculating communication data.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a communication LSI according to a first embodiment;
FIG. 2 is a block diagram for explaining a configuration of an arithmetic and control unit provided in the communication LSI according to the first embodiment;
FIG. 3 is a block diagram for explaining a configuration of another arithmetic and control unit provided in the communication LSI according to the first embodiment;
FIG. 4 is a block diagram for explaining a configuration of a communication LSI according to a second embodiment;
FIG. 5 is a block diagram showing a configuration of a communication LSI according to a third embodiment;
FIG. 6 is a block diagram for explaining an operation of an arbiter provided in a communication LSI according to a third embodiment;
FIG. 7 is a block diagram showing a configuration of a communication LSI according to a fourth embodiment;
FIG. 8 is a block diagram for explaining an operation of the communication LSI according to the fourth embodiment;
FIG. 9 is a block diagram for explaining a configuration of a communication LSI according to a fifth embodiment;
FIG. 10 is a block diagram showing a configuration of a communication LSI according to a sixth embodiment.
FIG. 11 is a block diagram showing a configuration of a conventional communication LSI.
FIG. 12 is a block diagram showing the configuration of another conventional communication LSI.
[Explanation of symbols]
1 Arithmetic controller
2 Operation controller
3 arithmetic logic unit
4 Multiply and accumulator
5 processor
6 Control code storage
7 Control code storage
8 Control code reader
9 Decoder
10 Data path controller
11 Operation unit control unit
12 Memory / Register
13-byte ALU
14-bit ALU
15-bit split / join operation unit
16 Dedicated instruction operation unit
17, 18, 19, 20 Arithmetic unit controller
21 Work memory
22 Arbiter
23 Operation unit decoder
24 Data Path Decoder
25 Data Queue
27 Operation unit control code storage
28 Data path control code storage

Claims (25)

Arithmetic means provided for arithmetically processing the communication data;
A processor that supplies a control code for controlling the operation of the arithmetic unit,
Arithmetic control means for controlling the arithmetic means based on the control code supplied by the processor,
Control code storage means for storing the control code,
The arithmetic control unit operates based on the control code without depending on the operation of the processor, and has a reading function from the control code storage unit,
A communication LSI, wherein the arithmetic unit includes a product-sum operation unit for performing a product-sum operation on the communication data and an arithmetic-logic operation unit for performing an arithmetic-logic operation on the communication data. The communication LSI according to claim 1, wherein the product-sum operation unit filters the communication data. 3. The communication LSI according to claim 2, wherein said filter processing includes any one of FIR filter processing, IIR filter processing, and echo canceller processing. The communication LSI according to claim 1, wherein the product-sum operation unit performs FEQ processing on the communication data. The communication LSI according to claim 1, wherein the product-sum operation unit performs an FFT process on the communication data. 2. The communication LSI according to claim 1, wherein the arithmetic and logic unit performs a bit mapping process on the communication data. 2. The communication LSI according to claim 1, wherein the arithmetic and logic unit performs a scramble process on the communication data. 2. The communication LSI according to claim 1, wherein the arithmetic and logic unit performs a CRC process on the communication data. 2. The communication LSI according to claim 1, wherein the arithmetic and logic unit performs a Viterbi process or an interleave process on the communication data. The arithmetic and logic unit includes a first arithmetic unit for performing a first type of arithmetic and logic operation;
2. The communication LSI according to claim 1, further comprising a second operation unit for executing a second type of arithmetic and logic operation. The arithmetic control means includes: a first arithmetic control instruction for controlling the first arithmetic unit provided in the arithmetic and logic unit; and a second arithmetic control instruction for controlling the second arithmetic unit. A decoder that generates based on the control code;
A first operation unit controller that controls the first operation unit provided in the arithmetic and logic operation unit based on the first operation control instruction generated by the decoder;
11. A second operation unit controller for controlling the second operation unit provided in the arithmetic and logic unit based on the second operation control instruction generated by the decoder. Communication LSI. The first type of arithmetic and logic operation performed by the first arithmetic unit provided in the arithmetic and logic unit is a byte arithmetic and logic operation,
The said 2nd kind of arithmetic and logic operation performed by the said 2nd arithmetic part provided in the said arithmetic and logic operation unit is any of a bit arithmetic and logic operation and a bit division / combination operation. Communication LSI. The arithmetic and logic unit further includes a memory unit provided to store data related to an arithmetic process performed by one of the first arithmetic unit and the second arithmetic unit provided in the arithmetic and logic unit,
The decoder generates a memory control instruction for controlling the memory based on the control code,
A data path controller for controlling the memory means based on the memory means control instruction generated by the decoder;
The memory means reads out data stored in the memory means and supplies the data to one of the first arithmetic unit and the second arithmetic unit in accordance with control by the data path controller, and The communication LSI according to claim 10, wherein data supplied from one of a unit and the second arithmetic unit is written to the memory unit. The processor supplies another control code for controlling an operation processing of the communication data by the arithmetic unit,
A work memory for storing the other control code supplied by the processor and work data related to a processing operation of the processor;
An arbiter for arbitrating an access request from the arithmetic control unit to the other control code stored in the work memory and an access request from the processor to the work data stored in the work memory. The communication LSI according to claim 1, comprising: The processor requests the arbiter to access the work memory according to a predetermined priority,
The arithmetic control means, according to an operation state of the processor, controls access to the work memory by one of a priority higher than the predetermined priority and a priority lower than the predetermined priority. The communication LSI according to claim 14, wherein the communication LSI is requested. The processor, after supplying the other control code to the work memory, instructs the arithmetic control unit to access the work memory, and the arithmetic control unit sends the access code to the work memory in accordance with an instruction from the processor. 15. The communication LSI according to claim 14, wherein access is requested to the arbiter. A work memory for storing the control code supplied by the processor;
The arithmetic control unit stops the arithmetic processing operation of the arithmetic unit during a training period for preparing to transmit and receive the communication data, and the work memory during a transmission and reception period to transmit and receive the communication data. 2. The communication LSI according to claim 1, wherein said arithmetic means controls said arithmetic means based on said control code stored in said arithmetic means so as to execute an arithmetic processing operation. 18. The communication LSI according to claim 17, wherein said operation means is an arithmetic and logic unit for performing an arithmetic and logic operation on said communication data. The work memory further stores work data related to the processing operation of the processor,
The communication LSI according to claim 17, wherein the processor executes the processing operation based on the work data stored in the work memory. Further comprising a memory means provided for storing data related to the arithmetic processing by the arithmetic means,
The control code supplied by the processor, an arithmetic unit control code for controlling the operation processing of the communication data by the arithmetic means,
A data path control code for controlling the operation of the memory means.
A computing unit control code storage for storing the computing unit control code supplied by the processor;
2. The communication LSI according to claim 1, further comprising a data path control code storage for storing the data path control code supplied by the processor. The operation control means is responsive to the start command issued by the processor, the operation unit control code stored in the operation unit control code storage unit and the data path stored in the data path control code storage unit. 21. The communication LSI according to claim 20, further comprising a control code reader that reads out the control code. The arithmetic control unit, based on the arithmetic unit control code read by the control code reader, an arithmetic unit decoder that generates an arithmetic control instruction for controlling the arithmetic processing operation of the arithmetic unit,
A data path decoder that generates a data path control instruction for controlling the operation of the memory unit based on the data path control code read by the control code reader.
The arithmetic means performs arithmetic processing on the communication data according to the arithmetic control command generated by the arithmetic unit decoder,
In response to the data path control command generated by the data path decoder, the memory unit reads out data stored in the memory unit and supplies the read data to the arithmetic unit. 22. The communication LSI according to claim 21, wherein the LSI is written into a memory. Memory means provided for storing data relating to the arithmetic processing by the arithmetic means,
A data queue for storing communication data supplied from the processor,
2. The communication LSI according to claim 1, further comprising: a data path controller configured to store the communication data stored in the data queue in the memory unit. 24. The communication LSI according to claim 23, wherein said arithmetic means performs arithmetic processing on said communication data stored in said memory means by said data path controller. 24. The communication LSI according to claim 23, wherein said data queue has a FIFO structure.

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