JP2004221176A - Wiring board with built-in solid state electrolytic capacitor and method of manufacturing the same - Google Patents

Wiring board with built-in solid state electrolytic capacitor and method of manufacturing the same Download PDF

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Publication number
JP2004221176A
JP2004221176A JP2003004448A JP2003004448A JP2004221176A JP 2004221176 A JP2004221176 A JP 2004221176A JP 2003004448 A JP2003004448 A JP 2003004448A JP 2003004448 A JP2003004448 A JP 2003004448A JP 2004221176 A JP2004221176 A JP 2004221176A
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Prior art keywords
electrolytic capacitor
solid electrolytic
wiring board
built
semiconductor chip
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Japanese (ja)
Inventor
Tatsuo Fujii
達雄 藤井
Katsumasa Miki
勝政 三木
Ryo Kimura
涼 木村
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2003004448A priority Critical patent/JP2004221176A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To realize a wiring board with a built-in solid state electrolytic capacitor which can load, in a low stress, a solid state electrolytic capacitor having reduced a loop inductance and also a semiconductor chip in the higher accuracy. <P>SOLUTION: The wiring board with built-in solid state electrolytic capacitor comprises a wiring board 1 provided with a semiconductor chip accommodating part 4 at the predetermined position on the wiring board 1, and a solid state electrolytic capacitor accommodating part 5 at the lower surface of the semiconductor chip accommodating part 4. A sheet type solid state electrolytic capacitor 2 providing, at the one surface thereof, a plurality of connection bumps 15 is allocated in the solid state electrolytic capacitor accommodating part 5. This capacitor 2 is provided with a porous part at the one surface of a valve metal sheet body 6. Moreover, at the surface of this porous part, a dielectric material film 7, a solid state electrolytic layer 8, and a collecting material layer 9, are provided. The wiring board with built-in electrolytic capacitor also comprises a first insulation part 11 provided to the valve metal sheet body 6, a connection terminal 14, and a first connection bump 15 provided on the exposed surface of a through-hole electrode 12. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は半導体チップなどの電子部品を載置する配線基板に関し、特に半導体チップに電荷を供給するためのコンデンサを内蔵した固体電解コンデンサ内蔵配線基板およびその製造方法に関するものである。
【０００２】
【従来の技術】
従来、情報通信関連機器で用いられる半導体チップにおいては、電源の安定供給のために電源と半導体チップの間にコンデンサを配置している。
【０００３】
しかしながら、１００ｋＨｚ以上の高速動作においては半導体チップの駆動電圧の変動も非常に大きくなることから、この用途に用いるコンデンサについては高周波特性を左右する等価直列抵抗（ＥＳＲ）、等価直列インダクタンス（ＥＳＬ）を低減することができるコンデンサが望まれていた。さらに、半導体チップをより高周波で動作させるためには、コンデンサと半導体チップ間の配線引き回しによるインダクタンスが無視できなくなるために半導体チップの誤動作の原因となり、電源供給を安定化させることも困難であった。
【０００４】
この要望に対して、高周波用の半導体チップの電源用に用いるコンデンサの構造を工夫するとともに、半導体チップの直下にこのコンデンサを配置し、電源ラインとグランドラインとの配線長を短くすることによってループインダクタンスを低減する実装方法などが提案されている。
【０００５】
例えば、上記コンデンサの構造としては特許文献１に開示されているように、アルミニウム固体電解コンデンサの同一平面内に陽極端子と陰極端子を配置したマトリクス電極を形成し、これらの電極端子と半導体チップを直接接続バンプを介して接続するという構造を有しているものである。その固体電解コンデンサの具体的な構造は、片面に集電体層を形成した固体電解コンデンサの陽極箔に複数のスルホールを設け、スルホール内に集電体層と接続されるスルホール電極を形成し、スルホール電極上および陽極箔上の所定の位置に電極端子を形成し、同一平面内に陽極端子と陰極端子を配置したマトリクス電極を構成しているものである。
【０００６】
また、特許文献２に開示されている前記実装方法の構成としては複数の接続端子を有する積層セラミックコンデンサを複数の接続端子を有する配線基板の中に設けた凹部に配置し、前記積層セラミックコンデンサの複数の接続端子と前記配線基板の複数の接続端子とをフリップチップ接続したコンデンサ付配線基板の構造が提案されている。
【０００７】
【特許文献１】
特開２００１−３０７９５５号公報
【特許文献２】
特開２０００−３４９２２５号公報
【０００８】
【発明が解決しようとする課題】
しかしながら、上述の固体電解コンデンサは多数の接続バンプが存在するため、半導体チップと精度よく実装することが困難であり、半導体チップの接続バンプに対して高精度かつ生産性に優れた実装構造が望まれていた。
【０００９】
また、前記コンデンサ付配線基板では積層セラミックコンデンサの機械的強度の観点から厚みの薄い積層セラミックコンデンサを用いることは困難であるので、前記コンデンサ付配線基板の低背化を実現することが困難であった。
【００１０】
そこで、本発明の目的は、上述した従来の問題点を解決するためになされたものであり、ループインダクタンスを低減した薄い固体電解コンデンサを低応力で実装して構成される小型、低背の固体電解コンデンサ内蔵配線基板およびその製造方法を提供しようとするものである。
【００１１】
【課題を解決するための手段】
上記課題を解決するために本発明の請求項１に記載の発明は、少なくとも所定の位置に設けた半導体チップ収納部と前記半導体チップ収納部の下面に少なくとも一つ以上の固体電解コンデンサ収納部とを設けた配線基板と、少なくとも片面に複数の接続端子を設けたシート状の固体電解コンデンサを前記固体電解コンデンサ収納部に配置し、前記固体電解コンデンサが少なくとも弁金属シート体の片面に多孔質部を設け、この多孔質部の表面に誘電体被膜、この誘電体被膜上に固体電解質層、この固体電解質層上に集電体層を設け、前記弁金属シート体に設けた複数のスルホールと、このスルホールの内壁及び弁金属シート体の多孔質化されていない面に設けた第一絶縁部と、前記スルホール内に設けた前記集電体層と接続されるスルホール電極と、前記第一絶縁部の所定の位置に設けた開口部に設けた接続端子と、前記スルホール電極と前記接続端子の表出面に第一接続バンプを設けた構成とした固体電解コンデンサ内蔵配線基板であり、固体電解コンデンサをほぼ無応力で実装することが可能で、かつ固体電解コンデンサ収納部と半導体チップ収納部によって位置決めすることにより半導体チップを高精度に実装することができる固体電解コンデンサ内蔵配線基板を実現することができる。
【００１２】
請求項２に記載の発明は、少なくとも所定の位置に設けた半導体チップ収納部と前記半導体チップ収納部の下面に少なくとも一つ以上の固体電解コンデンサ収納部とを設けた配線基板と、少なくとも片面に複数の接続端子を設けたシート状の固体電解コンデンサを前記固体電解コンデンサ収納部に配置し、前記固体電解コンデンサが誘電体被膜上の所定の位置に前記固体電解質層と前記集電体層を貫通して設けた複数の第二絶縁部と、前記集電体層および前記第二絶縁部上に設けた第一絶縁部と、前記第二絶縁部に弁金属シート体まで渡って設けた複数のビアホールと、このビアホールの中に設けた前記弁金属シート体と接続されるビアホール電極と、前記第一絶縁部の所定の位置に設けた開口部に設けた接続端子と、前記ビアホール電極および前記接続端子の表出面に設けた第一接続バンプとで構成した固体電解コンデンサ内蔵配線基板であり、請求項１の作用に加えて固体電解コンデンサの陽極と陰極の距離を短くすることが可能であるためにリアクタンス成分のより小さい固体電解コンデンサを内蔵した固体電解コンデンサ内蔵配線基板を実現することができる。
【００１３】
請求項３に記載の発明は、固体電解コンデンサ収納部を半導体チップ収納部の面内に設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板であり、固体電解コンデンサが半導体チップの直下に配置可能であるためにリアクタンス成分のより小さい固体電解コンデンサ内蔵配線基板を実現することができる。
【００１４】
請求項４に記載の発明は、固体電解コンデンサ収納部を半導体チップ収納部面内に複数設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板であり、半導体チップの直下に最適な性能を有する固体電解コンデンサを配置することができる固体電解コンデンサ内蔵配線基板を実現することが可能である。
【００１５】
請求項５に記載の発明は、半導体チップ収納部の側面が開口側に拡大するようにテーパーを設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板であり、半導体チップの搭載不良を低減することができる。
【００１６】
請求項６に記載の発明は、固体電解コンデンサ収納部の側面が開口側に拡大するようにテーパーを設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板であり、固体電解コンデンサの搭載不良を低減することが可能である。
【００１７】
請求項７に記載の発明は、固体電解コンデンサ収納部の高さを少なくとも固体電解コンデンサの厚みより低くした請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板であり、固体電解コンデンサの第一接続バンプが半導体チップ収納部の底面より高い位置に来ることにより、半導体チップと確実に接続することができる。
【００１８】
請求項８に記載の発明は、固体電解コンデンサ収納部と固体電解コンデンサの間に第三絶縁部を設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板であり、固体電解コンデンサの位置を固定することができ、固体電解コンデンサを起点とする応力が発生したとしても、第三絶縁部により緩和することが可能である。
【００１９】
請求項９に記載の発明は、第三絶縁部が無機フィラーを含有した樹脂材料である請求項８に記載の固体電解コンデンサ内蔵配線基板であり、請求項８の作用に加えて固体電解コンデンサの放熱を効率よく行うことができる。
【００２０】
請求項１０に記載の発明は、半導体チップ収納部と半導体チップ間の間に第四絶縁部を設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板であり、半導体チップの位置を固定することができ、半導体チップを起点とする応力が発生したとしても、第四絶縁部により緩和することが可能である。
【００２１】
請求項１１に記載の発明は、第四絶縁部が無機フィラーを含有した樹脂材料である請求項１０に記載の固体電解コンデンサ内蔵配線基板であり、請求項１０の作用に加えて半導体チップの放熱を効率良く行うことが可能である。
【００２２】
請求項１２に記載の発明は、半導体チップと固体電解コンデンサが第一接続バンプを介して接続されるように構成した請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板であり、接続が最短で実現できることからより小型化と薄型化および高周波対応性の向上を実現することができる。
【００２３】
請求項１３に記載の発明は、半導体チップの上面が配線基板の上面と一致するように半導体チップ収納部を形成した請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板であり、凹凸のない平坦な固体電解コンデンサ内蔵配線基板を実現することができる。
【００２４】
請求項１４に記載の発明は、半導体チップの上面が配線基板の上面よりも低い位置になるように半導体チップ収納部を形成した請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板であり、半導体チップ上にさらに配線あるいは部品を実装することができる固体電解コンデンサ内蔵配線基板を実現することができる。
【００２５】
請求項１５に記載の発明は、固体電解コンデンサ収納部が設けられていない半導体チップ収納部の下面に第二接続バンプを設け、半導体チップと配線基板が第二接続バンプを介して接続されるように構成した請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板であり、他の電子部品もしくは電源と半導体チップとの接続を可能にすることができる。
【００２６】
請求項１６に記載の発明は、固体電解コンデンサ収納部の下面に第三接続バンプを設け、固体電解コンデンサと配線基板が第三接続バンプを介して接続した請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板であり、他の電子部品もしくは電源と固体電解コンデンサとの接続を可能にすることができる。
【００２７】
請求項１７に記載の発明は、固体電解コンデンサに外装を設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板であり、耐応力性や信頼性を向上させることができる。
【００２８】
請求項１８に記載の発明は、固体電解コンデンサの外装の外周部に切り欠き部を設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板であり、固体電解コンデンサ収納部と固体電解コンデンサの間に設ける第三絶縁部を容易に形成することができる。
【００２９】
請求項１９に記載の発明は、固体電解コンデンサの外装の表面に粗面化処理を施した請求項１７に記載の固体電解コンデンサ内蔵配線基板であり、半導体チップと第四絶縁部または固体電解コンデンサと第三絶縁部との密着性が高くなり、高信頼性の固体電解コンデンサ内蔵配線基板とすることができる。
【００３０】
請求項２０に記載の発明は、配線基板の内部および表層に配線ラインを設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板であり、配線基板上に設けた接続バンプを介して半導体チップや固体電解コンデンサと他の電子部品もしくは電源と高密度に最短で接続することができる。
【００３１】
請求項２１に記載の発明は、配線基板が、半導体チップ収納部に対応した箇所に開口部を形成した第一樹脂シートおよび第一プリプレグと、前記第一プリプレグ下に設けた固体電解コンデンサ収納部に対応した箇所に開口部を形成した第二樹脂シートおよび第二プリプレグと、前記第二プリプレグ下に設けた第三樹脂シートとからなる請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板であり、生産性に優れた固体電解コンデンサ内蔵配線基板の構成とすることができる。
【００３２】
請求項２２に記載の発明は、配線基板を形成する工程が、第一樹脂シートに半導体チップ収納部を形成し、第二樹脂シートに固体電解コンデンサ収納部を形成する工程と、第一プリプレグに半導体チップ収納部を形成し、第二プリプレグに固体電解コンデンサ収納部を形成する工程と、第一樹脂シート、第二樹脂シート、第一プリプレグおよび第二プリプレグに配線ラインを形成する工程と、第一樹脂シート、第一プリプレグ、第二樹脂シート、第二プリプレグ、第三樹脂シートの順に積層して接着する工程と、固体電解コンデンサ収納部に固体電解コンデンサを収納する工程とからなる固体電解コンデンサ内蔵配線基板の製造方法であり、生産性に優れた固体電解コンデンサ内蔵配線基板の製造方法を実現することができる。
【００３３】
請求項２３に記載の発明は、配線ラインを形成する工程が、第一樹脂シート、第二樹脂シート、第三樹脂シートの所定の位置に電極パターンとスルホールを形成する工程と、第一プリプレグ、第二プリプレグの所定の位置にスルホールを形成する工程と、スルホール内に導電体を形成する工程と、第一樹脂シート、第一プリプレグ、第二樹脂シート、第二プリプレグ、第三樹脂シートの順に積層し熱硬化する工程とからなる請求項２２に記載の固体電解コンデンサ内蔵配線基板の製造方法であり、半導体チップ収納部と固体電解コンデンサ収納部の形成のための開口部の形成と同時に配線ラインのスルホールを形成することができる。
【００３４】
【発明の実施の形態】
以下、本発明の固体電解コンデンサ内蔵配線基板およびその製造方法について実施の形態および図面を用いて説明する。
【００３５】
（実施の形態１）
本発明の実施の形態１および図１〜図７により請求項１、３〜２３に記載の発明を説明する。
【００３６】
図１は本発明の実施の形態１における固体電解コンデンサ内蔵配線基板の断面図であり、図２は同上面図である。また図３は固体電解コンデンサ２の要部拡大断面図であり、図４、図５は図１とは別の形態の固体電解コンデンサ内蔵配線基板の断面図、図６は半導体チップ３を実装していない固体電解コンデンサ内蔵配線基板の上面図であり、図７は配線基板の断面図である。
【００３７】
図１に示す固体電解コンデンサ内蔵配線基板は半導体チップ収納部４、半導体チップ３に電荷を供給する固体電解コンデンサ２とを備えたものであり、この半導体チップ収納部４に半導体チップ３を高精度かつ容易に実装することができる構造を実現しているものである。この固体電解コンデンサ内蔵配線基板は所定の位置に半導体チップ収納部４を設け、前記半導体チップ収納部４の下面に少なくとも一つ以上の固体電解コンデンサ収納部５を設け、さらに前記固体電解コンデンサ収納部５内に固体電解コンデンサ２を配置し、前記固体電解コンデンサ２の上の半導体チップ収納部４に半導体チップ３を実装できるように構成していることを特徴としている。
【００３８】
また、前記固体電解コンデンサ２は図１、図３に示すように、少なくとも弁金属シート体６の片面に多孔質部を設け（図示せず）、この多孔質部の表面に誘電体被膜７、この誘電体被膜７上に固体電解質層８、この固体電解質層８上に集電体層９を設けて固体電解コンデンサ２の容量素子部を形成している（容量素子部とはコンデンサ機能を果たす基本的な構成要素を含んでいる。）。
【００３９】
この固体電解コンデンサ２はアルミニウム箔を利用できることから、その厚みを１００〜２００μｍの薄いシート状のコンデンサ素子とすることができる。
【００４０】
このような固体電解コンデンサ２において、前記弁金属シート体６に複数のスルホール１０を設け、このスルホール１０の内壁及び弁金属シート体６の多孔質化されていない面に第一絶縁部１１を設けている。さらに、前記スルホール１０内に前記集電体層９と接続されるスルホール電極１２を設け、前記第一絶縁部１１の所定の位置に開口部１３を設け、この開口部１３の上に接続端子１４を設け、前記接続端子１４およびスルホール電極１２の表出部に第一接続バンプ１５を設けて構成している。
【００４１】
また、スルホール電極１２と接続端子１４とを交互に配置するように構成することにより、固体電解コンデンサ２の内部で電流が流れる方向が反対となることから、発生する磁界を相殺する電極配置となり等価直列インダクタンス（ＥＳＬ）値を極小にすることができることから、小型・低背で高周波特性に優れるとともに配線基板１の表面への高密度実装を実現するとともに、生産性にも優れたものとすることができる。
【００４２】
次に、前記固体電解コンデンサ２を配線基板１に実装する方法について説明する。
【００４３】
図１に示すように、固体電解コンデンサ２より若干大きめの固体電解コンデンサ収納部５を許容される寸法範囲内で形成することにより、許容寸法範囲内の精度で配置することができる。また、同様に半導体チップ収納部４を許容される寸法範囲内で半導体チップ３より若干大きく形成することによって、固体電解コンデンサ２と半導体チップ３を許容される寸法範囲内で効率良く実装することができる。
【００４４】
また、半導体チップ収納部４および固体電解コンデンサ収納部５の側面には開口側が拡大するようにテーパーを設けたほうがよい。このテーパーを設けることにより、半導体チップ収納部４および固体電解コンデンサ収納部５の中心部に半導体チップ３および固体電解コンデンサ２を高精度に実装することができる。
【００４５】
さらに、固体電解コンデンサ収納部５と前記固体電解コンデンサ２の間に第三絶縁部１６を設けることにより、固体電解コンデンサ２の位置を固定することが可能である。また、固体電解コンデンサ２を起点とする応力が発生したとしても、第三絶縁部１６により緩和することが可能である。また第三絶縁部１６に無機フィラーを含有した樹脂などを用いることにより、第三絶縁部１６の熱伝導率を向上させて固体電解コンデンサ２や半導体チップ３の放熱をより効率良く行うことも可能である。さらにまた無機フィラーの含有によって第三絶縁部１６を構成する樹脂材料の線膨張係数の制御や耐熱性の向上等の機能を付与することもできることから低応力で薄型の固体電解コンデンサ２を用いることができるために、配線基板１の厚みも薄くすることが可能となる。
【００４６】
また、同様に半導体チップ収納部４と半導体チップ３の間に第四絶縁部１７を形成することにより、上記と同じ効果を得ることができる。
【００４７】
さらに、この半導体チップ収納部４と半導体チップ３の位置関係において第四絶縁部１７によって封止された半導体チップ３の上面が配線基板１の上面と一致するように設けることにより、凹凸のない平坦な固体電解コンデンサ内蔵配線基板を形成することができる。
【００４８】
また、図４に示すように半導体チップ３の上面が配線基板１の上面より少なくとも低い位置になるように半導体チップ収納部４を設けることにより、半導体チップ３の上にさらに他の電子部品の搭載層もしくは配線層の形成が可能である。
【００４９】
さらに、固体電解コンデンサ収納部５の高さを前記固体電解コンデンサ２の厚さより低くすることで、固体電解コンデンサ２の上面が半導体チップ収納部４の底面より高い位置にくることになり、その上に配置する半導体チップ３を確実に接続することができる。
【００５０】
次に、図５に示すように固体電解コンデンサ収納部５を半導体チップ収納部４面内に複数配置することにより、複数の固体電解コンデンサ２を半導体チップ３の直下に配置することが可能である。なお、この固体電解コンデンサ収納部５には固体電解コンデンサ２以外の電子部品を実装することも可能である。
【００５１】
また、図１、図４に示すように前記固体電解コンデンサ２以外の電子部品もしくは配線ラインと半導体チップ３の接続方法としては、半導体チップ収納部４の固体電解コンデンサ収納部５が設けられない下面に第二接続バンプ１８を設け、半導体チップ３と配線基板１が第二接続バンプ１８を介して接続することにより配線ライン２１ａへ接続することができる。
【００５２】
また、固体電解コンデンサ収納部５の下面に第三接続バンプ１９を設け、固体電解コンデンサ２と配線基板１が第三接続バンプ１９を介して配線ライン２１ｂに接続することにより、他の電子部品と固体電解コンデンサ２との接続を可能にすることができる。上記のような配線ライン２１ａ、２１ｂを形成することにより高密度配線による高密度実装構造の固体電解コンデンサ内蔵配線基板を実現することができる。
【００５３】
なお、固体電解コンデンサ２に外装３４を施すことにより、固体電解コンデンサ２の耐応力性をより向上させることが可能であり、耐熱性や耐湿性等の信頼性においてもより向上させることができる。
【００５４】
また、図６に示すように固体電解コンデンサ２の外装３４の外周部に切り欠き部２０を形成しておくことにより、固体電解コンデンサ２の実装方向を正確に確認することができるとともに切り欠き部２０から樹脂を充填することができ、固体電解コンデンサ収納部５と固体電解コンデンサ２の間に設ける第三絶縁部１６を容易に形成することができる。
【００５５】
次に、図７を用いて配線基板１の構成の一例を説明する。
【００５６】
図７に示すように、半導体チップ収納部４に対応した箇所に開口部を形成した第一樹脂シート２２の下に、半導体チップ収納部４に対応した箇所に開口部を形成した第一プリプレグ２３を積層する。次に、前記第一プリプレグ２３の下に固体電解コンデンサ収納部５に対応した箇所に開口部を形成した第二樹脂シート２４を積層し、前記第二樹脂シート２４の下に固体電解コンデンサ収納部５に対応した箇所に開口部を形成した第二プリプレグ２５を積層する。最後に、前記第二プリプレグ２５の下に第三樹脂シート２６を形成して順次積層することにより、配線基板１を形成することができる。この開口部の形成方法は連続したシート状の材料にパンチング、レーザー加工法等を用いて形成することにより高速連続形成が可能であり、生産性に優れたものとすることができる。
【００５７】
次に、本発明の実施の形態１における固体電解コンデンサ内蔵配線基板の製造方法の一例について説明する。はじめに、配線基板１の製造方法について説明する。
【００５８】
まず、第一樹脂シート２２と第一プリプレグ２３に半導体チップ３を埋め込むための半導体チップ収納部４に対応する箇所にパンチング加工、レーザー加工、ドリル加工、放電加工等で開口部を形成する。次に第二樹脂シート２４と第二プリプレグ２５に固体電解コンデンサ２を埋め込むための固体電解コンデンサ収納部５に対応する箇所に同様にして開口部を形成する。
【００５９】
このとき、それぞれの各層に配線ラインを形成したいときには第一樹脂シート２２、第二樹脂シート２４、第三樹脂シート２６の各層に導体材料を用いてあらかじめ形成しておくことにより所望の配線ラインを各層に設けることもできる。このときの樹脂基板としてはＢＴ（ビスマレイミド−トリアジン）レジンまたはガラスエポキシ樹脂等からなる樹脂基板を用いることができる。なお、ＦＲ４、ＦＲ５、ガラスエポキシ樹脂などの補強材が含浸された基材などを用いることもできる。
【００６０】
また、これ以外にも熱膨張率を整合させるために、樹脂基板中にシリカ、アルミナなどの無機粒子を含有させてもよい。
【００６１】
次に、第一樹脂シート２２、第一プリプレグ２３、第二樹脂シート２４、第二プリプレグ２５、第三樹脂シート２６を準備して位置合わせをして積層し、熱プレスを行うことによって、熱硬化性接着剤である第一プリプレグ２３および第二プリプレグ２５を介して積層接着することにより配線基板１とする。また、配線基板１を直接レーザー加工、ドリル加工、放電加工等によって研削し、半導体チップ収納部４および固体電解コンデンサ収納部５を加工することも可能である。
【００６２】
また、固体電解コンデンサ収納部５を半導体チップ収納部４の面内に複数配置する場合、第二樹脂シート２４の開口部を第一樹脂シート２２の開口部形成箇所に複数形成することによって形成することができる。
【００６３】
また、半導体チップ収納部４および固体電解コンデンサ収納部５の側面に開口側が拡大するようなテーパーを設けるためには第一樹脂シート２２、第二樹脂シート２４への開口部を形成する時にテーパーを形成することもできる。
【００６４】
なお、配線基板１内に配線ライン２１を設ける場合、第一樹脂シート２２、第二樹脂シート２４、第三樹脂シート２６内に配線ライン２１と一致した箇所にスルホールを形成し、あらかじめ銅、銀等の導電性ペーストを充填しておき、積層後に電気的接続をとることができる。また、接続抵抗を下げるためにスルホール内壁を銅、銀等のめっきによって電極形成する方法も使用できる。
【００６５】
また、半導体チップ３と他の電子部品もしくは電源ラインが配線基板１を介して接続される場合、第二樹脂シート２４の半導体チップ３と接続するスルホール上に第二接続バンプ１８を形成することにより、半導体チップ３と配線ライン２１ａとの接続を行うことができる。第二接続バンプ１８は半田ボールや印刷したクリーム半田を溶融することにより形成可能である。また、めっきによって錫、銅、金等のバンプを形成することも可能であるし、金等の金属のワイヤーによってバンプ形成することもできる。固体電解コンデンサ２と他の電子部品もしくは電源と接続する固体電解コンデンサ収納部５の底面の第三接続バンプ１９も同様に形成し、上記と同様にして配線ライン２１ｂに接続することができる。
【００６６】
また、最終形態として固体電解コンデンサ収納部５の高さが少なくとも前記固体電解コンデンサ２の厚みより低い固体電解コンデンサ収納部５を形成する場合、第二樹脂シート２４を固体電解コンデンサ２の厚みより薄くすると良い。
【００６７】
さらに、半導体チップ３の上面が配線基板１の上面と一致した位置にしたい場合、第二樹脂シート２４と第一樹脂シート２２の厚みを固体電解コンデンサ２と半導体チップ３の厚みに一致させるように設計することも可能である。
【００６８】
半導体チップ３の上面が配線基板１の上面より少なくとも低い位置にしたい場合においても同様にして第二樹脂シート２４と第一樹脂シート２２の厚みを固体電解コンデンサ２と半導体チップ３の厚みよりも薄くなるよう設計することにより実現可能であり、以上のような構成方法により配線基板１を柔軟に設計対応することができる。
【００６９】
続いて、図１および図３に示すような固体電解コンデンサ２の製造方法について説明する。まず、片面がエッチング処理されたアルミニウム箔を弁金属シート体６として準備する。このアルミニウム箔は片面をマスキングしてエッチング処理することによって容易に得ることができる。次に弁金属シート体６の多孔質面の表面に誘電体被膜７を形成する。この誘電体被膜７としてはアルミニウム、タンタル、ニオブ等を化成液中で陽極酸化することにより片面に誘電体被膜７を形成することができる。
【００７０】
次に、弁金属シート体６の外周部の誘電体被膜７の上に第五絶縁部２７を形成する。続いて、弁金属シート体６の所定の位置に複数のスルホール１０を形成する。その後、スルホール１０の内壁及び弁金属シート体６の多孔質化されていない面に第一絶縁部１１を形成する。第一絶縁部１１の形成方法の一例としては誘電体被膜７側をレジストでマスクし絶縁性の樹脂を電着することによって形成することができ、形成プロセスが容易で膜厚の薄い絶縁膜を得ることができる。
【００７１】
次に、前記第五絶縁部２７の開口面の誘電体被膜７の上に固体電解質層８を形成する。この固体電解質層８の形成方法はポリピロールやポリチオフェン等のパイ電子共役高分子およびまたはこれ以外の導電性高分子を含む組成物を化学重合や電解重合、またはそれらを組み合わせて行うことができる。
【００７２】
その後、固体電解質層８の上の外周部に第六絶縁部２８を設ける。第六絶縁部２８は粘度１Ｐａ・ｓ以上の樹脂を使用することにより、塗布時に樹脂が流動しないため容量ばらつきを低減することが可能である。
【００７３】
次に、この第六絶縁部２８の開口面の固体電解質層８上に前記集電体層９を設ける。この集電体層９はカーボン微粒子の懸濁液、および銀ペーストを主成分とする導電性接着剤を用いて、カーボン層と銀ペースト層の積層構造とすることにより効率的に電荷を引き出すことが可能である。
【００７４】
続いて、スルホール１０内に集電体層９と接続されるスルホール電極１２を形成する。スルホール電極１２は集電体層９の形成と同時に形成することも可能である。集電体層９として銀ペーストを塗布する工程において、同時に銀ペーストをスルホール１０内に充填し硬化させスルホール電極１２を形成する。また、スルホール電極１２の抵抗を低減する手法としては、スルホール内壁に銅、金、銀等のめっきを施した後、銀ペーストを充填する方法や、スルホールをめっきによりフィリングする方法も用いることができる。
【００７５】
さらに、第一絶縁部１１の所定の位置にＹＡＧレーザー等の加工により開口部１３を形成する。そして、第一絶縁部１１の開口部１３の表出面に導電性接着剤もしくは電気めっき、無電解めっきのいずれかを用いて接続端子１４を形成した後、スルホール電極１２の表出面と接続端子１４の表面に第一接続バンプ１５を形成する。この第一接続バンプ１５は半田ボールや印刷したクリーム半田を溶融することにより形成可能である。また、めっきによって錫、銅、金等のバンプを形成することも可能であるし、金等の金属のワイヤーによってバンプ形成することもできる。
【００７６】
以上の構成であっても本発明に用いる固体電解コンデンサ２としては機能するが、信頼性と機械的強度をより向上させたい場合には固体電解コンデンサ２の周辺に外装３４を形成することが望ましい。その際、固体電解コンデンサ２の下面側と側面に外装３４を貫通するように引出電極２９を形成し、この引出電極２９を介して固体電解コンデンサ２の陽極と陰極と電気的に接続する第四接続バンプ３０を形成することもできる。このような方法により内蔵する固体電解コンデンサ２の完成品とすることができる。
【００７７】
次に、図１に示すように前記固体電解コンデンサ収納部５内に前記固体電解コンデンサ２を収容するが、この固体電解コンデンサ収納部５によって前記固体電解コンデンサ２を位置決めすることが可能である。前記固体電解コンデンサ２を収容後、リフロー等により固体電解コンデンサ２の第四接続バンプ３０と固体電解コンデンサ収納部５に形成した第三接続バンプ１９を接続するとともに、その他の電子部品もしくは電源ラインと電気的に接続することができる。
【００７８】
次に、固体電解コンデンサ２を固定するために、固体電解コンデンサ収納部５と固体電解コンデンサ２の間に第三絶縁部１６を形成する。この第三絶縁部１６の形成方法としてはディスペンサ等によって樹脂を流し込むことができる。
【００７９】
また、図２に示すように固体電解コンデンサ２の外装３４の周辺部に切り欠き部２０を形成しておくことで、固体電解コンデンサ２の収納方向を間違うことなく収納することができるとともに、下面と固体電解コンデンサ収納部５の上面の空間にも第三絶縁部１６を構成する樹脂などを流し込むことが可能である。この第三絶縁部１６としては熱硬化性樹脂、感光性樹脂、熱可塑性樹脂あるいはそれらの複合体を用いることができる。
【００８０】
なお、固体電解コンデンサ２の放熱を効率良く行うために第三絶縁部１６には無機フィラーを含有した樹脂がより望ましい。また無機フィラーとしてはアルミナ、マグネシア、カルシウム化合物およびケイ素化合物からなる無機粒子が挙げられる。それらは熱伝導性、線膨張係数などの特性を考慮して最適なものを選択することができる。続いて、前記半導体チップ収納部４内に前記半導体チップ３を収容する。この半導体チップ収納部４によって半導体チップ３を位置決めすることが可能である。この半導体チップ３を収容後、リフロー等により半導体チップ３の接続バンプと固体電解コンデンサ２の第一接続バンプ１５を接続することができる。
【００８１】
次に、半導体チップ３を固定するために、半導体チップ収納部４と半導体チップ３の間に第四絶縁部１７を形成する。その形成方法としては第三絶縁部１６と同様の方法で形成することが可能である。
【００８２】
なお、第三絶縁部１６および第四絶縁部１７の形成は同時に行っても良い。固体電解コンデンサ収納部５内に固体電解コンデンサ２を搭載し、さらに固体電解コンデンサ２上の半導体チップ収納部４に半導体チップ３を搭載して実装した後、第三絶縁部１６の形成方法と同様の手法で同時に形成することもできる。
【００８３】
また、固体電解コンデンサ２の外装３４にあらかじめ粗面化処理を施すこともできる。これにより、固体電解コンデンサ２と第三絶縁部１６または半導体チップ３と第四絶縁部１７との密着性がより高くなり、ヒートサイクル試験を実施しても、界面での絶縁部の剥離が発生することをより少なくすることができる。
【００８４】
以上のような固体電解コンデンサ内蔵配線基板を構成することにより、固体電解コンデンサ２を低応力で実装することが可能で、固体電解コンデンサ収納部５によって位置決めされた固体電解コンデンサ２を配置し、半導体チップ３を半導体チップ収納部４によって位置決めすることにより精度良く固体電解コンデンサ２の上に半導体チップ３を実装配置することができる小型・低背型の固体電解コンデンサ内蔵配線基板を提供することができる。
【００８５】
（実施の形態２）
本発明の実施の形態２および図８、図９により請求項２に記載の発明を説明する。図８は本発明の実施の形態２における固体電解コンデンサ内蔵配線基板の断面図であり、図９は固体電解コンデンサ２の要部拡大断面図である。但し、ここでは説明の便宜上固体電解コンデンサ内蔵配線基板の上面を決定しているだけで、本実施の形態２の固体電解コンデンサ内蔵配線基板の使用時において上面および下面は決定されるものではない。また、図は模式図であり、各位置を寸法的に正しく示したものではない。
【００８６】
図８の固体電解コンデンサ内蔵配線基板は、半導体チップ３を収納する半導体チップ収納部４および前記半導体チップ３に電荷を供給する固体電解コンデンサ２とを備えた配線基板１から構成されている。
【００８７】
本発明の実施の形態２における固体電解コンデンサ内蔵配線基板は実施の形態１の固体電解コンデンサ内蔵配線基板とほぼ同じ構成であるが、特に固体電解コンデンサ２の内部構造が異なる。
【００８８】
この固体電解コンデンサ収納部５に収納される固体電解コンデンサ２は図８、図９に示すように、少なくとも弁金属シート体６の片面に多孔質部を設け、この多孔質部の表面に誘電体被膜７、この誘電体被膜７上に固体電解質層８、この固体電解質層８上に集電体層９を設けて固体電解コンデンサ２の容量素子部を形成している（容量素子部とはコンデンサ機能を果たす基本的な構成要素を含んでいる。）。
【００８９】
このような固体電解コンデンサ２において、前記誘電体被膜７の上の所定の位置に前記固体電解質層８と前記集電体層９を貫通し複数の第二絶縁部３１を設け、前記集電体層９および前記第二絶縁部３１上に第一絶縁部１１を設ける。次に、前記第二絶縁部３１に弁金属シート体６まで渡って複数のビアホール３２を設け、前記ビアホール３２の中に前記弁金属シート体６と接続されるビアホール電極３３を設けている。
【００９０】
さらに、前記第一絶縁部１１の所定の位置に開口部１３を設け、前記開口部１３の上に接続端子１４を設け、この接続端子１４およびビアホール電極３３の表出面に第一接続バンプ１５を設けるように構成している。
【００９１】
このように固体電解コンデンサ２を上記の構成とすることにより、小型で高周波特性に優れ、かつ高密度実装を実現するとともに生産性にも優れたものとすることができる。加えて、本発明の実施の形態２で構成した固体電解コンデンサ２には最も短い距離で形成したビアホール電極３３に電流が流れることにより、低いインダクタンス成分の固体電解コンデンサ２とすることができるとともに、ビアホール電極３３と接続端子１４を交互に配置した電極構造とすることにより、電極から発生する磁界の発生を相殺する電極配置になり、固体電解コンデンサ２の持つリアクタンス成分を大幅に低減することができる。
【００９２】
また、配線基板１は所定の位置に半導体チップ収納部４を設け、前記半導体チップ収納部４の下面に少なくとも一つ以上の固体電解コンデンサ収納部５を設けている。
【００９３】
このように構成された固体電解コンデンサ内蔵配線基板は小型・低背化を実現するとともに、前記固体電解コンデンサ収納部５内に固体電解コンデンサ２を配置し、この固体電解コンデンサ２の上に半導体チップ収納部４を設けた構成とすることにより、前記半導体チップ収納部４に半導体チップ３を効率良く実装することができるという特徴を有している。
【００９４】
次に、本発明の実施の形態２における固体電解コンデンサ２の製造方法について図８、図９を用いて説明する。上記弁金属シート体６としては、片面をエッチングして多孔質化されたアルミニウム箔を用いることができる。次に、弁金属シート体６の多孔質面の表面に誘電体被膜７を形成する。上記誘電体被膜７としては、アルミニウムを化成液中で陽極酸化することにより片面に誘電体被膜７を形成して構成することができる。
【００９５】
その後、前記弁金属シート体６の外周部に第五絶縁部２７を実施の形態１にて説明した同様の方法で形成する。続いて、誘電体被膜７上の所定の位置に第二絶縁部３１を形成する。第二絶縁部３１の形成方法としては、絶縁樹脂のポッティング、感光性樹脂のパターニング等によって形成することができる。
【００９６】
このとき、後に形成する固体電解質層８と集電体層９が第二絶縁部３１によって貫通するように、少なくとも固体電解質層８と集電体層９の厚み以上形成する。
【００９７】
さらに、誘電体被膜７上に固体電解質層８を形成する。この固体電解質層８の上の外周部に第六絶縁部２８を形成し、第六絶縁部２８の内周部の開口面の固体電解質層８上に集電体層９を形成する。
【００９８】
次に、前記集電体層９および前記第二絶縁部３１上に第一絶縁部１１を形成する。例えば、第一絶縁部１１の形成方法としては絶縁性の塗料を印刷することによって形成することができ、容易な形成プロセスで絶縁膜を得ることができる。
【００９９】
その後、前記第二絶縁部３１に弁金属シート体６まで渡ってビアホール３２を形成する。ビアホール３２を形成する方法としてレーザー加工法、ドリル加工法、放電加工法のいずれかを用いることが可能である。
【０１００】
次に、ビアホール３２中に弁金属シート体６と接続されるビアホール電極３３を形成する。ビアホール電極３３は導電性ペーストをビアホール内に充填し硬化させビアホール電極３３を形成することができる。また、めっきによってビアホール電極３３を形成することもできる。
【０１０１】
次に、第一絶縁部１１の所定の位置にＹＡＧレーザー等の加工により開口部１３を形成する。その他の開口部１３の形成方法としては、第一絶縁部１１の形成前に集電体層９上の所定の位置に光硬化性樹脂などを用いてあらかじめレジストをパターニングしておき、第一絶縁部１１を形成した後レジストを剥離する方法によっても形成することが可能である。
【０１０２】
そして、第一絶縁部１１の開口部１３の表出面に導電性接着剤もしくは電気めっき、無電解めっきのいずれかを用いて接続端子１４を形成した後、接続端子１４およびビアホール電極３３の表出面に第一接続バンプ１５を形成する。
【０１０３】
このような方法により固体電解コンデンサ２を実施の形態１と同じ方法で作製した配線基板１に実装配置することによって、半導体チップ３と直接接続でき、高周波特性に優れ、陽極と陰極との距離を狭くすることが可能であるためリアクタンス成分のより小さい固体電解コンデンサ２を内蔵した固体電解コンデンサ内蔵配線基板を実現することができる。
【０１０４】
【発明の効果】
以上のように本発明の固体電解コンデンサ内蔵配線基板の構成およびその製造方法により、高周波特性に優れた薄型の固体電解コンデンサを低応力で配線基板に搭載し、接続バンプを介して半導体チップと直接電気的に接続することが可能となることから、小型低背で高周波特性に優れ、かつ高密度実装を実現するとともに生産性にも優れた固体電解コンデンサ内蔵配線基板およびその製造方法を実現することができる。
【図面の簡単な説明】
【図１】本発明の実施の形態１における固体電解コンデンサ内蔵配線基板の断面図
【図２】同上面図
【図３】同固体電解コンデンサの要部拡大断面図
【図４】同固体電解コンデンサ内蔵配線基板の断面図
【図５】同断面図
【図６】同固体電解コンデンサを実装した状態の上面図
【図７】同配線基板の断面図
【図８】本発明の実施の形態２における固体電解コンデンサ内蔵配線基板の断面図
【図９】同固体電解コンデンサの要部拡大断面図
【符号の説明】
１ 配線基板
２ 固体電解コンデンサ
３ 半導体チップ
４ 半導体チップ収納部
５ 固体電解コンデンサ収納部
６ 弁金属シート体
７ 誘電体被膜
８ 固体電解質層
９ 集電体層
１０ スルホール
１１ 第一絶縁部
１２ スルホール電極
１３ 開口部
１４ 接続端子
１５ 第一接続バンプ
１６ 第三絶縁部
１７ 第四絶縁部
１８ 第二接続バンプ
１９ 第三接続バンプ
２０ 切り欠き部
２１ａ 配線ライン
２１ｂ 配線ライン
２２ 第一樹脂シート
２３ 第一プリプレグ
２４ 第二樹脂シート
２５ 第二プリプレグ
２６ 第三樹脂シート
２７ 第五絶縁部
２８ 第六絶縁部
２９ 引出電極
３０ 第四接続バンプ
３１ 第二絶縁部
３２ ビアホール
３３ ビアホール電極
３４ 外装[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a wiring board on which electronic components such as a semiconductor chip are mounted, and more particularly to a wiring board with a built-in solid electrolytic capacitor having a built-in capacitor for supplying a charge to the semiconductor chip, and a method of manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a semiconductor chip used in information communication related equipment, a capacitor is arranged between a power supply and the semiconductor chip for stable supply of power.
[0003]
However, in a high-speed operation of 100 kHz or more, the fluctuation of the driving voltage of the semiconductor chip becomes very large. Therefore, for a capacitor used for this purpose, an equivalent series resistance (ESR) and an equivalent series inductance (ESL) which affect high frequency characteristics are reduced. A capacitor that can be reduced has been desired. Further, in order to operate the semiconductor chip at a higher frequency, the inductance due to the wiring between the capacitor and the semiconductor chip cannot be ignored, which causes a malfunction of the semiconductor chip and makes it difficult to stabilize the power supply. .
[0004]
In response to this demand, while devising the structure of the capacitor used for the power supply of the high-frequency semiconductor chip, placing this capacitor directly under the semiconductor chip and shortening the wiring length between the power supply line and the ground line, A mounting method for reducing inductance has been proposed.
[0005]
For example, as disclosed in Patent Document 1, as the structure of the capacitor, a matrix electrode having an anode terminal and a cathode terminal arranged in the same plane of an aluminum solid electrolytic capacitor is formed, and these electrode terminals and a semiconductor chip are connected. It has a structure in which connection is made via direct connection bumps. The specific structure of the solid electrolytic capacitor is that a plurality of through holes are provided on the anode foil of the solid electrolytic capacitor having a current collector layer formed on one side, and a through hole electrode connected to the current collector layer is formed in the through hole. An electrode terminal is formed at a predetermined position on the through-hole electrode and on the anode foil, and a matrix electrode in which the anode terminal and the cathode terminal are arranged in the same plane is formed.
[0006]
Further, as a configuration of the mounting method disclosed in Patent Document 2, a multilayer ceramic capacitor having a plurality of connection terminals is arranged in a recess provided in a wiring board having a plurality of connection terminals, and A structure of a wiring board with a capacitor in which a plurality of connection terminals and a plurality of connection terminals of the wiring board are flip-chip connected has been proposed.
[0007]
[Patent Document 1]
JP 2001-307955 A
[Patent Document 2]
JP 2000-349225 A
[0008]
[Problems to be solved by the invention]
However, since the above-mentioned solid electrolytic capacitor has a large number of connection bumps, it is difficult to mount it on a semiconductor chip with high accuracy. Therefore, a mounting structure with high accuracy and high productivity is required for the connection bumps of the semiconductor chip. Had been rare.
[0009]
In addition, it is difficult to use a thin multilayer ceramic capacitor in the wiring board with a capacitor from the viewpoint of the mechanical strength of the multilayer ceramic capacitor, so it is difficult to reduce the height of the wiring board with a capacitor. Was.
[0010]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-described conventional problems, and it is a small, low-profile solid formed by mounting a thin solid electrolytic capacitor with reduced loop inductance with low stress. An object of the present invention is to provide a wiring board with a built-in electrolytic capacitor and a method for manufacturing the same.
[0011]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the invention according to claim 1 of the present invention provides a semiconductor chip housing provided at least in a predetermined position and at least one or more solid electrolytic capacitor housings on a lower surface of the semiconductor chip housing. And a sheet-like solid electrolytic capacitor provided with a plurality of connection terminals on at least one surface is disposed in the solid electrolytic capacitor storage portion, and the solid electrolytic capacitor is provided on at least one surface of the valve metal sheet body with a porous portion. Provided, a dielectric film on the surface of the porous portion, a solid electrolyte layer on the dielectric film, a current collector layer on the solid electrolyte layer, a plurality of through holes provided in the valve metal sheet body, A first insulating portion provided on an inner wall of the through hole and a nonporous surface of the valve metal sheet, and a through hole connected to the current collector layer provided in the through hole A solid electrolytic capacitor built-in wiring having a configuration in which a pole, a connection terminal provided in an opening provided in a predetermined position of the first insulating portion, and a first connection bump provided on an exposed surface of the through-hole electrode and the connection terminal. Built-in solid electrolytic capacitor that can mount the solid electrolytic capacitor with almost no stress and that can be mounted with high precision by positioning the solid electrolytic capacitor housing and the semiconductor chip housing. A wiring board can be realized.
[0012]
According to a second aspect of the present invention, there is provided a wiring board provided with at least a semiconductor chip storage portion provided at a predetermined position and at least one solid electrolytic capacitor storage portion on a lower surface of the semiconductor chip storage portion, and at least one surface. A sheet-shaped solid electrolytic capacitor provided with a plurality of connection terminals is arranged in the solid electrolytic capacitor storage section, and the solid electrolytic capacitor penetrates the solid electrolyte layer and the current collector layer at predetermined positions on a dielectric film. A plurality of second insulating portions provided as a first insulating portion provided on the current collector layer and the second insulating portion, and a plurality of second insulating portions provided over the valve metal sheet body in the second insulating portion. A via hole, a via hole electrode provided in the via hole and connected to the valve metal sheet body, a connection terminal provided in an opening provided at a predetermined position of the first insulating portion, and a via hole electrode and And a first connection bump provided on an exposed surface of the connection terminal. A wiring board with a built-in solid electrolytic capacitor, wherein the distance between the anode and the cathode of the solid electrolytic capacitor can be reduced in addition to the function of claim 1. Therefore, a wiring board with a built-in solid electrolytic capacitor having a built-in solid electrolytic capacitor having a smaller reactance component can be realized.
[0013]
According to a third aspect of the present invention, there is provided the wiring board with a built-in solid electrolytic capacitor according to any one of the first and second aspects, wherein the solid electrolytic capacitor housing is provided in the plane of the semiconductor chip housing. Since it can be arranged directly below the chip, a wiring board with a built-in solid electrolytic capacitor having a smaller reactance component can be realized.
[0014]
According to a fourth aspect of the present invention, there is provided the wiring board with a built-in solid electrolytic capacitor according to any one of the first and second aspects, wherein a plurality of the solid electrolytic capacitor housings are provided in the surface of the semiconductor chip housing. It is possible to realize a wiring board with a built-in solid electrolytic capacitor on which a solid electrolytic capacitor having optimal performance can be arranged.
[0015]
According to a fifth aspect of the present invention, there is provided the wiring board with a built-in solid electrolytic capacitor according to any one of the first and second aspects, wherein the side surface of the semiconductor chip housing portion is tapered so as to expand toward the opening. Mounting defects can be reduced.
[0016]
According to a sixth aspect of the present invention, there is provided the wiring board with a built-in solid electrolytic capacitor according to any one of the first and second aspects, wherein the side surface of the solid electrolytic capacitor housing portion is tapered so as to expand toward the opening. It is possible to reduce the mounting failure of the capacitor.
[0017]
The invention according to claim 7 is the wiring board with a built-in solid electrolytic capacitor according to any one of claims 1 and 2, wherein the height of the solid electrolytic capacitor housing portion is at least lower than the thickness of the solid electrolytic capacitor. Since the first connection bump is located at a position higher than the bottom surface of the semiconductor chip housing portion, the semiconductor device can be reliably connected to the semiconductor chip.
[0018]
The invention according to claim 8 is the wiring board with a built-in solid electrolytic capacitor according to any one of claims 1 and 2, wherein a third insulating portion is provided between the solid electrolytic capacitor housing section and the solid electrolytic capacitor. The position of the capacitor can be fixed, and even if a stress originating from the solid electrolytic capacitor occurs, it can be alleviated by the third insulating portion.
[0019]
The invention according to claim 9 is the wiring board with a built-in solid electrolytic capacitor according to claim 8, wherein the third insulating portion is a resin material containing an inorganic filler. Heat can be efficiently dissipated.
[0020]
According to a tenth aspect of the present invention, there is provided the wiring board with a built-in solid electrolytic capacitor according to any one of the first and second aspects, wherein a fourth insulating portion is provided between the semiconductor chip housing portion and the semiconductor chip. The position can be fixed, and even if a stress originating from the semiconductor chip is generated, it can be alleviated by the fourth insulating portion.
[0021]
An eleventh aspect of the present invention is the wiring board with a built-in solid electrolytic capacitor according to the tenth aspect, wherein the fourth insulating portion is a resin material containing an inorganic filler. Can be performed efficiently.
[0022]
A twelfth aspect of the present invention is the wiring board with a built-in solid electrolytic capacitor according to any one of the first and second aspects, wherein the semiconductor chip and the solid electrolytic capacitor are connected through the first connection bump. Since the connection can be realized in the shortest time, it is possible to realize a further reduction in size and thickness and an improvement in high-frequency compatibility.
[0023]
A thirteenth aspect of the present invention is the wiring board with a built-in solid electrolytic capacitor according to any one of the first and second aspects, wherein the semiconductor chip housing portion is formed such that the upper surface of the semiconductor chip coincides with the upper surface of the wiring substrate. A flat wiring board with a built-in solid electrolytic capacitor without unevenness can be realized.
[0024]
According to a fourteenth aspect of the present invention, the wiring board with a built-in solid electrolytic capacitor according to any one of the first and second aspects, wherein the semiconductor chip housing portion is formed so that the upper surface of the semiconductor chip is lower than the upper surface of the wiring substrate. Thus, it is possible to realize a wiring board with a built-in solid electrolytic capacitor, on which a wiring or a component can be further mounted on a semiconductor chip.
[0025]
According to a fifteenth aspect of the present invention, the second connection bump is provided on the lower surface of the semiconductor chip storage part where the solid electrolytic capacitor storage part is not provided, and the semiconductor chip and the wiring board are connected via the second connection bump. The wiring board with a built-in solid electrolytic capacitor according to any one of claims 1 and 2, which is capable of connecting a semiconductor chip with another electronic component or a power supply.
[0026]
According to a sixteenth aspect of the present invention, the third connection bump is provided on the lower surface of the solid electrolytic capacitor housing portion, and the solid electrolytic capacitor and the wiring board are connected via the third connection bump. And a wiring board with a built-in solid electrolytic capacitor, which makes it possible to connect the solid electrolytic capacitor to another electronic component or power supply.
[0027]
According to a seventeenth aspect of the present invention, there is provided the wiring board with a built-in solid electrolytic capacitor according to any one of the first and second aspects, wherein the exterior is provided on the solid electrolytic capacitor, and the stress resistance and reliability can be improved.
[0028]
The invention according to claim 18 is the wiring board with a built-in solid electrolytic capacitor according to any one of claims 1 and 2, wherein a cutout portion is provided in an outer peripheral portion of an exterior of the solid electrolytic capacitor. The third insulating portion provided between the solid electrolytic capacitors can be easily formed.
[0029]
The invention according to claim 19 is the wiring board with a built-in solid electrolytic capacitor according to claim 17, wherein the surface of the exterior of the solid electrolytic capacitor is subjected to a surface roughening treatment, wherein the semiconductor chip and the fourth insulating portion or the solid electrolytic capacitor are provided. Adhesion between the solid electrolytic capacitor and the third insulating portion is increased, and a highly reliable wiring board with a built-in solid electrolytic capacitor can be obtained.
[0030]
According to a twentieth aspect of the present invention, there is provided the wiring board with a built-in solid electrolytic capacitor according to any one of the first and second aspects, wherein wiring lines are provided inside and on a surface layer of the wiring board. The semiconductor chip or the solid electrolytic capacitor can be connected to other electronic components or a power supply at a high density and in the shortest distance through the semiconductor device.
[0031]
The invention according to claim 21, wherein the wiring board has a first resin sheet and a first prepreg having an opening formed at a location corresponding to the semiconductor chip housing, and a solid electrolytic capacitor housing provided under the first prepreg. 3. The built-in solid electrolytic capacitor according to claim 1, comprising a second resin sheet and a second prepreg having openings formed at locations corresponding to the first and second prepregs, and a third resin sheet provided below the second prepreg. It is a wiring board, and can be configured as a wiring board with a built-in solid electrolytic capacitor having excellent productivity.
[0032]
In the invention according to claim 22, the step of forming the wiring board includes: forming a semiconductor chip housing portion in the first resin sheet; forming a solid electrolytic capacitor housing portion in the second resin sheet; Forming a semiconductor chip housing, forming a solid electrolytic capacitor housing in the second prepreg, forming a wiring line in the first resin sheet, the second resin sheet, the first prepreg and the second prepreg, A solid electrolytic capacitor comprising: a step of laminating and bonding one resin sheet, a first prepreg, a second resin sheet, a second prepreg, and a third resin sheet in this order; and a step of storing the solid electrolytic capacitor in the solid electrolytic capacitor storage section. This is a method for manufacturing a built-in wiring board, and can realize a method for manufacturing a wiring board with a built-in solid electrolytic capacitor having excellent productivity.
[0033]
The invention according to claim 23, wherein the step of forming the wiring line includes: a step of forming an electrode pattern and a through hole at predetermined positions of the first resin sheet, the second resin sheet, and the third resin sheet; A step of forming a through hole at a predetermined position of the second prepreg, a step of forming a conductor in the through hole, and a first resin sheet, a first prepreg, a second resin sheet, a second prepreg, and a third resin sheet in this order. 23. The method for producing a wiring board with a built-in solid electrolytic capacitor according to claim 22, comprising a step of laminating and thermosetting, wherein a wiring line is formed simultaneously with formation of an opening for forming a semiconductor chip housing section and a solid electrolytic capacitor housing section. Can be formed.
[0034]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a wiring board with a built-in solid electrolytic capacitor and a method of manufacturing the same according to the present invention will be described with reference to embodiments and drawings.
[0035]
(Embodiment 1)
Embodiment 1 of the present invention and FIGS. 1 to 7 will be used to explain the inventions described in claims 1 and 3 to 23.
[0036]
FIG. 1 is a sectional view of a wiring board with a built-in solid electrolytic capacitor according to Embodiment 1 of the present invention, and FIG. 2 is a top view of the same. FIG. 3 is an enlarged cross-sectional view of a main part of the solid electrolytic capacitor 2, FIGS. 4 and 5 are cross-sectional views of a wiring board with a built-in solid electrolytic capacitor having a different form from FIG. 1, and FIG. FIG. 7 is a top view of a wiring board with a built-in solid electrolytic capacitor not shown, and FIG. 7 is a cross-sectional view of the wiring board.
[0037]
The wiring board with a built-in solid electrolytic capacitor shown in FIG. 1 is provided with a semiconductor chip housing 4 and a solid electrolytic capacitor 2 for supplying electric charge to the semiconductor chip 3. In addition, a structure that can be easily mounted is realized. The wiring board with a built-in solid electrolytic capacitor has a semiconductor chip housing 4 provided at a predetermined position, at least one solid electrolytic capacitor housing 5 provided on the lower surface of the semiconductor chip housing 4, The solid electrolytic capacitor 2 is disposed inside the solid electrolytic capacitor 5 so that the semiconductor chip 3 can be mounted in the semiconductor chip housing 4 above the solid electrolytic capacitor 2.
[0038]
As shown in FIGS. 1 and 3, the solid electrolytic capacitor 2 is provided with a porous portion (not shown) on at least one surface of the valve metal sheet member 6, and a dielectric film 7 is provided on the surface of the porous portion. A solid electrolyte layer 8 is provided on the dielectric film 7 and a current collector layer 9 is provided on the solid electrolyte layer 8 to form a capacitor element of the solid electrolytic capacitor 2 (the capacitor element functions as a capacitor). Includes basic components.)
[0039]
Since this solid electrolytic capacitor 2 can use an aluminum foil, it can be a thin sheet-shaped capacitor element having a thickness of 100 to 200 μm.
[0040]
In such a solid electrolytic capacitor 2, a plurality of through holes 10 are provided in the valve metal sheet member 6, and a first insulating portion 11 is provided on the inner wall of the through hole 10 and the nonporous surface of the valve metal sheet member 6. ing. Further, a through-hole electrode 12 connected to the current collector layer 9 is provided in the through-hole 10, an opening 13 is provided at a predetermined position of the first insulating portion 11, and a connection terminal 14 is provided on the opening 13. And a first connection bump 15 is provided on the exposed portion of the connection terminal 14 and the through-hole electrode 12.
[0041]
Further, by arranging the through-hole electrodes 12 and the connection terminals 14 alternately, the direction of current flow inside the solid electrolytic capacitor 2 is reversed, so that the electrode arrangement cancels out the generated magnetic field. Since the series inductance (ESL) value can be minimized, it is compact, low-profile, has excellent high-frequency characteristics, and can realize high-density mounting on the surface of the wiring board 1 and has excellent productivity. Can be.
[0042]
Next, a method of mounting the solid electrolytic capacitor 2 on the wiring board 1 will be described.
[0043]
As shown in FIG. 1, by forming the solid electrolytic capacitor housing portion 5 slightly larger than the solid electrolytic capacitor 2 within the allowable dimensional range, it is possible to arrange the solid electrolytic capacitor housing portion 5 with accuracy within the allowable dimensional range. Similarly, by forming the semiconductor chip housing portion 4 to be slightly larger than the semiconductor chip 3 within the allowable size range, the solid electrolytic capacitor 2 and the semiconductor chip 3 can be efficiently mounted within the allowable size range. it can.
[0044]
Further, it is preferable that the side surfaces of the semiconductor chip housing portion 4 and the solid electrolytic capacitor housing portion 5 are provided with a taper so that the opening side is enlarged. By providing this taper, the semiconductor chip 3 and the solid electrolytic capacitor 2 can be mounted with high precision at the center of the semiconductor chip housing 4 and the solid electrolytic capacitor housing 5.
[0045]
Further, by providing the third insulating portion 16 between the solid electrolytic capacitor storage section 5 and the solid electrolytic capacitor 2, the position of the solid electrolytic capacitor 2 can be fixed. Further, even if a stress originating from the solid electrolytic capacitor 2 is generated, it can be alleviated by the third insulating portion 16. Also, by using a resin or the like containing an inorganic filler for the third insulating portion 16, it is possible to improve the thermal conductivity of the third insulating portion 16 and more efficiently radiate the heat of the solid electrolytic capacitor 2 and the semiconductor chip 3. It is. In addition, since a function such as control of the coefficient of linear expansion of the resin material constituting the third insulating portion 16 and improvement of heat resistance can be imparted by containing an inorganic filler, a low-stress and thin solid electrolytic capacitor 2 is used. Therefore, the thickness of the wiring board 1 can be reduced.
[0046]
Similarly, by forming the fourth insulating portion 17 between the semiconductor chip housing portion 4 and the semiconductor chip 3, the same effect as described above can be obtained.
[0047]
Further, by providing the upper surface of the semiconductor chip 3 sealed by the fourth insulating portion 17 so as to coincide with the upper surface of the wiring board 1 in the positional relationship between the semiconductor chip housing portion 4 and the semiconductor chip 3, a flat surface without unevenness is provided. A wiring board with a built-in solid electrolytic capacitor can be formed.
[0048]
Further, as shown in FIG. 4, by providing the semiconductor chip housing 4 so that the upper surface of the semiconductor chip 3 is at least lower than the upper surface of the wiring board 1, further electronic components can be mounted on the semiconductor chip 3. A layer or a wiring layer can be formed.
[0049]
Further, by making the height of the solid electrolytic capacitor housing 5 lower than the thickness of the solid electrolytic capacitor 2, the upper surface of the solid electrolytic capacitor 2 comes to a position higher than the bottom of the semiconductor chip housing 4. The semiconductor chips 3 arranged in the semiconductor device can be reliably connected.
[0050]
Next, as shown in FIG. 5, by arranging a plurality of solid electrolytic capacitor housings 5 in the surface of the semiconductor chip housing 4, it is possible to arrange a plurality of solid electrolytic capacitors 2 directly below the semiconductor chip 3. . Electronic components other than the solid electrolytic capacitor 2 can be mounted in the solid electrolytic capacitor housing 5.
[0051]
As shown in FIGS. 1 and 4, a method of connecting an electronic component or a wiring line other than the solid electrolytic capacitor 2 to the semiconductor chip 3 includes a lower surface of the semiconductor chip housing 4 where the solid electrolytic capacitor housing 5 is not provided. The semiconductor chip 3 and the wiring board 1 are connected via the second connection bumps 18 so that the semiconductor chip 3 and the wiring board 1 can be connected to the wiring line 21a.
[0052]
Also, a third connection bump 19 is provided on the lower surface of the solid electrolytic capacitor housing 5, and the solid electrolytic capacitor 2 and the wiring board 1 are connected to the wiring line 21b via the third connection bump 19, so that it can be connected to other electronic components. Connection with the solid electrolytic capacitor 2 can be enabled. By forming the wiring lines 21a and 21b as described above, a wiring board with a built-in solid electrolytic capacitor having a high-density mounting structure with high-density wiring can be realized.
[0053]
In addition, by providing the exterior 34 to the solid electrolytic capacitor 2, the stress resistance of the solid electrolytic capacitor 2 can be further improved, and the reliability such as heat resistance and moisture resistance can be further improved.
[0054]
In addition, as shown in FIG. 6, by forming the notch 20 on the outer peripheral portion of the exterior 34 of the solid electrolytic capacitor 2, the mounting direction of the solid electrolytic capacitor 2 can be accurately confirmed, and the notch 20 Resin 20 can be filled with resin, and third insulating portion 16 provided between solid electrolytic capacitor housing 5 and solid electrolytic capacitor 2 can be easily formed.
[0055]
Next, an example of the configuration of the wiring board 1 will be described with reference to FIG.
[0056]
As shown in FIG. 7, a first prepreg 23 having an opening formed at a location corresponding to the semiconductor chip storage section 4 under a first resin sheet 22 having an opening formed at a location corresponding to the semiconductor chip storage section 4. Are laminated. Next, a second resin sheet 24 having an opening formed at a position corresponding to the solid electrolytic capacitor housing section 5 is laminated below the first prepreg 23, and a solid electrolytic capacitor housing section is formed below the second resin sheet 24. The second prepreg 25 having openings formed at locations corresponding to No. 5 is laminated. Finally, the wiring board 1 can be formed by forming the third resin sheet 26 under the second prepreg 25 and sequentially stacking them. The opening can be formed by continuous punching, laser processing, or the like on a continuous sheet-like material, whereby high-speed continuous formation can be achieved, and productivity can be improved.
[0057]
Next, an example of a method for manufacturing the wiring board with a built-in solid electrolytic capacitor according to the first embodiment of the present invention will be described. First, a method for manufacturing the wiring board 1 will be described.
[0058]
First, an opening is formed by punching, laser processing, drilling, electric discharge machining, or the like at a position corresponding to the semiconductor chip housing portion 4 for embedding the semiconductor chip 3 in the first resin sheet 22 and the first prepreg 23. Next, an opening is formed in the same manner at a position corresponding to the solid electrolytic capacitor housing 5 for embedding the solid electrolytic capacitor 2 in the second resin sheet 24 and the second prepreg 25.
[0059]
At this time, when it is desired to form a wiring line on each layer, a desired wiring line can be formed by forming in advance a conductive material on each layer of the first resin sheet 22, the second resin sheet 24, and the third resin sheet 26. It can be provided in each layer. At this time, a resin substrate made of BT (bismaleimide-triazine) resin or glass epoxy resin can be used as the resin substrate. Note that a base material impregnated with a reinforcing material such as FR4, FR5, or a glass epoxy resin can also be used.
[0060]
In addition, in order to match the coefficient of thermal expansion, inorganic particles such as silica and alumina may be contained in the resin substrate.
[0061]
Next, the first resin sheet 22, the first prepreg 23, the second resin sheet 24, the second prepreg 25, and the third resin sheet 26 are prepared, aligned, laminated, and hot-pressed to perform heat pressing. The wiring board 1 is obtained by laminating and bonding via the first prepreg 23 and the second prepreg 25 which are curable adhesives. Further, it is also possible to directly grind the wiring board 1 by laser processing, drill processing, electric discharge processing or the like, and to process the semiconductor chip housing section 4 and the solid electrolytic capacitor housing section 5.
[0062]
When a plurality of the solid electrolytic capacitor housings 5 are arranged in the plane of the semiconductor chip housing 4, the openings of the second resin sheet 24 are formed by forming a plurality of openings in the openings of the first resin sheet 22. be able to.
[0063]
In order to form a taper on the side surface of the semiconductor chip housing portion 4 and the solid electrolytic capacitor housing portion 5 so that the opening side is enlarged, the taper is required when forming the openings to the first resin sheet 22 and the second resin sheet 24. It can also be formed.
[0064]
When the wiring lines 21 are provided in the wiring substrate 1, through holes are formed in the first resin sheet 22, the second resin sheet 24, and the third resin sheet 26 at locations corresponding to the wiring lines 21, and copper, silver, Or other conductive paste, and electrical connection can be made after lamination. Further, a method of forming an electrode by plating the inner wall of the through hole with copper, silver, or the like to reduce the connection resistance can also be used.
[0065]
When the semiconductor chip 3 is connected to another electronic component or power supply line via the wiring board 1, the second connection bumps 18 are formed on through holes of the second resin sheet 24 connected to the semiconductor chip 3. The connection between the semiconductor chip 3 and the wiring line 21a can be made. The second connection bumps 18 can be formed by melting solder balls or printed cream solder. Further, a bump of tin, copper, gold, or the like can be formed by plating, or a bump can be formed of a wire of metal, such as gold. The third connection bump 19 on the bottom surface of the solid electrolytic capacitor housing 5 for connecting the solid electrolytic capacitor 2 to another electronic component or power supply can be similarly formed and connected to the wiring line 21b in the same manner as described above.
[0066]
When the solid electrolytic capacitor housing 5 is formed as a final form in which the height of the solid electrolytic capacitor housing 5 is lower than at least the thickness of the solid electrolytic capacitor 2, the second resin sheet 24 is thinner than the thickness of the solid electrolytic capacitor 2. Good.
[0067]
Further, when it is desired to make the upper surface of the semiconductor chip 3 coincide with the upper surface of the wiring board 1, the thickness of the second resin sheet 24 and the first resin sheet 22 should be made equal to the thickness of the solid electrolytic capacitor 2 and the semiconductor chip 3. It is also possible to design.
[0068]
Similarly, even when the upper surface of the semiconductor chip 3 is to be at least lower than the upper surface of the wiring board 1, the thickness of the second resin sheet 24 and the first resin sheet 22 is smaller than the thickness of the solid electrolytic capacitor 2 and the semiconductor chip 3. This can be realized by designing so that the wiring board 1 can be flexibly designed and supported by the above configuration method.
[0069]
Subsequently, a method of manufacturing the solid electrolytic capacitor 2 as shown in FIGS. 1 and 3 will be described. First, an aluminum foil having one surface etched is prepared as a valve metal sheet body 6. This aluminum foil can be easily obtained by masking one side and etching. Next, a dielectric coating 7 is formed on the porous surface of the valve metal sheet 6. The dielectric film 7 can be formed on one surface by anodizing aluminum, tantalum, niobium, or the like in a chemical conversion solution.
[0070]
Next, a fifth insulating portion 27 is formed on the dielectric film 7 on the outer peripheral portion of the valve metal sheet member 6. Subsequently, a plurality of through holes 10 are formed at predetermined positions of the valve metal sheet member 6. After that, the first insulating portion 11 is formed on the inner wall of the through hole 10 and the nonporous surface of the valve metal sheet member 6. As an example of a method of forming the first insulating portion 11, the first insulating portion 11 can be formed by masking the dielectric film 7 side with a resist and electrodepositing an insulating resin. Obtainable.
[0071]
Next, the solid electrolyte layer 8 is formed on the dielectric film 7 on the opening surface of the fifth insulating portion 27. This solid electrolyte layer 8 can be formed by chemical polymerization, electrolytic polymerization, or a combination thereof using a composition containing a pi-electron conjugated polymer such as polypyrrole or polythiophene and other conductive polymers.
[0072]
Thereafter, a sixth insulating portion 28 is provided on the outer peripheral portion on the solid electrolyte layer 8. By using a resin having a viscosity of 1 Pa · s or more for the sixth insulating portion 28, the resin does not flow at the time of application, so that the capacity variation can be reduced.
[0073]
Next, the current collector layer 9 is provided on the solid electrolyte layer 8 on the opening surface of the sixth insulating portion 28. The current collector layer 9 has a laminated structure of a carbon layer and a silver paste layer by using a suspension of carbon fine particles and a conductive adhesive mainly containing silver paste to efficiently extract electric charges. Is possible.
[0074]
Subsequently, a through-hole electrode 12 connected to the current collector layer 9 is formed in the through-hole 10. The through-hole electrode 12 can be formed simultaneously with the formation of the current collector layer 9. In the step of applying the silver paste as the current collector layer 9, the silver paste is simultaneously filled in the through hole 10 and cured to form the through hole electrode 12. Further, as a method of reducing the resistance of the through-hole electrode 12, a method of filling the inner wall of the through-hole with copper, gold, silver or the like and then filling with a silver paste, or a method of filling the through-hole by plating can be used. .
[0075]
Further, an opening 13 is formed at a predetermined position of the first insulating portion 11 by processing with a YAG laser or the like. Then, a connection terminal 14 is formed on the exposed surface of the opening 13 of the first insulating portion 11 using a conductive adhesive, electroplating, or electroless plating, and then the exposed surface of the through-hole electrode 12 and the connection terminal 14 are formed. The first connection bumps 15 are formed on the surface of the substrate. The first connection bumps 15 can be formed by melting solder balls or printed cream solder. Further, a bump of tin, copper, gold, or the like can be formed by plating, or a bump can be formed of a wire of metal, such as gold.
[0076]
Even with the above configuration, it functions as the solid electrolytic capacitor 2 used in the present invention, but it is desirable to form the exterior 34 around the solid electrolytic capacitor 2 in order to further improve reliability and mechanical strength. . At this time, the extraction electrode 29 is formed on the lower surface side and the side surface of the solid electrolytic capacitor 2 so as to penetrate the outer package 34, and the fourth electrode electrically connected to the anode and the cathode of the solid electrolytic capacitor 2 via the extraction electrode 29. The connection bump 30 can also be formed. By such a method, the completed solid electrolytic capacitor 2 can be obtained.
[0077]
Next, as shown in FIG. 1, the solid electrolytic capacitor 2 is housed in the solid electrolytic capacitor housing 5. The solid electrolytic capacitor 2 can be positioned by the solid electrolytic capacitor housing 5. After accommodating the solid electrolytic capacitor 2, the fourth connection bump 30 of the solid electrolytic capacitor 2 is connected to the third connection bump 19 formed on the solid electrolytic capacitor housing 5 by reflow or the like, and is connected to another electronic component or power supply line. Can be electrically connected.
[0078]
Next, in order to fix the solid electrolytic capacitor 2, a third insulating portion 16 is formed between the solid electrolytic capacitor housing 5 and the solid electrolytic capacitor 2. As a method for forming the third insulating portion 16, a resin can be poured by a dispenser or the like.
[0079]
Further, as shown in FIG. 2, by forming the cutout portion 20 in the peripheral portion of the exterior 34 of the solid electrolytic capacitor 2, the solid electrolytic capacitor 2 can be stored without making a mistake in the storage direction, and It is also possible to pour the resin or the like constituting the third insulating portion 16 into the space on the upper surface of the solid electrolytic capacitor housing 5. As the third insulating portion 16, a thermosetting resin, a photosensitive resin, a thermoplastic resin, or a composite thereof can be used.
[0080]
In order to efficiently radiate the heat of the solid electrolytic capacitor 2, the third insulating portion 16 is more preferably made of a resin containing an inorganic filler. Examples of the inorganic filler include inorganic particles made of alumina, magnesia, a calcium compound, and a silicon compound. They can be selected optimally in consideration of properties such as thermal conductivity and linear expansion coefficient. Subsequently, the semiconductor chip 3 is housed in the semiconductor chip housing 4. The semiconductor chip 3 can be positioned by the semiconductor chip housing 4. After housing the semiconductor chip 3, the connection bumps of the semiconductor chip 3 and the first connection bumps 15 of the solid electrolytic capacitor 2 can be connected by reflow or the like.
[0081]
Next, a fourth insulating part 17 is formed between the semiconductor chip housing part 4 and the semiconductor chip 3 to fix the semiconductor chip 3. The third insulating portion 16 can be formed in the same manner as the third insulating portion 16.
[0082]
Note that the formation of the third insulating portion 16 and the fourth insulating portion 17 may be performed simultaneously. After mounting the solid electrolytic capacitor 2 in the solid electrolytic capacitor housing 5 and further mounting and mounting the semiconductor chip 3 in the semiconductor chip housing 4 on the solid electrolytic capacitor 2, the same as the method of forming the third insulating portion 16 It can also be formed simultaneously by the method described above.
[0083]
Further, the outer surface 34 of the solid electrolytic capacitor 2 may be subjected to a roughening treatment in advance. As a result, the adhesion between the solid electrolytic capacitor 2 and the third insulating portion 16 or between the semiconductor chip 3 and the fourth insulating portion 17 becomes higher, and even if a heat cycle test is performed, the insulating portion is separated at the interface. To do less.
[0084]
By configuring the wiring board with a built-in solid electrolytic capacitor as described above, the solid electrolytic capacitor 2 can be mounted with low stress. By positioning the chip 3 by the semiconductor chip housing 4, it is possible to provide a small-sized and low-profile wiring board with a built-in solid electrolytic capacitor that can accurately mount and arrange the semiconductor chip 3 on the solid electrolytic capacitor 2. .
[0085]
(Embodiment 2)
The second embodiment of the present invention will be described with reference to FIGS. 8 and 9. FIG. 8 is a cross-sectional view of a wiring board with a built-in solid electrolytic capacitor according to Embodiment 2 of the present invention, and FIG. 9 is an enlarged cross-sectional view of a main part of solid electrolytic capacitor 2. However, only the upper surface of the wiring board with a built-in solid electrolytic capacitor is determined here for convenience of description, and the upper and lower surfaces are not determined when the wiring board with a built-in solid electrolytic capacitor of the second embodiment is used. In addition, the figure is a schematic view, and does not show each position correctly in dimensions.
[0086]
The wiring board with a built-in solid electrolytic capacitor shown in FIG. 8 includes a wiring board 1 having a semiconductor chip housing part 4 for housing a semiconductor chip 3 and a solid electrolytic capacitor 2 for supplying electric charges to the semiconductor chip 3.
[0087]
The wiring board with a built-in solid electrolytic capacitor according to the second embodiment of the present invention has substantially the same configuration as the wiring board with a built-in solid electrolytic capacitor of the first embodiment, but the internal structure of solid electrolytic capacitor 2 is particularly different.
[0088]
As shown in FIGS. 8 and 9, the solid electrolytic capacitor 2 accommodated in the solid electrolytic capacitor accommodating portion 5 has a porous portion provided on at least one surface of the valve metal sheet member 6, and a dielectric material is provided on the surface of the porous portion. The capacitive element of the solid electrolytic capacitor 2 is formed by providing a coating 7, a solid electrolyte layer 8 on the dielectric coating 7, and a current collector layer 9 on the solid electrolyte layer 8 (the capacitor element is a capacitor). It contains the basic components that perform the function.)
[0089]
In such a solid electrolytic capacitor 2, a plurality of second insulating portions 31 are provided at predetermined positions on the dielectric film 7, penetrating the solid electrolyte layer 8 and the current collector layer 9, and The first insulating part 11 is provided on the layer 9 and the second insulating part 31. Next, a plurality of via holes 32 are provided in the second insulating portion 31 over the valve metal sheet member 6, and a via hole electrode 33 connected to the valve metal sheet member 6 is provided in the via hole 32.
[0090]
Further, an opening 13 is provided at a predetermined position of the first insulating portion 11, a connection terminal 14 is provided on the opening 13, and a first connection bump 15 is provided on the exposed surfaces of the connection terminal 14 and the via-hole electrode 33. It is configured to be provided.
[0091]
By thus configuring the solid electrolytic capacitor 2 as described above, it is possible to achieve compactness, excellent high-frequency characteristics, high-density mounting, and excellent productivity. In addition, a current flows through the via hole electrode 33 formed at the shortest distance in the solid electrolytic capacitor 2 configured in Embodiment 2 of the present invention, so that the solid electrolytic capacitor 2 having a low inductance component can be obtained. By using an electrode structure in which the via-hole electrodes 33 and the connection terminals 14 are alternately arranged, the electrode arrangement cancels the generation of a magnetic field generated from the electrodes, and the reactance component of the solid electrolytic capacitor 2 can be significantly reduced. .
[0092]
The wiring board 1 has a semiconductor chip housing 4 at a predetermined position, and at least one solid electrolytic capacitor housing 5 on the lower surface of the semiconductor chip housing 4.
[0093]
The wiring board with a built-in solid electrolytic capacitor configured in this way realizes a small size and a low profile, and the solid electrolytic capacitor 2 is arranged in the solid electrolytic capacitor housing 5, and a semiconductor chip is mounted on the solid electrolytic capacitor 2. The configuration in which the storage portion 4 is provided has a feature that the semiconductor chip 3 can be efficiently mounted in the semiconductor chip storage portion 4.
[0094]
Next, a method for manufacturing solid electrolytic capacitor 2 according to Embodiment 2 of the present invention will be described with reference to FIGS. As the valve metal sheet member 6, an aluminum foil that has been made porous by etching one surface can be used. Next, a dielectric coating 7 is formed on the porous surface of the valve metal sheet 6. The dielectric film 7 can be formed by forming aluminum on one surface by anodizing aluminum in a chemical conversion solution.
[0095]
Thereafter, a fifth insulating portion 27 is formed on the outer peripheral portion of the valve metal sheet member 6 by the same method as described in the first embodiment. Subsequently, a second insulating portion 31 is formed at a predetermined position on the dielectric film 7. The second insulating portion 31 can be formed by potting an insulating resin, patterning a photosensitive resin, or the like.
[0096]
At this time, at least the thickness of the solid electrolyte layer 8 and the current collector layer 9 is formed so that the solid electrolyte layer 8 and the current collector layer 9 to be formed later are penetrated by the second insulating portion 31.
[0097]
Further, a solid electrolyte layer 8 is formed on the dielectric film 7. The sixth insulating portion 28 is formed on the outer peripheral portion of the solid electrolyte layer 8, and the current collector layer 9 is formed on the solid electrolyte layer 8 on the opening surface of the inner peripheral portion of the sixth insulating portion 28.
[0098]
Next, the first insulating part 11 is formed on the current collector layer 9 and the second insulating part 31. For example, the first insulating portion 11 can be formed by printing an insulating paint, and an insulating film can be obtained by an easy forming process.
[0099]
Thereafter, a via hole 32 is formed in the second insulating portion 31 so as to extend to the valve metal sheet member 6. As a method for forming the via hole 32, any of a laser processing method, a drill processing method, and an electric discharge processing method can be used.
[0100]
Next, a via hole electrode 33 connected to the valve metal sheet 6 is formed in the via hole 32. The via-hole electrode 33 can be formed by filling a conductive paste into the via-hole and curing the via-hole electrode 33. Further, the via-hole electrode 33 can be formed by plating.
[0101]
Next, an opening 13 is formed at a predetermined position of the first insulating portion 11 by processing with a YAG laser or the like. As another method for forming the opening 13, before forming the first insulating portion 11, a resist is patterned in advance at a predetermined position on the current collector layer 9 using a photocurable resin or the like, and the first insulating portion 11 is formed. It can also be formed by a method of removing the resist after the formation of the portion 11.
[0102]
Then, after forming the connection terminal 14 on the exposed surface of the opening 13 of the first insulating portion 11 using a conductive adhesive, electroplating, or electroless plating, the exposed surface of the connection terminal 14 and the via-hole electrode 33 are formed. Then, the first connection bumps 15 are formed.
[0103]
By mounting and disposing the solid electrolytic capacitor 2 on the wiring board 1 manufactured by the same method as in the first embodiment by such a method, it can be directly connected to the semiconductor chip 3, has excellent high frequency characteristics, and has a long distance between the anode and the cathode. Since the width can be reduced, a wiring board with a built-in solid electrolytic capacitor incorporating the solid electrolytic capacitor 2 having a smaller reactance component can be realized.
[0104]
【The invention's effect】
As described above, according to the configuration of the wiring board with a built-in solid electrolytic capacitor of the present invention and the method for manufacturing the same, a thin solid electrolytic capacitor having excellent high-frequency characteristics is mounted on the wiring board with low stress, and directly connected to the semiconductor chip via the connection bump. To realize a wiring board with a built-in solid electrolytic capacitor and a method of manufacturing the same that are compact, low-profile, have excellent high-frequency characteristics, realize high-density mounting, and are also excellent in productivity because they can be electrically connected. Can be.
[Brief description of the drawings]
FIG. 1 is a sectional view of a wiring board with a built-in solid electrolytic capacitor according to a first embodiment of the present invention.
FIG. 2 is a top view of the same.
FIG. 3 is an enlarged sectional view of a main part of the solid electrolytic capacitor.
FIG. 4 is a sectional view of the wiring board with a built-in solid electrolytic capacitor.
FIG. 5 is a sectional view of the same.
FIG. 6 is a top view showing a state where the solid electrolytic capacitor is mounted.
FIG. 7 is a sectional view of the wiring board.
FIG. 8 is a sectional view of a wiring board with a built-in solid electrolytic capacitor according to a second embodiment of the present invention.
FIG. 9 is an enlarged sectional view of a main part of the solid electrolytic capacitor.
[Explanation of symbols]
1 Wiring board
2 Solid electrolytic capacitors
3 Semiconductor chip
4 Semiconductor chip storage
5 Solid electrolytic capacitor storage
6 Valve metal sheet
7 Dielectric coating
8 Solid electrolyte layer
9 Current collector layer
10 Through Hole
11 First insulation part
12 Through-hole electrode
13 Opening
14 Connection terminal
15 First connection bump
16 Third insulation
17 Fourth insulating part
18 Second connection bump
19 Third connection bump
20 Notch
21a Wiring line
21b Wiring line
22 First resin sheet
23 first prepreg
24 Second resin sheet
25 Second prepreg
26 Third resin sheet
27 Fifth insulation part
28 Sixth insulating part
29 Extraction electrode
30 Fourth connection bump
31 Second insulation part
32 Via Hole
33 Via hole electrode
34 Exterior

Claims (23)

少なくとも所定の位置に設けた半導体チップ収納部と前記半導体チップ収納部の下面に少なくとも一つ以上の固体電解コンデンサ収納部とを設けた配線基板と、少なくとも片面に複数の接続端子を設けたシート状の固体電解コンデンサを前記固体電解コンデンサ収納部に配置し、前記固体電解コンデンサが少なくとも弁金属シート体の片面に多孔質部を設け、この多孔質部の表面に誘電体被膜、この誘電体被膜上に固体電解質層、この固体電解質層上に集電体層を設け、前記弁金属シート体に設けた複数のスルホールと、このスルホールの内壁及び弁金属シート体の多孔質化されていない面に設けた第一絶縁部と、前記スルホール内に設けた前記集電体層と接続されるスルホール電極と、前記第一絶縁部の所定の位置に設けた開口部に設けた接続端子と、前記スルホール電極と前記接続端子の表出面に第一接続バンプを設けた構成とした固体電解コンデンサを内蔵した固体電解コンデンサ内蔵配線基板。A wiring board having at least a semiconductor chip storage portion provided at a predetermined position and at least one or more solid electrolytic capacitor storage portions on a lower surface of the semiconductor chip storage portion, and a sheet having at least one connection terminal provided with a plurality of connection terminals; The solid electrolytic capacitor is disposed in the solid electrolytic capacitor storage portion, the solid electrolytic capacitor has a porous portion provided on at least one surface of the valve metal sheet body, and a dielectric film is formed on the surface of the porous portion. A solid electrolyte layer, a current collector layer provided on the solid electrolyte layer, a plurality of through holes provided in the valve metal sheet, provided on the inner wall of the through hole and on the nonporous surface of the valve metal sheet. A first insulating portion, a through-hole electrode connected to the current collector layer provided in the through-hole, and an opening provided at a predetermined position of the first insulating portion. And connection terminals, the through hole electrode and the solid electrolytic capacitor built-in wiring board with a built-in solid electrolytic capacitor has a structure in which a first connection bumps exposed surface of the connection terminal. 少なくとも所定の位置に設けた半導体チップ収納部と前記半導体チップ収納部の下面に少なくとも一つ以上の固体電解コンデンサ収納部とを設けた配線基板と、少なくとも片面に複数の接続端子を設けたシート状の固体電解コンデンサを前記固体電解コンデンサ収納部に配置し、前記固体電解コンデンサが前記誘電体被膜上の所定の位置に前記固体電解質層と前記集電体層を貫通して設けた複数の第二絶縁部と、前記集電体層および前記第二絶縁部上に設けた第一絶縁部と、前記第二絶縁部に弁金属シート体まで渡って設けた複数のビアホールと、このビアホールの中に設けた前記弁金属シート体と接続されるビアホール電極と、前記第一絶縁部の所定の位置に設けた開口部に設けた接続端子と、前記ビアホール電極および前記接続端子の表出面に設けた第一接続バンプとで構成した固体電解コンデンサ内蔵配線基板。A wiring board having at least a semiconductor chip storage portion provided at a predetermined position and at least one or more solid electrolytic capacitor storage portions on a lower surface of the semiconductor chip storage portion, and a sheet having at least one connection terminal provided with a plurality of connection terminals; A plurality of second solid electrolytic capacitors are disposed in the solid electrolytic capacitor housing portion, and a plurality of second solid electrolytic capacitors are provided at predetermined positions on the dielectric film by penetrating the solid electrolytic layer and the current collector layer. An insulating portion, a first insulating portion provided on the current collector layer and the second insulating portion, a plurality of via holes provided over the valve insulating sheet body in the second insulating portion, and A table of the via-hole electrode connected to the provided valve metal sheet body, a connection terminal provided in an opening provided at a predetermined position of the first insulating portion, and a table of the via-hole electrode and the connection terminal. The solid electrolytic capacitor built-in wiring board that is constituted by a first connection bump provided on the surface. 固体電解コンデンサ収納部を半導体チップ収納部の面内に設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。3. The wiring board with a built-in solid electrolytic capacitor according to claim 1, wherein the solid electrolytic capacitor housing is provided in a plane of the semiconductor chip housing. 固体電解コンデンサ収納部を半導体チップ収納部の面内に複数設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。The wiring board with a built-in solid electrolytic capacitor according to claim 1 or 2, wherein a plurality of the solid electrolytic capacitor housings are provided in the plane of the semiconductor chip housing. 半導体チップ収納部の側面が開口側に拡大するようにテーパーを設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。3. The wiring board with a built-in solid electrolytic capacitor according to claim 1, wherein a taper is provided so that a side surface of the semiconductor chip housing portion expands toward the opening. 固体電解コンデンサ収納部の側面が開口側に拡大するようにテーパーを設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。3. The wiring board with a built-in solid electrolytic capacitor according to claim 1, wherein a taper is provided so that a side surface of the solid electrolytic capacitor housing portion expands toward the opening side. 固体電解コンデンサ収納部の高さを少なくとも固体電解コンデンサの厚みより低くした請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。3. The wiring board with a built-in solid electrolytic capacitor according to claim 1, wherein the height of the solid electrolytic capacitor housing portion is at least lower than the thickness of the solid electrolytic capacitor. 固体電解コンデンサ収納部と固体電解コンデンサ間の間に第三絶縁部を設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。3. The wiring board with a built-in solid electrolytic capacitor according to claim 1, wherein a third insulating portion is provided between the solid electrolytic capacitor housing portion and the solid electrolytic capacitor. 第三絶縁部が無機フィラーを含有した樹脂材料である請求項８に記載の固体電解コンデンサ内蔵配線基板。9. The wiring board with a built-in solid electrolytic capacitor according to claim 8, wherein the third insulating portion is a resin material containing an inorganic filler. 半導体チップ収納部と半導体チップ間の間に第四絶縁部を設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。3. The wiring board with a built-in solid electrolytic capacitor according to claim 1, wherein a fourth insulating portion is provided between the semiconductor chip housing portion and the semiconductor chip. 第四絶縁部が無機フィラーを含有した樹脂材料である請求項１０に記載の固体電解コンデンサ内蔵配線基板。The wiring board with a built-in solid electrolytic capacitor according to claim 10, wherein the fourth insulating portion is a resin material containing an inorganic filler. 半導体チップと固体電解コンデンサとを第一接続バンプを介して接続してなる請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。3. The wiring board with a built-in solid electrolytic capacitor according to claim 1, wherein the semiconductor chip and the solid electrolytic capacitor are connected via a first connection bump. 半導体チップの上面が配線基板の上面と一致するように半導体チップ収納部を形成した請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。3. The wiring board with a built-in solid electrolytic capacitor according to claim 1, wherein the semiconductor chip housing portion is formed so that an upper surface of the semiconductor chip coincides with an upper surface of the wiring board. 半導体チップの上面が配線基板の面よりも低い位置になるように半導体チップ収納部を形成した請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。3. The wiring board with a built-in solid electrolytic capacitor according to claim 1, wherein the semiconductor chip housing portion is formed such that an upper surface of the semiconductor chip is lower than a surface of the wiring board. 固体電解コンデンサ収納部が設けられていない半導体チップ収納部の下面に第二接続バンプを設け、半導体チップと配線基板が第二接続バンプを介して接続するように構成した請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。3. The semiconductor device according to claim 1, wherein a second connection bump is provided on a lower surface of the semiconductor chip housing portion where the solid electrolytic capacitor housing portion is not provided, and the semiconductor chip and the wiring board are connected via the second connection bump. A wiring board with a built-in solid electrolytic capacitor according to any of the above. 固体電解コンデンサ収納部の下面に第三接続バンプを設け、固体電解コンデンサと配線基板が第三接続バンプを介して接続した請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。The wiring board with a built-in solid electrolytic capacitor according to claim 1, wherein a third connecting bump is provided on a lower surface of the solid electrolytic capacitor housing portion, and the solid electrolytic capacitor and the wiring board are connected via the third connecting bump. 固体電解コンデンサに外装を設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。The wiring board with a built-in solid electrolytic capacitor according to claim 1, wherein an exterior is provided on the solid electrolytic capacitor. 固体電解コンデンサの外装の外周部に切り欠き部を設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。3. The wiring board with a built-in solid electrolytic capacitor according to claim 1, wherein a cutout portion is provided on an outer peripheral portion of an exterior of the solid electrolytic capacitor. 固体電解コンデンサの外装の表面に粗面化処理を施した請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。The wiring board with a built-in solid electrolytic capacitor according to claim 1, wherein a surface of an exterior of the solid electrolytic capacitor is subjected to a roughening treatment. 配線基板の内部および表層に配線ラインを設けた請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。3. The wiring board with a built-in solid electrolytic capacitor according to claim 1, wherein wiring lines are provided inside and on a surface layer of the wiring board. 配線基板が、半導体チップ収納部に対応した箇所に開口部を形成した第一樹脂シートおよび第一プリプレグと、前記第一プリプレグの下に設けた固体電解コンデンサ収納部に対応した箇所に開口部を形成した第二樹脂シートおよび第二プリプレグと、前記第二プリプレグの下に設けた第三樹脂シートとからなる請求項１または２のいずれかに記載の固体電解コンデンサ内蔵配線基板。The wiring board has a first resin sheet and a first prepreg having an opening formed at a location corresponding to the semiconductor chip housing, and an opening at a location corresponding to the solid electrolytic capacitor housing provided under the first prepreg. 3. The wiring board with a built-in solid electrolytic capacitor according to claim 1, comprising a formed second resin sheet and a second prepreg, and a third resin sheet provided below the second prepreg. 配線基板を形成する工程が、第一樹脂シートに半導体チップ収納部を形成し、第二樹脂シートに固体電解コンデンサ収納部を形成する工程と、第一プリプレグに半導体チップ収納部を形成し、第二プリプレグに固体電解コンデンサ収納部を形成する工程と、第一樹脂シート、第二樹脂シート、第一プリプレグおよび第二プリプレグに配線ラインを形成する工程と、第一樹脂シート、第一プリプレグ、第二樹脂シート、第二プリプレグ、第三樹脂シートの順に積層して接着する工程と、固体電解コンデンサ収納部に固体電解コンデンサを収納する工程とからなる固体電解コンデンサ内蔵配線基板の製造方法。Forming a wiring board, forming a semiconductor chip housing portion on the first resin sheet, forming a solid electrolytic capacitor housing portion on the second resin sheet, forming a semiconductor chip housing portion on the first prepreg, A step of forming a solid electrolytic capacitor storage portion in the two prepregs, a step of forming wiring lines in the first resin sheet, the second resin sheet, the first prepreg and the second prepreg, and a first resin sheet, a first prepreg, A method for manufacturing a wiring board with a built-in solid electrolytic capacitor, comprising the steps of laminating and bonding two resin sheets, a second prepreg, and a third resin sheet in this order, and storing the solid electrolytic capacitor in a solid electrolytic capacitor storage section. 配線ラインを形成する工程が、第一樹脂シート、第二樹脂シート、第三樹脂シートの所定の位置に電極パターンとスルホールを形成する工程と、第一プリプレグ、第二プリプレグの所定の位置にスルホールを形成する工程と、スルホール内に導電体を形成する工程と、第一樹脂シート、第一プリプレグ、第二樹脂シート、第二プリプレグ、第三樹脂シートの順に積層し熱硬化する工程とからなる請求項２２に記載の固体電解コンデンサ内蔵配線基板の製造方法。The step of forming a wiring line includes the steps of forming an electrode pattern and a through hole at a predetermined position of the first resin sheet, the second resin sheet, and the third resin sheet; and forming a through hole at a predetermined position of the first prepreg and the second prepreg. Forming a conductor, forming a conductor in the through hole, and laminating and thermosetting a first resin sheet, a first prepreg, a second resin sheet, a second prepreg, and a third resin sheet in this order. A method for manufacturing the wiring board with a built-in solid electrolytic capacitor according to claim 22.
JP2003004448A 2003-01-10 2003-01-10 Wiring board with built-in solid state electrolytic capacitor and method of manufacturing the same Pending JP2004221176A (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165152A (en) * 2004-12-06 2006-06-22 Matsushita Electric Ind Co Ltd Solid electrolytic capacitor and substrate with built-in solid electrolytic capacitor, and those manufacturing methods
WO2007007830A1 (en) * 2005-07-13 2007-01-18 Matsushita Electric Industrial Co., Ltd. Mounted board, mounted body, and electronic device using same
US7317610B2 (en) 2004-11-16 2008-01-08 Nec Toppan Circuit Solutions, Inc. Sheet-shaped capacitor and method for manufacture thereof
JP2008277415A (en) * 2007-04-26 2008-11-13 Kyocera Corp Substrate having built-in electronic component and manufacturing method thereof
US7652347B2 (en) * 2006-06-29 2010-01-26 Hynix Semiconductor Inc. Semiconductor package having embedded passive elements and method for manufacturing the same
JP2011166161A (en) * 2011-04-01 2011-08-25 Fujitsu Ltd Interposer module with built-in capacitor
US8320135B2 (en) 2005-12-16 2012-11-27 Ibiden Co., Ltd. Multilayer printed circuit board

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7317610B2 (en) 2004-11-16 2008-01-08 Nec Toppan Circuit Solutions, Inc. Sheet-shaped capacitor and method for manufacture thereof
JP2006165152A (en) * 2004-12-06 2006-06-22 Matsushita Electric Ind Co Ltd Solid electrolytic capacitor and substrate with built-in solid electrolytic capacitor, and those manufacturing methods
WO2007007830A1 (en) * 2005-07-13 2007-01-18 Matsushita Electric Industrial Co., Ltd. Mounted board, mounted body, and electronic device using same
US7667977B2 (en) 2005-07-13 2010-02-23 Panasonic Corporation Mounting board, mounted body, and electronic equipment using the same
US8320135B2 (en) 2005-12-16 2012-11-27 Ibiden Co., Ltd. Multilayer printed circuit board
JP5188816B2 (en) * 2005-12-16 2013-04-24 イビデン株式会社 Multilayer printed wiring board and manufacturing method thereof
US8705248B2 (en) 2005-12-16 2014-04-22 Ibiden Co., Ltd. Multilayer printed circuit board
US7652347B2 (en) * 2006-06-29 2010-01-26 Hynix Semiconductor Inc. Semiconductor package having embedded passive elements and method for manufacturing the same
JP2008277415A (en) * 2007-04-26 2008-11-13 Kyocera Corp Substrate having built-in electronic component and manufacturing method thereof
JP2011166161A (en) * 2011-04-01 2011-08-25 Fujitsu Ltd Interposer module with built-in capacitor

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