JP2004215417A - Dc-dc converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a small-sized cooling fin usable even if a DC power voltage is raised, by suppressing switching loss and conduction loss . <P>SOLUTION: In a DC-DC converter that drives a switch element 2 connected to the positive pole side of a DC power supply by using an auxiliary winding of a transformer 4, the switching loss and the conduction loss can be reduced by driving the switch element 2 by a saturable transformer 20 and allowing control of the on-time width of the switch element 2, though the on-time width of the switch element cannot be intentionally controlled conventionally because it is determined by a resonance frequency determined by constants of a capacitor 3 and the transformer 4. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a half-bridge DC / DC converter.
[0002]
[Prior art]
FIG. 8 shows a conventional example of a half-bridge type DC / DC converter (see Patent Document 1).
In the case of Patent Document 1, two switch elements (MOSFETs 1 and 2) are connected in parallel with a DC power supply 10, and a series circuit of a capacitor 3 and a primary winding 5 of a transformer 4 is connected in parallel with one of the elements. The switch element 2 connected to the positive terminal of the DC power supply 10 is supplied with an ON / OFF signal from the quaternary winding 7 of the transformer 4. The tertiary winding 6 of the transformer 4 is used as a power supply for the control circuit 23, and the control circuit 23 detects the timing of switching the positive / negative of the tertiary winding 6 of the transformer 4, and detects the DC An on / off signal is given to the switch element 1 connected to the negative side of the power supply 10.
[0003]
FIG. 9 shows an example of voltage and current waveforms of each part in FIG.
First, in the period (1), the MOSFET 1 sets the voltage VP3 of the tertiary winding 6 of the transformer 4 which generates a voltage of the same polarity in proportion to the voltage VP1 of the primary winding 5 of the transformer 4 to be more positive than negative. Turns on after a short-circuit prevention period Td from the timing of switching to. As a result, the resonance current between the capacitor 3 and the transformer 4 flows through the path of the DC power supply 10 → the capacitor 3 → the primary winding 5 of the transformer 4 → the MOSFET 1, and the capacitor 3 is charged. At this time, the difference voltage VP1 between the DC power supply voltage Ed and the voltage VC of the capacitor 3 is applied to the primary winding 5 of the transformer 4, and the voltage generated in the secondary winding 8 of the transformer 4 is applied to the diode 13, The power is supplied to the load after being rectified and smoothed by the capacitor 15.
[0004]
When the voltage of the VP3 of the tertiary winding 6 of the transformer 4 is switched from negative to positive, the control circuit 23 increases the reference signal value that increases in proportion to time and the secondary signal from the output voltage detection circuit. This is performed when a reference signal value exceeds an output voltage detection value (shown as an output voltage command value in FIG. 9). Further, when the voltage VP3 of the tertiary winding 6 of the transformer 4 drops due to a load condition or the like before the reference signal value exceeds the output voltage detection value, the control circuit 23 switches the voltage VP3 from positive to negative. The timing is detected and the MOSFET 1 is turned off. When the MOSFET 1 is turned off, the voltage VP1 of the primary winding 5 of the transformer 4 and the voltage VP3 of the tertiary winding 6 are switched from positive to negative.
[0005]
In the period (2), when the MOSFET 1 is turned off, the current flowing through the primary winding 5 of the transformer 4 is commutated to the output capacitance of the MOSFETs 1 and 2, and the voltages of the MOSFETs 1 and 2 gradually increase or decrease. .
In the period (3), when the voltage of the MOSFET 1 reaches the DC voltage Ed, the current flowing through the transformer 4 is commutated to the parasitic diode of the MOSFET 2. At this time, when the voltage VP4 of the quaternary winding 7 of the transformer 4 exceeds the gate threshold value of the MOSFET 2, the MOSFET 2 is turned on and the capacitor 3 is connected to the capacitor 3 through the path of the MOSFET 3 → the primary winding 5 of the transformer 4. A resonance current with the transformer 4 flows, and the capacitor 3 is discharged. Further, a capacitor voltage VC is applied to the primary winding 5 of the transformer 4, and the voltage generated in the secondary winding 9 of the transformer is rectified and smoothed by the diode 14 and the capacitor 15, and power is supplied to the load. I do. When the resonance current decreases, the voltage VP4 of the quaternary winding 7 of the transformer 4 decreases, and when the voltage drops below the gate threshold value of the MOSFET 2, the MOSFET 2 is turned off.
[0006]
During the period (4), when the MOSFET 2 is turned off, the voltage VP1 of the primary winding 5 of the transformer 4 changes from negative to positive. The current flowing through the primary winding 5 of the transformer 4 is commutated to the parasitic capacitance of the MOSFETs 1 and 2, and the voltages of the MOSFETs 1 and 2 gradually increase or decrease. In the period (1), when the voltage of the MOSFET 2 reaches the DC voltage Ed, the current flowing through the primary winding 5 of the transformer 4 is commutated to the parasitic diode of the MOSFET 1. Thereafter, by repeating this series of operations, power is supplied from the DC power supply 10 to the load.
[0007]
[Patent Document 1]
JP-A-2002-209381 (page 4-5, FIG. 1)
[0008]
[Problems to be solved by the invention]
However, in the conventional example, when the DC voltage Ed increases due to input voltage fluctuation or the like, not only does the cutoff current of the switch element increase, but also the effective value of the current flowing through the two switch elements increases, so that switching loss and conduction loss increase. However, there is a problem that it is necessary to increase the size of the cooling fin of the switch element.
In FIG. 8, FIG. 10 shows a waveform example of each part when the DC power supply voltage Ed rises due to a voltage fluctuation or the like. If the DC power supply voltage or load fluctuates in the conventional example, the output voltage is adjusted by adjusting the on-time of the MOSFET 1 connected to the negative electrode side of the DC power supply 10. On the other hand, the time width during which the MOSFET 2 connected to the positive electrode side of the DC power supply 10 is turned on depends on the voltage VP4 of the quaternary winding 7 of the transformer 4, and the time is determined by the constants of the capacitor 3 and the transformer 4. The on-time width cannot be adjusted intentionally because it depends on the resonance frequency.
[0009]
That is, when the load is light or when the input DC voltage rises, the on-time width of the MOSFET 1 becomes narrower than the on-time width of the MOSFET 2. In particular, when the input voltage increases, the cutoff current and the effective current value of the MOSFET increase. Therefore, switching loss and conduction loss increase.
Therefore, an object of the present invention is to prevent switching loss and conduction loss from increasing even when the load is light or when the input DC voltage increases.
[0010]
[Means for Solving the Problems]
In order to solve such a problem, according to the invention of claim 1, in a DC / DC converter in which a series circuit of two switch elements is connected between a positive electrode and a negative electrode of a DC power supply,
A saturable transformer for providing an on / off signal to a switch element connected to the positive side of the DC power supply, and an adjusting device for adjusting an exciting current of the saturable transformer are provided.
[0011]
According to the invention of claim 2, a series circuit of two switch elements is connected between a positive electrode and a negative electrode of a DC power supply, and a series circuit of at least one capacitor and a primary winding of a transformer is connected to the switch element. One side is connected in parallel, and the two switch elements are turned on and off alternately, thereby rectifying half- or full-wave positive and negative voltages generated in the secondary winding of the transformer to obtain a DC / DC output. In DC converter,
A primary winding of a saturable transformer is connected in parallel with a tertiary winding of the transformer, and a switching element connected to the positive side of the DC power supply is turned on and off by a secondary winding of the saturable transformer. And a tertiary winding of the transformer is used as a power supply for a control circuit. The control circuit detects a positive / negative switching timing of the tertiary winding voltage, and detects the negative timing of the DC power supply at that timing. An on / off signal is supplied to the switch element connected to the side, and an adjusting device for adjusting the exciting current of the saturable transformer according to the DC output voltage is provided.
[0012]
According to the first aspect of the present invention, the tertiary winding of the transformer is used as a power supply for a control circuit, and the control circuit detects a positive / negative switching timing of the tertiary winding voltage, and uses the DC / DC switching timing at that timing. An on / off signal is given to a switch element connected to the negative side of the power supply, and a primary winding of the saturable transformer can be connected in parallel with a fourth winding of the transformer. invention).
Further, in any one of the first to third aspects of the present invention, it is possible to provide limiting means for limiting the ON time width of one of the two switch elements so as not to be less than a certain time width. Invention 4).
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a configuration diagram showing a first embodiment of the present invention.
The difference from the conventional one is that a series circuit of the primary winding of the saturable transformer 20 and the resistors 17 and 18 is connected in parallel with the tertiary winding 6 of the transformer 4, and the secondary winding of the saturable transformer 20 is connected to the resistor. There is provided a point in which 19 series circuits are connected in parallel between the gate and source of the switch element 2 (MOSFET 2), and an adjuster 22 for adjusting the exciting current of the saturable transformer 20 according to the output of the voltage detector 21. Is a point. Hereinafter, points different from the related art will be mainly described.
[0014]
When lowering the output voltage in FIG. 1, a command to lower the output voltage is input from the voltage detector 21 to the controller 22. Then, the controller 22 increases the current flowing through the path of the capacitor 16 → the controller 22 → the resistor 18 → the capacitor 16 in accordance with the input command, and increases the voltage V18 generated in the resistor 18. Here, when the MOSFET 1 is on and the MOSFET 2 is off, the voltage polarity of the voltage VP3 generated in the tertiary winding 6 of the transformer 4 is positive, so that the tertiary winding 6 of the transformer 4 → A current flows through the saturable transformer 20 through the path of the saturable transformer 20 → the resistor 17 → the resistor 18 → the tertiary winding 6 of the transformer 4. At this time, since the voltage VR18 generated in the resistor 18 is large, the reset current of the saturable transformer 20 decreases. Therefore, when the MOSFET 1 is turned off and the MOSFET 2 is turned on, the reset current is reduced, so that the time until the saturable transformer 20 is saturated is short, and the pulse width of the on signal of the MOSFET 2 is short.
[0015]
On the other hand, when increasing the output voltage, a command to increase the output voltage is input from the voltage detector 21 to the controller 22. Then, the adjuster 22 reduces the current flowing through the path of the capacitor 16 → the adjuster 22 → the resistor 18 → the capacitor 16 according to the input command, and reduces the voltage VR18 generated at the resistor 18. Here, when the MOSFET 1 is on and the MOSFET 2 is off, the voltage polarity of the voltage VP3 generated in the tertiary winding 6 of the transformer 4 is positive, so that the tertiary winding 6 of the transformer 4 → A current flows through the saturable transformer 20 through the path of the saturable transformer 20 → the resistor 17 → the resistor 18 → the tertiary winding 6 of the transformer 4. At this time, since the voltage VR18 generated in the resistor 18 is small, the reset current of the saturable transformer 20 increases. Therefore, when the MOSFET 1 is turned off and the MOSFET 2 is turned on, the reset current is increased, so that the time until the saturable transformer 20 is saturated becomes longer, and the pulse width of the ON signal of the MOSFET 2 becomes longer.
[0016]
From the above, while it was impossible to intentionally adjust the on-time width of the MOSFET 2 conventionally, according to the present invention, the on-time width of the MOSFET 2 can be adjusted according to the output voltage command. It becomes.
FIG. 5 shows an example of an operation waveform when the input DC voltage rises in FIG. As shown in the figure, according to the present invention, the on-time width of the MOSFET 2 can be adjusted. Therefore, when the input DC voltage rises or the load is light, the current effective value and the cutoff current of the MOSFET 2 can be increased as compared with the related art. It can be seen that it can be suppressed (see IQ1, IQ2, ID13 and ID14).
[0017]
FIG. 2 shows a second embodiment of the present invention.
The difference from FIG. 1 is that a quaternary winding 7 of the transformer 4 is provided, and a primary circuit of a saturable transformer 20 and a series circuit of resistors 17 and 18 are connected in parallel with the quaternary winding 7. The point is that a series circuit of the secondary winding of the saturation transformer 20 and the resistor 19 is connected in parallel between the gate and the source of the switch element 2 (MOSFET 2). Even in this case, the same effect as in the case of FIG. 1 can be obtained.
[0018]
FIG. 3 shows a third embodiment of the present invention.
The difference from FIG. 1 is that a limiter 24 is provided between the output unit of the voltage detector 21 and the input unit 23 of the control circuit 23.
FIG. 6 is an explanatory diagram showing the relationship between the switching frequency Fs with respect to the device output Pout and the on-duty (on-duty ratio) of the switch element 1 in the cases shown in FIGS. 1 and 2 and in FIG. It is.
That is, in the configuration shown in FIGS. 1 and 2, it is possible to adjust the ON time width of the switch element 2, and as a result, the ON time of the switch element 1 and the switch element 2 is fixed and the ON time is fixed. Only the width changes. That is, only the switching frequency Fs changes according to the load and the input voltage (the characteristics of the first and second embodiments shown in FIG. 6 are examples in which the on-duty of the switch element 1 is 50%). .
[0019]
However, in the case of the characteristics described above, there may be a problem that the switching frequency Fs sharply increases at a light load, and the efficiency at a light load decreases. By providing the limiter 24 as shown in FIG. 3 to cope with such a case, it is possible to limit the ON time width of the switch element 1 so as not to be reduced below the time width set by the limiter 24. Thus, when the load is light, the control of the output voltage is controlled only by adjusting the ON time width of the switch element 2, and it is possible to suppress a sharp increase in the switching frequency Fs at the time of light load. In this case, when the load is light, the on-time width of the switch element 1 is fixed, and the output voltage is controlled by reducing the on-time width of the switch element 2 as the load decreases, so that the on-duty of the switch element 1 is controlled. Has a characteristic that increases as the load decreases.
[0020]
FIG. 4 shows a fourth embodiment of the present invention.
This is characterized in that a limiter 24 is provided between the output unit of the voltage detector 21 and the adjusting unit of the adjusting unit 22 in FIG.
FIG. 7 is an explanatory diagram showing the relationship between the switching frequency Fs with respect to the device output Pout and the on-duty of the switch element 1 in the case of FIGS. 1 and 2 and the case of FIG.
4, the ON time width of the switch element 2 is limited so as not to be reduced below the time width set by the limiter 24. Therefore, when the load is light, the output voltage is controlled by narrowing the on-time width of the switch element 1, so that the on-duty of the switch element 1 has a characteristic of decreasing at a light load, and the same effect as in the case of FIG. Will be obtained.
[0021]
【The invention's effect】
According to the present invention, especially when the DC power supply voltage rises due to the input voltage fluctuation, the switching current and the effective current value of the switch element can be reduced as compared with the related art, so that the switching loss and the conduction loss can be suppressed. This has the advantage that the cooling fins and the like of the element can be miniaturized. It is needless to say that the same applies to a light load.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a second embodiment of the present invention. FIG. 3 is a circuit diagram showing a third embodiment of the present invention. FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention. FIG. 5 is an explanatory diagram of the operation of the present invention. FIG. 6 is an explanatory diagram of a switching frequency and an on-duty characteristic of the switch element 1 with respect to the device output of FIG. 7 is an explanatory diagram of the switching frequency and the on-duty characteristic of the switch element 1 with respect to the output of the device of FIG. 4; FIG. 8 is a configuration diagram showing a conventional example; FIG. 9 is an operational explanatory diagram of FIG. Operation explanation diagram when DC voltage rises [Explanation of symbols]
1, 2, switch element (MOSFET: field effect transistor), 3, 15, 16, capacitor, 4 transformer, 5 transformer primary winding, 6 transformer tertiary winding, 7 transformer quaternary winding Wire, 8, 9 transformer secondary winding, 10 DC voltage source, 11 to 14 diode, 17 to 19 resistor, 20 saturable transformer, 21 voltage detector, 22 regulator, 23 Control circuit, 24 ... limiter.

Claims (4)

In a DC / DC converter in which a series circuit of two switch elements is connected between a positive electrode and a negative electrode of a DC power supply,
A DC / DC device comprising: a saturable transformer for providing an on / off signal to a switch element connected to a positive electrode side of the DC power supply; and an adjusting device for adjusting an exciting current of the saturable transformer. converter. A series circuit of two switch elements is connected between a positive electrode and a negative electrode of the DC power supply, and a series circuit of at least one capacitor and a primary winding of a transformer is connected in parallel to one of the switch elements. In a DC / DC converter which obtains a DC output by half-wave or full-wave rectifying a positive or negative voltage generated in a secondary winding of a transformer by alternately turning on and off the two switch elements,
A primary winding of a saturable transformer is connected in parallel with a tertiary winding of the transformer, and a switching element connected to the positive side of the DC power supply is turned on and off by a secondary winding of the saturable transformer. And a tertiary winding of the transformer is used as a power supply for a control circuit. The control circuit detects a positive / negative switching timing of the tertiary winding voltage, and detects the negative timing of the DC power supply at that timing. A DC / DC converter characterized by providing an on / off signal to a switch element connected to the side, and an adjusting device for adjusting an exciting current of the saturable transformer according to a DC output voltage. A tertiary winding of the transformer is used as a power supply of a control circuit, and the control circuit detects a positive / negative switching timing of the tertiary winding voltage, and at that timing, a switch connected to the negative side of the DC power supply. 2. The DC / DC converter according to claim 1, wherein an on / off signal is supplied to an element, and a primary winding of the saturable transformer is connected in parallel with a fourth winding of the transformer. 4. The DC / DC converter according to claim 1, further comprising a limiter configured to limit an on-time width of one of the two switch elements to be equal to or less than a certain time width. .

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