JP2004208075A - Method and device for digital/analog conversion - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital/analog conversion method which realizes both ripple suppression and high response, and to provide a device. <P>SOLUTION: A microcomputer 1 is provided with a port output determination part 2 which obtains the absolute value of the difference between a digital signal value V<SB>C</SB>' converted by an A/D conversion part 3 and an output set value V<SB>T</SB>when an interrupt occurs. When the absolute value is larger than a preliminarily set threshold A1, the part 2 compares the output set value V<SB>T</SB>and the digital signal value V<SB>C</SB>' with each other, makes an output port PC1 high for a time proportional to the absolute value and then makes the output port PC1 tristate in the case that the output set value V<SB>T</SB>is larger than the digital signal value V<SB>C</SB>'. In the case that the output set value V<SB>T</SB>is equal to or smaller than the digital signal value V<SB>C</SB>', the part 2 makes the output port PC1 low for the time proportional to the absolute value and then makes it tristate. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a digital / analog conversion method and a digital / analog conversion device for controlling a port output of a microcomputer to obtain a predetermined analog signal.
[0002]
[Prior art]
As a circuit configuration of a conventional digital / analog (D / A) conversion device, one shown in FIG. 7 is known (for example, see Patent Document 1).
[0003]
The microcomputer 01 includes an up counter 02, a timer register 03, a comparator 04, and an analog / digital (A / D) converter 05. When the internal clock of the up counter 02 is input, a value corresponding to a predetermined time is set in the timer register 03 via the internal bus. The up-counter value of the up-counter 02 is compared with the value of the timer register 03 by the comparator 04. When the values match, an interrupt is generated in the microcomputer 01 and the up-counter 02 is cleared.
[0004]
In this manner, by setting desired data in the timer register 03, an interrupt can be generated at regular intervals, and the result of processing during the timer interrupt is output as a PWM signal _VA to the port.
[0005]
The _{V A} is integrated by constructed low pass filter 06 from the resistor _{R 1} and capacitor _{C 1} Tokyo, it is converted into an analog waveform shown in _{V B.} The _{V B} is _{V C} are obtained are input to the non-inverting amplifier 07. Note that this V _C, by passing through the low pass filter 08 composed of the resistor R ₄ and the capacitor C ₂ Prefecture, after being reduce voltage ripple, is outputted as V _D from the voltage follower 09, A / It is also input to the D conversion unit 05 as a voltage-converted V _C ′.
[0006]
The microcomputer 01 compares V _C ′ input to the A / D conversion unit 05 with the D / A output set value _VT, and when V _T > V _C ′, sets the port output to low, and V _T > V _C. ', Set the port output to high.
[0007]
As described above, in the conventional D / A converter, the PWM signal _VA output from the microcomputer 01 as a port can be converted into a desired analog signal without using the timer of the microcomputer 01 by using the timer interrupt routine. it can be converted into the signal V _D.
[0008]
[Patent Document 1]
JP-A-6-4218
[Problems to be solved by the invention]
However, the conventional D / A converting device, a PWM signal V _A output from the microcomputer 01, since the converted analog signal V _B using a low-pass filter 06, the ripple having a constant period to V _B Is included. Therefore, in order to remove this ripple, it is necessary to use a low-pass filter 08 time constant long enough to V _B relative to the period of the PWM signal.
[0010]
That is, poor response when changing the duty of the PWM signal V _A to alter the D / A output setting value V _T, is large response delay until V _C is D / A output setting value V _T There was a problem.
[0011]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a digital / analog conversion method and a digital / analog conversion device capable of achieving both suppression of ripples and high responsiveness. It is in.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, in the digital / analog conversion method according to the first aspect of the present invention, in the digital / analog conversion method executed when an interruption to the microcomputer occurs at regular time intervals, the digital / analog conversion method is performed based on the output set value. The signal output from the output port of the computer is input to a low-pass filter, the analog signal output from the low-pass filter is converted into a corresponding digital signal, and the absolute value of the difference between the converted digital signal value and the output set value When the absolute value is equal to or greater than a predetermined threshold value, the output set value is compared with a digital signal value, and when the output set value is larger than the digital signal value, the output set value is proportional to the absolute value. After the time output port is set to high, the output port is three-stated while the output set value is a digital signal. When it is a value or less, after the low time output port proportional to the absolute value, characterized in that the output port and three-state.
[0013]
According to a second aspect of the present invention, in the digital-to-analog conversion method according to the first aspect, the cutoff frequency of the low-pass filter is set to a cycle equal to or less than an interval of an interruption time.
[0014]
In the digital / analog converter according to the third aspect, a microcomputer, a timer for interrupting the microcomputer every predetermined time, and a signal output from an output port of the microcomputer are converted into analog signals and output. A low-pass filter, and analog / digital conversion means for converting an analog signal output from the low-pass filter into a corresponding digital signal, wherein the microcomputer converts the converted digital signal value when an interrupt occurs. Obtain the absolute value of the difference from the output set value, compare the output set value and the digital signal value, and when the output set value is greater than the digital signal value, set the output port to high for a time proportional to the absolute value. Output port is three-stated while the output When issue value or less, after the low time output port proportional to the absolute value, characterized in that it comprises a port output determining section for the output port and three-state.
[0015]
According to a fourth aspect of the present invention, in the digital-to-analog converter according to the third aspect, the cutoff frequency of the low-pass filter is set to a period equal to or less than an interval of an interruption time.
[0016]
According to a fifth aspect of the present invention, in the digital / analog conversion apparatus according to the third or fourth aspect, the port output determination unit compares the absolute value with a preset threshold value, When the value does not exceed the threshold value, the output port is kept in a three-state state until the next interrupt occurs.
[0017]
According to a sixth aspect of the present invention, in the digital-to-analog conversion apparatus according to any one of the third to fifth aspects, the port output determination unit is configured to determine a proportional coefficient which is separately set for high and low in advance. A time for setting the output port to high or low by multiplying the absolute value is set.
[0018]
According to a seventh aspect of the present invention, in the digital-to-analog converter according to the third to sixth aspects, a plurality of output ports are set in the microcomputer, and a timer and a low-pass filter are provided for each of the output ports. A plurality of channels are set in the analog / digital conversion means in accordance with the number of analog signals output from the low-pass filter, and the microcomputer inputs the analog signal input to the analog / digital conversion means to any channel. A channel detection unit for detecting whether the signal is output, and outputting a signal from an output port corresponding to the detected channel.
[0019]
【The invention's effect】
In the digital / analog conversion method according to the first aspect, at the time of a timer interrupt, the absolute value of the difference between the digital signal value corresponding to the analog signal output from the low-pass filter and the output set value is obtained, and this absolute value is determined in advance. When the value is equal to or larger than the set threshold, the output set value is compared with the digital signal value.
[0020]
If the output set value is larger than the digital signal value, the output port is set to high for a time proportional to the absolute value, and then the output port is set to three-state (input mode). On the other hand, when the output set value is equal to or less than the digital signal value, the output port is set to low for a time proportional to the absolute value, and then the output port is set to three-state.
[0021]
That is, in the present invention, theoretically, a signal is output from the output port only for a moment when the level is changed, so that the time constant of the low-pass filter can be set small, and both high responsiveness and suppression of ripple can be achieved. Can be achieved.
[0022]
In the digital / analog conversion method according to the second aspect, the response can be further improved by setting the cutoff frequency of the low-pass filter to be equal to or shorter than the interrupt time interval.
[0023]
In the digital / analog conversion device according to the third aspect, the port output determination unit obtains the absolute value of the difference between the digital signal value output from the analog / digital conversion means and the output set value at the time of timer interruption, and further outputs Compare the set value with the digital signal value.
[0024]
If the output set value is larger than the digital signal value, the output port is set to high for a time proportional to the absolute value, and then the output port is set to three-state (input mode). On the other hand, if the output setting is equal to or less than the digital signal value, the output port is set to low for a time proportional to the absolute value, and then the output port is set to three-state.
[0025]
Therefore, since a signal is output from the output port only for a moment when the level is changed, the time constant of the low-pass filter can be set small, and both high responsiveness and suppression of ripple can be achieved.
[0026]
Further, by increasing the resolution of the analog / digital conversion means, the resolution of the obtained analog signal can be improved.
[0027]
In the digital / analog converter according to the fourth aspect, the response can be further improved by setting the cutoff frequency of the low-pass filter to be equal to or shorter than the interval of the interruption time.
[0028]
In the digital / analog conversion apparatus according to the fifth aspect, when the absolute value does not exceed the threshold value, the output port is kept in the three-state until the next interrupt occurs, so that the analog / digital conversion is always performed due to noise or the like. When the digital signal value output from the digital conversion means does not match the output set value, the output port goes high or low for a time proportional to the absolute value of the difference between the digital signal value and the output set value for each timer interrupt As a result, the analog value can be prevented from becoming unstable.
[0029]
In the digital / analog converter according to the sixth aspect, by setting different proportional coefficients for high and low, it is possible to speed up only the side where responsiveness is required.
[0030]
In the digital / analog conversion device according to the seventh aspect, it is detected which channel the analog signal input to the analog / digital conversion means has been input, and a signal is output from an output port corresponding to the detected channel. Thus, a plurality of desired analog signals can be output.
[0031]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments for realizing the digital / analog conversion device of the present invention will be described based on a first embodiment and a second embodiment.
[0032]
(First embodiment)
First, the configuration will be described.
FIG. 1 is a circuit diagram of the digital / analog converter of the first embodiment.
[0033]
The microcomputer 1 includes a port output determination unit 2 and an A / D conversion unit (analog / digital conversion unit) 3. The port output determination unit 2 compares the set D / A output set value _VT with the signal V _C ′ from the A / D conversion unit 3 in response to a timer interrupt request generated at regular intervals, and outputs the result. _VA is output from the port PC1.
[0034]
FIG. 2 shows the output timing of _VA . As shown in the figure, the port output _VA is output as digital data of “low level (low)”, “high level (high)”, and “high impedance state (three state)”. The V _A is integrated through composed low pass filter 4 by a resistor R ₁ and capacitor C _1, after becoming a analog signal V _B, is amplified by the noninverting amplifier 5 and the final output V _c is obtained. Also, _{V c} is inputted as _{V C} 'which was also the voltage conversion to the input port AN1 of the A / D converter 3.
[0035]
The gain (amplification rate) of the non-inverting amplifier 5 is determined by (maximum output voltage finally desired) / (maximum value of V _C ′).
[0036]
Note that in the pulse P ₁ to P ₃ in Figure 2, despite the D / A output setting value V _T has not changed, the pulse is being output, the capacitor C ₁ or noninverting amplifier 5 This is because the A / D conversion output voltage V _C ′ has decreased due to the input leakage current or the like.
[0037]
3, the D / A output setting value V _T constant at a state input leakage current or the like is not of the capacitor C ₁ and the non-inverting amplifier 5, port output V _A will remain the three-state.
[0038]
The configuration of the D / A conversion circuit of this embodiment is substantially the same as the configuration of the conventional D / A conversion circuit shown in FIG. 7 except that the low-pass filter 08 and the voltage follower 09 are deleted.
[0039]
Further, as the low-pass filter 4, a resistor R ₁ ′ and a capacitor C ₁ ′ having a smaller time constant than the resistor R ₁ and the capacitor C ₁ in the low-pass filter 06 of FIG. 7 are used. The cut-off frequency of the low-pass filter 4 is set to a cycle shorter than the interval of the interruption time of the timer.
[0040]
Next, the operation will be described.
[D / A conversion control processing]
In the microcomputer 1, in addition to the predetermined control as the main, subroutine for setting the D / A output setting value V _T is performed. In this subroutine, a target value determined by another routine or the like, that is, a D / A output set value _VT is set. When the timer interrupt time is set, a timer interrupt occurs every predetermined time. When this timer interrupt occurs, a timer interrupt routine is executed.
[0041]
FIG. 4 is a flowchart showing the flow of the D / A conversion control process executed in the timer interrupt routine of the microcomputer 1.
[0042]
In step S1, the A / D conversion value V _C ′ output from the A / D conversion unit 3 is read.
[0043]
In step S2, the D / A output set value _VT is read.
[0044]
In step S3, the absolute value of the difference between the A / D conversion value _{V C} 'and D / A output setting value _{V T,} and writes the result to the result R1 secured on the microcomputer 1 RAM.
[0045]
In step S4, the result R1 is compared with a preset threshold value A1, and when the result R1 is smaller than the threshold value A1, the present control is terminated, and when the result R1 is equal to or more than the threshold value A1. Proceeds to step S5.
[0046]
In step S5, the A / D conversion value _{V C} 'is compared with the D / A output setting value _{V T, if V T} is exceeded _{V C} proceeds to step S6, _{V T} is less _{V C} In this case, the process proceeds to step S7.
[0047]
In step S6, a value obtained by multiplying the result R1 by a preset proportional coefficient A2 is written in the ON time C1 secured on the RAM, and the level of the port output _VA is set to "high".
[0048]
In step S7, a value obtained by multiplying the result R1 by a preset proportional coefficient A3 is written in the ON time C1 secured on the RAM, and the level of the port output _VA is set to "low".
[0049]
In this embodiment, the ON time C1 is set as the number of times of looping from step S8 → step S9 → step S8.
[0050]
In step S8, it is determined whether the ON time C1 is 0. If the ON time C1 is 0, the process proceeds to step S10, and if the ON time C1 is other than 0, the process proceeds to step S9.
[0051]
In step S9, the ON time C1 is decremented.
[0052]
In step S10, the input / output direction of the port is set to input (three-state), and the control ends.
[0053]
[D / A conversion control action]
D / A output setting value _{V T} is greater than the A / D conversion value _{V C} ', when the difference is the threshold value A1 or more, in the flowchart of FIG. 4, step S1 → step S2 → step S3 → The flow proceeds to step S4 → step S5 → step S6 → step S8 → step S10.
[0054]
That is, in step S6, the ON time C1 is set by multiplying the result R1 by the proportional coefficient A2, and the port output _VA is set high. In steps S8 and S9, the countdown is performed until the ON time C1 becomes 0, In step S10, the port output is set to a three-state.
[0055]
When the D / A output set value _VT is equal to or less than the A / D conversion value V _C ′ and the difference is equal to or greater than the threshold value A1, in the flowchart of FIG. The flow proceeds to step S4 → step S5 → step S7 → step S8 → step S10.
[0056]
That is, in step S7, the ON time C1 is set by multiplying the result R1 by the proportional coefficient A3, and the port output _VA is set to low. In steps S8 and S9, the countdown is performed until the ON time C1 becomes zero. In step S10, the port output is set to a three-state.
[0057]
When the difference between the D / A output set value _VT and the A / D conversion value V _C ′ is smaller than the threshold value A1, in the flowchart of FIG. 4, go to step S1 → step S2 → step S3 → step S4. And the control ends without changing the state of the port output _VA .
[0058]
Next, effects will be described.
The digital / analog conversion device according to the present embodiment has the following effects.
[0059]
(1) when the output setting value V _T is greater than the digital signal value V _{C ',} after between output port PC1 ON-time C1 in proportion to result R1 to the high, three-state output port PC1 (input mode ) to one, when the output setting value V _T is equal to or less than the digital signal value V _{C ',} after between output port PC1 oN-time C1 in proportion to result R1 low, the output port PC1 and three-state By doing so, the time constant of the low-pass filter 4 can be set small, and both high responsiveness and suppression of ripples can be achieved.
[0060]
(2) Since the low-pass filter 4 uses a resistor R ₁ ′ and a capacitor C ₁ ′ having a small time constant and the cutoff frequency is set to a cycle shorter than the interval of the timer interrupt time, high responsiveness can be ensured. it can.
[0061]
(3) When the result R1 is equal to or less than the threshold value A1, the output port PC1 is kept in the three-state, so that the A / D conversion output voltage always output from the A / D conversion unit 3 due to noise or the like. when V C _'does not match the output set value V _T, even if the output port PC1 every timer interrupt becomes high or low, it is possible to prevent the analog signal V _C becomes unstable .
[0062]
(4) D / A output setting value V _T is set by multiplying the the ON time C1 and result R1 and the proportionality coefficient A2 is is greater than A / D conversion value V _{C ',} D / A output set value V _{When T} is equal to or less than the A / D conversion value V _C ′, the ON time C1 is set by multiplying the result R1 by the proportional coefficient A3, so that it is possible to speed up only the side that requires responsiveness. .
[0063]
(Second embodiment)
First, the configuration will be described.
The configuration of the digital / analog conversion circuit of the second embodiment is such that one channel of a D / A output circuit is added to the configuration of the first embodiment.
[0064]
Another circuit is added to the low-pass filter 4 and the non-inverting amplifier 5, and the A / D converter 3 has two input channels (AN1 and AN2) and a channel to which the feedback voltage V _C ″ of the added output circuit is added. To enter.
[0065]
The port output determination unit 2 changed by the D / A output circuit having two channels also has two channels.
[0066]
Next, the operation will be described.
[D / A conversion control processing]
The D / A conversion control process of the second embodiment is obtained by adding step S21 between step S1 and step S2 and adding step S22 after step S10 in the flowchart shown in FIG. Only the parts different from 4 will be described.
[0067]
In step S21, it is checked whether the channel of the A / D converter 3 is the channel (AN1 or AN2) corresponding to the port to be output.
If the channel of the A / D converter 3 is the channel corresponding to the port to be output, the process proceeds to step S2, and the channel of the A / D converter 3 is not the channel corresponding to the port to be output. In this case, the present control ends.
[0068]
In step S4, the result R1 is compared with a preset threshold value A1, and if the result R1 is smaller than the threshold value A1, the process proceeds to step S22, and if the result R1 is equal to or larger than the threshold value A1, Goes to step S5.
[0069]
In step S22, the channel of the A / D converter 3 is changed to another channel, and the control ends.
[0070]
Next, effects will be described.
(5) In order to output the port signal _VA ( _VA ′) from the corresponding output port PC1 (PC2) only when the channel of the A / D converter 3 is the channel corresponding to the port to be output, A plurality of desired analog signals can be output.
[0071]
(Other Examples)
[0072]
Although the embodiment of the present invention has been described based on the first and second embodiments, the specific configuration of the present invention is not limited to the first and second embodiments. In addition, the present invention includes any design changes that do not depart from the gist of the invention.
[0073]
For example, the values of the threshold value A1 and the proportional coefficients A2 and A3 may be set in advance by experiments or the like, or may be set after the apparatus is actually operated.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a digital / analog conversion device according to a first embodiment.
FIG. 2 is a diagram showing the output timing of a port output _VA .
3 is a diagram showing the output timing of the port output V _A of a state input leakage current or the like is not of the capacitor C ₁ and a non-inverting amplifier 5.
FIG. 4 is a flowchart illustrating a flow of a D / A conversion control process executed in a timer interrupt routine of the microcomputer 1 according to the first embodiment.
FIG. 5 is a circuit diagram of a digital / analog conversion device according to a second embodiment.
FIG. 6 is a flowchart illustrating a flow of a D / A conversion control process executed in a timer interrupt routine of the microcomputer 1 according to the second embodiment.
FIG. 7 is a circuit diagram of a conventional digital / analog converter.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Microcomputer 2 Port output judgment part 3 A / D conversion part 4 Low-pass filter 5 Non-inverting amplifier

Claims (7)

In a digital / analog conversion method which is executed when an interrupt occurs at regular intervals for a microcomputer,
Input the signal output from the output port of the microcomputer to the low-pass filter based on the output setting value,
Convert the analog signal output from this low-pass filter to a corresponding digital signal,
Find the absolute value of the difference between the converted digital signal value and the output set value,
When the absolute value is equal to or greater than a predetermined threshold value, the output set value is compared with a digital signal value. When the output set value is larger than the digital signal value, a time output port proportional to the absolute value is output. And then set the output port to three-state,
When the output set value is equal to or less than the digital signal value, the output port is set to a low state for a time proportional to the absolute value, and then the output port is set to a three-state. The digital / analog conversion method according to claim 1,
A digital / analog conversion method, wherein a cut-off frequency of the low-pass filter is set to a cycle equal to or less than an interval of an interruption time. A microcomputer,
A timer for interrupting the microcomputer at predetermined time intervals,
A low-pass filter that converts a signal output from an output port of the microcomputer into an analog signal and outputs the analog signal;
Analog / digital conversion means for converting an analog signal output from the low-pass filter into a corresponding digital signal;
With
When an interrupt occurs, the microcomputer obtains the absolute value of the difference between the converted digital signal value and the output set value, compares the output set value with the digital signal value, and sets the output set value to a digital signal. When the output value is greater than the digital signal value, the output port is set to three-state after the output port is set to high for a time proportional to the absolute value, and when the output set value is equal to or less than the digital signal value, the time output is proportional to the absolute value. A digital / analog conversion device comprising: a port output determination unit that sets an output port to three-state after setting a port to low. The digital / analog converter according to claim 3,
A digital / analog conversion device, wherein a cutoff frequency of the low-pass filter is set to a cycle equal to or less than an interval of an interruption time. The digital / analog converter according to claim 3 or 4,
The port output determination unit compares the absolute value with a preset threshold value, and when the absolute value does not exceed the threshold value, holds the output port in a three-state state until the next interrupt occurs. A digital / analog conversion device characterized by the above-mentioned. The digital / analog converter according to claim 3, wherein:
The digital / analog conversion device according to claim 1, wherein the port output determining unit multiplies the proportional coefficient separately set in advance by a high value and a low value by the absolute value to set a time for setting the output port to high or low. The digital / analog conversion device according to claim 3, wherein:
A plurality of output ports are set in the microcomputer, and a timer and a low-pass filter are provided for each of the output ports,
Setting a plurality of channels according to the number of analog signals output from the low-pass filter to the analog / digital conversion means;
The microcomputer is provided with a channel detection unit for detecting which channel the analog signal input to the analog / digital conversion unit is input, and outputs a signal from an output port corresponding to the detected channel. Digital / analog converter.

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