JP2004207894A - Parallel/series conversion circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a parallel/series conversion circuit capable of realizing a parallel/series conversion using the signal wiring delays and a simple logic circuit. <P>SOLUTION: The parallel/series conversion circuit uses the transmission lines as the different delay elements when parallel signals 1-1 inputted through an input unit 1-2 are transmitted through the transmission lines whose number is corresponding to that of the parallel signals 1-1, and is equipped with a delay unit 1-3 which outputs a plurality of delay element outputs different from each other in delay time and a logic circuit 1-4 which puts together the delay element outputs from the delay unit 1-3 to output series signals to an output unit 1-5. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to, for example, a parallel / serial conversion circuit that converts a parallel signal into a serial signal.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in an interface of various systems, it has been necessary to realize a parallel-serial conversion circuit in order to connect modules having different bit widths. In order to realize such a circuit, the timing of a signal between input and output is controlled using a mechanism such as a state machine. In order to absorb the time difference, a method of temporarily holding a value using a flip-flop circuit or the like has been used.
[0003]
Japanese Patent Application Laid-Open No. H11-163873 discloses a phase shifter provided in each path between an amplitude modulator and a power synthesizer, and a phase shifter according to an oscillation frequency of a frequency synthesizer so that a peak factor is reduced by a phase controller. Discloses an amplitude modulation orthogonal frequency division multiplexing (OFDM) apparatus that multiplexes an amplitude modulation frequency hopping signal by controlling a phase shift amount of the signal.
[0004]
[Patent Document 1]
JP 09-298495 A
[0005]
[Problems to be solved by the invention]
However, in order to control the above-described conventional state machine or the like, it is necessary to configure a logic circuit, and the specification of the configuration must be examined, and the circuit scale increases.
[0006]
Further, in the method using the flip-flop circuit, especially in a circuit having a large bit width, a large number of flip-flop circuits are required, and there is a disadvantage that the circuit scale similarly increases.
[0007]
In Patent Document 1, adjusting the time position of an OFDM carrier using a delay element (that is, a phase shifter) and synthesizing the time position are operations closest to parallel-serial conversion using a delay element. However, there is no closer technology, and the technical field of the parallel-serial conversion, which is the object of the present application, and the OFDM multiplexing described in Patent Document 1 are completely different.
[0008]
The present invention has been made in view of such a point, and an object of the present invention is to provide a parallel-serial conversion circuit that realizes parallel-serial conversion using a signal wiring delay and a simple logic circuit.
[0009]
[Means for Solving the Problems]
The parallel-serial conversion circuit of the present invention, when transmitting a parallel signal input to the input unit through a number of transmission lines corresponding to the number of signals of the parallel signal, each transmission line as a different delay element respectively A delay unit that outputs a plurality of delay element outputs having different delay times, and a combining unit that combines the plurality of delay element outputs output from the delay unit and outputs a serial signal to an output unit. It is.
[0010]
Therefore, according to the present invention, the following operations are performed.
When transmitting a parallel signal input to the input unit through a number of transmission lines corresponding to the number of parallel signals, the delay unit uses each transmission line as a different delay element to generate a plurality of signals having different delay times. Is output. The combining unit combines a plurality of delay element outputs output from the delay unit and outputs a serial signal to the output unit.
[0011]
The parallel-to-serial conversion circuit of the present invention can realize a parallel-to-serial conversion circuit whose circuit scale is significantly smaller than that of the existing configuration by utilizing the signal transmission delay. By arranging wirings with different transmission delays in parallel and connecting their ends to the logical sum, negative logical sum, pull-down circuit, etc. of the synthesis unit, a parallel-to-serial conversion circuit is realized using the difference in the arrival time of the signal can do.
[0012]
The parallel-serial conversion circuit of the present invention performs parallel-serial conversion by using a transmission line as a delay element and synthesizing a plurality of delay element outputs having different delay times to obtain an output. Since the delay section uses the propagation delay itself as a physical phenomenon, the circuit configuration can be simple and the mounting reliability can be high. The signal whose transmission is delayed by the delay unit can be applied to electromagnetic waves, light, and sound waves other than electricity.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described with reference to the drawings as appropriate.
[System basic configuration]
The parallel-serial conversion circuit applied to the embodiment of the present invention converts a parallel signal (1-1) input to an input unit (1-2) into a serial signal and outputs a serial signal (1-6). It is configured to be used in a parallel-to-serial conversion circuit that outputs to the section (1-5).
[0014]
Here, the parallel-serial conversion circuit applied to the embodiment of the present invention converts the parallel signal (1-1) input to the input section (1-2) into the number of parallel signals (1-1). When transmitting through a desired number of transmission lines, each transmission line is used as a different delay element, and is configured to include a delay unit (1-3) that outputs a plurality of delay element outputs having different delay times. You.
[0015]
In addition, the parallel-serial conversion circuit applied to the embodiment of the present invention combines a plurality of delay element outputs output from the delay units (1-3) to output a serial signal (1-6) to the output unit (1). -5).
[0016]
In the parallel / serial conversion circuit applied to the embodiment of the present invention, the wiring (1-3-1, 1-3-2, 1-3-3, 1-3-3) of the delay unit (1-3) is used. 4) is configured to use a transmission delay resulting from a difference between the wiring lengths L1, L2, and L3.
[0017]
In the parallel-to-serial conversion circuit applied to the embodiment of the present invention, the combining unit is configured to use the logic circuit (1-4).
[0018]
In the parallel-serial conversion circuit applied to the embodiment of the present invention, the logic circuit 1-4 includes an OR circuit as a logical sum and a NOR circuit as a negative logical sum, for example, a pull-down circuit connected to the ground via a resistor. It is configured to utilize circuits and combinations thereof.
[0019]
FIG. 6 is a diagram illustrating an example of an OR circuit realized by combining NAND circuits. 6, the OR circuit 61 can be configured to include the NAND circuits 1 to 4 and the NAND circuit 5.
[0020]
In the parallel-serial conversion circuit applied to the embodiment of the present invention, the parallel signal 1-1 input to the input unit 1-2 is an electric signal, an electromagnetic wave signal, an optical signal, a sound wave signal, and an elastic wave signal. It is configured to include.
[0021]
Accordingly, the parallel-to-serial conversion circuit applied to the embodiment of the present invention can be applied to a case where not only an electric signal but also an electromagnetic wave signal, an optical signal, a sound wave signal, and an elastic wave signal are transmitted through a wiring. . In this case, in the case of an optical signal, an optical fiber is used for the wiring.
[0022]
In the parallel-to-serial conversion circuit applied to the embodiment of the present invention, a delay unit (1-3) and a logic circuit (1-4) are provided. Here, the logical circuit (1-4) includes a logical OR, a negative logical OR, a pull-down circuit, and a logical circuit that provides a similar mechanism by a combination thereof, but here, for example, the logical OR is used. .
[0023]
The input parallel signal (1-1) is input to the input unit (1-2), and passes through the delay unit (1-3) and the logic circuit unit (1-4), so that it is output to the output unit (1-5). A configuration in which the output serial signal (1-6) is output can be realized.
[0024]
By using the parallel-serial conversion circuit applied to the embodiment of the present invention, parallel-serial conversion can be realized with a simple configuration.
[0025]
As a result, there are man-hours required for studying the specifications of the mechanism such as the state machine, the problem that the circuit scale increases due to the mechanism of the state machine, etc., and the circuit scale increases by using a large number of flip-flop circuits. Problem can be solved.
[0026]
The operation of the basic configuration of the system shown in FIG. 1 will be described below.
In FIG. 1, an input parallel signal (1-1) is transmitted in the order of an input unit (1-2), a delay unit (1-3), a logic circuit unit (1-4), and an output unit (1-5). At this time, first, an input parallel signal (1-1) is input to the input unit (1-2), and an output serial signal (P / S) after the parallel / serial conversion is performed from the output unit (1-5). 1-6) is output.
[0027]
The input unit (1-2) has a number of wires (1-3-1, 1-3-2, 1-3-3, 1-3-4) corresponding to the bit width of the input parallel signal (1-1). There is. As the input parallel signal (1-1), it is assumed that all the parallel signals are input simultaneously. The signal input at the same time propagates to the delay section (1-3).
[0028]
The delay unit (1-3) adjusts the delay amount by changing the wiring lengths L1, L2, L3, and L4 so that simultaneously input signals are output with different delay times. With this mechanism, the input parallel signal (1 -1) input simultaneously at the input section (1-2) is supplied to the subsequent logic circuit section (1-4) by the respective delay times T1, T2, T3, T4. Will be entered later.
[0029]
As the logic circuit section (1-4), a logic circuit that includes a logic circuit that provides a similar mechanism by using a logical sum, a negative logical sum, a pull-down circuit, and a combination thereof can be used. In this description, the logical sum is used. The result is output to the output unit (1-5).
[0030]
As a result, the output serial signal (1-6) output from the output unit (1-5) is a signal obtained by performing parallel / serial conversion on the input parallel signal (1-6).
[0031]
By changing the wiring lengths L1, L2, L3, and L4 in the delay section (1-3), simultaneously input signals are output with different delay times T1, T2, T3, and T4. By utilizing the physical property of wiring delay by adjusting the delay amount, the number of steps for examining the specifications of a mechanism such as a state machine as in the existing method can be reduced.
[0032]
Further, since there is no need to use a complicated mechanism as compared with a state machine or the like, the circuit scale is reduced.
[0033]
Further, a flip-flop circuit required for temporarily holding a signal is not required, so that the circuit scale is reduced.
[0034]
In addition, the possibility of illegitimate mounting is reduced by simplifying the mechanism.
[0035]
[Modification 1]
FIG. 2 shows a first modification. FIG. 2 differs from FIG. 1 only in the configuration of the delay unit (2-3), so only the configuration of the delay unit (2-3) will be described.
[0036]
In the parallel-serial conversion circuit applied to the embodiment of the present invention, the delay unit (2-3) is configured to use a transmission delay caused by a difference between the wiring widths W1, W2, W3, and W4.
[0037]
In the delay unit (2-3), the wiring widths W1, W2, W3, and W4 of the wirings (2-3-1, 2-3-2, 2-3-3, 2-3-4) are modified. In the first modification, the delay adjustment is performed by changing the wiring widths W1, W2, W3, and W4. With this mechanism, the input parallel signal (1-1) simultaneously input at the input unit (1-2) is transmitted to the subsequent logic circuit unit (1-4) by the respective delay times T11, T12, T13, and T14. Will be entered later.
[0038]
Here, the wiring widths W1, W2, W3, and W4 are values related to the cross-sectional area of the wiring, and the delay amount can be adjusted regardless of the cross-sectional shape.
[0039]
Thus, in the delay unit (2-3), by changing the wiring widths W1, W2, W3, and W4, simultaneously input signals are output with different delay times T11, T12, T13, and T14. By utilizing the physical property of wiring delay by adjusting the delay amount, the number of steps for examining the specifications of a mechanism such as a state machine as in the existing method can be reduced.
[0040]
[Modification 2]
FIG. 3 shows a second modification. FIG. 3 differs from FIG. 1 only in the configuration of the delay unit (3-3), so only the configuration of the delay unit (3-3) will be described.
[0041]
In the parallel-to-serial conversion circuit applied to the embodiment of the present invention, the delay unit (3-3) includes the wiring (3-3-1, 3-3-2, 3-3-3, 3-3-4). ) Is configured to utilize a transmission delay resulting from a difference between the materials constituting the above.
[0042]
Further, in the parallel-serial conversion circuit applied to the embodiment of the present invention, the difference between the materials constituting the wirings (3-3-1, 3-3-2, 3-3-3, 3-3-4). Is the resistivity ρ1, ρ2, ρ3, ρ4 of the wiring (3-3-1, 3-3-2, 3-3-3, 3-3-4), the capacitance c1, c2, c3, c4, or the dielectric It is configured to be based on the rates ε1, ε2, ε3, ε4.
[0043]
In the delay section (3-3), the material of the wiring (3-3-1, 3-3-2, 3-3-3, 3-3-4) is changed.
[0044]
Since the materials have different properties, even if the wiring lengths L1, L2, L3, and L4 and the wiring widths W1, W2, W3, and W4 are the same, the delay varies depending on the material. Here, the delay adjustment is performed using the property. With this mechanism, the input parallel signal (1-1) input simultaneously at the input unit (1-2) is transmitted to the subsequent logic circuit unit (1-4) by the respective delay times T21, T22, T23, and T24. Will be entered later.
[0045]
As a result, in the delay unit (3-3), the wiring (3-3-1, 3-3-2, 3-3-3, 3-3-4) is determined as the difference between the materials forming the wiring (3-3-1, 3-3-4). 3-1, 3-3-2, 3-3-3, 3-3-4) resistivity ρ1, ρ2, ρ3, ρ4, capacitance c1, c2, c3, c4, or dielectric constant ε1, ε2, ε3. , Ε4, the physical property of wiring delay by adjusting the amount of delay so that each signal input simultaneously is output with different delay times T21, T22, T23, T24 is used. Thus, the number of steps for examining the specifications of a mechanism such as a state machine as in the existing method can be reduced.
[0046]
[Variation 3]
The third modification is configured as follows although not shown.
In the parallel-to-serial conversion circuit applied to the embodiment of the present invention, the delay unit transmits a transmission delay resulting from a difference between the wiring lengths L1, L2, L3, and L4, and a transmission delay resulting from a difference between the wiring widths W1, W2, W3, and W4. Physical reasons other than the transmission delay resulting from the delay, the resistivity ρ1, ρ2, ρ3, ρ4, the capacitance c1, c2, c3, c4, or the difference between the dielectric constants ε1, ε2, ε3, ε4 as a material constituting the wiring. Is configured to take advantage of the transmission delay resulting from.
[0047]
The wiring lengths L1, L2, L3, L4, the wiring widths W1, W2, W3, W4, the materials ρ1, ρ2, ρ3, ρ4, the capacitances c1, c2, c3, c4, or the dielectric constants ε1, ε2, ε3 , Ε4, when a delay is caused by a physical factor, the delay is adjusted by utilizing the nature of the delay. With this mechanism, the input parallel signal (1-1) simultaneously input at the input unit (1-2) is input to the subsequent logic circuit unit (1-4) after each delay time.
[0048]
Here, the transmission delay caused by the difference between the wiring lengths L1, L2, L3, and L4, the transmission delay caused by the difference between the wiring widths W1, W2, W3, and W4, and the resistivity ρ1, ρ2, ρ3, and ρ4 as the material constituting the wiring The physical reasons other than the transmission delay resulting from the capacitance c1, c2, c3, c4 or the difference between the dielectric constants ε1, ε2, ε3, ε4 are, for example, the temperature around the wiring.
[0049]
As a result, in the delay unit, a transmission delay resulting from the difference between the wiring lengths L1, L2, L3, and L4, a transmission delay resulting from the difference between the wiring widths W1, W2, W3, and W4, and the resistivity ρ1, ρ2 as a material forming the wiring , Ρ3, ρ4, capacitances c1, c2, c3, c4, or a transmission delay caused by a difference between the dielectric constants ε1, ε2, ε3, ε4. By utilizing the physical property of wiring delay by adjusting the amount of delay so that simultaneously input signals are output with different delay times, the state machine and other The man-hour for examining the specifications of the mechanism can be reduced.
[0050]
[Modification 4]
FIG. 4 shows a fourth modification. FIG. 4 differs from FIG. 1 only in the configuration of the delay unit (4-3), so only the configuration of the delay unit (4-3) will be described.
[0051]
In the parallel-to-serial conversion circuit applied to the embodiment of the present invention, the delay unit (4-3) includes the wiring (4-3-1, 4-3-2, 4-3-3, 4-3-4). ), The transmission delay resulting from the difference between the wiring lengths L1, L2, L3, and L, the transmission delay resulting from the difference between the wiring widths W1, W2, W3, and W4, and the resistivity ρ1, ρ2, ρ3, ρ4, The transmission delay resulting from the combination of the transmission delay resulting from the difference between the capacitances c1, c2, c3, and c4 or the dielectric constants ε1, ε2, ε3, and ε4, and the transmission delay resulting from physical reasons is used. Be composed.
[0052]
In the delay section (4-3), the wiring lengths L1, L2, L3, L4 of the wirings (4-3-1, 4-3-2, 4-3-3, 4-3-4) and the wiring width W1 , W2, W3, W4, resistivity ρ1, ρ2, ρ3, ρ4, capacitance c1, c2, c3, c4, or dielectric constant ε1, ε2, ε3, ε4, or other physical factors that change the delay. By using them in combination, delay adjustment is performed. With this mechanism, the input parallel signal (1-1) simultaneously input at the input unit (1-2) is transmitted to the subsequent logic circuit unit (1-4) by the respective delay times T31, T32, T33, and T34. Will be entered later.
[0053]
Thereby, in the delay unit (4-3), the difference between the wiring lengths L1, L2, L3, and L4 of the wirings (4-3-1, 4-3-2, 4-3-3, 4-3-4) is obtained. , The transmission delay resulting from the difference between the wiring widths W1, W2, W3, and W4, the resistivity ρ1, ρ2, ρ3, ρ4, the capacitance c1, c2, c3, c4, or the dielectric constant ε1 as a material constituting the wiring. , .Epsilon.2, .epsilon.3, and .epsilon.4, and by combining the transmission delay differences resulting from the physical reasons, the resulting transmission delays are changed so that the simultaneously input signals have different delay times. By utilizing the physical property of wiring delay by adjusting the amount of delay so that it is output, the number of steps for examining the specifications of a mechanism such as a state machine as in the existing method can be reduced.
[0054]
[Variation 5]
FIG. 5 shows a fifth modification. FIG. 5 differs from FIG. 1 only in the configuration of the delay unit 5-3 and the logic circuits 1-4-1 and 1-4-2, so that the delay unit 5-3 and the logic circuits 1-4-1 and 1-4 are different. Only the configuration of -2 will be described.
[0055]
In the parallel-to-serial conversion circuit applied to the embodiment of the present invention, the delay unit (5-3) includes the wirings (5-3-1, 5-3-2) and (5-3-1 ', 5- 3-2 ′), and each transmission line (5-3-1, 5-3-2) and (5-3-1 ′, 5-3-2 ′) is provided for each group. A plurality of delay element outputs having different delay times T41 and T42 are output for each set by using different delay elements, respectively, and the synthesizing unit outputs a logic circuit (1-4-1, 1-4-) corresponding to the number of sets. 2), a plurality of delay element outputs of each set of the delay unit (5-3) are combined for each set, and a parallel signal (1-7) having a plurality of bit widths corresponding to the number of sets is output. It is configured to output to the section (1-5).
[0056]
The delay unit (5-3) includes the wiring lengths L1, L2, and L1 of the wirings (5-3-1, 5-3-2) and (5-3-1 ', 5-3-2'). By changing L2, the amount of delay is adjusted so that each signal input simultaneously is output with different delay times T41 and T42. With this mechanism, the input parallel signal (1-1) simultaneously input in the input unit (1-2) is transmitted to the subsequent logic circuit unit (1-4-1) and the logic circuit unit (1-4-2). Are input after the respective delay times T41 and T42 and after the delay times T41 and T42.
[0057]
As a result, in the delay unit (5-3), the wiring lengths L1, L2 of the wirings (5-3-1, 5-3-2) and (5-3-1 ', 5-3-2') are obtained. And L1 and L2 are changed to utilize the physical property of wiring delay by adjusting the amount of delay so that each signal input simultaneously is output with a different delay time T41, T42 and T41, T42. By performing parallel-to-parallel conversion with different bit widths instead of parallel-to-serial conversion, the number of steps for examining the specifications of a mechanism such as a state machine as in an existing method can be reduced.
[0058]
Note that not only the wiring lengths L1, L2 and the difference between L1, L2, but also the transmission delay resulting from the difference between the wiring widths W1, W2, and W1, W2, the resistivity ρ1, ρ2, and ρ1, The same applies to the case where conversion is performed using a delay caused by physical factors such as ρ2, capacitances c1, c2, and c1, c2 or a transmission delay caused by a difference between dielectric constants ε1, ε2 and ε1, ε2. be able to.
[0059]
In the parallel-to-serial conversion or the parallel-to-parallel conversion according to the above-described embodiment, the following effects are obtained by performing conversion using a delay caused by a physical factor.
[0060]
First, conventionally, it was necessary to examine the specifications of the mechanism such as a state machine. However, since the present embodiment is realized by a very simple mechanism, the number of steps can be reduced.
[0061]
Second, there is a possibility that the size of a circuit such as a state machine is increased, but in the present embodiment, the size can be significantly reduced.
[0062]
Third, the required flip-flop circuit is not used in other methods, so that the circuit scale can be reduced. This effect is particularly large in a circuit having a large bit width.
[0063]
Fourth, since the mechanism is simple, the possibility of performing improper implementation is reduced.
[0064]
It goes without saying that the present invention is not limited to the above-described embodiment, and that other configurations can be appropriately adopted without departing from the scope of the claims of the present invention.
[0065]
【The invention's effect】
The parallel-serial conversion circuit according to the present invention is a parallel-serial conversion circuit that converts a parallel signal input to an input unit into a serial signal and outputs a serial signal to an output unit. A delay unit that outputs a plurality of delay element outputs having different delay times by using each of the transmission lines as a different delay element when transmitting the signal through a number of transmission lines corresponding to the number of signals of the signal; And a synthesizing unit for synthesizing the plurality of delay element outputs output from the unit and outputting a serial signal to an output unit, thereby changing the delay time of the plurality of delay element outputs in the delay unit. By utilizing the physical property of wiring delay by adjusting the amount of delay so that each signal input simultaneously has a different delay time, the existing method As described above, the number of steps for examining the specifications of a mechanism such as a state machine can be reduced, and since there is no need to use a complicated mechanism as compared with a state machine or the like, the circuit scale is reduced, and furthermore, signals are temporarily held. Since the flip-flop circuit required for the above is not required, the circuit size is reduced, and the mechanism is simplified, so that there is an effect that the possibility of improper mounting can be reduced.
[0066]
Further, in the parallel-serial conversion circuit of the present invention, in the above, since the delay unit uses a transmission delay resulting from a difference in the wiring length, the delay unit changes the wiring length so that each signal input simultaneously is changed. Has an effect that the amount of delay can be adjusted so that is output with different delay times.
[0067]
Further, in the parallel-serial conversion circuit according to the present invention, in the above, the delay unit utilizes a transmission delay resulting from a difference in the wiring width, so that the delay unit changes the wiring width to thereby simultaneously input signals. This has the effect that the delay amount can be adjusted so that the respective signals are output with different delay times.
[0068]
Further, in the parallel-to-serial conversion circuit of the present invention, in the above, the delay unit uses a transmission delay generated from a difference between the materials forming the wiring, and thus the difference between the materials forming the wiring in the delay unit. By changing the delay time, the delay amount can be adjusted so that the signals input simultaneously are output with different delay times.
[0069]
Further, in the parallel-serial conversion circuit according to the present invention, in the above-mentioned configuration, the delay unit may include a transmission delay caused by a difference in a wiring length, a transmission delay caused by a difference in a wiring width, and a transmission delay caused by a difference in a material constituting the wiring. Since the transmission delay caused by the physical property is used, the transmission delay caused by the difference in the wiring length, the transmission delay caused by the difference in the wiring width, and the transmission delay caused by the difference in the material constituting the wiring in the delay unit. As another physical reason, for example, by changing the temperature around the wiring, it is possible to adjust the amount of delay so that simultaneously input signals are output with different delay times. To play.
[0070]
Further, in the parallel-serial conversion circuit according to the present invention, in the above, the delay unit includes a transmission delay caused by a difference in wiring length, a transmission delay caused by a difference in wiring width, a transmission delay caused by a difference in material forming the wiring, and Since the transmission delay generated as a result of combining the transmission delay difference generated due to the physical property is used, the transmission delay generated from the difference in the wiring length of the wiring, the transmission delay generated from the difference in the wiring width, By combining the transmission delay caused by the difference between the materials that make up the wiring and the difference in transmission delay caused by physical reasons, the resulting transmission delay is changed, so that simultaneously input signals are output with different delay times. The effect is that the amount of delay can be adjusted as described above.
[0071]
In the parallel-to-serial conversion circuit according to the present invention, in the above description, the delay unit is constituted by a plurality of sets, and each of the transmission lines is used as a different delay element for each set. The combining unit is configured to correspond to the number of sets, and the plurality of delay element outputs of each set of the delay unit are combined for each set, and a plurality of outputs corresponding to the number of sets are output. Since a parallel signal having a bit width is output to the output unit, the delay unit changes the delay time of each set of a plurality of delay element outputs for each set so that each simultaneously input signal is By utilizing the physical property of wiring delay by adjusting the amount of delay so that each set has a different delay time, parallel-to-parallel conversion with different bit widths is performed instead of parallel-to-serial conversion. There is an effect that it is possible.
[0072]
Further, in the parallel-serial conversion circuit of the present invention, since the difference between the materials constituting the wiring in the above is based on the resistivity, capacitance, or permittivity of the wiring, the wiring in the delay unit By changing the transmission delay resulting from the resistivity, capacitance, or dielectric constant of the wiring as the difference between the constituent materials, the amount of delay is adjusted so that each signal input simultaneously is output with a different delay time. This has the effect that it can be performed.
[0073]
Further, in the parallel-serial conversion circuit of the present invention, in the above, since the synthesizing unit uses a logic circuit, there is an effect that a delayed parallel signal can be synthesized with a simple configuration.
[0074]
Further, in the parallel-serial conversion circuit of the present invention, since the logic circuit uses a logical sum, a negative logical sum, a pull-down circuit and a combination thereof, the logical sum circuit synthesizes the delayed parallel signal with a simple configuration. , It is possible to form a negative OR circuit.
[0075]
Further, in the parallel-serial conversion circuit according to the present invention, in the above, the parallel signal input to the input unit includes an electric signal, an electromagnetic wave signal, an optical signal, a sound wave signal, and an elastic wave signal. However, the present invention is also applied to a case where an electromagnetic wave signal, an optical signal, a sound wave signal, and an elastic wave signal are transmitted in a wiring, thereby changing the delay time of a plurality of delay element outputs in a delay unit. In addition, it is possible to adjust the amount of delay so that not only simultaneously input electric signals but also electromagnetic wave signals, optical signals, sound wave signals, and elastic wave signals are output with different delay times.
[Brief description of the drawings]
FIG. 1 is a diagram showing a basic configuration of a system applied to an embodiment.
FIG. 2 is a diagram showing a first modification;
FIG. 3 is a diagram illustrating a second modification;
FIG. 4 is a diagram showing a fourth modification;
FIG. 5 is a diagram showing Modification Example 5;
FIG. 6 is a diagram illustrating an example of an OR circuit realized by combining NAND circuits.
[Explanation of symbols]
1-1 ... input parallel signal, 1-2 ... input section, 1-3, 2-3, 3-3, 4-3, 5-3 ... delay section, 1-4 ... logic circuit, 1 -5: output section, 1-6: output serial signal, output parallel signal

Claims (11)

In a parallel-to-serial conversion circuit that converts a parallel signal input to an input unit into a serial signal and outputs the serial signal to an output unit,
When transmitting the parallel signal input to the input unit through a number of transmission lines corresponding to the number of signals of the parallel signal, using each of the transmission lines as a different delay element, a plurality of different delay times. A delay unit that outputs a delay element output;
A synthesizing unit for synthesizing the plurality of delay element outputs output from the delay unit and outputting a serial signal to an output unit. The parallel-serial conversion circuit according to claim 1,
The parallel-to-serial conversion circuit, wherein the delay unit uses a transmission delay caused by a difference in wiring length. The parallel-serial conversion circuit according to claim 1,
The parallel-to-serial conversion circuit, wherein the delay unit uses a transmission delay caused by a difference in wiring width. The parallel-serial conversion circuit according to claim 1,
The parallel-to-serial conversion circuit, wherein the delay unit uses a transmission delay caused by a difference between materials constituting wiring. The parallel-serial conversion circuit according to claim 1,
The delay unit uses a transmission delay caused by a physical reason other than a transmission delay caused by a difference in a wiring length, a transmission delay caused by a difference in a wiring width, and a transmission delay caused by a difference in a material constituting a wiring. Characteristic parallel-to-serial conversion circuit. The parallel-serial conversion circuit according to claim 1,
The delay unit combines the transmission delay caused by the difference in the wiring length, the transmission delay caused by the difference in the wiring width, the transmission delay caused by the difference between the materials constituting the wiring, and the difference of the transmission delay caused by the physical property. , A parallel-to-serial conversion circuit characterized by utilizing a transmission delay that occurs. The parallel-serial conversion circuit according to claim 1,
The delay unit is configured by a plurality of sets, each transmission line is used as a different delay element for each set, and a plurality of delay element outputs having different delay times are output for each set.
The synthesizing unit is configured corresponding to the number of sets, synthesizes a plurality of delay element outputs of each set of the delay unit for each set, and outputs a parallel signal having a plurality of bit widths corresponding to the number of sets. A parallel-to-serial conversion circuit, which outputs the signal to a unit. The parallel-serial conversion circuit according to claim 4,
A parallel-to-serial conversion circuit, wherein the difference between the materials forming the wiring is based on the resistivity, capacitance, or dielectric constant of the wiring. The parallel-serial conversion circuit according to claim 1,
The parallel-to-serial conversion circuit, wherein the synthesis unit uses a logic circuit. The parallel-to-serial conversion circuit according to claim 9,
A parallel-to-serial conversion circuit, wherein the logic circuit uses a logical sum, a negative logical sum, a pull-down circuit, and a combination thereof. The parallel-serial conversion circuit according to claim 1,
A parallel-to-serial conversion circuit, wherein the parallel signal input to the input unit includes an electric signal, an electromagnetic wave signal, an optical signal, a sound wave signal, and an elastic wave signal.

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