JP5716561B2 - Clock operating system - Google Patents

Description

  The present invention relates to a clock operation system.

  Signals (data) are transmitted within the integrated circuit chip, between chips, and between bodies (within the device and between devices). In general, signal transmission is performed in the form of 1-bit serial data. Therefore, parallel-serial conversion processing for converting parallel data into serial data is performed on the transmission side (transmission circuit: transmitter). On the receiving side (receiving circuit: receiver), serial / parallel conversion processing is performed for converting the received serial data into parallel data. In a circuit that performs parallel-serial conversion processing and serial-parallel conversion processing, processing is performed using a clock signal having a multiplication relationship. Hereinafter, an example in which such a circuit is referred to as a clock operation circuit and a parallel-serial conversion processing circuit is used as the clock operation circuit will be described. However, the configuration described below is not limited thereto.

  In a typical parallel-serial conversion processing circuit, a plurality of parallel data is multiplexed (MUX) gradually from a low rate to a high-speed rate over a plurality of stages, and finally, the serial data is collected. In a general circuit system including a clock operation circuit, a clock distribution line is used so that a clock signal group (multi-rate clock) having a different frequency and phase including the clock with the highest rate is not skewed. Distribute accurately. Each circuit in the system operates in accordance with the supplied clock signal group, so that the entire system operates in synchronization. Hereinafter, a circuit system including such a clock distribution circuit is referred to as a clock operation system.

  In recent years, with the improvement in performance of data transmission equipment such as a chip-to-chip / device interface for computers and a transceiver, there has been a demand for higher speed for increasing the data rate of signal transmission / reception inside and outside the device. As the data rate is improved, it is necessary to compensate for the delay generated between the distribution of the clock signal and the data transmission line, and the process voltage temperature (PVT) variation. Therefore, a highly accurate phase compensation circuit (Variable Delay Line), a phase adjustment circuit (Phase Interpolator (PI)), a clock buffer group (Clock repeater), or the like) is provided. The Phase Interpolator (PI) is generally called a “phase interpolator”, but may be called a “phase adjustment circuit” here.

  In order to accurately distribute the multi-rate clock without causing skew, it is necessary to arrange a large number of clock repeaters on the clock distribution line. However, the clock signals supplied via a plurality of circuits have a time difference (skew) in the delay from the input terminal to the output node. Therefore, even in the parallel-serial conversion processing circuit, an error occurs between the multiplexers between the stages. In particular, when the number of stages in the clock buffer group is large, the occurrence of skew is sensitive to PVT fluctuations, and the phase shift between multi-rate clocks becomes large, and an error may occur. Therefore, the speed performance in serializing the data is affected, the circuit scale of the phase adjustment block (PI) is increased, and the power consumption is also increased.

Japanese Patent Publication No. 7-73219 JP-A-4-343129

  The embodiment realizes a clock operation system capable of performing an operation accurately synchronized with a clock signal with a small circuit scale.

  According to the embodiment, a transmission clock generation circuit that generates a clock signal group including a clock signal pair having an antiphase relationship, a transmission path of the clock signal group, and a plurality of clock signals having a multiplication relationship with respect to the clock signal group A clock operation circuit having a multiplied clock generation circuit that generates a plurality of clock signals from a group of clock signals transmitted via a transmission path. The

  According to the embodiment, a clock operation system with a small circuit scale and few errors is realized.

FIG. 1 is a diagram showing an overall configuration of a general clock operation system having a plurality of parallel-serial conversion circuits. FIG. 2 is a time chart showing a clock signal supplied to the parallel-serial conversion circuit of FIG. FIG. 3 is a diagram illustrating an overall configuration of the clock operation system according to the first embodiment. FIG. 4 is a diagram illustrating a circuit configuration of the multiplied clock generation circuit according to the first embodiment. FIG. 5 is a diagram showing a circuit configuration and an operation of a multiplier that generates a clock signal having a double frequency. FIG. 6 is a diagram showing another circuit configuration and operation of a multiplier that generates a clock signal having a double frequency. FIG. 7 is a diagram showing another circuit configuration and operation of a multiplier that generates a clock signal having a double frequency. FIG. 8 is a diagram for explaining generation of a phase error between a clock signal and data in the first embodiment. FIG. 9 is a diagram for explaining generation of a phase error between a clock signal and data in the first embodiment. FIG. 10 is a diagram illustrating a configuration of a one-channel parallel-serial conversion circuit of the clock operation system according to the second embodiment. FIG. 11 is a diagram illustrating a circuit configuration of the multiplied clock generation circuit 32 according to the second embodiment. FIG. 12 is a diagram comparing the number of elements in the general clock operation system shown in FIG. 1 with the number of elements in the first and second embodiments. FIG. 13 compares the number of elements in the general clock operation system shown in FIG. 1 with the number of elements in the first and second embodiments converted to FF when the number of channels N is eight. FIG. FIG. 14 is a diagram illustrating a configuration of a one-channel parallel-serial conversion circuit of the clock operation system according to the third embodiment. FIG. 15 is a time chart showing the operation of the parallel-serial conversion circuit of the third embodiment. FIG. 16 is a diagram illustrating a configuration of a one-channel parallel-serial conversion circuit of the clock operation system according to the fourth embodiment. FIG. 17 is a time chart illustrating the operation of the multiplied clock generation circuit according to the fourth embodiment. FIG. 18 is a time chart showing the operation of the parallel-serial conversion circuit of the fourth embodiment. FIG. 19 is a diagram illustrating a schematic configuration when the configuration of the embodiment is applied to a general clock operation system.

  Before describing the embodiments, a general clock operation system having a parallel-serial conversion circuit will be described.

  FIG. 1 is a diagram showing an overall configuration of a general clock operation system having a plurality of parallel-serial conversion circuits provided corresponding to a plurality of channels. As shown in FIG. 1, the clock operation system generates a plurality of parallel-serial conversion circuits 14-0, 14-1,..., 14-n and a group of clock signals (multi-rate clocks) having different frequencies and phases. A clock generation circuit 11 that distributes the clock signal group, and phase adjustment circuits 13-1 and 13-2 that adjust the phase of the distributed clock signal group. The distribution circuit has a large number of buffers BF for each clock signal in order to distribute the clock signal group to a large number of locations including the plurality of parallel-serial conversion circuits 14-0, 14-1, ..., 14-n. Here, a clock buffer group (Clock repeater) for distributing the full-rate clock signal CKf0 having the highest frequency is represented by 12f. A clock buffer group that distributes a half-rate clock signal CKh0 that is ½ the frequency of CKf0 generated by the clock generation circuit and a clock signal CKhx that is opposite in phase to the half-rate clock signal CKhx is represented by 12h. Similarly, 12q represents a clock buffer group that distributes a quarter-rate clock signal CKq0 that is 1/4 of the frequency of CKf0 generated by the clock generation circuit and the clock signal CKqx of the opposite phase. Here, the half-phase and quarter-rate clock signals are transmitted with the opposite phase clock signals, but the full rate clock signal may also be transmitted with the opposite phase clock signals. In addition to signals other than the full-rate clock signal, a signal having a phase shifted by an integer multiple of the cycle of the full-rate clock signal may be transmitted. Further, there are cases where the clock signal shifted in phase and phase is not transmitted, or only the full-rate clock signal is distributed. In such a case, a necessary clock signal is generated from a distributed signal including a full rate clock signal by a frequency dividing circuit or the like.

  The plurality of parallel-serial conversion circuits 14-0, 14-1,..., 14-n perform a clock operation based on the distributed clock signal group. Here, one parallel-serial conversion circuit performs parallel-serial conversion processing for converting 4-input parallel data into 1-output serial data. The circuit configuration and operation of the parallel-serial conversion circuit will be described.

  As shown in FIG. 1, the parallel-serial conversion circuit 14-0 converts 4-input parallel data IN0 including dqa, dqb, dqc, dqd into 1-output serial data OUT0 and outputs it. The multiplexer (MUX) Mq0 receives two parallel data dqa and dqb, and generates one output diha that alternately outputs dqa and dqb. The multiplexer (MUX) Mq1 receives the two parallel data dqc and dqd and generates one output dihb that alternately outputs dqc and dqd. The flip-flop (FF) FFh0 latches the output diha of Mq0 and outputs it as dha. The flip-flop (FF) FFh1 latches the output dihb of Mq1 and outputs it as dhb. The multiplexer (MUX) Mh receives the two parallel data dha and dhb, and generates one output df that alternately outputs dha and dhb. The flip-flop (FF) FFf latches the output df of Mh and outputs it as the output OUT0. Each multiplexer (MUX) and flip-flop (FF) operate in response to the clock signal shown.

  FIG. 2 is a time chart showing a clock signal supplied to the parallel-serial conversion circuit 14-0 of FIG. CKf is a full rate clock signal, and CKh is a half rate clock signal. CKh ′ is a signal obtained by shifting CKh by ¼ phase. In other words, CKh ′ is a signal obtained by shifting CKh by a half cycle of CKf. Although not shown, the CKh anti-phase signal CKhx is a signal obtained by shifting CKh by 1/2 phase. CKq is a quarter rate clock signal. CKqx is a reverse phase signal of CKq, that is, a signal obtained by shifting CKq by 1/2 phase.

  The 4-input parallel data dia, dib, dic, and did input to the parallel-serial conversion circuit 14-0 are data signals that change every four cycles of CKf. dia, dib, dic, and did are latched at different timings by an FF (not shown), and input to Mq0 and Mq1 as dqa, dqb, dqc, and dqd, respectively. Since Mq0 selects dqa while CKq is H (high) and dqb while L (low), its output diha alternately includes dqa and dqb every two cycles of CKf. Since Mq1 selects dqc while CKq is H (high) and dqd while CKq is L (low), its output dihb includes dqc and dqd alternately every two cycles of CKf. The value of dqa is stable while Mq0 selects dqa, and the value of dqb is stable while Mq0 selects dqb. The same applies to Mq1.

  FFh0 latches diha according to CKh 'and outputs it as dha. Similarly, FFh1 latches dihb according to CKhx 'having a phase opposite to CKh' and outputs it as dhb. Therefore, the timing at which dha and dhb change is shifted by one cycle of CKf.

  Since Mh selects dha while CKh is H (high) and dhb while L (low), the output df includes dha and dhb alternately for each cycle of CKf. As a result, the 4-input parallel data dia, dib, dic, and did are converted into 1-output serial data df. The FFf latches df with CKf and generates an output OUT0 that changes every cycle of CKf.

  As described above, the parallel-serial conversion circuit 14-0 performs a parallel-serial conversion operation using clock signal groups having different frequencies and phases. Although an example of converting 4-input parallel data to 1-output serial data has been described here, the same applies to conversion of parallel data with 8 or more inputs to serial data. A clock signal having a cycle more than twice the clock signal is transmitted.

  The other parallel / serial conversion circuits 14-1,..., 14-n have the same configuration as the parallel / serial conversion circuit 14-0, and perform the same operation based on the supplied clock signal group.

  In the clock operation system shown in FIG. 1, a clock signal group generated by dividing and shifting the full-rate clock signal CKf by the clock generation circuit is generated, and the clock signal group including CKf is distributed to each part in the system. . Therefore, one clock generation circuit may be provided for a plurality of parallel-serial conversion circuits, and can be shared.

  A “centralized” clock distribution line that distributes a clock group generated by a single clock generation circuit as described above is required to accurately distribute the clock to each location. For this reason, as described above, it is necessary to arrange a large number of clock buffer groups (clock repeaters), and it is necessary to adjust the phase between multi-rate clocks. Therefore, as shown in FIG. 1, a phase adjustment circuit 13-1 for adjusting the phase of the half rate clock signal group and a phase adjustment circuit 13-2 for adjusting the phase of the quarter rate clock signal group are provided. . Therefore, there is a problem that the circuit scale becomes large.

  Further, the clock signals that have passed through a large number of clock buffer groups and phase adjustment circuits have a temporal difference (skew), and therefore an error occurs between the operations of the MUX. In particular, when the number of stages of the clock buffer group (clock repeater) is large, the clock distribution circuit and the clock operation circuit are sensitive to PVT (power, voltage, temperature) fluctuations, and the phase shift between the data and clock changes significantly. May cause an error. Therefore, there may be a problem that the speed when data is serialized cannot be increased.

  FIG. 3 is a diagram illustrating an overall configuration of the clock operation system according to the first embodiment. The clock operation system of the first embodiment also performs parallel-serial conversion processing for converting 4-input parallel data into 1-output serial data, and such parallel-serial conversion processing can be performed in n channels in parallel.

  The clock operation system of the first embodiment includes a plurality of parallel-serial conversion circuits 23-0, 23-1,..., 23-n, and a clock generation circuit 21 that generates a quarter-rate clock signal pair having a reverse phase relationship. And a distribution circuit for distributing the quarter rate clock signal pair. A plurality of parallel-serial conversion circuits 23-0, 23-1,..., 23-n generate a multiplied clock signal that generates a multiplied clock signal (multi-rate clock signal) based on the distributed quarter rate clock signal pair. Each circuit 24 is provided.

  The clock generation circuit 21 divides the full-rate clock signal CKf0 by two to generate a half-rate clock signal, and a half-frequency clock signal by two to divide the half-rate clock signal by two to make a positive phase and a reverse phase quarter And two frequency dividers D1 and D2 for generating rate clock signals CKq0 and CKq0x. The quarter rate clock signal pair CKq0 and CKq0x are distributed to a plurality of parallel-serial conversion circuits 23-0, 23-1,..., 23-n via a clock buffer group 23, respectively.

  In other words, the clock operation system of the first embodiment does not distribute the full-rate clock signal and the half-rate clock signal, but generates the multi-rate clock signal that is required by the multiplying clock generation circuit of each parallel-serial conversion circuit. This is different from the system of FIG. Therefore, the configuration and operation of the parallel-serial converter circuit are the same as those described with reference to FIGS. 1 and 2, and a description thereof is omitted. Hereinafter, the multiplied clock generation circuit 24 will be described.

  FIG. 4 is a diagram showing a circuit configuration of the multiplied clock generation circuit 24. The multiplied clock generation circuit 24 generates a half-rate clock signal CKh, a full-rate clock signal CKf, and a phase-shifted signal from the quarter-rate clock signals CKq and CKqx. The multiplication clock generation circuit 24 has a configuration in which a frequency doubler is provided in two stages. First, a single-stage multiplier will be described.

  FIG. 5 is a diagram showing a multiplier 25 that generates a clock signal having a double frequency. (A) shows a circuit configuration, and (B) and (C) show that the duty of the input clock signal is greater than 50%. The time chart in case and small case is shown.

  As shown in FIG. 5A, the multiplier 25 includes a multiplexer (MUX) MM and a frequency divider Di. The multiplexer (MUX) MM receives the clock signals CK180 and CK000 having a reverse phase relationship, and alternately selects CK180 and CK000 according to the signal CK090-50% output from the frequency divider Di. The output of the multiplexer MM is a clock signal CK-2f-180 that is twice the frequency of the clock signals CK180 and CK000.

  As shown in FIGS. 5B and 5C, when CK090-50% is L, the multiplexer MM selects the portion including the rising edge of CK180 and outputs it as CK-2f-180. This rising edge acts as a clock on the frequency divider Di, and the output CK090-50% of the frequency divider Di is inverted and becomes H. In response to this, the multiplexer MM selects CK000. At this time, immediately after the rising edge of CK180, and CK000 is in the opposite phase to CK180, CK-2f-180 changes to L. Thereafter, since CK000 rises, CK-2f-180 changes to H. Thereafter, the above operation is repeated to generate a clock signal CK-2f-180 having a double frequency. As shown in FIGS. 5A and 5B, the clock signal CK-2f-180 having a frequency twice as large is generated regardless of whether the duty of the input clock signals CK180 and CK000 is larger or smaller than 50%. . Further, CK090-50% is a signal obtained by dividing CK-2f-180 by 2, and is a signal having a duty of 50%.

  Various modifications can be made to the multiplier. FIG. 6 is a diagram showing a multiplier 26 using a flip-flop (FF), where (A) shows the circuit configuration, and (B) and (C) are when the duty of the input clock signal is greater than 50%. And shows a time chart for a small case.

  In FIG. 6, the flip-flop FF has an inverting output connected to the input and operates as a divide-by-2 of the clock signal CK-2f-180. The positive output is inverted by the inverter IV and supplied to the multiplexer MM. As shown in FIGS. 6B and 6C, the multiplier 26 generates a clock signal CK-2f− having a frequency twice that of the input clock signals CK180 and CK000 regardless of whether the duty is larger or smaller than 50%. 180 is generated.

  FIG. 7 is a diagram showing another multiplier 27 using a flip-flop (FF), where (A) shows a circuit configuration, and (B) and (C) show that the duty of an input clock signal is 50% or more. The time chart when large and small is shown. The multiplier 27 is the same as the multiplier 26 in FIG. 6 except that it operates in response to the falling edge of the clock signal CK-2f-180. Since the clock signal CK-2f-180 operates in response to the falling edge of the clock signal CK-2f-180, the clock signal CK-2f-180 generated by the multiplier 27 in FIG. Is shifted in phase.

  Returning to FIG. 4, the multiplied clock generation circuit 24 includes multiplexers MM10 and MM11, a frequency divider Dh, a buffer BFh, a multiplexer MM0, a frequency divider Df, a buffer BFf, and a buffer BF. Quater rate clock signals CKq and CKqx are input to multiplexers MM10 and MM11 in a different order. Multiplexer MM10 and frequency divider Dh form the multiplier shown in FIG. Further, since the multiplexer MM11 performs a selection operation with the output of the frequency divider Dh, a multiplier is similarly formed. The output CKh of the multiplexer MM10 and the output CKhx of the multiplexer MM11 are opposite phase signals because the order of inputs of the multiplexers MM10 and M11 is changed. Multiplexer MM0 and frequency divider Df form the multiplier shown in FIG. As a result, the buffer BF outputs a full rate clock signal CKf having a frequency four times that of the quarter rate clock signals CKq and CKqx.

  When the parallel / serial conversion circuit of FIG. 3 requires a phase shift signal other than the clock signal generated by the multiplication clock generation circuit 24 of FIG. 4, the CK090-50% is used, or other A necessary clock signal is generated according to the circuit configuration. A circuit for this purpose can be realized by using the circuit used in the clock generation circuit 11 of FIG.

  In the clock operation system according to the first embodiment, a multiplied clock generation circuit 24 is provided in a parallel-serial conversion circuit that requires a clock group (full-rate and half-rate clock signals), and a clock is generated from the transmitted quarter-rate clock signal. Create a group. For this reason, it is possible to design the multiplying clock generation circuit 24 so as to be located at a distance close to the parallel-serial conversion circuit, and it is possible to minimize delay time and phase shift generated in the wiring.

  Since the clock signal of each rate is generated near the multiplexer (MUX) cell of the parallel-serial converter circuit, the distance between the multiplied clock generation circuit 24 and the MUX cell can be shortened. As a result, the number of clock buffer groups can be reduced. Further, in order to generate a high-frequency clock signal from the multiplication clock generation circuit 24 using a circuit having the same configuration as the MUX cell in the parallel-serial conversion circuit, so-called replica, a phase (time) between the clock signal and the data Errors can be compensated.

  8 and 9 are diagrams for explaining generation of a phase error between the clock signal and the data in the first embodiment. FIG. 8 shows the half-rate clock signal generated by the multiplier and the error in the first-stage parallel-serial conversion, and FIG. 9 shows the error in the full-rate clock signal generated by the multiplier and the second-stage parallel-serial conversion. Indicates.

  As shown in FIG. 8, the quarter rate clock signal CKq is applied to the multiplexer Mq1 via the buffer BFr, and alternately selects dqc or dqd. The delay time t1 from the rising edge of CKq to the change of the output dihb of Mq1 is t1 = tbuf + tmux, where tbuf is the delay time of the buffer BFr and tmux is the delay time of the multiplexer Mq1. On the other hand, the MM 10 alternately selects CKq and CKqx and outputs CKhx, which is applied to FFh1 via BFs. The delay time t2 from the rising edge of CKq until the output of the BFs changes is t2 = tmux '+ tbuf', where tmux 'is the delay time of the multiplexer MM10 and tbuf' is the delay time of the buffer BFs. When the multiplexers Mq1 and MM10 and the buffers BFr and BFs are respectively made as replicas, the delay times t1 and t2 are the same when the conditions such as fan-out, load, and parasitic capacitance are the same, and the data in FFh1 There is no delay difference in the clock signal.

  As shown in FIG. 9, the clock signal CKh-50% generated by the frequency divider Df is output through the buffer BFf and further applied to the multiplexer Mh through the buffer BFt. Also in this case, the delay time t3 from the rising edge of the output of the BFf to the change of the output df of the Mh is t3 = tbuf + tmux. On the other hand, the clock signal output from the buffer BFf is applied to the multiplexer MM0, the output is applied to the FFf via the buffer BFu, and the delay time t4 is t4 = tmux '+ tbuf'. Therefore, the delay times t3 and t4 are also the same, and no delay difference occurs between the data and the clock signal at FFf.

  FIG. 10 is a diagram illustrating a configuration of a one-channel parallel-serial conversion circuit of the clock operation system according to the second embodiment. In the clock operation system according to the second embodiment, the clock generation circuit 21 generates and transmits CKq0 ′ obtained by shifting CKq by ¼ period in addition to the quarter rate clock signals CKq0 and CKq0x. And different. In the second embodiment, the multiplied clock generation circuit 32 generates a full-rate clock signal, a half-rate clock signal, and a shifted signal based on the transmitted CKq, CKqx, and CKq ′, and a parallel-serial conversion processing unit To supply.

  FIG. 11 is a diagram illustrating a circuit configuration of the multiplied clock generation circuit 32. As is clear from the multiplication clock generation circuit 24 of the first embodiment of FIG. 3 except for the frequency divider Dh, the multiplication clock generation circuit 32 of the second embodiment replaces CKq ′ with MM10 and MM11. The difference is that it is applied. Since the operation of the multiplied clock generation circuit 32 of the second embodiment is the same as that of the first embodiment, description thereof is omitted.

  In FIG. 10, the delay time until the output dihb of Mq1 changes when the quarter rate clock signal CKq is applied to Mq1 via the buffer is represented by t5. In FIG. 11, CKq changes, the output CKh of MM10 changes, and the delay time until the output of the buffer BFj changes is represented by t6. When circuit elements are created as replicas, when the conditions such as fan-out, load, and parasitic capacitance are the same, the delay times t5 and t6 are the same, and there is no delay difference between the data and the clock signal.

  By transmitting a signal whose phase is shifted as in the second embodiment, the configuration of the multiplied clock generation circuit can be simplified and the circuit scale can be reduced.

  FIG. 12 is a diagram comparing the number of elements in the general clock operation system shown in FIG. 1 with the number of elements in the first and second embodiments. This figure shows the number of elements in different circuit portions when the quarter rate clock signal CKq is 7 GHz and the full rate clock signal CKf is 28 GHz, and shows the number of elements operating at each frequency. The clock signals of 7 GHz, 14 GHz, and 28 GHz correspond to 7 Gbps, 14 Gbps, and 28 Gbps, respectively.

  In the general clock operation system shown in FIG. 1, a clock buffer group (clock repeater) operating at 7 GHz is required 16 times the number of channels, and a clock buffer group operating at 14 GHz (clock repeater) is 16 times the number of channels. Double is necessary. Also, a clock buffer group (clock repeater) operating at 28 GHz is required 8 times the number of channels. Further, it is necessary to increase the number of flip-flops (FF) operating at 28 Gbps by the number of channels. Further, in the general clock operation system shown in FIG. 1, the phase adjustment circuit (PI) operating at 7 GHz needs 8 times the number of channels, and the phase adjustment circuit (PI) operating at 14 GHz is 8 channels. Double is necessary. Since the phase adjustment circuit is an analog system, the circuit scale is 8 FFs.

  In contrast, in the first embodiment, a multiplexer (MUX) that operates at 7 Gbps requires twice the number of channels, a multiplexer (MUX) that operates at 14 Gbps is required for the number of channels, and the frequency divider is a channel. Two times the number is required. Further, FFs operating at 14 Gbps and 28 Gbps are required for the respective number of channels. Furthermore, a clock buffer group (clock repeater) operating at 7 GHz is required 32 times the number of channels.

  In the second embodiment, a multiplexer (MUX) operating at 7 Gbps requires twice the number of channels, a multiplexer (MUX) operating at 14 Gbps is required for the number of channels, and a frequency divider is required for twice the number of channels. It is. Further, FFs operating at 28 Gbps are required for each channel. Furthermore, a clock buffer group (clock repeater) operating at 7 GHz is required 48 times the number of channels.

  As described above, the first and second embodiments can be expected to reduce the circuit scale and the layout size. In the first and second embodiments, since a phase adjustment circuit is not required, it can be realized only by a standard CMOS process advantageous in design.

  FIG. 13 compares the number of elements in the general clock operation system shown in FIG. 1 with the number of elements in the first and second embodiments converted to FF when the number of channels N is eight. FIG. This figure shows the number of elements in different circuit portions when the quarter rate clock signal CKq is 7 GHz and the full rate clock signal CKf is 28 GHz, and shows the number of elements operating at each frequency.

  In the general clock operation system shown in FIG. 1, in the clock buffer group, there are 128 FFs operating at 7 GHz, 128 FFs operating at 14 GHz, and 64 FFs operating at 28 GHz. . In the phase adjustment circuit (PI), there are 64 FFs operating at 7 GHz, 64 FFs operating at 14 GHz, and 8 additional FFs operating at 28 Gbps. As a result, a total of 456 FFs are required.

  On the other hand, in the first embodiment, the additional MUX requires 16 FFs operating at 7 Gbps and 8 FFs operating at 14 Gbps. In the frequency divider, 16 FFs are required. In the additional FF, eight FFs each operating at 14 Gbps and 28 Gbps are required. Furthermore, 256 FFs operating at 7 GHz are required in the clock buffer group. Thereby, a total of 312 FFs are required, and the number of FFs can be reduced by 32% compared to the example of FIG.

  In the second embodiment, the additional MUX requires 16 FFs operating at 7 Gbps and 8 FFs operating at 14 Gbps. In the frequency divider, 8 FFs are required. In the additional FF, eight FFs operating at 28 Gbps are required. Further, 384 FFs operating at 7 GHz are required in the clock buffer group. Thereby, a total of 424 FFs are required, and the number of FFs can be reduced by 7% compared to the example of FIG.

  As described above, the first and second embodiments can be expected to reduce the circuit scale and the layout size. In the first and second embodiments, since a phase adjustment circuit is not required, it can be realized only by a standard CMOS process advantageous in design.

  FIG. 14 is a diagram illustrating a configuration of a one-channel parallel-serial conversion circuit of the clock operation system according to the third embodiment. This parallel-serial conversion circuit converts 2-input parallel data into 1-output serial data.

FIG. 15 is a time chart showing the operation of the parallel-serial conversion circuit of the third embodiment.
In the parallel-serial conversion circuit of the third embodiment, the flip-flop FFi latches the input diha according to CKh, the flip-flop FFj latches the input dihb according to CKh, and the flip-flop FFk is FFj. Is latched according to CKhx. As a result, the output dhb of FFk changes with a delay of ½ cycle of CKh with respect to the output dha of FFi. The multiplexer Mh alternately selects the inputs dha and dhb according to CKh and outputs it as df. In this way, 2-input parallel data is converted to 1-output serial data.

  The multiplied clock generation circuit 41 includes the multiplier shown in FIG. 5 and generates a full-rate clock signal CKf from the opposite-phase signal pair CKh and CKhx generated from the transmitted half-rate clock signal CKh0. The FFf latches the output df of Mh according to CKf and outputs it as OUT.

  The delay time when the output df of Mh changes according to the change of CKh is t7, and the delay time when the output CKf of MM0 of the multiplied clock generation circuit 41 changes according to the change of CKh is t8. When circuit elements are created as replicas, when conditions such as fan-out, load, and parasitic capacitance are the same, the delay times t7 and t8 are the same, and there is no delay difference between the data and the clock signal.

  FIG. 16 is a diagram illustrating a configuration of a one-channel parallel-serial conversion circuit of the clock operation system according to the fourth embodiment. This parallel-serial conversion circuit converts 4-input parallel data into 1-output serial data. Here, the first multiplier 51 is the circuit shown in FIG. 6, and the second multiplier 52 is the circuit shown in FIG.

  FIG. 17 is a time chart illustrating the operation of the multiplied clock generation circuit according to the fourth embodiment. FIG. 18 is a time chart showing the operation of the parallel-serial conversion circuit of the fourth embodiment.

  In the parallel-serial conversion circuit of the clock operation system according to the fourth embodiment, one FF is arranged in front of one input of the MUX, two FFs are arranged in front of the other input, and the other input is arranged in one of the inputs. This is a circuit in which the configuration of the third embodiment for delaying the input by 1/2 cycle is applied to four inputs. In addition, the multiplication frequency generation circuit generates half-rate clock signals CKh and CKhx and a full-rate clock signal CKf from the opposite-phase signal pair CKq and CKqx generated from the transmitted quarter-rate clock signal CKq0. The first multiplier 51 is the multiplier of FIG. 6 and generates the original signal CKh ′ of the half-rate clock signal. The second multiplier 52 is the multiplier shown in FIG. 7, and generates the original signal CKhx ′ of the half-phase clock signal having the opposite phase. The third multiplier 53 is the multiplier shown in FIG. 5, and generates a full rate clock signal CKf from the half rate clock signals CKh and CKhx.

  In the fourth embodiment, the delay time when the output df of Mh changes according to the change of CKhx is t9, and the delay time when the output CKf of MM0 of the multiplier 53 changes according to the change of CKhx is t10. To do. When circuit elements are created as replicas, when the conditions such as fan-out, load, and parasitic capacitance are the same, the delay times t9 and t10 are the same, and no delay difference occurs between the data and the clock signal.

  Since the configuration and operation of the parallel-serial conversion circuit of the clock operation system of the fourth embodiment are clear from the drawing, further description is omitted.

  As described above, the clock operation system having the parallel-serial conversion circuit has been described as an example. However, the configuration of the described embodiment can be applied to any clock operation system using a plurality of clock signals having different frequencies having a multiplication relationship. .

FIG. 19 is a diagram illustrating a schematic configuration when the configuration of the embodiment is applied to a general clock operation system.
This clock operation system includes a plurality of clock operation circuits 64-0, 64-1,..., 64-n, and each clock operation circuit includes a multiplied clock generation circuit 63. A transmission clock generation circuit 61 provided in the system generates a clock signal group to be transmitted from the full rate clock signal CKf. The clock signal group is a clock signal generated by dividing the full-rate clock signal CKf, and includes a clock signal whose phase is shifted as necessary. The clock signal group is transmitted to a plurality of clock operation circuits 64-0, 64-1,..., 64-n through a clock buffer group (clock repeater) 62. The full-rate clock signal CKf is not included in the transmitted clock signal group. The multiplied clock generation circuit 63 of each clock operation circuit multiplies the transmitted clock signal group, and the full-rate clock signal CKf, half-rate clock signals CKh and CKhx necessary for the clock operation circuit, and those as necessary. A clock signal with a shifted phase is generated.

  As described above, in the embodiment, a clock signal with a low frequency is transmitted, and each clock operation circuit performs a multiplication process on the transmitted clock signal with a low frequency, so that a clock signal with a high frequency necessary for the operation is obtained. Create a group. As a result, the scale of the circuit that distributes the clock signal can be reduced, and each clock operation circuit performs clock synchronous operation using a clock signal group including a full rate clock signal generated by a multiplying clock generation circuit existing in the vicinity. Since this is done, the error can be reduced.

  Regarding the number of bits for parallel-serial conversion, in the above embodiment, the example of 4 or 2, that is, 4: 1 or 2: 1 has been described, but the same applies to the number of bits of 8: 1 or more. Yes. In addition, when the number of bits is 8: 1 or more, it is possible to transmit a clock signal pair obtained by dividing by 4 without transmitting a clock signal pair obtained by dividing the full rate clock signal by 8.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

21 Transmission Clock Generation Circuit 22 Transmission Path of Clock Signal Group (Clock Buffer Group (clock repeater))
23-0 to 23-n Clock operation circuit (parallel serial conversion circuit)
24 Multiplication clock generation circuit

Claims (6)

A transmission clock generation circuit for generating a clock signal group including a pair of clock signals of opposite phase relationship;
A transmission path of the clock signal group;
A clock operation circuit that operates based on a plurality of clock signals having a multiplication relationship with respect to the clock signal group, and
The clock operation circuit includes a multiplied clock generation circuit that generates the plurality of clock signals from the clock signal group transmitted via the transmission path ,
The multiplication clock generation circuit includes a plurality of double clock generation stages,
Each double clock generation stage
A plurality of double clock generators, each of which includes a multiplexer and a frequency divider that divides the output of the multiplexer and selects the output of the multiplexer according to the output of the frequency divider Prepare according to the number of stages,
The outputs of the two double clock generation circuits in the preceding stage are input to one double clock generation circuit in the subsequent stage,
The clock operation system , wherein the clock signal pair is input to the multiplexer of the first double clock generation stage . The clock operation circuit is a parallel-serial conversion circuit that converts parallel data into serial data,
The parallel-serial conversion circuit includes a plurality of selection stages,
Each selection stage
A two-input parallel serial circuit having a multiplexer and a flip-flop that holds an output of the multiplexer according to a clock signal corresponding to the plurality of clock signals output from the multiplied clock generation circuit ; Prepare according to the number of stages,
The output of the previous stage of the two two-input parallel-serial circuit, clocked system of claim 1 wherein the input to one of the 2 input parallel-serial circuit of the subsequent stage. The clock signal group is supplied to a plurality of the clock operation circuits,
It said plurality of clocked circuits, according to claim 1 or 2 clock operation system according each with the multiplication clock generating circuit. The double clock generation circuit includes:
A multiplexer to which two clock signals of opposite phase relation are input;
A frequency dividing circuit for frequency-dividing the output of the multiplexer,
Clocking system of claim 1, wherein for selecting the output of said multiplexer in response to the output of the divider. The multiplication clock generation circuit includes two double clock generation stages,
The first double clock generation stage is:
Two first-stage multiplexers in which two clock signals having opposite phase relations are input in different orders, and a frequency dividing circuit that divides one output of the two first-stage multiplexers, Select the outputs of the two first stage multiplexers according to the output of the divider circuit,
The second double clock generation stage is
A second-stage multiplexer to which the outputs of the two first-stage multiplexers are input; and a frequency-dividing circuit that divides the output of the second-stage multiplexer. clocking system of claim 1, wherein for selecting the output of the second stage multiplexers. The multiplication clock generation circuit includes a reverse phase clock generator and two double clock generation stages.
The negative phase clock generator generates two quarter rate clock signals having a reverse phase relationship from the quarter rate clock signal,
The first double clock generation stage is
The first and second multipliers are inputted with the two quarter-rate clock signals having the opposite phase relations in different order. The first multiplier includes a first stage first multiplexer, and the first stage first multiplier. A first-stage first flip-flop that divides the output of the multiplexer, and selects an output of the first-stage first multiplexer according to an inverted signal of the output of the first-stage first flip-flop, The second multiplier has a first-stage second multiplexer and a first-stage second flip-flop that divides the output of the first-stage second multiplexer, and the output of the first-stage second flip-flop. The first stage second multiplexer output is selected in accordance with the inverted signal of the first stage, and the first stage first and second flip-flops perform a latch operation at different change edges,
The second double clock generation stage is
A second-stage multiplexer to which the outputs of the first-stage first and second multiplexers are input, and a frequency-dividing circuit that divides the output of the second-stage multiplexer, according to the output of the frequency-dividing circuit clocking system of claim 1, wherein for selecting the output of the second stage multiplexer Te.

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